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MT6516 sm/gprs/edge application processor data sheet version: 1.02 release date: 2009-05-05 ? 2009 mediatek inc. this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this info rmation in whole or in part is strictly prohibited. specifications are subject to change without notice. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 2 of 1535 revision history revision date comments 1.00 feb 24, 2009 first release 1.01 april 1, 2009 minor format change updated pin definitions: w31, w33, aa37, ab32 1.02 may 5, 2009 removed one debug pin. updated auxiliary adc unit section modified msdc clksrc description of msdc_cfg added irda framer section added mpeg-4/h.263 video codec free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 3 of 1535 table of contents revision history ............................................................................................................... ......................2 preface ........................................................................................................................ ............................6 1 product description ............................................................................................................ .........7 1.1 pin outs ....................................................................................................................... .........7 1.2 top marking definition......................................................................................................... .9 1.3 dc characteristics............................................................................................................. ...9 1.4 pin description................................................................................................................ ....10 1.5 power description.............................................................................................................. .20 1.6 ordering information ........................................................................................................... 20 2 application micro-controller unit subsystem ........................................................................20 2.1 processor core................................................................................................................. ..20 2.2 memory management.........................................................................................................20 2.3 bus system..................................................................................................................... ....20 2.4 uuid ........................................................................................................................... ........20 2.5 interrupt controller........................................................................................................... ...20 2.6 direct memory access........................................................................................................20 2.7 ap config register..........................................................................................................20 2.8 apmcusys config register ..........................................................................................20 2.9 ap extended gpt ..............................................................................................................20 2.10 auxiliary adc unit ............................................................................................................. .20 2.11 coresight...................................................................................................................... ......20 2.12 cpu-cpu interface (ccif).................................................................................................20 2.13 efuse controller (efusec) .................................................................................................20 2.14 external memory interface..................................................................................................20 2.15 general purpose inputs/outputs ........................................................................................20 2.16 general purpose timer (ap) ..............................................................................................20 2.17 graph1sys clock management register .......................................................................20 2.18 graph2sys clock management register .......................................................................20 2.19 hdq/1-wire ..................................................................................................................... ....20 2.20 i2c / sccb controller.........................................................................................................2 0 2.21 irda framer .................................................................................................................... ....20 2.22 keypad scanner ................................................................................................................. 20 2.23 memory stick and sd memory card controller .................................................................20 2.24 nand flash interface ......................................................................................................20 2.25 nand flash ecc ............................................................................................................20 2.26 reset generation unit (aprgu)........................................................................................20 2.27 sim interface .................................................................................................................. ....20 2.28 slow clocking unit for ap side ...........................................................................................20 2.29 uart ........................................................................................................................... .......20 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 4 of 1535 2.30 usb 2.0 high-speed dual-role controller.........................................................................20 3 modem micro-controller unit subsystem................................................................................20 3.1 processor core................................................................................................................. ..20 3.2 memory management.........................................................................................................20 3.3 bus system..................................................................................................................... ....20 3.4 interrupt controller........................................................................................................... ...20 3.5 direct memory access........................................................................................................20 3.6 general purpose inputs/outputs ........................................................................................20 3.7 general purpose timer (md) .............................................................................................20 3.8 l1 cache controller............................................................................................................ .20 3.9 mpu ............................................................................................................................ ........20 3.10 log accelerator................................................................................................................ ...20 3.11 md config register.........................................................................................................20 3.12 mdmcusys config register .........................................................................................20 3.13 reset generation unit (mdrgu) .......................................................................................20 4 2.75g modem subsystem .......................................................................................................... 20 4.1 automatic frequency control (afc) unit ...........................................................................20 4.2 automatic power control (apc) unit..................................................................................20 4.3 baseband front end.......... .................................................................................................20 4.4 baseband parallel interface ...............................................................................................20 4.5 baseband serial interf ace ..................................................................................................20 4.6 csd accelerator ................................................................................................................ .20 4.7 divider........................................................................................................................ .........20 4.8 fcs codec ...................................................................................................................... ...20 4.9 gprs cipher unit............................................................................................................... 20 4.10 md2gsys config register.............................................................................................20 4.11 timing generator............................................................................................................... .20 4.12 voice front-end................................................................................................................ ..20 5 multimedia subsystem........................................................................................................... ....20 5.1 2d acceleration................................................................................................................ ...20 5.2 audio src mixer ................................................................................................................ 20 5.3 backlight scaling .............................................................................................................. ..20 5.4 camera interface ............................................................................................................... .20 5.5 camera interface ............................................................................................................... .20 5.6 capture resize ................................................................................................................. ..20 5.7 cevasys subsystem ........................................................................................................20 5.8 display pixel interface controller .......................................................................................20 5.9 drop resize .................................................................................................................... ....20 5.10 display serial interface controller ......................................................................................20 5.11 graphics memory interface ................................................................................................20 5.12 gmc fake engine ..............................................................................................................20 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 5 of 1535 5.13 graph1sys config register ........................................................................................20 5.14 graph2sys config register ........................................................................................20 5.15 h.264 decoder.................................................................................................................. ..20 5.16 image dma...................................................................................................................... ...20 5.17 image processor................................................................................................................ .20 5.18 jpeg decoder................................................................................................................... .20 5.19 jpeg encoder ................................................................................................................... .20 5.20 lcd interface.................................................................................................................. ....20 5.21 m3d ............................................................................................................................ ........20 5.22 mpeg-4 deblocking filters ................................................................................................20 5.23 mpeg-4/h.263 video codec ...........................................................................................20 5.24 post resize.................................................................................................................... .....20 5.25 spi interface controller ......................................................................................................2 0 5.26 tv controller.................................................................................................................. .....20 5.27 tv encoder ..................................................................................................................... ....20 5.28 wavetable synthesizer .......................................................................................................20 6 clock, mixed subsystem ......................................................................................................... ..20 6.1 analog front-end & analog blocks.....................................................................................20 6.2 clocks ......................................................................................................................... ........20 6.3 pulse-width modulation outputs ........................................................................................20 6.4 real time clock ................................................................................................................ .20 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 6 of 1535 preface acronym for register type r/w capable of both read and write access ro read only rc read only. after reading the register bank, each bit which is high(1) will be cleared to low(0 ) automatically. wo write only w1s write only. when writing data bits to register bank, each bit which is high(1) will cause the corresponding bit to be set to 1. data bits which are low(0) has no effect on the corresponding bit. w1c write only. when writing data bits to register bank, each bit which is high(1) will cause the corresponding bit to be cleared to 0. data bits which are low(0) has no effect on the corresponding bit. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 7 of 1535 1 product description 1.1 pin outs one type of package for this product, tfbga 15mm*15mm, 564-ball, 0.378mm pitch (0.53457mm stagger) package, is offered. pin outs and the top view are illustrated in figure 1 for this package. outline and dimension of package is illustrated in figure 2 , while the definition of package is shown in table 1 . 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132333435363738 a pad_td p1 spi_cs_ n krow3 kcol1 kcol5 pad_us b_dm pad_us b_id avss12 _pll aux_in0 _vbout pad_bd laip pad_au _vcm_n o pad_au _vcm_p o pad_au _out0_ p pad_au _moutr avdd28 _mbuf a b pad_tc p pad_td n1 krow2 kcol0 kcol2 kcol6 pad_us b_dp avdd12 _pll avss28 _tvdac pad_au x_in6 pad_au x_ym pad_bd lain avss28 _afe avdd28 _afe pad_au _out0_ n pad_au _moutl avss28 _mbuf irda_p dn b c pad_td p0 pad_tc n spi_sc k krow6 kcol3 kcol7 pad_tv out pad_au x_in4 pad_au x_xm pad_bd laqn pad_au _vin1_n pad_au _vin0_n pad_au _fminr bpi_bu s3 c d pad_td n0 spi_mo si krow1 krow5 kcol4 usb_dr vvbus avdd12 _usb pad_sy sclk pad_au x_in2 pad_au x_yp pad_ap c pad_au _vin1_p pad_au _vin0_p pad_au _fminl bpi_bu s5 urxd1 d e pad_rd n0 pad_rd p0 spi_mis o krow4 krow7 avdd28 _pll pad_fs res pad_au x_xp pad_bd laqp bpi_bu s7 ucts1 e f pad_rc n krow0 avdd33 _usb pad_au x_in8 avss28 _pll pad_au x_in7 pad_af c bpi_bu s9 irda_r xd i2s_ws f g pad_rd n1 pad_rc p pad_tv rt avdd28 _mipitx vdd33_ spi avss33 _usb aux_in3 _isense bsi_dat a bpi_bu s2 i2s_clk g h pad_rd p1 dvdd28 _mipitx dvss28 _mipitx pad_us b_vrt avdd28 _tvdac aux_in5 _chrin avss28 _rfe pad_au _micbia s_p bsi_cs0 bpi_bu s1 i2s_dat gpio115 h j mc1ck mc1da0 dvdd28 _mipirx dvdd12 _mipi dvdd28 _mipitx dvss28 _mipitx pad_us b_vbus avss12 _usb pad_au x_in1 avdd28 _rfe bsi_cl k bpi_bu s8 urts1 sysrst _b j k mc1da2 mc2ck mc2cm0 dvdd12 _mipi vdd33 vdd33 bpi_bu s6 bpi_bu s4 eint7 pwr_k ey k l mc0cm0 mc1cm0 mc2da1 mc2da0 avss28 _mipitx vdd33_ mipi vddk bpi_bu s0 eint9 sda0 l m mc1ins mc2ins mc2pw ron dvss12 _mipi vss33 vddk vss33 vss33 vss33 vss33 vss33 vss33 vdd33 irda_tx d utxd1 eint0 gpio129 m n mc0da1 mc1wp mc2wp vdd33_ mc2 dvss12 _mipi vddk vss33 vdd33 srclke na eint6 gpio130 n p mc0da3 mc1da3 mc1da1 vss33 vddk vss33 vss33 vddk vddk eint8 gpio131 gpio132 srclke nan p r mc0wp mc0da2 mc1pw ron dvss28 _mipirx vddk vddk vss33 vddk vddk vddk vddk scl0 gpio133 gpio128 r t mc0ins mc0pw ron vdd33_ mc0 mc0da0 vddk vss33 vddk vddk vss33 vddk vdd33 gpio127 gpio126 ionejt ag t u lsda lsa0 lsck mc0ck vdd33_ mc1 vddk vss33 vss33 vss33 vddk vss33 vdd33 icoresi ght hdq secu_e n u v lpce1b lsce0b lsce1b vddk vss33 vss33 vss33 vss33 vss33 vss33 pad_si o ceva_r tck ceva_t di nc iboot v w lpce0b lpte dpihsy nc lrstb vdd33_ nld vddk vddk vss33 vss33 vss33 vddk vss33 avss30 _vsim avdd30 _vsim ceva_t do ceva_t ms w y lrdb lpa0 nld25 nld19 vddk vss33 vss33 vss33 vss33 vss33 vss33 pad_sc lk2 pad_sc lk pad_sr st2 pad_sr st ceva_t ck y aa lwrb dpivsy nc nld17 nld21 vdd33_ nld vddk vss33 vss33 vss33 vddk vss33 pad_si o2 testmo de bbwak eup avdd30 _vsim2 aa ab dpide nld24 nld15 nld13 vss33 vddk vss33 vss33 vss33 vss33 vddk avdd_r tc avss30 _vsim2 jrtck jtdi xin ab ac dpick nld20 nld5 nld11 vdd33_ nld vddk vss33 vss33 vss33 vss33 vss33 vddk vss33 gpio125 jtms jtdo xout ac ad nld22 nld12 nld3 nld1 vddk vddk vddk vddk vddk vddk vddk vddk utxd3 gpio119 jtrst_ b gpio120 jtck ad ae nld23 nld14 nale nrnb vddk vss33 vss33 vddk vddk vddk scl2 utxd4 urxd4 gpio121 ae af nld16 nld6 nreb vdd33_i 2c vss33 vddk vddk vddk vddk vdd33 eint2 gpio122 gpio116 gpio124 af ag nld18 nld7 scl1 pwm3 cmpcl k vddk vss33 vddk vss33 vddk vss33 vddk vss33 vdd33 urts2 eint4 gpio117 ag ah nld9 ncle pwm5 cmvref vss33 vss33 vss33 vdd33 daisyn c utxd2 pwm0 gpio118 ah aj nld10 nld2 nce0b cmrst vdd33_ camer a vddk vddk vddk daipcm out srclke nai pwm6 aj ak nld4 pwm4 cam_m echsh0 cmdat7 vdd33_ camer a vdd33_ emi vss33 vdd33_ emi vdd33_ emi vss33 vdd33_ emi vss33 vss33 vdd33_ trace j2tck btdmp_ dout2 btdmp_ clk2 eint3 urxd3 ak al nld8 nce1b cmdat9 cmdat1 ed16 ea6 vss33 ecs1_b vss33 vdd33_ emi vdd33_ emi vss33 vdd33_ trace traced ata5 j2rtck btdmp_ fsp1 urxd2 sda2 al am nweb cmpdn cmdat3 ed18 ed28 ea3 ea15 ea22 ed15 traced ata1 traced ata7 j2trst_ b btdmp_ din1 ucts2 pwm1 am an nld0 cam_st robe cmdat6 cmdat5 cmflas h ed30 ea5 ea0 ecas_b ea19 watch dog ed14 ed0 traced ata3 j2tdi btdmp_ fsp2 eint1 an ap sda1 cmdat8 ed23 ed19 ed31 ea4 ea10 ecs0_b ed_clk _b ea26 erd_b ed11 ed3 tracec lk traced ata6 j2tms daipcmi n eint5 ap ar pwm2 cmmcl k ed20 ed29 ed24 ea9 ed_clk ea23 ea20 fsourc e ed12 ed7 ed5 tracec tl traced ata4 j2tdo daiclk ar at cmhre f cmdat2 ed22 ed27 edqs3 ea2 ea11 ecke ec_clk ea17 ea13 eadmu x ed13 ed8 ed6 ed1 traced ata2 btdmp_ clk1 dairst at au cam_m echsh1 cmdat4 ed21 edqm2 ed26 ea1 ea14 ea12 eras_b ea25 ea16 ecs3_b ewait edqm1 ed9 edqm0 ed2 traced ata0 gpio123 au av cmdat0 ed17 edqs2 ed25 edqm3 ea7 ea8 ewr_b ea24 ea18 ea21 ecs2_b eadv_b edqs1 ed10 edqs0 ed4 mfiq av 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132333435363738 figure 1 top view of MT6516 tfbga 15mm *15mm, 564-ball, 0.378 mm pitch package free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 8 of 1535 MT6516 top view (balls facing down) MT6516 bottom view figure 2 outlines and dimension of tfbga 15mm*15mm, 564-ball, 0.378 mm pitch package free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 9 of 1535 package size edge ball center to center ball pitch ball dia. package thk. stand off substrate thk. symbol d e d1 e1 e1/e2 b a (max.) a1 c dimension in mm 15 15 13.99 13.99 0.535/0.378 0.3 1.2 0.21 0.26 table 1 definition of tfbga 15mm*15mm, 564-ball, 0.378 mm pitch package (unit: mm) 1.2 top marking definition figure 3 MT6516 t op m arking 1.3 dc characteristics 1.3.1 absolute maximum ratings prolonged exposure to absolute maximum ratings may reduce device reliability. functional operation at these maximum ratings is not implied. item symbol min max unit io power supply vdd33 -0.3 vdd33+0.3 v i/o input voltage vdd33i -0.3 vdd33+0.3 v operating temperature topr -20 80 celsius storage temperature tstg -55 125 celsius free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 10 of 1535 1.4 pin description table 2 pin descriptions (bolded types are functions at reset.) ball 38x38 name dir description mode0 mode1 mode2 mode3 uart interface d38 urxd1 io uart 1 receive data m34 utxd1 io uart 1 transmit data e37 ucts1 io uart 1 clear to send j35 urts1 io uart 1 request to send al35 urxd2 io uart 2 receive data ah34 utxd2 io uart 2 transmit data am36 ucts2 io uart 2 clear to send gpio109 i:ucts2 ag33 urts2 io uart 2 request to send gpio108 o:urts2 ak38 urxd3 io uart 3 receive data gpio67 i:urxd3 i:ucts4 ad30 utxd3 io uart 3 transmit data gpio68 o:utxd3 o:urts4 ae35 urxd4 io uart 4 receive data gpio69 i:urxd4 i:ucts3 ae33 utxd4 io uart 4 transmit data gpio70 o:utxd4 o:urts3 dedicated gpio interface h38 gpio115 io general purpose input/output 115 gpio115 o: clkm0 af36 gpio116 io general purpose input/output 116 gpio116 o: clkm1 ag37 gpio117 io general purpose input/output 117 gpio117 o: clkm2 ah38 gpio118 io general purpose input/output 118 gpio118 o: clkm3 ad32 gpio119 io general purpose input/output 119 gpio119 o: clkm4 ad36 gpio120 io general purpose input/output 120 gpio120 ae37 gpio121 io general purpose input/output 121 gpio121 af34 gpio122 io general purpose input/output 122 gpio122 au37 gpio123 io general purpose gpio123 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 11 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 input/output 123 af38 gpio124 io general purpose input/output 124 gpio124 ac31 gpio125 io general purpose input/output 125 gpio125 t36 gpio126 io general purpose input/output 126 gpio126 t32 gpio127 io general purpose input/output 127 gpio127 r37 gpio128 io general purpose input/output 128 gpio128 m38 gpio129 io general purpose input/output 129 gpio129 i:ucts4 n37 gpio130 io general purpose input/output 130 gpio130 o:urts4 p34 gpio131 io general purpose input/output 131 gpio131 i:ucts3 p36 gpio132 io general purpose input/output 132 gpio132 o:urts3 r35 gpio133 io general purpose input/output 133 gpio133 irda interface f36 irda_rxd io irda receive data gpio84 i:irda_rxd ceva_gpio0 i:mfiq m32 irda_txd io irda transmit data gpio85 o:irda_txd ceva_gpio1 b38 irda_pdn io irda power down control gpio86 o:irda_pdn ceva_gpio2 sim card interface y36 pad_srst io sim card 1 reset output y32 pad_sclk io sim card 1 clock output v30 pad_sio io sim card 1 data input/output y34 pad_srst2 io sim card 2 reset output y30 pad_sclk2 io sim card 2 clock output aa31 pad_sio2 io sim card 2 data input/output keypad interface c13 kcol7 io keypad column 7 gpio71 i:kcol7 o:clkm4 ceva_gpio14 b12 kcol6 io keypad column 6 gpio72 i:kcol6 o:clkm5 ceva_gpio15 a11 kcol5 io keypad column 5 gpio28 i:kcol5 i:d2ick o:usb_probe_out[4] d12 kcol4 io keypad column 4 gpio91 i:kcol4 ceva_gpio7 i:eint14 c11 kcol3 io keypad column 3 gpio90 i:kcol3 ceva_gpio6 i:eint13 b10 kcol2 io keypad column 2 gpio89 i:kcol2 ceva_gpio5 i:eint12 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 12 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 a9 kcol1 io keypad column 1 gpio88 i:kcol1 ceva_gpio4 i:eint11 b8 kcol0 io keypad column 0 gpio87 i:kcol0 ceva_gpio3 i:eint10 e11 krow7 io keypad row 7 gpio73 krow7 o:clkm6 ceva_gpio16 c9 krow6 io keypad row 6 gpio74 krow6 o:clkm7 ceva_gpio17 d10 krow5 io keypad row 5 gpio23 krow5 o:dsp2_gpo1 e9 krow4 io keypad row 4 gpio114 krow4 a7 krow3 io keypad row 3 gpio113 krow3 b6 krow2 io keypad row 2 gpio112 krow2 d8 krow1 io keypad row 1 gpio111 krow1 f10 krow0 io keypad row 0 gpio110 krow0 k38 pwr_key io dedicated key for power detection jtag port ad34 jtrst_b i jtag test port reset input gpio48 i:jtrst_b o:clkm6 ad38 jtck i jtag test port clock input gpio49 i:jtck o:clkm7 ab36 jtdi i jtag test port data input gpio50 i:jtdi ac33 jtms i jtag test port mode switch gpio51 i:jtms ac35 jtdo io jtag test port data output gpio52 jtdo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 13 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 ab34 jrtck io jtag test port returned clock output gpio53 jrtck am32 j2trst_b i jtag test port reset input gpio100 i:j2trst_b o:tracedata8 ak30 j2tck i jtag test port clock input gpio101 i:j2tck o:tracedata9 an33 j2tdi i jtag test port data input gpio102 i:j2tdi o:tracedata10 ap34 j2tms i jtag test port mode switch gpio103 i:j2tms o:tracedata11 ar35 j2tdo io jtag test port data output gpio104 j2tdo o:tracedata12 al31 j2rtck io jtag test port returned clock output gpio105 j2rtck o:tracedata13 miscellaneous j37 sysrst_b i system reset input active low an21 watchdog io watchdog reset output n33 srclkena io external tcxo enable output active high gpio56 o:srclkena i:eint18 p38 srclkenan io external tcxo enable output active low gpio57 o:srclkenan i:eint19 aj35 srclkenai io external tcxo enable input gpio58 o:srclkenai i:eint20 v38 iboot i boot device configuration input at24 eadmux io nor/psram a/d mux bus selection gpio1 i:eadmux o:clkm1 i:eint15 v36 nc i no connection u37 secu_en i security configuration input u35 hdq io hdq gpio107 hdq f38 i2s_ws io i2s_ws gpio25 i2s_ws i:d1ick o:usb_probe_out[7] h36 i2s_dat io i2s data gpio27 i2s_dat i:d1ims o:usb_probe_out[5] g37 i2s_clk io i2s clock gpio26 i2s_clk d1id o:usb_probe_out[6] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 14 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 u33 icoresight i coresight configuration input t38 ionejtag i serial jtag enable d14 usb_drvvbus io usb otg host mode 5v charge pump enable gpio32 usb_drvvbus external interrupt m36 eint0 io external interrupt 0 gpio59 i:eint0 ceva_gpio18 an37 eint1 io external interrupt 1 gpio60 i:eint1 ceva_gpio19 af32 eint2 io external interrupt 2 gpio61 i:eint2 ceva_gpio20 ak36 eint3 io external interrupt 3 gpio62 i:eint3 ceva_gpio21 ag35 eint4 io external interrupt 4 gpio63 i:eint4 ceva_gpio22 ap38 eint5 io external interrupt 5 gpio64 i:eint5 ceva_gpio23 n35 eint6 io external interrupt 6 gpio65 i:eint6 ceva_gpio24 k36 eint7 io external interrupt 7 gpio66 i:eint7 ceva_gpio25 p32 eint8 io external interrupt 8 gpio21 i:eint8 o:dsp_gpo1 o:tbrxen l35 eint9 io external interrupt 9 gpio22 i:eint9 o:dsp_gpo0 o:tbrxfs av36 mfiq io interrupt to mcu spi interface a5 spi_cs_n io spi chip select gpio80 o:spi_cs_n i:irda_rxd o:bsi_cs1 c5 spi_sck io spi serial clock gpio81 o:spi_sck o:irda_txd d6 spi_mosi io spi master output (slave input) gpio82 o:spi_mosi o:irda_pdn mc2da2 e7 spi_miso io spi master input (slave output gpio83 i:spi_miso i:mirq mc2da3 digital audio interface ar37 daiclk io dai clock output gpio75 o:daiclk ceva_gpio26 aj33 daipcmout io dai pcm data out gpio76 o:daipcmout ceva_gpio27 ap36 daipcmin io dai pcm data input gpio77 i:daipcmin ceva_gpio28 at38 dairst io dai reset signal input gpio78 i:dairst o:clkm5 ceva_gpio29 ah32 daisync io dai frame synchronization gpio79 o:daisync ceva_gpio30 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 15 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 signal output rf parallel control unit l33 bpi_bus0 io rf hard-wire control bus 0 h34 bpi_bus1 io rf hard-wire control bus 1 g35 bpi_bus2 io rf hard-wire control bus 2 c37 bpi_bus3 io rf hard-wire control bus 3 k34 bpi_bus4 io rf hard-wire control bus 4 d36 bpi_bus5 io rf hard-wire control bus 5 k32 bpi_bus6 io rf hard-wire control bus 6 md_gpi o0 o:bpi_bus6 e35 bpi_bus7 io rf hard-wire control bus 7 md_gpi o1 o:bpi_bus7 j33 bpi_bus8 io rf hard-wire control bus 8 md_gpi o2 o:bpi_bus8 f34 bpi_bus9 io rf hard-wire control bus 9 md_gpi o3 o:bpi_bus9 rf serial control unit h32 bsi_cs0 io rf 3-wire interface chip select 0 g33 bsi_data io rf 3-wire interface data output j31 bsi_clk io rf 3-wire interface clock output analog interface a3 pad_tdp1 aio mipi dsi data lane 1 + gpio4 i2s_dat b4 pad_tdn1 aio mipi dsi data lane 1 - gpio5 c1 pad_tdp0 aio mipi dsi data lane 0 + gpio2 i2s_ws d2 pad_tdn0 aio mipi dsi data lane 0 - gpio3 i2s_clk b2 pad_tcp aio mipi dsi clock lane + gpio6 c3 pad_tcn aio mipi dsi clock lane - gpio7 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 16 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 h2 pad_rdp1 aio mipi dsi data lane 1 + gpio10 g1 pad_rdn1 aio mipi dsi data lane 1 - gpio11 e3 pad_rdp0 aio mipi dsi data lane 0 + gpio8 clkm2 e1 pad_rdn0 aio mipi dsi data lane 0 - gpio9 clkm3 g3 pad_rcp aio mipi csi clock lane + gpio12 f2 pad_rcn aio mipi csi clock lane - gpio106 e21 pad_fsres aio pad_fsres g5 pad_tvrt aio pad_tvrt a35 pad_au_moutr aio audio analog output right channel b34 pad_au_moutl aio audio analog output left channel c33 pad_au_fminr aio fm radio analog input right channel d34 pad_au_fminl aio fm radio analog input left channel a33 pad_au_out0_p aio earphone 0 amplifier output (+) b32 pad_au_out0_n aio earphone 0 amplifier output (-) h28 pad_au_micbias_p aio microphone bias supply (+) a31 pad_au_vcm_po aio audio output reference voltage (+) a29 pad_au_vcm_no aio audio output reference voltage (-) d28 pad_au_vin0_p aio microphone 0 amplifier input (+) c29 pad_au_vin0_n aio microphone 0 amplifier input (-) d26 pad_au_vin1_p aio microphone 1 amplifier input (+) c27 pad_au_vin1_n aio microphone 1 amplifier input (-) e25 pad_bdlaqp aio quadrature input (q+) baseband codec downlink free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 17 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 c25 pad_bdlaqn aio quadrature input (q-) baseband codec downlink a27 pad_bdlaip aio in-phase input (i+) baseband codec downlink b26 pad_bdlain aio in-phase input (i-) baseband codec downlink d24 pad_apc aio automatic power control dac output a21 aux_in0_vbout aio auxiliary adc input 0 j21 pad_aux_in1 aio auxiliary adc input 1 d20 pad_aux_in2 aio auxiliary adc input 2 g21 aux_in3_isense aio auxiliary adc input 3 c21 pad_aux_in4 aio auxiliary adc input 4 h22 aux_in5_chrin aio auxiliary adc input 5 b22 pad_aux_in6 aio auxiliary adc input 6 f22 pad_aux_in7 aio auxiliary adc input 7 f18 pad_aux_in8 aio auxiliary adc input 8 e23 pad_aux_xp aio touch panel x plus(+) input d22 pad_aux_yp aio touch panel y plus(+) input c23 pad_aux_xm aio touch panel x minus(-) input b24 pad_aux_ym aio touch panel y minus(-) input f24 pad_afc aio automatic frequency control dac output c19 pad_tvout ao tv dac current output d18 pad_sysclk ai clksq input pad j15 pad_usb_vbus aio usb 5v power from usb host a15 pad_usb_id aio usb id pin for otg free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 18 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 device a13 pad_usb_dm aio usb d- input/output b14 pad_usb_dp aio usb d+ input/output h16 pad_usb_vrt aio for usb phy bandgap reference image sensor interface aj7 cmrst io image sensor reset signal output gpio17 o:cmrst o:dsp2_gpo3 o:d1_tid0 am4 cmpdn io image sensor power down control gpio18 o:cmpdn o:dsp2_gpo2 o:d1_tid1 ah8 cmvref io sensor vertical reference signal input gpio19 i:cmvref o:dsp_gpo3 o:tbtxen at2 cmhref io sensor horizontal reference signal input gpio20 i:cmhref o:dsp_gpo2 o:tbtxfs ag9 cmpclk io image sensor pixel clock input ar3 cmmclk io image sensor master clock output al7 cmdat9 io image sensor data input 9 ap4 cmdat8 io image sensor data input 8 ak8 cmdat7 io image sensor data input 7 an5 cmdat6 io image sensor data input 6 an7 cmdat5 io image sensor data input 5 au3 cmdat4 io image sensor data input 4 am8 cmdat3 io image sensor data input 3 at4 cmdat2 io image sensor data input 2 al9 cmdat1 io image sensor data input 1 av2 cmdat0 io image sensor data input 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 19 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 an9 cmflash io camera flash light control gpio33 o:cmflash o:d2_tid2 r33 scl0 io i2c clock i2c controller 2 (i2c2 scl) ag5 scl1 io i2c clock gpio34 i2c controller 1 (i2c scl) o:d2_tid3 ae31 scl2 io i2c clock gpio135 i2c controller 3 (i2c3 scl) l37 sda0 io i2c data i2c controller 2 (i2c2 sda) ap2 sda1 io i2c data gpio35 i2c controller 1 (i2c sda) o:d2_tid4 al37 sda2 io i2c data gpio136 i2c controller 3 (i2c3 sda) pwm interface ah36 pwm0 io pulse width modulated signal 0 gpio54 o:pwm0 i:eint16 am38 pwm1 io pulse width modulated signal 1 gpio55 o:pwm1 i:bsi_rfin i:eint17 ar1 pwm2 io pulse width modulated signal 2 gpio36 o:pwm2 o:d2_tid5 ag7 pwm3 io pulse width modulated signal 3 gpio37 o:pwm3 o:d2_tid6 ceva_gpio31 ak4 pwm4 io pulse width modulated signal 4 gpio0 o:pwm4 o:clkm0 ah6 pwm5 io pulse width modulated signal 5 gpio99 o:pwm5 aj37 pwm6 io pulse width modulated signal 6 gpio24 o:pwm6 o:dsp2_gpo0 serial lcd/pm ic interface u5 lsck io serial display interface data output gpio42 o:lsck o:tdma_ck u3 lsa0 io serial display interface address output gpio43 o:lsa0 o:tdma_d1 o:tdtirq u1 lsda io serial display interface clock output gpio44 lsda o:tdma_d0 o:tctirq2 v4 lsce0b io serial display interface chip select 0 output gpio45 o:lsce0b o:tdma_fs o:tctirq1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 20 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 v6 lsce1b io serial display interface chip select 1 output gpio46 o:lsce1b o:lpce2b o:tevtval free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 21 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 parallel lcd/nand-flash interface v2 lpce1b io parallel display interface chip select 1 output gpio47 o:lpce1b o:d2_tid1 o:usb_probe_out[0] w1 lpce0b io parallel display interface chip select 0 output w3 lpte io w7 lrstb io parallel display interface reset signal y2 lrdb io parallel display interface read strobe y4 lpa0 io parallel display interface address output aa1 lwrb io parallel display interface write strobe y6 nld25 io parallel lcd/nand-flash data 25 ab4 nld24 io parallel lcd/nand-flash data 24 ae1 nld23 io parallel lcd/nand-flash data 23 ad2 nld22 io parallel lcd/nand-flash data 22 aa7 nld21 io parallel lcd/nand-flash data 21 ac3 nld20 io parallel lcd/nand-flash data 20 y8 nld19 io parallel lcd/nand-flash data 19 ag1 nld18 io parallel lcd/nand-flash data 18 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 22 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 aa5 nld17 io parallel lcd/nand-flash data 17 af2 nld16 io parallel lcd/nand-flash data 16 ab6 nld15 io parallel lcd/nand-flash data 15 ae3 nld14 io parallel lcd/nand-flash data 14 ab8 nld13 io parallel lcd/nand-flash data 13 ad4 nld12 io parallel lcd/nand-flash data 12 ac7 nld11 io parallel lcd/nand-flash data 11 aj1 nld10 io parallel lcd/nand-flash data 10 ah2 nld9 io parallel lcd/nand-flash data 9 al1 nld8 io parallel lcd/nand-flash data 8 ag3 nld7 io parallel lcd/nand-flash data 7 af4 nld6 io parallel lcd/nand-flash data 6 ac5 nld5 io parallel lcd/nand-flash data 5 ak2 nld4 io parallel lcd/nand-flash data 4 ad6 nld3 io parallel lcd/nand-flash data 3 aj3 nld2 io parallel lcd/nand-flash data 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 23 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 ad8 nld1 io parallel lcd/nand-flash data 1 an1 nld0 io parallel lcd/nand-flash data 0 ae7 nrnb io nand-flash read/busy flag ah4 ncle io nand-flash command latch signal ae5 nale io nand-flash address latch signal am2 nweb io nand-flash write strobe af6 nreb io nand-flash read strobe aj5 nce0b io nand-flash chip select output al3 nce1b io nand-flash chip select output dpi interface w5 dpihsync io dpi horizontal sync signal aa3 dpivsync io dpi vertical sync signal ab2 dpide io dpi data enable signal ac1 dpick io dpi clock memory card interface l1 mc0cm0 io sd command/ms bus state output t8 mc0da0 io sd serial data io 0/ms serial data io n1 mc0da1 io sd serial data io 1 r3 mc0da2 io sd serial data io 2 p2 mc0da3 io sd serial data io 3 u7 mc0ck io sd serial clock/ms serial clock output t4 mc0pwron io sd power on control output r1 mc0wp io sd write protect free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 24 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 input t2 mc0ins io sd card detect input l3 mc1cm0 io sd command/ms bus state output j3 mc1da0 io sd serial data io 0/ms serial data io p6 mc1da1 io sd serial data io 1 k2 mc1da2 io sd serial data io 0/ms serial data io p4 mc1da3 io sd serial data io 1 j1 mc1ck io sd serial clock/ms serial clock output r5 mc1pwron io sd power on control output n3 mc1wp io sd write protect input m2 mc1ins io sd card detect input k6 mc2cm0 io sd command/ms bus state output gpio40 mc2cm mc0da6 l7 mc2da0 io sd serial data io 0/ms serial data io l5 mc2da1 io sd serial data io 1 k4 mc2ck io sd serial clock/ms serial clock output m6 mc2pwron io sd power on control output gpio39 o:mc2pwron mc0da5 n5 mc2wp io sd write protect input gpio38 i:mc2wp mc0da4 m4 mc2ins io sd card detect input gpio41 i:mc2ins mc0da7 trace32 interface ap30 traceclk io trace32 clock gpio137 o:traceclk ar31 tracectl io trace32 control signal gpio138 o:tracectl au35 tracedata0 io trace32 data bus 0 gpio139 o:tracedata0 am28 tracedata1 io trace32 data bus 1 gpio140 o:tracedata1 at34 tracedata2 io trace32 data bus gpio141 o:tracedata2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 25 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 2 an29 tracedata3 io trace32 data bus 3 gpio142 o:tracedata3 ar33 tracedata4 io trace32 data bus 4 gpio143 o:tracedata4 al29 tracedata5 io trace32 data bus 5 gpio144 o:tracedata5 ap32 tracedata6 io trace32 data bus 6 gpio145 o:tracedata6 am30 tracedata7 io trace32 data bus 7 gpio146 o:tracedata7 rtc interface ab38 xin ao 32.768 khz crystal input ac37 xout ai 32.768 khz crystal output aa35 bbwakeup aio baseband power on/off control aa33 testmode ai testmode enable input external memory interface 1 ap20 ea26 io external memory address bus 26 au19 ea25 io external memory address bus 25 av18 ea24 io external memory address bus 24 ar19 ea23 io external memory address bus 23 am20 ea22 io external memory address bus 22 av22 ea21 io external memory address bus 21 ar21 ea20 io external memory address bus 20 an19 ea19 io external memory address bus 19 av20 ea18 io external memory address bus 18 at20 ea17 io external memory address bus 17 au21 ea16 io external memory address bus 16 am16 ea15 io external memory address bus 15 au13 ea14 io external memory address bus 14 at22 ea13 io external memory free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 26 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 address bus 13 au15 ea12 io external memory address bus 12 at14 ea11 io external memory address bus 11 ap14 ea10 io external memory address bus 10 ar13 ea9 io external memory address bus 9 av14 ea8 io external memory address bus 8 av12 ea7 io external memory address bus 7 al13 ea6 io external memory address bus 6 an13 ea5 io external memory address bus 5 ap12 ea4 io external memory address bus 4 am14 ea3 io external memory address bus 3 at12 ea2 io external memory address bus 2 au11 ea1 io external memory address bus 1 an15 ea0 io external memory address bus 0 au25 ewait io external memory wait signal at10 edqs3 io external memory strobe signal 3 av6 edqs2 io external memory strobe signal 2 av28 edqs1 io external memory strobe signal 1 av32 edqs0 io external memory strobe signal 0 av10 edqm3 io external memory mask signal 3 au7 edqm2 io external memory mask signal 2 au27 edqm1 io external memory mask signal 1 au31 edqm0 io external memory mask signal 0 au17 eras_b io external memory row address select signal an17 ecas_b io external memory free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 27 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 column address select signal av26 eadv_b io flash, psram and cellularram address valid at18 ec_clk io flash, psram and cellularram clock ar17 ed_clk io mobileram clock ap18 ed_clk_b io mobileram clock at16 ecke io mobileram clock enable av16 ewr_b io external memory write strobe ap22 erd_b io external memory read strobe ap16 ecs0_b io external memory chip select 0 al17 ecs1_b io external memory chip select 1 av24 ecs2_b io external memory chip select 2 au23 ecs3_b io external memory chip select 3 ap10 ed31 io external memory data bus 31 an11 ed30 io external memory data bus 30 ar9 ed29 io external memory data bus 29 am12 ed28 io external memory data bus 28 at8 ed27 io external memory data bus 27 au9 ed26 io external memory data bus 26 av8 ed25 io external memory data bus 25 ar11 ed24 io external memory data bus 24 ap6 ed23 io external memory data bus 23 at6 ed22 io external memory data bus 22 au5 ed21 io external memory data bus 21 ar7 ed20 io external memory data bus 20 ap8 ed19 io external memory free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 28 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 data bus 19 am10 ed18 io external memory data bus 18 av4 ed17 io external memory data bus 17 al11 ed16 io external memory data bus 16 am22 ed15 io external memory data bus 15 an23 ed14 io external memory data bus 14 at26 ed13 io external memory data bus 13 ar25 ed12 io external memory data bus 12 ap24 ed11 io external memory data bus 11 av30 ed10 io external memory data bus 10 au29 ed9 io external memory data bus 9 at28 ed8 io external memory data bus 8 ar27 ed7 io external memory data bus 7 at30 ed6 io external memory data bus 6 ar29 ed5 io external memory data bus 5 av34 ed4 io external memory data bus 4 ap28 ed3 io external memory data bus 3 au33 ed2 io external memory data bus 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 29 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 at32 ed1 io external memory data bus 1 an27 ed0 io external memory data bus 0 ceva interface y38 ceva_tck io jtag protocol tck gpio13 i:ceva_tck w37 ceva_tms io jtag protocol tms gpio14 i:ceva_tms v34 ceva_tdi io jtag protocol tdi gpio15 i:ceva_tdi w35 ceva_tdo io jtag protocol tdo gpio16 ceva_tdo v32 ceva_rtck io jtag protocol rtck gpio98 ceva_rtck am34 btdmp_din1 io btdmp transmit channel - serial data in gpio92 i:btdmp_din1 ceva_gpio8 al33 btdmp_fsp1 io btdmp transmit channel - frame synchronization pulse gpio93 btdmp_fsp1 ceva_gpio9 phy_clk at36 btdmp_clk1 io btdmp transmit channel - clock gpio94 btdmp_clk1 ceva_gpio10 line_state0 ak32 btdmp_dout2 io btdmp receive channel - serial data out gpio95 o:btdmp_dou2 ceva_gpio11 line_state1 an35 btdmp_fsp2 io btdmp receive channel - frame synchronization pulse gpio96 btdmp_fsp2 ceva_gpio12 o:tracedata14 ak34 btdmp_clk2 io btdmp receive channel - clock gpio97 btdmp_clk2 ceva_gpio13 o:tracedata15 an3 cam_strobe io camera strobe gpio29 cam_strobe d2id o:usb_probe_out[3] au1 cam_mechsh1 io camera mechsh1 gpio31 o:cam_mechsh1 o:d2_tid0 o:usb_probe_out[1] ak6 cam_mechsh0 io camera mechsh0 gpio30 o:cam_mechsh0 i:d2ims o:usb_probe_out[2] supply voltages h8 dvdd28_mipitx supply voltage of mipi tx j9 dvdd28_mipitx supply voltage of mipi tx j5 dvdd28_mipirx supply voltage of mipi rx j7 dvdd12_mipi supply voltage of mipi k8 dvdd12_mipi supply voltage of mipi h10 dvss28_mipitx gnd for mipi tx free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 30 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 j11 dvss28_mipitx gnd for mipi tx r9 dvss28_mipirx gnd for mipi rx m8 dvss12_mipi gnd for mipi n9 dvss12_mipi gnd for mipi aa15 vddk supply voltage of internal logic aa23 vddk supply voltage of internal logic ab14 vddk supply voltage of internal logic ab24 vddk supply voltage of internal logic ac13 vddk supply voltage of internal logic ac25 vddk supply voltage of internal logic ad12 vddk supply voltage of internal logic ad14 vddk supply voltage of internal logic ad16 vddk supply voltage of internal logic ad18 vddk supply voltage of internal logic ad20 vddk supply voltage of internal logic ad22 vddk supply voltage of internal logic ad24 vddk supply voltage of internal logic ad26 vddk supply voltage of internal logic ae15 vddk supply voltage of internal logic ae21 vddk supply voltage of internal logic ae23 vddk supply voltage of internal logic ae27 vddk supply voltage of internal logic af14 vddk supply voltage of internal logic free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 31 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 af18 vddk supply voltage of internal logic af24 vddk supply voltage of internal logic af28 vddk supply voltage of internal logic ag13 vddk supply voltage of internal logic ag17 vddk supply voltage of internal logic ag21 vddk supply voltage of internal logic ag25 vddk supply voltage of internal logic aj17 vddk supply voltage of internal logic aj21 vddk supply voltage of internal logic aj25 vddk supply voltage of internal logic l13 vddk supply voltage of internal logic m14 vddk supply voltage of internal logic n15 vddk supply voltage of internal logic p16 vddk supply voltage of internal logic p22 vddk supply voltage of internal logic p30 vddk supply voltage of internal logic r15 vddk supply voltage of internal logic r17 vddk supply voltage of internal logic r21 vddk supply voltage of internal logic r23 vddk supply voltage of internal logic r25 vddk supply voltage of internal logic r27 vddk supply voltage of internal logic t14 vddk supply voltage of internal logic free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 32 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 t18 vddk supply voltage of internal logic t20 vddk supply voltage of internal logic t24 vddk supply voltage of internal logic u15 vddk supply voltage of internal logic u23 vddk supply voltage of internal logic v8 vddk supply voltage of internal logic w13 vddk supply voltage of internal logic w15 vddk supply voltage of internal logic w23 vddk supply voltage of internal logic y12 vddk supply voltage of internal logic aa17 vss33 ground of internal logic aa19 vss33 ground of internal logic aa21 vss33 ground of internal logic aa27 vss33 ground of internal logic ab12 vss33 ground of internal logic ab16 vss33 ground of internal logic ab18 vss33 ground of internal logic ab20 vss33 ground of internal logic ab22 vss33 ground of internal logic ac15 vss33 ground of internal logic ac17 vss33 ground of internal logic ac19 vss33 ground of internal logic ac21 vss33 ground of internal logic free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 33 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 ac23 vss33 ground of internal logic ac27 vss33 ground of internal logic ae17 vss33 ground of internal logic ae19 vss33 ground of internal logic af12 vss33 ground of internal logic ag15 vss33 ground of internal logic ag19 vss33 ground of internal logic ag23 vss33 ground of internal logic ag27 vss33 ground of internal logic ah14 vss33 ground of internal logic ah20 vss33 ground of internal logic ah24 vss33 ground of internal logic ak14 vss33 ground of internal logic ak20 vss33 ground of internal logic ak24 vss33 ground of internal logic ak26 vss33 ground of internal logic al15 vss33 ground of internal logic al19 vss33 ground of internal logic al25 vss33 ground of internal logic m12 vss33 ground of internal logic m16 vss33 ground of internal logic m18 vss33 ground of internal logic m20 vss33 ground of internal logic free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 34 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 m22 vss33 ground of internal logic m24 vss33 ground of internal logic m26 vss33 ground of internal logic n27 vss33 ground of internal logic p12 vss33 ground of internal logic p18 vss33 ground of internal logic p20 vss33 ground of internal logic r19 vss33 ground of internal logic t16 vss33 ground of internal logic t22 vss33 ground of internal logic u17 vss33 ground of internal logic u19 vss33 ground of internal logic u21 vss33 ground of internal logic u27 vss33 ground of internal logic v14 vss33 ground of internal logic v16 vss33 ground of internal logic v18 vss33 ground of internal logic v20 vss33 ground of internal logic v22 vss33 ground of internal logic v24 vss33 ground of internal logic w17 vss33 ground of internal logic w19 vss33 ground of internal logic w21 vss33 ground of internal logic free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 35 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 w27 vss33 ground of internal logic y14 vss33 ground of internal logic y16 vss33 ground of internal logic y18 vss33 ground of internal logic y20 vss33 ground of internal logic y22 vss33 ground of internal logic y24 vss33 ground of internal logic ak28 vdd33_trace supply voltage of trace al27 vdd33_trace supply voltage of trace ak10 vdd33_camera supply voltage of camera aj9 vdd33_camera supply voltage of camera g11 vdd33_spi supply voltage of spi aa9 vdd33_nld supply voltage of nld ac9 vdd33_nld supply voltage of nld w9 vdd33_nld supply voltage of nld l11 vdd33_mipi supply voltage of mipi n7 vdd33_mc2 supply voltage of memory card interface drivers u9 vdd33_mc1 supply voltage of memory card interface drivers t6 vdd33_mc0 supply voltage of memory card interface drivers af8 vdd33_i2c supply voltage of i2c ak12 vdd33_emi supply voltage of memory interface drivers free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 36 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 ak16 vdd33_emi supply voltage of memory interface drivers ak18 vdd33_emi supply voltage of memory interface drivers ak22 vdd33_emi supply voltage of memory interface drivers al21 vdd33_emi supply voltage of memory interface drivers al23 vdd33_emi supply voltage of memory interface drivers af30 vdd33 3.3v supply voltage ag31 vdd33 3.3v supply voltage ah30 vdd33 3.3v supply voltage k14 vdd33 3.3v supply voltage k28 vdd33 3.3v supply voltage m30 vdd33 3.3v supply voltage n31 vdd33 3.3v supply voltage t30 vdd33 3.3v supply voltage u31 vdd33 3.3v supply voltage ar23 fsource analog supply ab30 avdd_rtc supply voltage for real time clock b18 avdd12_pll supply voltage for pll d16 avdd12_usb supply voltage usb b30 avdd28_afe supply voltage for voice band receive section a37 avdd28_mbuf supply voltage for audio band section g7 avdd28_mipitx supply voltage for mipitx e19 avdd28_pll supply voltage for pll j25 avdd28_rfe gnd for baseband receive section, apc, afc and auxadc h20 avdd28_tvdac tv dac vdd aa37 avdd30_vsim2 supply voltage for sim2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 37 of 1535 ball 38x38 name dir description mode0 mode1 mode2 mode3 w33 avdd30_vsim1 supply voltage for sim1 f16 avdd33_usb supply voltage usb a19 avss12_pll gnd for pll j17 avss12_usb gnd for usb b36 avss28_mbuf gnd for voice band transmit section b28 avss28_afe gnd for voice band receive section l9 avss28_mipitx gnd for mipitx f20 avss28_pll gnd for pll h24 avss28_rfe supply voltage for baseband receive section, apc, afc and auxadc b20 avss28_tvdac tv dac vss w31 avss30_vsim1 gnd for vsim1 ab32 avss30_vsim2 gnd for vsim2 g15 avss33_usb gnd for usb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 38 of 1535 1.5 power description table 3 power descriptions ball 38x3 8 name io supply io gnd core supply core gnd remark avdd28_mbuf avdd28_mbuf b34 pad_au_moutl a35 pad_au_moutr avdd28_afe avss28_afe avdd28_afe avss28_afe avss28_mbuf avss28_mbuf c33 pad_au_fminr d34 pad_au_fminl a33 pad_au_out0_p b32 pad_au_out0_n h28 pad_au_micbias_p avdd28_afe avss28_afe avdd28_afe avss28_afe av dd28_ afe av dd28_ afe av dd28_ afe avss28_afe a31 pad_au_vcm_po a29 pad_au_vcm_no d28 pad_au_vin0_p c29 pad_au_vin0_n d26 pad_au_vin1_p c27 pad_au_vin1_n avdd28_afe avss28_afe avdd28_afe avss28_afe avss28_afe avss28_afe a27 pad_bdlaip b26 pad_bdlain e25 pad_bdlaqp c25 pad_bdlaqn avdd28_rfe avss28_rfe avdd28_rfe avss28_rfe av dd28_rfe av dd28_rfe avss28_rfe avss28_rfe avss28_rfe d24 pad_apc f24 pad_afc e23 pad_aux_xp d22 pad_aux_yp c23 pad_aux_xm b24 pad_aux_ym f18 pad_aux_in8 f22 pad_aux_in7 b22 pad_aux_in6 avdd28_rfe avss28_rfe avdd28_rfe avss28_rfe free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 39 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark h22 aux_in5_chrin c21 pad_aux_in4 g21 aux_in3_isense d20 pad_aux_in2 j21 pad_aux_in1 a21 aux_in0_vbout avss28_tvdac c19 pad_tvout e21 pad_fsres avdd28_tvdac avss28_tvdac avdd28_tvdac avss28_tvda c avss28_tvdac avss28_pll d18 pad_sysclk avdd28_pll avss28_pll avdd28_pll avss28_pll av dd28_pll av dd12_pll avss12_pll av dd12_pll avss12_pll av dd12_pll avss12_pll av dd12_pll vss33 avss12_usb av dd12_usb avss12_usb av dd12_usb a15 pad_usb_id avdd33_usb avss33_usb vddk vss33 vss33 av dd33_usb h16 pad_usb_vrt avdd33_usb avss33_usb vddk vss33 av dd33_usb avss33_usb av dd33_usb avss33_usb b14 pad_usb_dp avdd33_usb avss33_usb vddk vss33 avss33_usb a13 pad_usb_dm j15 pad_usb_vbus avdd33_usb avss33_usb vddk vss33 vss33 vss33 vddk vss33 vddk vss33 d14 usb_drvvbus c13 kcol7 vdd33 vss33 vddk vss33 vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 40 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark b12 kcol6 a11 kcol5 vdd33 vss33 vddk vss33 vss33 d12 kcol4 c11 kcol3 vdd33 vss33 vddk vss33 vss33 b10 kcol2 a9 kcol1 vdd33 vss33 vddk vss33 vss33 b8 kcol0 vdd33 vss33 vddk vss33 vdd33 vss33 e11 krow7 vdd33 vss33 vddk vss33 vss33 c9 krow6 d10 krow5 vdd33 vss33 vddk vss33 vss33 e9 krow4 a7 krow3 vdd33 vss33 vddk vss33 vss33 b6 krow2 d8 krow1 vdd33 vss33 vddk vss33 vss33 f10 krow0 a5 spi_cs_n vdd33 vss33 vddk vss33 vss33 c5 spi_sck vdd33 vss33 vddk vss33 vdd33_spi vss33 d6 spi_mosi vdd33 vss33 vddk vss33 vss33 e7 spi_miso vdd33 vss33 vddk vss33 vdd33_mipi vss33 dvdd28_mipitx dvss28_mipitx a3 pad_tdp1 b4 pad_tdn1 c1 pad_tdp0 d2 pad_tdn0 b2 pad_tcp c3 pad_tcn vdd33_mipi vss33 vddk vss33 dvdd28_mipitx dvss28_mipitx dvdd28_mipitx dvss28_mipitx free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 41 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark avdd28_mipitx avss28_mipitx g5 pad_tvrt vdd33_mipi vss33 vddk vss33 dvss28_mipitx dvdd28_mipitx dvss28_mipitx dvdd28_mipitx h2 pad_rdp1 g1 pad_rdn1 e3 pad_rdp0 e1 pad_rdn0 g3 pad_rcp f2 pad_rcn vdd33_mipi vss33 vddk vss33 dvss28_mipitx dvdd28_mipitx vss33 vdd33_mipi vss33 vddk vss33 vddk vss33 k6 mc2cm0 l7 mc2da0 vdd33_mc2 dvss vddk dvss vss33 l5 mc2da1 vdd33_mc2 dvss vddk dvss vdd33_mc2 vss33 k4 mc2ck vdd33_mc2 dvss vddk dvss vss33 m6 mc2pwron n5 mc2wp vdd33_mc2 dvss vddk dvss vss33 m4 mc2ins vdd33_mc2 dvss vddk dvss l3 mc1cm0 vdd33_mc1 dvss vddk dvss vss33_mc1 j3 mc1da0 p6 mc1da1 vdd33_mc1 dvss vddk dvss vss33_mc1 k2 mc1da2 vdd33_mc1 dvss vddk dvss vdd33_mc1 vss33 p4 mc1da3 vdd33_mc1 dvss vddk dvss vss33 j1 mc1ck r5 mc1pwron vdd33_mc1 dvss vddk dvss free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 42 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vss33 n3 mc1wp m2 mc1ins vdd33_mc1 dvss vddk dvss vss33 l1 mc0cm0 t8 mc0da0 vdd33_mc0 dvss vddk dvss vss33 n1 mc0da1 r3 mc0da2 vdd33_mc0 dvss vddk dvss vss33 vdd33_mc0 vss33 vss33 p2 mc0da3 u7 mc0ck vdd33_mc0 dvss vddk dvss vss33 t4 mc0pwron r1 mc0wp vdd33_mc0 dvss vddk dvss vss33 t2 mc0ins vdd33_mc0 dvss vddk dvss vddk vss33 vddk vss33 u5 lsck vdd33 vss33 vddk vss33 vss33 u3 lsa0 u1 lsda vdd33 vss33 vddk vss33 vss33 v4 lsce0b v6 lsce1b vdd33 vss33 vddk vss33 vss33 vdd33_nld vss33 vss33 w1 lpce0b v2 lpce1b vdd33 vss33 vddk vss33 vss33 w3 lpte w7 lrstb vdd33 vss33 vddk vss33 vss33 y2 lrdb y4 lpa0 vdd33 vss33 vddk vss33 vss33 aa1 lwrb w5 dpihsync vdd33 vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 43 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vss33 aa3 dpivsync vdd33 vss33 vddk vss33 vdd33_nld vss33 ab2 dpide vdd33 vss33 vddk vss33 vss33 ac1 dpick vdd33 vss33 vddk vss33 y6 nld25 vdd33_nld vss33 vddk vss33 vss33 ab4 nld24 vdd33_nld vss33 vddk vss33 ae1 nld23 vdd33_nld vss33 vddk vss33 vss33 ad2 nld22 vdd33_nld vss33 vddk vss33 aa7 nld21 vdd33_nld vss33 vddk vss33 vss33 ac3 nld20 vdd33_nld vss33 vddk vss33 y8 nld19 vdd33_nld vss33 vddk vss33 vss33 vdd33_nld vss33 vddk vss33 vddk vss33 ag1 nld18 vdd33_nld vss33 vddk vss33 aa5 nld17 vdd33_nld vss33 vddk vss33 vss33 af2 nld16 vdd33_nld vss33 vddk vss33 ab6 nld15 vdd33_nld vss33 vddk vss33 vss33 ae3 nld14 vdd33_nld vss33 vddk vss33 ab8 nld13 vdd33_nld vss33 vddk vss33 vss33 ad4 nld12 vdd33_nld vss33 vddk vss33 ac7 nld11 vdd33_nld vss33 vddk vss33 vss33 aj1 nld10 vdd33_nld vss33 vddk vss33 ah2 nld9 vdd33_nld vss33 vddk vss33 vss33 vdd33_nld vss33 al1 nld8 vdd33_nld vss33 vddk vss33 ag3 nld7 vdd33_nld vss33 vddk vss33 vss33 af4 nld6 vdd33_nld vss33 vddk vss33 ac5 nld5 vdd33_nld vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 44 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vss33 ak2 nld4 vdd33_nld vss33 vddk vss33 ad6 nld3 vdd33_nld vss33 vddk vss33 vss33 aj3 nld2 vdd33_nld vss33 vddk vss33 ad8 nld1 vdd33_nld vss33 vddk vss33 vss33 an1 nld0 vdd33_nld vss33 vddk vss33 ae7 nrnb vdd33_nld vss33 vddk vss33 vss33 vdd33_nld vss33 ah4 ncle vdd33_nld vss33 vddk vss33 ae5 nale vdd33_nld vss33 vddk vss33 vss33 am2 nweb vdd33_nld vss33 vddk vss33 af6 nreb vdd33_nld vss33 vddk vss33 vss33 al3 nce1b vdd33_nld vss33 vddk vss33 aj5 nce0b vdd33_nld vss33 vddk vss33 vss33 vddk vss33 vddk vss33 ap2 sda1 vdd33_i2c vss33 vddk vss33 vdd33_i2c vss33 ag5 scl1 vdd33_i2c vss33 vddk vss33 vss33 ar1 pwm2 vdd33_camer a vss33 vddk vss33 ag7 pwm3 vdd33_camer a vss33 vddk vss33 vss33 ak4 pwm4 vdd33_camer a vss33 vddk vss33 ah6 pwm5 vdd33_camer a vss33 vddk vss33 vss33 vdd33_camera vss33 an3 cam_strobe ak6 cam_mechsh0 vdd33_camer a vss33 vddk vss33 vss33 au1 cam_mechsh1 vdd33_camer vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 45 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark aj7 cmrst a vss33 am4 cmpdn ah8 cmvref vdd33_camer a vss33 vddk vss33 vss33 at2 cmhref ag9 cmpclk vdd33_camer a vss33 vddk vss33 vss33 vdd33_camera vdd33_camera vss33 ar3 cmmclk al7 cmdat9 vdd33_camer a vss33 vddk vss33 vss33 ap4 cmdat8 ak8 cmdat7 vdd33_camer a vss33 vddk vss33 vss33 an5 cmdat6 an7 cmdat5 vdd33_camer a vss33 vddk vss33 vss33 au3 cmdat4 am8 cmdat3 vdd33_camer a vss33 vddk vss33 vss33 vdd33_camera vss33 at4 cmdat2 al9 cmdat1 vdd33_camer a vss33 vddk vss33 vss33 av2 cmdat0 an9 cmflash vdd33_camer a vss33 vddk vss33 vss33 ap6 ed23 at6 ed22 vdd33_emi vss33 vddk vss33 vss33 au5 ed21 vdd33_emi vss33 vddk vss33 vdd33_emi vss33 ar7 ed20 vdd33_emi vss33 vddk vss33 vss33 ap8 ed19 am10 ed18 vdd33_emi vss33 vddk vss33 vss33 av4 ed17 al11 ed16 vdd33_emi vss33 vddk vss33 vss33 au7 edqm2 vdd33_emi vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 46 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vddk vss33 vddk vss33 vss33 av6 edqs2 vdd33_emi vss33 vddk vss33 vss33 ap10 ed31 an11 ed30 vdd33_emi vss33 vddk vss33 vss33 ar9 ed29 am12 ed28 vdd33_emi vss33 vddk vss33 vss33 at8 ed27 vdd33_emi vss33 vddk vss33 vdd33_emi vss33 au9 ed26 vdd33_emi vss33 vddk vss33 vss33 av8 ed25 ar11 ed24 vdd33_emi vss33 vddk vss33 vss33 av10 edqm3 at10 edqs3 vdd33_emi vss33 vddk vss33 vss33 ap12 ea4 vdd33_emi vss33 vddk vss33 vdd33_emi vss33 al13 ea6 vdd33_emi vss33 vddk vss33 vss33 at12 ea2 an13 ea5 vdd33_emi vss33 vddk vss33 vss33 ar13 ea9 am14 ea3 vdd33_emi vss33 vddk vss33 vss33 au11 ea1 vdd33_emi vss33 vddk vss33 vdd33_emi vss33 av12 ea7 vdd33_emi vss33 vddk vss33 vss33 au13 ea14 ap14 ea10 vdd33_emi vss33 vddk vss33 vss33 at14 ea11 an15 ea0 vdd33_emi vss33 vddk vss33 vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 47 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark av14 ea8 vdd33_emi vss33 vddk vss33 vss33 vddk vss33 vddk vss33 au15 ea12 am16 ea15 vdd33_emi vss33 vddk vss33 vss33 ap16 ecs0_b al17 ecs1_b vdd33_emi vss33 vddk vss33 vss33 at16 ecke av16 ewr_b vdd33_emi vss33 vddk vss33 vss33 au17 eras_b an17 ecas_b vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 ar17 ed_clk ap18 ed_clk_b vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 at18 ec_clk ar19 ea23 vdd33_emi vss33 vddk vss33 vss33 av18 ea24 an19 ea19 vdd33_emi vss33 vddk vss33 vss33 au19 ea25 am20 ea22 vdd33_emi vss33 vddk vss33 vss33 at20 ea17 av20 ea18 vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 au21 ea16 ap20 ea26 vdd33_emi vss33 vddk vss33 vss33 av22 ea21 ar21 ea20 vdd33_emi vss33 vddk vss33 vss33 at22 ea13 vdd33_emi vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 48 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark au23 ecs3_b ar23 fsource vss33 vdd33_emi vss33 vddk33 vss33 vddk33 vss33 av24 ecs2_b an21 watchdog vdd33_emi vss33 vddk vss33 vss33 av26 eadv_b ap22 erd_b vdd33_emi vss33 vddk vss33 vss33 au25 ewait at24 eadmux vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 av28 edqs1 au27 edqm1 vdd33_emi vss33 vddk vss33 vss33 am22 ed15 an23 ed14 vdd33_emi vss33 vddk vss33 vss33 at26 ed13 ar25 ed12 vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 ap24 ed11 av30 ed10 vdd33_emi vss33 vddk vss33 vss33 au29 ed9 at28 ed8 vdd33_emi vss33 vddk vss33 vss33 av32 edqs0 au31 edqm0 vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 ar27 ed7 at30 ed6 vdd33_emi vss33 vddk vss33 vss33 ar29 ed5 vdd33_emi vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 49 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark av34 ed4 vss33 ap28 ed3 au33 ed2 vdd33_emi vss33 vddk vss33 vss33 vdd33_emi vss33 vddk33 vss33 vddk33 vss33 at32 ed1 an27 ed0 vdd33_emi vss33 vddk vss33 vss33 av36 mfiq vdd33 vss33 vddk vss33 vss33 ap30 traceclk ar31 tracectl vdd33_trace vss33 vddk vss33 vss33 au35 tracedata0 am28 tracedata1 vdd33_trace vss33 vddk vss33 vss33 vdd33_trace vdd33_trace vss33 at34 tracedata2 an29 tracedata3 vdd33_trace vss33 vddk vss33 vss33 ar33 tracedata4 vdd33_trace vss33 vddk vss33 vdd33_trace vss33 vdd33_trace al29 tracedata5 vdd33_trace vss33 vddk vss33 vss33 ap32 tracedata6 am30 tracedata7 vdd33_trace vss33 vddk vss33 vss33 am32 j2trst_b ak30 j2tck vdd33 vss33 vddk vss33 vss33 an33 j2tdi ap34 j2tms vdd33 vss33 vddk vss33 vss33 ar35 j2tdo al31 j2rtck vdd33 vss33 vddk vss33 vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 50 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark am34 btdmp_din1 vdd33 vss33 vddk vss33 vdd33 vss33 al33 btdmp_fsp1 vdd33 vss33 vddk vss33 vss33 at36 btdmp_clk1 ak32 btdmp_dout2 vdd33 vss33 vddk vss33 vss33 an35 btdmp_fsp2 ak34 btdmp_clk2 vdd33 vss33 vddk vss33 vss33 au37 gpio123 aj33 daipcmout vdd33 vss33 vddk vss33 vss33 ap36 daipcmin ah32 daisync vdd33 vss33 vddk vss33 vss33 ar37 daiclk ah34 utxd2 vdd33 vss33 vddk vss33 vss33 al35 urxd2 vdd33 vss33 vddk vss33 vddk vss33 vddk vss33 vdd33 vss33 ag33 urts2 vdd33 vss33 vddk vss33 vss33 am36 ucts2 vdd33 vss33 vddk vss33 af34 gpio122 vdd33 vss33 vddk vss33 vss33 at38 dairst an37 eint1 vdd33 vss33 vddk vss33 vss33 aj35 srclkenai af32 eint2 vdd33 vss33 vddk vss33 vss33 ak36 eint3 ag35 eint4 vdd33 vss33 vddk vss33 vss33 ap38 eint5 ae31 scl2 vdd33 vss33 vddk vss33 vss33 al37 sda2 ah36 pwm0 vdd33 vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 51 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vss33 vdd33 vss33 am38 pwm1 aj37 pwm6 vdd33 vss33 vddk vss33 vss33 ak38 urxd3 ad30 utxd3 vdd33 vss33 vddk vss33 vss33 ae35 urxd4 ae33 utxd4 vdd33 vss33 vddk vss33 vss33 af36 gpio116 ag37 gpio117 vdd33 vss33 vddk vss33 vss33 ah38 gpio118 ad32 gpio119 vdd33 vss33 vddk vss33 vss33 ad36 gpio120 ae37 gpio121 vdd33 vss33 vddk vss33 vss33 af38 gpio124 vdd33 vss33 vddk vss33 vddk vss33 vddk vss33 vdd33 vss33 ac31 gpio125 vdd33 vss33 vddk vss33 vss33 ad34 jtrst_b ad38 jtck vdd33 vss33 vddk vss33 vss33 ab36 jtdi ac33 jtms vdd33 vss33 vddk vss33 vss33 ac35 jtdo ab34 jrtck vdd33 vss33 vddk vss33 vss33 vss33 ac37 xout vdd33 vss33 vddk vss33 vss33 ab38 xin vdd33 vss33 vddk vss33 avdd_rtck aa33 testmode vdd33 vss33 vddk vss33 avdd_rtck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 52 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark aa35 bbwakeup vdd33 vss33 vddk vss33 vss33 aa31 pad_sio2 y34 pad_srst2 y30 pad_sclk2 vdd33 vss33 vddk vss33 avdd30_vsim2 avdd30_vsim2 avdd30_vsim avdd30_vsim v30 pad_sio y36 pad_srst y32 pad_sclk vdd33 vss33 vddk vss33 vddk vss33 vddk vss33 y38 ceva_tck vdd33 vss33 vddk vss33 vss33 w37 ceva_tms v34 ceva_tdi vdd33 vss33 vddk vss33 vss33 w35 ceva_tdo v32 ceva_rtck vdd33 vss33 vddk vss33 vss33 v38 iboot vdd33 vss33 vddk vss33 v36 nc vss33 vdd33 vss33 u37 secu_en u33 icoresight vdd33 vss33 vddk vss33 vss33 t38 ionejtag u35 hdq vdd33 vss33 vddk vss33 vss33 p38 srclkenan vdd33 vss33 vddk vss33 vss33 t36 gpio126 t32 gpio127 vdd33 vss33 vddk vss33 vss33 r37 gpio128 m38 gpio129 vdd33 vss33 vddk vss33 vss33 n37 gpio130 p34 gpio131 vdd33 vss33 vddk vss33 vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 53 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark p36 gpio132 vdd33 vss33 vddk vss33 vdd33 vss33 r35 gpio133 vdd33 vss33 vddk vss33 vss33 k38 pwr_key r33 scl0 vdd33 vss33 vddk vss33 vss33 l37 sda0 m36 eint0 vdd33 vss33 vddk vss33 vss33 h38 gpio115 n33 srclkena vdd33 vss33 vddk vss33 vss33 j37 sysrst_b n35 eint6 vdd33 vss33 vddk vss33 vss33 k36 eint7 p32 eint8 vdd33 vss33 vddk vss33 vss33 l35 eint9 f38 i2s_ws vdd33 vss33 vddk vss33 vss33 g37 i2s_clk vdd33 vss33 vddk vss33 vddk vss33 vddk vss33 vdd33 vss33 h36 i2s_dat vdd33 vss33 vddk vss33 vss33 d38 urxd1 m34 utxd1 vdd33 vss33 vddk vss33 vss33 e37 ucts1 j35 urts1 vdd33 vss33 vddk vss33 vss33 f36 irda_rxd m32 irda_txd vdd33 vss33 vddk vss33 vss33 b38 irda_pdn l33 bpi_bus0 vdd33 vss33 vddk vss33 vss33 h34 bpi_bus1 g35 bpi_bus2 vdd33 vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 54 of 1535 ball 38x3 8 name io supply io gnd core supply core gnd remark vss33 c37 bpi_bus3 k34 bpi_bus4 vdd33 vss33 vddk vss33 vss33 d36 bpi_bus5 vdd33 vss33 vddk vss33 vdd33 vss33 k32 bpi_bus6 vdd33 vss33 vddk vss33 vss33 e35 bpi_bus7 j33 bpi_bus8 vdd33 vss33 vddk vss33 vss33 f34 bpi_bus9 h32 bsi_cs0 vdd33 vss33 vddk vss33 vss33 g33 bsi_data j31 bsi_clk vdd33 vss33 vddk vss33 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 55 of 1535 1.6 ordering information 1.6.1 MT6516 part number package operational temperature range MT6516 15x15x1.2 mm 564-tfbga -20~80c table 4 MT6516 ordering information free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 56 of 1535 2 application micro-controller unit subsystem figure 2-1 illustrates the block diagram of the micro-contro ller unit subsystem in MT6516. the subsystem utilizes a main 32-bit arm926ej-s risc processor, wh ich plays the role of the main bus master controlling the whole subsystem. the arm926ej-s risc is equipped with instruction cache, instruction tcm, data cache, and data tcm. both instruction and data cache have 32kb and the size of all tcm is 16kb. if the requested content is found in tcm or in cache, no bus transaction is required. if the code cache hit rate is high enough, bus traffic can be effectively reduced and processor core performance maximized. the bus comprises of two-level system buses: advanced high-performance bus (ahb) and advanced peripheral bus (apb). all bus transactions originate from bus masters, while slaves can only respond to requests from bus masters. before data transfer can be established, the bus master must ask for bus ownership, accomplished by request-grant handshaking protocol between masters and arbiters. two levels of bus hierarchy are designed to provide optimum usage for different performance requirements. specifically, ahb bus, the main system bus, is tailored toward high-speed requirements and provides 32-bit data path with multiplex scheme for bus interconnections. the apb bus, on the other hand, is designed to reduce interface complexity for lower data transfer rate, and so it is isolated from high bandwidth ahb bus by apb bridge. apb bus supports 16-bit addressing and both 16-bit and 32-bit data paths. apb bus is also optimized for minimal power consumption by turning off the clock when there is no apb bus activity. during operation, if the target slave is located on ahb bus, the transaction is conducted directly on ahb bus. however, if the target slave is a peripheral and is attached to the apb bus, then the transaction is conducted between ahb and apb bus through the use of apb bridge. the MT6516 mcu subsystem supports only memory addressing method. therefore all components are mapped onto the mcu 32-bit address space. in order to off-load the processor core, a dma controller is designated to act as a master and share the bus resources on ahb bus to perform fast data movement between modules. this controller provides eleven dma channels. the interrupt controller provides a software interface to manipulate interrupt events; it can handle up to 64 interrupt sources asserted at the same time. in general, the controller generates 2 levels of interrupt requests, fiq and irq, to the processor. a 304k byte sram is provided as system memory for high-speed data access. for factory programming purposes, a boot rom module is also integrated. external memory interface supports 8-bit, 16-bit and 32-bit devices. this interface supports both synchronous and asynchronous components, such as flash, sram and sdr, ddr sdram. this interface also supports page and burst mode type of flash, cellular ram, as well as high performance mobileram. since ahb bus is 32-bit wide, all data transfers are converted into several 8-bit or 16-bit cycles depending on the data width of the target device. in contrast to code cache, contents in data cache are queried when mcu issues data requests, or when other ahb bus masters issue memory requests to emi. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 57 of 1535 atb figure 2-1 block diagram of the micro-controller unit subsystem in MT6516 2.1 processor core 2.1.1 general description the micro-controller unit subsystem in MT6516 uses the 32-bit arm926ej-s risc processor that is based on the harvard architecture with two separated 32-bit data buses that carry instructions and data independently. the running clock frequency is up to 416mhz, 4 times the speed of the ahb bus. the memory interface of arm926ej-s is totally compliant with the amba based bus system, which allows direct connection to the ahb bus. 2.1.2 general programming guide 2.1.2.1 idle insertion between operations in MT6516, the cpu runs at 416 mhz in default, which is 4 times faster than the connected 104 mhz ahb buses. therefore, only one clock cycle of the outside system bus passes while cpu executes 4 instructions (assuming no stall, branch or abort). for example, if you insert 4 nops between two single-word memory write, you have chances to see the two ahb writes are consecutive on ahb bus. this must be noticed since certain codes would intentionally insert idle cycles between two operations and the absolute time of idleness may vary with the cpu clock speed. let?s assume that you used to insert 8 nops to separate two ahb operations in earlier product, which has cpu running at 208 mhz. the truth is the two operations would appear at least four bus clock cycles away from each other. but in MT6516 it may have only two idle cycles injected on the bus. 2.1.3 arm926ej-s power down to stop the clock and make the arm926ej-s sleep, the following step should be taken: 1. make sure the cpu is in the privileged mode. 2. execute the wait for interrupt instruction. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 58 of 1535 mcr p15, 0, , c7, c0, 4 the arm926ej-s core will be put into the sleep mode now and will be waken up by external fiq or irq. 2.2 memory management 2.2.1 general description the processor core of MT6516 supports only a memory addressing method for instruction fetch and data access. the core manages a 32-bit address space that has addressing capability of up to 4 gb. system ram, system rom, registers, mcu peripherals and external components are all mapped onto such 32-bit address space, as depicted in figure 2-2 . bank base address description bank0 0000_0000h emi band 0 / boot code bank1 1000_0000h emi bank 1 bank2 2000_0000h emi bank 2 bank3 3000_0000h emi bank 3 4000_0000h system ram 4800_0000h system rom bank5 5000_0000h tcm bank6 not used bank7 not used 8000_0000h apb peripheral 8010_0000h usb 8011_0000h virtual fifo slave 8012_0000h lcd 8013_0000h dpi 8014_0000h dsi bank9 not used bank10 not used bank11 b000_0000h ceva bank12 not used bank13 not used bank14 not used bank15 f000_0000h back door ap mcusys bank4 bank8 figure 2-2 memory layout of MT6516 the address space is organized into blocks of 256 mb each. the block number is uniquely selected by address line a31-a28 of the internal system bus. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 59 of 1535 2.2.1.1 external access to allow external access, the MT6516 outputs 27 bits (a26-a0) of address lines along with 4 selection signals that correspond to associated memory blocks. that is, MT6516 can support up to 4 mcu addressable external components. the data width of internal system bus is fixed at 32-bit wide, while the data width of the external components can be 8-, 16- or 32- bit. since devices are usually available with varied operating grades, adaptive configurations for different applications are needed. MT6516 provides software programmable registers to configure their wait-states to adapt to different operating conditions. 2.2.1.2 memory re-mapping mechanism to permit more flexible system configuration, a memory re-mapping mechanism is provided. the mechanism allows software program to swap bank0 (ecs0#) and bank1 (ecs1#) dynamically. whenever the bit value of rm0 in register emi_remap is changed, these two banks are swapped accordingly. furthermore, it allows system to boot from system rom as detailed in 2.2.1.3 boot sequence. 2.2.1.3 boot sequence since the arm926ej-s core always starts to fetch instructions from the lowest memory address at 00000000h after system has been reset, the system is designed to have a dynamic mapping architecture capable of associating boot code, external flash or external sram with the memory block 0000_0000h ? 0fff_ffffh. by default, the boot code is mapped onto 0000_0000h ? 0fff_ffffh after a system reset. in this special boot mode, external memory controller does not access external memory; instead, the emi controller send predefined boot code back to the arm926ej-s core, which instructs the processor to execute the program in system rom. this configuration can be changed by programming bit value of rm1 in register emi_remap directly. MT6516 system provides one boot up scheme: z start up system of running codes from boot code for factory programming or nand flash boot. 2.2.1.3.1 boot code the boot code is placed together with memory re-mapping mechanism in external memory controller, and comprises of just two words of instructions as shown be low. a jump instruction leads the processor to run the code starting at address 4800_0000h where the system rom is placed. address binary code assembly 00000000h e51ff004h ldr pc, 0x4 00000004h 48000000h (data) 2.2.1.3.2 factory programming the configuration for factory programming is shown in figure 2-3 . usually the factory programming host connects with MT6516 via the uart interface. the download speed can be up to 921k bps while mcu is running at 26mhz. after the system has reset, the boot code guides the processor to run the factory programming software placed in system rom. then, MT6516 starts and polls the uart1 port until valid information is detected. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 60 of 1535 the first information received on the uart1 is used to configure the chip for factory programming. the flash downloader program is then transferred into system ram or external sram. further information is detailed in the mt 6516 software programming specification. MT6516 factory programming host flash uart external memory interface figure 2-3 system configuration required for factory programming 2.2.1.3.3 nand flash booting if MT6516 cannot receive data from uart1 for a certain amount of time, the program in system rom checks if any valid boot loader exists in nand flash. if found, the boot loader code is copied from nand flash to ram (internal or external) and executed to start the real application software. if no valid boot loader can be found in nand flash, MT6516 starts executing code in emi bank0 memory. the whole boot sequence is shown in the following figure. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 61 of 1535 boot from system rom check uart input receive from uart copy loader from nand to ram valid loader on nand y n y n factory programming boot from loader in ram boot from emi bank 0 boot from system rom check uart input receive from uart copy loader from nand to ram valid loader on nand y n y n factory programming boot from loader in ram boot from emi bank 0 figure 2-4 boot sequence 2.2.1.4 little endian mode the MT6516 system always treats 32-bit words of memory in little endian format. in little endian mode, the lowest numbered byte in a word is stored in the least significant position, and the highest numbered byte in the most significant position. byte 0 of the memory system is therefore connected to data lines 7 through 0. 2.3 bus system 2.3.1 general description three levels of bus hierarchy are employed in the micro-controller unit subsystem of MT6516. as depicted in figure 2-1 , ahb bus and apb bus serve as system backbone and peripheral buses, while an apb bridge connects these two buses. both ahb and apb buses operate at the same or half the clock rate of processor core. the apb bridge is the only bus master residing on the apb bus. all apb slaves are mapped onto memory block mb8 in the mcu 32-bit addressing space. a central address decoder is implemented inside the bridge to generate select signals for individual peripherals. in addition, since the base address of each apb slave is associated with select signals, the address bus on apb contains only the value of offset address. the maximum address space that can be allocated to a single apb slave is 64 kb, i.e. 16-bit address lines. the width of the data bus is mainly constrained to 16 bits to minimize the design complexity and power consumption while some use 32-bit data buses to accommodate more bandwidth. in the case where an apb slave needs large amount of transfers, the device driver can also request dma channels to conduct a burst of data transfer. the base address and data width of each peripheral are listed in table 2-1 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 62 of 1535 table 2-1 register base addresses for mcu peripherals ap side apb brdige definition address description dw software_base id module name apb bus0 8000_0000h efuse 32 efuse_base efusec (apconfig) 8000_1000h configuration registers (clock, power down, version and reset) 32 confg_base apconfg 8000_2000h general purpose inputs/outputs 32 gpio_base gpio 8000_3000h reset generation unit 32 rgu_base rgu apb bus1 8002_0000h external memory interface 32 emi_base emi (apmcu) 8002_1000h interrupt controller 32 cirq_base cirq 8002_2000h dma controller 32 dma_base dma 8002_3000h uart 1 16 uart1_base uart 8002_4000h uart 2 16 uart2_base uart 8002_5000h uart 3 16 uart3_base uart 8002_6000h general purpose timer 16 gpt_base apgpt 8002_7000h hdq 16 hdq_base hdq_onewire 8002_8000h keypad scanner 16 kp_base kp 8002_9000h pulse-width modulation outputs 16 pwm_base pwm 8002_b000h uart4 16 uart4_base uart 8002_c000h real time clock 16 rtc_base rtc 8002_d000h sej 32 sej_base sej 8002_e000h i2c controller 3 16 i2c3_base i2c 8002_f000h irda 16 irda_base irda 8003_0000h i2c controller 1 16 i2c_base i2c 8003_1000h ms/sd controller 1 32 msdc1_base msdc 8003_2000h nand flash interface 32 nfi_base nfi 8003_3000h sim2 16 sim_base sim 8003_4000h ms/sd controller 2 32 msdc2_base msdc 8003_5000h i2c controller 2 16 i2c2_base i2c 8003_6000h ccif 32 ccif_base ccif 8003_8000h nfi ecc 32 nfiecc_base nfi free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 63 of 1535 8003_9000h apmcusys config 32 amconfg_base apmcusys_confg 8003_a000h ap2md back door 32 ap2md_base ap2md 8003_b000h ap side voice front end 32 apvfe_base vfe 8003_c000h ap sleep control 16 apslp_base ap_sleep_ctrl 8003_d000h auxadc 16 auxadc_base auxadc 8003_e000h ap x general purpose timer 16 apxgpt_base apxgpt 8003_f000h ms/sd controller 3 32 msdc3_base msdc apb bus2 8004_0000h coresight debug 32 csdbg_base csdbg apb bus3 8006_0000h pll config 16 pll_base confg_cci apb bus4 8008_0000h graphics memory controller 32 gmc1_base gmc1_ahb 8008_1000h 2d accelerator 32 g2d_base g2d 8008_2000h 2d command queue 32 gcmq_base gcmq 8008_3000h fake engine 32 gifdec_base g1fake 8008_4000h image dma 32 imgdma_base image_dma 8008_5000h png decoder 32 pngdec_base png_decoder 8008_6000h 8008_7000h spi (for mobile tv) 16 mtvspi_base spi 8008_8000h tv controller 32 tvcon_base tvc 8008_9000h tv encoder 32 tvenc_base tve 8008_a000h camera interface 32 cam_base cam 8008_b000h camera ispmem 32 cam_isp_base cam_ispmem 8008_c000h back light scaling 32 bls_base bls 8008_d000h capture resizer 32 crz_base crz 8008_e000h drop resizer 32 drz_base drz 8008_f000h asm 32 asm_base asm 8009_0000h wavetable 32 wt_base wavetable 8009_1000h image processing 32 img_base imgproc 8009_2000h graph1sys config 16 graph1sys_confg_base graph1sys_confg apb bus5 800a_0000h graphics memory controller 32 gmc2_base gmc2 800a_1000h jpeg decoder 32 jpeg_base jpg 800a_2000h 3d engine 32 m3d_base m3d 800a_3000h post processing resizer 32 prz_base prz 800a_4000h image dma 1 32 imgdma1_base image_dma_1 800a_5000h mp4 deblocking 32 mp4_deblk_base mp4_deblk 800a_6000h fake engine 32 fake_eng2_base fake_eng_2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 64 of 1535 800a_7000h graph2sys config 32 graph2sys_base graph2sys_confg apb bus6 800c_0000h keypad scanner 32 mp4_base mp4 800c_1000h h264 32 h264_base h264 2.4 uuid 2.4.1 general description uuid is a 128-bit codes and unique among all chips. in general, you always get the different uuids between any two chips. uuid can be obtained by reading the address 0x8000_0010, 0x8000_0014, 0x8000_0018, 0x8000_001c (four 32-bit words, from lsb to msb, total: 32*4=128 bits) 2.5 interrupt controller 2.5.1 general description figure 2-5 outlines the major functionality of the mcu interrupt controller. the interrupt controller processes all interrupt sources coming from external lines and internal mcu peripherals. since arm926ej-s core supports two levels of interrupt latency, this controller generates two request signals: fiq for fast, low latency interrupt request and irq for more gener al interrupts with lower priority. a figure 2-6 block diagram of the interrupt controller free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 65 of 1535 one and only one of the interrupt sources can be assigned to fiq controller and have the highest priority in requesting timing critical service. all the others share the same irq signal by connecting them to irq controller. the irq controller manages up 64 interrupt lines of irq0 to irq63 with fixed priority in descending order. the interrupt controller provides a simple software interf ace by mean of registers to manipulate the interrupt request shared system. irq selection registers and fiq selection register determine the source priority and connecting relation among sources and interrupt lines. irq source status register allows software program to identify the source of interrupt that generates the interrupt request. irq mask register provides software to mask out undesired sources some time. end of interrupt register permits software program to indicate to the controller that a certain interrupt service routine has been finished. binary coded version of irq source status register is also made available for software program to helpfully identify the interrupt source. note that while taking advantage of this feature, it should also take the binary coded version of end of interrupt register coincidently. the essential interrupt table of arm926ej-s core is shown as table 2-2. address description 00000000h system reset 00000018h irq 0000001ch fiq table 2-3 interrupt table of arm926ej-s 2.5.1.1 interrupt source masking interrupt controller provides the function of interrupt source masking by the way of programming mask register. any of them can be masked individually. however, because of the bus latency, th e masking takes effect no earlier than 3 clock cycles later. in this time, the to-be-masked interrupts could come in and generate an irq pulse to mcu, and then disappear immediately. this irq forces mcu going to inte rrupt service routine and polling status register (irq_sta(irq_stah+irq_stal) or irq_sta2), but the register shows there is no interrupt. this might cause mcu malfunction. there are two ways for programmer to protect their software. 1. return from isr (interrupt service routine) immediately while the status register shows no interrupt. 2. set i bit of mcu before doing interrupt masking, and then clear it after interrupt masking done. both avoid the problem, but the first item recommended to have in the isr. 2.5.1.2 external interrupt this interrupt controller also integrates an external interrupt controller that can support up to 20 interrupt requests coming from external sources, the eint0~19, and 4 wakeup interrupt requests, i.e. eint20~23, coming from peripherals. all external interrupts can inform system to resume the system clock. eint0~4 interrupt request can be configured as from external pins or internal peripherals. the 20 external interrupts can be used for different kind of applications, mainly for event detections: detection of hand free connection, detection of hood opening, detection of battery charger connection. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 66 of 1535 since the external event may be unstable in a certain period, a de-bounce mechanism is introduced to ensure the functionality. the circuitry is ma inly used to verify that the input signal remains stable for a programmable number of periods of the clock. when this condition is satisfied, for the appearance or the disappearance of the input, the output of the de-bounce logic changes to the desired state. note that, because it uses the 32 khz slow clock for performing the de-bounce process, the parameter of de-bounce period and de-bounce enable takes effect no sooner than one 32 khz clock cycle (~31.25us) after the software program sets them. when the sources of external interrupt controller are used to resume the system clock in sleep mode, the de- bounce mechanism must be enabled. however, the polarities of eints are clocked with the system clock. however, the polarities of eints are clocked with the system clock. any changes to them take effect immediately. debounce logic interrupt control register apb bus eint23-20 eint_irq debounce logic eint19-0 figure 2-7 block diagram of external interrupt controller free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 67 of 1535 2.5.1.3 external interrupt input pins eint edge / level hw debounce source pin supplement eint0 edge / level yes if (gpio59 m==1) then eint0= usb dp pin else eint0= gpio59 eint1 edge / level yes if (gpio60 m==1) then eint1= uart1_rxd else eint1= gpio60 eint2 edge / level yes if (gpio61 m==1) then eint2= urxd2 else eint2= gpio61 eint3 edge / level yes if (gpio62 m==1) then eint3 = urxd3 else eint3= gpio62 eint4 edge / level yes if(gpio63_m==1) then eint4=gpio63 else eint4=1 eint5 edge / level yes if(gpio64_m==1) then eint5=gpio64 else eint5=1 eint6 edge / level yes if(gpio65_m==1) then eint6=gpio65 else eint6=1 eint7 edge / level yes if(gpio66_m==1) then eint7=gpio66 else eint7=1 eint8 edge / level yes if(gpio21_m==1) then eint8=gpio21 else eint8=1 eint9 edge / level yes if(gpio22_m==3) then eint9=gpio22 else eint9=1 eint10 edge / level yes if(gpio87_m==3) then eint10=gpio87 else eint10=1 eint11 edge / level if(gpio88_m==3) then eint11=gpio88 else eint11=1 1. gpios should be in the input mode and are effected by gpio data input inversion registers. 2. gpioxx_m is the gpio mode control registers, please refer to gpio segment. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 68 of 1535 yes eint12 edge / level yes if(gpio89_m==3) then eint12=gpio89 else eint12=1 eint13 edge / level yes if(gpio90_m==3) then eint13=gpio90 else eint13=1 eint14 edge / level yes if(gpio91_m==3) then eint14=gpio91 else eint14=1 eint15 edge / level yes if(gpio1_m==3) then eint15=gpio1 else eint15=1 eint16 edge / level yes if(gpio54_m==2) then eint16=gpio54 else eint16=1 eint17 edge / level yes if(gpio55_m==3) then eint17=gpio55 else eint17=1 eint18 edge / level yes if(gpio56_m==2) then eint18=gpio56 else eint18=1 eint19 edge / level yes if(gpio57_m==2) then eint19=gpio57 else eint19=1 eint20 edge / level yes usb20 iddig eint21 edge / level yes usb20 vbusvalid eint22 edge / level yes cpu interface irq_b eint23 edge / level yes dsp interface irq_b register register name synonym free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 69 of 1535 address cirq + 0000h irq selection 0 register irq_sel0 cirq + 0004h irq selection 1 register irq_sel1 cirq + 0008h irq selection 2 register irq_sel2 cirq + 000ch irq selection 3 register irq_sel3 cirq + 0010h irq selection 4 register irq_sel4 cirq + 0014h irq selection 5 register irq_sel5 cirq + 0018h irq selection 6 register irq_sel6 cirq + 001ch irq selection 7 register irq_sel7 cirq + 0034h fiq selection register fiq_sel cirq + 0038h irq mask register (lsb) irq_maskl cirq + 003ch irq mask register (msb) irq_maskh cirq + 0040h irq mask clear register (lsb) irq_mask_clrl cirq + 0044h irq mask clear register (msb) irq_mask_clrh cirq + 0048h irq mask set register (lsb) irq_mask_setl cirq + 004ch irq mask set register (msb) irq_mask_seth cirq + 0050h irq status register (lsb) irq_stal cirq + 0054h irq status register (msb) irq_stah cirq + 0058h irq end of interrupt register (lsb) irq_eoil cirq + 005ch irq end of interrupt register (msb) irq_eoih cirq + 0060h irq sensitive register (lsb) irq_sensl cirq + 0064h irq sensitive register (msb) irq_sensh cirq + 0068h irq software interrupt register (lsb) irq_softl cirq + 006ch irq software interrupt register (msb) irq_softh cirq + 0070h fiq control register fiq_con cirq + 0074h fiq end of interrupt register fiq_eoi cirq + 0078h binary coded value of irq_status irq_sta2 cirq + 007ch binary coded value of irq_eoi irq_eoi2 cirq + 0080h binary coded value of irq_soft irq_soft2 cirq + 0100h eint status register eint_sta cirq + 0104h eint mask register eint_mask cirq + 0108h eint mask disable register eint_mask_dis cirq + 010ch eint mask enable register eint_mask_en cirq + 0110h eint interrupt acknowledge register eint_intack cirq + 0114h eint sensitive register eint_sens cirq + 0120h eint0 de-bounce control register eint0_con cirq + 0130h eint1 de-bounce control register eint1_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 70 of 1535 cirq + 0140h eint2 de-bounce control register eint2_con cirq + 0150h eint3 de-bounce control register eint3_con cirq + 0160h eint4 de-bounce control register eint4_con cirq + 0170h eint5 de-bounce control register eint5_con cirq + 0180h eint6 de-bounce control register eint6_con cirq + 0190h eint7 de-bounce control register eint7_con cirq + 01a0h eint8 de-bounce control register eint8_con cirq + 01b0h eint9 de-bounce control register eint9_con cirq + 01c0h eint10 de-bounce control register eint10_con cirq + 01d0h eint11 de-bounce control register eint11_con cirq + 01e0h eint12 de-bounce control register eint12_con cirq + 01f0h eint13 de-bounce control register eint13_con cirq + 0200h eint14 de-bounce control register eint14_con cirq + 0210h eint15 de-bounce control register eint15_con cirq + 0220h eint16 de-bounce control register eint16_con cirq + 0230h eint17 de-bounce control register eint17_con cirq + 0240h eint18 de-bounce control register eint18_con cirq + 0250h eint19 de-bounce control register eint19_con cirq + 0260h eint20 de-bounce control register eint20_con cirq + 0270h eint21 de-bounce control register eint21_con cirq + 0280h eint22 de-bounce control register eint22_con cirq + 0290h eint23 de-bounce control register eint23_con table 2-4 interrupt controller register map 2.5.2 register definitions cirq+0000h irq selection 0 register irq_sel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq4 irq3 irq2 type r/w r/w r/w reset 000100b 000011b 00b bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2 irq1 irq0 type r/w r/w r/w reset 0010b 000001b 000000b cirq+0004h irq selection 1 register irq_sel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq9 irq8 irq7 type r/w r/w r/w reset 0x9 0x8 0x7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 71 of 1535 name irq7 irq6 irq5 type r/w r/w r/w reset 7 6 5 cirq+0008h irq selection 2 register irq_sel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irqe irqd irqc type r/w r/w r/w reset e d c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqc irqb irqa type r/w r/w r/w reset c b a cirq+000ch irq selection 3 register irq_sel3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq13 irq12 irq11 type r/w r/w r/w reset 13 12 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq11 irq10 irqf type r/w r/w r/w reset 11 10 f cirq+0010h irq selection 4 register irq_sel4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq18 irq17 irq16 type r/w r/w r/w reset 18 17 16 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq16 irq15 irq14 type r/w r/w r/w reset 16 15 14 cirq+0014h irq selection 5 register irq_sel5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1d irq1c irq1b type r/w r/w r/w reset 1d 1c 1b bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq1b irq1a irq19 type r/w r/w r/w reset 1b 1a 19 cirq+0018h irq selection 6 register irq_sel6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq22 irq21 irq20 type r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 72 of 1535 reset 22 21 20 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq20 irq1f irq1e type r/w r/w r/w reset 20 1f 1e cirq+001ch irq selection 7 register irq_sel7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq27 irq26 irq25 type r/w r/w r/w reset 27 26 25 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq25 irq24 irq23 type r/w r/w r/w reset 25 24 23 cirq+0020h irq selection 8 register irq_sel8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq2c irq2b irq2a type r/w r/w r/w reset 2c 2b 2a bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2a irq29 irq28 type r/w r/w r/w reset 2a 29 28 cirq+0024h irq selection 9 register irq_sel9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq31 irq30 irq2f type r/w r/w r/w reset 31 30 2f bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d type r/w r/w r/w reset 2f 2e 2d cirq+0028h irq selection 10 register irq_sel10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq36 irq35 irq34 type r/w r/w r/w reset 36 35 34 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq34 irq33 irq32 type r/w r/w r/w reset 34 33 32 cirq+002ch irq selection 11 register irq_sel11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 73 of 1535 name irq3b irq3a irq39 type r/w r/w r/w reset 3b 3a 39 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq39 irq38 irq37 type r/w r/w r/w reset 39 38 37 cirq+0030h irq selection 12 register irq_sel12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e type r/w r/w reset 3f 3e bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq3e irq3d irq3c type r/w r/w r/w reset 3e 3d 3c cirq+0034h fiq selection register fiq_sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fiq type r/w reset 0 the irq/fiq selection registers provide system designers with a flexible routing scheme to make various mappings of priority among interrupt sources possible. the registers allow the interrupt sources to be mapped onto interrupt requests of either fiq or irq. while only one interrupt source can be assigned to fiq, the other ones share irqs by mapping them onto irq0 to irq3f connected to irq controller. the priority sequence of irq0~irq3f is fixed, i.e. irq0 > irq1 > irq2 > ? > irq3e > irq3f. during the software configuration process, the interrupt source code of desired interrupt source should be written into source field of the corresponding irq_sel0-irq_sel12/fiq_sel. 6-bit interrupt source codes for all interrupt sources are fixed and defined. interrupt source sta2 (hex) stah_stal gpi_fiq 0 0000_00000001 sim2 1 0000_00000002 dma 2 0000_00000004 uart1 3 0000_00000008 kp 4 0000_00000010 uart2 5 0000_00000020 gpt 6 0000_00000040 eint 7 0000_00000080 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 74 of 1535 usb 8 0000_00000100 rtc 9 0000_00000200 msdc1 a 0000_00000400 irda b 0000_00000800 lcd c 0000_00001000 uart3 d 0000_00002000 gpi e 0000_00004000 wdt f 0000_00008000 tvc 10 0000_00010000 i2c3 11 0000_00020000 nfi 12 0000_00040000 i2c2 13 0000_00080000 image dma 14 0000_00100000 image dma2 15 0000_00200000 png 16 0000_00400000 i2c 17 0000_00800000 g2d 18 0000_01000000 image proc 19 0000_02000000 cam 1a 0000_04000000 mpeg4 decode 1b 0000_08000000 mpeg4 encode 1c 0000_10000000 jpeg decode 1d 0000_20000000 jpeg encode 1e 0000_40000000 resizer crz 1f 0000_80000000 resizer drz 20 0001_00000000 resizer prz 21 0002_00000000 tve 22 0004_00000000 usb dma 23 0008_00000000 pwm 24 0010_00000000 mpeg4 deblock 25 0020_00000000 h264 decode 26 0040_00000000 msdc1 event 27 0080_00000000 dpi 28 0100_00000000 apccif 29 0200_00000000 m3d 2a 0400_00000000 emi 2b 0800_00000000 msdc2 2c 1000_00000000 msdc2 event 2d 2000_00000000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 75 of 1535 reserved 2e 4000_00000000 ceva ccif 2f 8000_00000000 nfi ecc 30 1_0000_00000000 wavetable 31 2_0000_00000000 dvf controller 32 4_0000_00000000 reserved 33 8_0000_00000000 gmc1 34 10_0000_00000000 gmc2 35 20_0000_00000000 ap_sleep_ctr l 36 40_0000_00000000 asm 37 80_0000_00000000 touch screen 38 100_0000_0000000 0 apxgpt 39 200_0000_0000000 0 lowbat 3a 400_0000_0000000 0 mobile tv spi 3b 800_0000_0000000 0 uart4 3c 1000_0000_000000 00 msdc3 3d 2000_0000_000000 00 msdc3 event 3e 4000_0000_000000 00 onewire 3f 8000_0000_000000 00 table 2-5 interrupt source code for interrupt sources z fiq, irq0-26 the 6-bit content of this field corresponds to an interrupt source code shown above. cirq+0038h irq mask register (lsb) irq_maskl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq1 8 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc ir qb irqa irq9 irq8 irq7 irq6 ir q5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cirq+003ch irq mask register (msb) irq_maskh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 76 of 1535 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq2 5 irq24 irq23 irq22 irq21 irq20 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register contains a mask bit for each interrupt line in irq controller. the regi ster allows each interrupt source irq0 to irq1f to be disabled or masked separately under software control. after a system reset, all bit values are set to 1 to indicate that interrupt requests are prohibited. z irq0-3f mask control for the associated interrupt source in the irq controller z 0 interrupt is enabled. z 1 interrupt is disabled. cirq+0040h irq mask clear register (lsb) irq_mask_cl rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c cirq+0044h irq mask clear register (msb) irq_mask_cl rh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c this register is used to clear bits in irq mask register. when writing to this register, the data bits that are high cause the corresponding bits in irq mask register to be cleared. data bits that are low have no effect on the corresponding bits in irq mask register. z irq0-3f clear corresponding bits in irq mask register. z 0 no effect. z 1 disable the corresponding mask bit. cirq+0048h irq mask set register (lsb) irq_mask_se tl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 77 of 1535 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s cirq+004ch irq mask set register (msb) irq_mask_se th bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s this register is used to set bits in the irq mask register . when writing to this regi ster, the data bits that are high cause the corresponding bits in irq mask register to be set. data bits that are low have no effect on the corresponding bits in irq mask register. z irq0-3f set corresponding bits in irq mask register. z 0 no effect. z 1 enable corresponding mask bit. cirq+0050h irq source status register (lsb) irq_stal bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cirq+0054h irq source status register (msb) irq_stah bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register allows software to poll which interrupt line has generated an irq interrupt request. a bit set to 1 indicates a corresponding active interrupt line. only one flag is active at a time. the irq_sta is type of read-clear; write access has no effect on the content. z irq0-3f interrupt indicator for the associated interrupt source. z 0 the associated interrupt source is non-active. z 1 the associated interrupt source is asserted. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 78 of 1535 cirq+0058h irq end of interru pt register (lsb) irq_eoil bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cirq+005ch irq end of interru pt register (msb) irq_eoih bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register provides a mean for software to relinquish and to refresh the interrupt controller. writing a 1 to a specific bit position results in an end of interrupt command issued internally to the corresponding interrupt line. z irq0-3f end of interrupt command for the associated interrupt line. z 0 no service is currently in progress or pending. z 1 interrupt request is in-service. cirq+0060h irq sensitive register (lsb) irq_sensl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cirq+0064h irq sensitive register (msb) irq_sensh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 all interrupt lines of irq controller, irq0~irq1f can be programmed as either edge or level sensitive. by default, all the interrupt lines are edge sensitive and should be active low. once a interrupt line is free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 79 of 1535 programmed as edge sensitive, an interrupt request is t riggered only at the falling e dge of interrupt line, and the next interrupt is not accepted until the eoi command is given. however, level sensitive interrupts trigger is according to the signal level of the interrupt line. once the interrupt line become from high to low, an interrupt request is triggered, and anot her interrupt request is triggered if the signal level remain low after an eoi command. note that in edge sensitive mode, even if the signal level remains low after eoi command, another interrupt request is not triggered. that is because edge sensitive interrupt is only triggered at the falling edge. z irq0-3f sensitivity type of the associated interrupt source z 0 edge sensitivity with active low z 1 level sensitivity with active low cirq+0068h irq software interrupt register (lsb) irq_softl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cirq+006ch irq software interrupt register (msb) irq_softh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq3f irq3e irq3d irq3c irq3b irq3a irq39 irq38 irq37 irq36 irq35 irq34 irq33 irq32 irq31 irq30 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2f irq2e irq2d irq2c irq2b ir2a irq29 irq28 irq27 irq26 irq25 irq24 irq23 irq22 irq21 irq20 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 setting ?1? to the specific bit position generates a software interrupt for corresponding interrupt line before mask. this register is used for debug purpose. z irq0-irq3f software interrupt cirq+0070h fiq control register fiq_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sens mask type r/w r/w reset 0 1 this register provides a means for software program to control the fiq controller. z mask mask control for the fiq interrupt source free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 80 of 1535 z 0 interrupt is enabled. z 1 interrupt is disabled. z sens sensitivity type of the fiq interrupt source z 0 edge sensitivity with active low z 1 level sensitivity with active low cirq+0074h fiq end of in terrupt register fiq_eoi bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eoi type wo reset 0 this register provides a means for software to relinquish and to refresh the fiq controller. writing a ?1? to the specific bit position results in an end of interrupt command issued internally to the corresponding interrupt line. z eoi end of interrupt command cirq+0078h binary coded value of irq_status irq_sta2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name noirq sts type rc rc reset 0 0 this register is a binary coded version of irq_sta. it is used by the software program to poll which interrupt line has generated the irq interrupt request in a much ea sier way. any read to it has the same result as reading irq_sta. the irq_sta2 is also read-only and read-clear; write access has no effect on the content. note that irq_sta2 should be coupled with irq_eoi2 while using it. z sts binary coded value of irq_sta z noirq indicating if there is an irq or not. if there is no irq, this bit is high, and the value of sts is 00_0000b. cirq+007ch binary coded value of irq_eoi irq_eoi2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eoi type wo reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 81 of 1535 this register is a binary coded version of irq_eoi. it provides an easier way for software program to relinquish and to refresh the interrupt controller. writing a specific code results in an end of interrupt command issued internally to the corresponding interrupt line. note that irq_eoi2 should be coupled with irq_sta2 while using it. z eoi binary coded value of irq_eoi cirq+0080h binary coded value of irq_soft irq_soft2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name soft type wo reset 0 this register is a binary coded version of irq_soft. z soft binary coded value of irq_soft cirq+0100h eint interrupt status register eint_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register keeps up with current status that which eint source generates the interrupt request. the status will be changed to zero if the corresponding eint source mask bit is set. z eint0-eint23 interrupt status z 0 no interrupt request is generated. z 1 interrupt request is pending. cirq+0104h eint interrup t mask register eint_mask bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 82 of 1535 this register controls whether or not eint source is allowed to generate an interrupt request. setting a ?1? to the specific bit position prohibits the external interrupt line from becoming active. z eint0-eint23 interrupt mask z 0 interrupt request is enabled. z 1 interrupt request is disabled. cirq+0108h eint interr upt mask clear register eint_mask_cl r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type w1c w1c w1c w1c w1c w1c w1c w1c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c this register is used to clear individual mask bits. only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are cleared (set to 0). otherwise the interrupt mask bit retains its original value. z eint0-eint23 disable mask for the associated external interrupt source. z 0 no effect. z 1 disable the corresponding mask bit. cirq+010ch eint interr upt mask set register eint_mask_se t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type w1s w1s w1s w1s w1s w1s w1s w1s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s this register is used to set individual mask bits. only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are set to 1. otherwise the interrupt mask bit retains its original value. z eint0-eint23 disable mask for the associated external interrupt source. z 0 no effect. z 1 enable corresponding mask bit. cirq+0110h eint interrupt acknowledge register eint_intack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 83 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 writing ?1? to the specific bit position is to acknowledge the interrupt request that correspondingly to the external interrupt line source. write this register to clear edge sensitive eint triggered status. write this register to clear eint edge status first, if the eint source is changed from level sensitive to edge sensitive. z eint0-eint23 interrupt acknowledgement z 0 no effect z 1 interrupt request is acknowledged. cirq+0114h eint sensitive register eint_sens bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 sensitivity type of external interrupt source. z eint0-eint23 sensitivity type of the associated external interrupt source. z 0 edge sensitivity z 1 level sensitivity cirq+0120h+ n*10h eintn de-bounce control register eintn_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en pol cnt type r/w r/w r/w reset 0 0 0 these registers control the de-bounce logic for external interrupt sources in order to minimize the possibility of false activations. note that n is from 0 to 23 when the external interrupt sources is used to resume the system clock from the sleep mode, the de-bounce control circuit must be enabled. z cnt de-bounce duration in terms of number of 32 khz clock cycles. z pol activation type of the eint source z 0 negative polarity z 1 positive polarity z en de-bounce control circuit z 0 disable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 84 of 1535 z 1 enable 2.6 direct memory access 2.6.1 general description a generic dma controller is placed on layer 2 ahb bus to support fast data transfers and to off-load the processor. with this controller, specific devices on ahb or apb buses can benefit greatly from quick completion of data movement from or to memory modules such as internal system ram or external sram, excluding tcm. tcm is invisible for dma engine. such generic dma controller can also be used to connect any two devices other than memory module as long as they can be addressed in memory space. figure 8 varity data paths of dma transfers up to 24 channels of simultaneous data transfers are supported. they are channel 1 to channel 24. each channel has a similar set of registers to be configured to different scheme as desired. if more than 24 devices are requesting the dma resources at the same time, software based arbitration should be employed. once the service candidate is decided, the responsible device driver should configure the generic dma controller properly in order to conduct dma transfers. both interrupt and polling based schemes in handling the completion event are supported. the block diagram of such generic dma co ntroller is illustrated in figure 9 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 85 of 1535 figure 9 block diagram of direct memory access module 2.6.1.1 full-size , half-size & virtual fifo dma channels there are three types of dma channels in the dma controller. the first one is called a full-size dma channel, the second one is called a half-size dma channel, and the last is virtual fifo dma. channels 1 through 8 are full-size dma channels; channels 9 through 16 are half-size ones; and channels 17 through 24 are virtual fifo dma channels. the difference between the first two types of dma channels is that both source and destination address are programmable in full-size dma ch annels, but only the address of one side can be programmed in half-size dma channel. in half-size channels, only either the source or destination address can be programmed, while the addresses of the other side is preset. which preset address is used depends on the setting of mas in dma channel control register. refer to the register definition section for more detail. 2.6.1.2 ring buffer & double buffer memory data movement dma channels 1 through 16 support ring-buffer and double-buffer memory data movement. this can be achieved by programming dma_wppt and dma_wpto, as well as setting wpen in dma_con register to enable. figure 10 illustrates how this function works. once th e transfer counter reaches the value of wppt, the next address jumps to the wpto address after completing the wppt data transfer. note that only one side can be configured as ring-buffer or double-buffer memory, and this is controlled by wpsd in dma_con register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 86 of 1535 figure 10 ring buffer and double buffer memory data movement unaligned word access the address of word access on ahb bus must be aligned to word boundary, or the 2 lsb is truncated to 00b. if programmers do not notice this, it may cause an incorrect data fetch. in the case where data is to be moved from unaligned addresses to aligned addresses, the word is usually first split into four bytes and then moved byte by byte. this result in four read and four write transfers on the bus. to improve bus efficiency, unaligned-word access is provided in dma9~16. while this function is enabled, dmas move data from unaligned address to aligned address by executing four continuous byte-read access and one word-write access, reducing the number of transfers on the bus by three. figure 11 unaligned word access free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 87 of 1535 2.6.1.3 virtual fifo dma virtual fifo dma is used to ease uart control. the difference between the virtual fifo dmas and the ordinary dmas is that virtual fifo dma contains additional fifo controller. the read and write pointers are kept in the virtual fifo dma. during a read from the fifo, the read pointer points to the address of the next data. during a write to the fifo, the write pointer moves to the next address. if the fifo is empty, a fifo read is not allowed. similarly, data is not written into the fifo if the fifo is full. due to uart flow control requirements, an alert length is programmed. once the fifo space is less than this value, an alert signal is issued to enable uart flow control. the type of flow control performed depends on the setting in uart. each virtual fifo dma can be programmed as rx or tx fifo. this depends on the setting of dir in dma_con register. if dir is ?0?(read), it means tx fifo. on the other hand, if dir is ?1?(write), the virtual fifo dma is specified as a rx fifo. virtual fifo dma provides an interrupt to mcu. this interrupt informs mc u that there is data in the fifo, and the amount of data is over or under the value defined in dma_count register. with this, mcu does not need to poll dma to know when data must be removed from or put into the fifo. note that virtual fifo dmas cannot be used as generic dmas, i.e. dma1~16. figure 12 virtual fifo dma dma number address of virtual fifo access port dma17 8011_0000h dma18 8011_0100h dma19 8011_0200h dma20 8011_0300h dma21 8011_0400h dma22 8011_0500h dma23 8011_0600h dma24 8011_0700h free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 88 of 1535 table 6 virtual fifo access port dma number type ring buffer double buffer burst mode unaligned word access dma1 full size dma2 full size dma3 full size dma4 full size dma5 full size dma6 full size dma7 full size dma8 full size dma9 half size dma10 half size dma11 half size dma12 half size dma13 half size dma14 half size dma15 half size dma16 half size dma17 virtual fifo dma18 virtual fifo dma19 virtual fifo dma20 virtual fifo dma21 virtual fifo dma22 virtual fifo dma23 virtual fifo dma24 virtual fifo table 7 function list of dma channels register address register name synonym dma + 0000h dma global status register dma_glbsta dma + 0004h dma global status 2 register dma_glbsta2 dma + 0028h dma global bandwidth limiter register dma_glblimiter dma + 0080h dma channel 1 source address register dma1_src dma + 0084h dma channel 1 destination address register dma1_dst dma + 0088h dma channel 1 wrap point address register dma1_wppt dma + 008ch dma channel 1 wrap to address register dma1_wpto free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 89 of 1535 dma + 0090h dma channel 1 transfer count register dma1_count dma + 0094h dma channel 1 control register dma1_con dma + 0098h dma channel 1 start register dma1_start dma + 009ch dma channel 1 interrupt status register dma1_intsta dma + 00a0h dma channel 1 interrupt acknowledge register dma1_ackint dma + 00a4h dma channel 1 remaining length of current transfer dma1_rlct dma + 00a8h dma channel 1 bandwidth limiter register dma1_limiter dma + 0100h dma channel 2 source address register dma2_src dma + 0104h dma channel 2 destination address register dma2_dst dma + 0108h dma channel 2 wrap point address register dma2_wppt dma + 010ch dma channel 2 wrap to address register dma2_wpto dma + 0110h dma channel 2 transfer count register dma2_count dma + 0114h dma channel 2 control register dma2_con dma + 0118h dma channel 2 start register dma2_start dma + 011ch dma channel 2 interrupt status register dma2_intsta dma + 0120h dma channel 2 interrupt acknowledge register dma2_ackint dma + 0124h dma channel 2 remaining length of current transfer dma2_rlct dma + 0128h dma channel 2 bandwidth limiter register dma2_limiter dma + 0180h dma channel 3 source address register dma3_src dma + 0184h dma channel 3 destination address register dma3_dst dma + 0188h dma channel 3 wrap point address register dma3_wppt dma + 018ch dma channel 3 wrap to address register dma3_wpto dma + 0190h dma channel 3 transfer count register dma3_count dma + 0194h dma channel 3 control register dma3_con dma + 0198h dma channel 3 start register dma3_start dma + 019ch dma channel 3 interrupt status register dma3_intsta dma + 01a0h dma channel 3 interrupt acknowledge register dma3_ackint dma + 01a4h dma channel 3 remaining length of current transfer dma3_rlct dma + 01a8h dma channel 3 bandwidth limiter register dma3_limiter dma + 0200h dma channel 4 source address register dma4_src dma + 0204h dma channel 4 destination address register dma4_dst dma + 0208h dma channel 4 wrap point address register dma4_wppt dma + 020ch dma channel 4 wrap to address register dma4_wpto dma + 0210h dma channel 4 transfer count register dma4_count dma + 0214h dma channel 4 control register dma4_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 90 of 1535 dma + 0218h dma channel 4 start register dma4_start dma + 021ch dma channel 4 interrupt status register dma4_intsta dma + 0220h dma channel 4 interrupt acknowledge register dma4_ackint dma + 0224h dma channel 4 remaining length of current transfer dma4_rlct dma + 0228h dma channel 4 bandwidth limiter register dma4_limiter dma + 0280h dma channel 5 source address register dma5_src dma + 0284h dma channel 5 destination address register dma5_dst dma + 0288h dma channel 5 wrap point address register dma5_wppt dma + 028ch dma channel 5 wrap to address register dma5_wpto dma + 0290h dma channel 5 transfer count register dma5_count dma + 0294h dma channel 5 control register dma5_con dma + 0298h dma channel 5 start register dma5_start dma + 029ch dma channel 5 interrupt status register dma5_intsta dma + 02a0h dma channel 5 interrupt acknowledge register dma5_ackint dma + 02a5h dma channel 5 remaining length of current transfer dma5_rlct dma + 02a8h dma channel 5 bandwidth limiter register dma5_limiter dma + 0300h dma channel 6 source address register dma6_src dma + 0304h dma channel 6 destination address register dma6_dst dma + 0308h dma channel 6 wrap point address register dma6_wppt dma + 030ch dma channel 6 wrap to address register dma6_wpto dma + 0310h dma channel 6 transfer count register dma6_count dma + 0314h dma channel 6 control register dma6_con dma + 0318h dma channel 6 start register dma6_start dma + 031ch dma channel 6 interrupt status register dma6_intsta dma + 0320h dma channel 6 interrupt acknowledge register dma6_ackint dma + 0324h dma channel 6 remaining length of current transfer dma6_rlct dma + 0328h dma channel 6 bandwidth limiter register dma6_limiter dma + 0380h dma channel 7 source address register dma7_src dma + 0384h dma channel 7 destination address register dma7_dst dma + 0388h dma channel 7 wrap point address register dma7_wppt dma + 038ch dma channel 7 wrap to address register dma7_wpto dma + 0390h dma channel 7 transfer count register dma7_count dma + 0394h dma channel 7 control register dma7_con dma + 0398h dma channel 7 start register dma7_start dma + 039ch dma channel 7 interrupt status register dma7_intsta free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 91 of 1535 dma + 03a0h dma channel 7 interrupt acknowledge register dma7_ackint dma + 03a4h dma channel 7 remaining length of current transfer dma7_rlct dma + 03a8h dma channel 7 bandwidth limiter register dma7_limiter dma + 0400h dma channel 8 source address register dma8_src dma + 0404h dma channel 8 destination address register dma8_dst dma + 0408h dma channel 8 wrap point address register dma8_wppt dma + 040ch dma channel 8 wrap to address register dma8_wpto dma + 0410h dma channel 8 transfer count register dma8_count dma + 0414h dma channel 8 control register dma8_con dma + 0418h dma channel 8 start register dma8_start dma + 041ch dma channel 8 interrupt status register dma8_intsta dma + 0420h dma channel 8 interrupt acknowledge register dma8_ackint dma + 0424h dma channel 8 remaining length of current transfer dma8_rlct dma + 0428h dma channel 8 bandwidth limiter register dma8_limiter dma + 0488h dma channel 9 wrap point address register dma9_wppt dma + 048ch dma channel 9 wrap to address register dma9_wpto dma + 0490h dma channel 9 transfer count register dma9_count dma + 0494h dma channel 9 control register dma9_con dma + 0498h dma channel 9 start register dma9_start dma + 049ch dma channel 9 interrupt status register dma9_intsta dma + 04a0h dma channel 9 interrupt acknowledge register dma9_ackint dma + 04a4h dma channel 9 remaining length of current transfer dma9_rlct dma + 04a8h dma channel 9 bandwidth limiter register dma9_limiter dma + 04ach dma channel 9 programmable address register dma9_pgmaddr dma + 0508h dma channel 10 wrap point address register dma10_wppt dma + 050ch dma channel 10 wrap to address register dma10_wpto dma + 0510h dma channel 10 transfer count register dma10_count dma + 0514h dma channel 10 control register dma10_con dma + 0518h dma channel 10 start register dma10_start dma + 051ch dma channel 10 interrupt status register dma10_intsta dma + 0520h dma channel 10 interrupt acknowledge register dma10_ackint dma + 0524h dma channel 10 remaining length of current transfer dma10_rlct dma + 0528h dma channel 10 bandwidth limiter register dma10_limiter free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 92 of 1535 dma + 052ch dma channel 10 programmable address register dma10_pgmaddr dma + 0588h dma channel 11 wrap point address register dma11_wppt dma + 058ch dma channel 11 wrap to address register dma11_wpto dma + 0590h dma channel 11 transfer count register dma11_count dma + 0594h dma channel 11 control register dma11_con dma + 0598h dma channel 11 start register dma11_start dma + 059ch dma channel 11 interrupt status register dma11_intsta dma + 05a0h dma channel 11 interrupt acknowledge register dma11_ackint dma + 05a4h dma channel 11 remaining length of current transfer dma11_rlct dma + 05a8h dma channel 11 bandwidth limiter register dma11_limiter dma + 05ach dma channel 11 programmable address register dma11_pgmaddr dma + 0608h dma channel 12 wrap point address register dma12_wppt dma + 060ch dma channel 12 wrap to address register dma12_wpto dma + 0610h dma channel 12 transfer count register dma12_count dma + 0614h dma channel 12 control register dma12_con dma + 0618h dma channel 12 start register dma12_start dma + 061ch dma channel 12 interrupt status register dma12_intsta dma + 0620h dma channel 12 interrupt acknowledge register dma12_ackint dma + 0624h dma channel 12 remaining length of current transfer dma12_rlct dma + 0628h dma channel 12 bandwidth limiter register dma12_limiter dma + 062ch dma channel 12 programmable address register dma12_pgmaddr dma + 0688h dma channel 13 wrap point address register dma13_wppt dma + 068ch dma channel 13 wrap to address register dma13_wpto dma + 0690h dma channel 13 transfer count register dma13_count dma + 0694h dma channel 13 control register dma13_con dma + 0698h dma channel 13 start register dma13_start dma + 069ch dma channel 13 interrupt status register dma13_intsta dma + 06a0h dma channel 13 interrupt acknowledge register dma13_ackint dma + 06a4h dma channel 13 remaining length of current transfer dma13_rlct dma + 06a8h dma channel 13 bandwidth limiter register dma13_limiter dma + 06ach dma channel 13 programmable address register dma13_pgmaddr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 93 of 1535 dma + 0708h dma channel 14 wrap point address register dma14_wppt dma + 070ch dma channel 14 wrap to address register dma14_wpto dma + 0710h dma channel 14 transfer count register dma14_count dma + 0714h dma channel 14 control register dma14_con dma + 0718h dma channel 14 start register dma14_start dma + 071ch dma channel 14 interrupt status register dma14_intsta dma + 0720h dma channel 14 interrupt acknowledge register dma14_ackint dma + 0724h dma channel 14 remaining length of current transfer dma14_rlct dma + 0728h dma channel 14 bandwidth limiter register dma14_limiter dma + 072ch dma channel 14 programmable address register dma14_pgmaddr dma + 078ch dma channel 15 wrap to address register dma15_wpto dma + 0790h dma channel 15 transfer count register dma15_count dma + 0794h dma channel 15 control register dma15_con dma + 0798h dma channel 15 start register dma15_start dma + 079ch dma channel 15 interrupt status register dma15_intsta dma + 07a0h dma channel 15 interrupt acknowledge register dma15_ackint dma + 07a4h dma channel 15 remaining length of current transfer dma15_rlct dma + 07a8h dma channel 15 bandwidth limiter register dma15_limiter dma + 07ach dma channel 15 programmable address register dma15_pgmaddr dma + 0808h dma channel 16 wrap point address register dma16_wppt dma + 080ch dma channel 16 wrap to address register dma16_wpto dma + 0810h dma channel 16 transfer count register dma16_count dma + 0814h dma channel 16 control register dma16_con dma + 0818h dma channel 16 start register dma16_start dma + 081ch dma channel 16 interrupt status register dma16_intsta dma + 0820h dma channel 16 interrupt acknowledge register dma16_ackint dma + 0824h dma channel 16 remaining length of current transfer dma16_rlct dma + 0828h dma channel 16 bandwidth limiter register dma16_limiter dma + 082ch dma channel 16 programmable address register dma16_pgmaddr dma + 0890h dma channel 17 transfer count register dma17_count dma + 0894h dma channel 17 control register dma17_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 94 of 1535 dma + 0898h dma channel 17 start register dma17_start dma + 089ch dma channel 17 interrupt status register dma17_intsta dma + 08a0h dma channel 17 interrupt acknowledge register dma17_ackint dma + 08a8h dma channel 17 bandwidth limiter register dma17_limiter dma + 08ach dma channel 17 programmable address register dma17_pgmaddr dma + 08b0h dma channel 17 virtual fifo write pointer dma17_wrptr dma + 08b4h dma channel 17 virtual fifo read pointer dma17_rdptr dma + 08b8h dma channel 17 virtual fifo data count dma17_ffcnt dma + 08bch dma channel 17 virtual fifo status dma17_ffsta dma + 08c0h dma channel 17 virtual fifo alert length dma17_altlen dma + 08c4h dma channel 17 virtual fifo size dma17_ffsize dma + 0910h dma channel 18 transfer count register dma18_count dma + 0914h dma channel 18 control register dma18_con dma + 0918h dma channel 18 start register dma18_start dma + 091ch dma channel 18 interrupt status register dma18_intsta dma + 0920h dma channel 18 interrupt acknowledge register dma18_ackint dma + 0928h dma channel 18 bandwidth limiter register dma18_limiter dma + 092ch dma channel 18 programmable address register dma18_pgmaddr dma + 0930h dma channel 18 virtual fifo write pointer dma18_wrptr dma + 0934h dma channel 18 virtual fifo read pointer dma18_rdptr dma + 0938h dma channel 18 virtual fifo data count dma18_ffcnt dma + 093ch dma channel 18 virtual fifo status dma18_ffsta dma + 0940h dma channel 18 virtual fifo alert length dma18_altlen dma + 0944h dma channel 18 virtual fifo size dma18_ffsize dma + 0980h dma channel 19 transfer count register dma19_count dma + 0984h dma channel 19 control register dma19_con dma + 0988h dma channel 19 start register dma19_start dma + 098ch dma channel 19 interrupt status register dma19_intsta dma + 09a0h dma channel 19 interrupt acknowledge register dma19_ackint dma + 09a8h dma channel 19 bandwidth limiter register dma19_limiter dma + 09ach dma channel 19 programmable address register dma19_pgmaddr dma + 09b0h dma channel 19 virtual fifo write pointer dma19_wrptr dma + 09b4h dma channel 19 virtual fifo read pointer dma19_rdptr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 95 of 1535 dma + 09b8h dma channel 19 virtual fifo data count dma19_ffcnt dma + 09bch dma channel 19 virtual fifo status dma19_ffsta dma + 09c0h dma channel 19 virtual fifo alert length dma19_altlen dma + 09c4h dma channel 19 virtual fifo size dma19_ffsize dma + 0a00h dma channel 20 transfer count register dma20_count dma + 0a04h dma channel 20 control register dma20_con dma + 0a08h dma channel 20 start register dma20_start dma + 0a0ch dma channel 20 interrupt status register dma20_intsta dma + 0a20h dma channel 20 interrupt acknowledge register dma20_ackint dma + 0a28h dma channel 20 bandwidth limiter register dma20_limiter dma + 0a2ch dma channel 20 programmable address register dma20_pgmaddr dma + 0a30h dma channel 20 virtual fifo write pointer dma20_wrptr dma + 0a34h dma channel 20 virtual fifo read pointer dma20_rdptr dma + 0a38h dma channel 20 virtual fifo data count dma20_ffcnt dma + 0a3ch dma channel 20 virtual fifo status dma20_ffsta dma + 0a40h dma channel 20 virtual fifo alert length dma20_altlen dma + 0a44h dma channel 20 virtual fifo size dma20_ffsize dma + 0a90h dma channel 21 transfer count register dma21_count dma + 0a94h dma channel 21 control register dma21_con dma + 0a98h dma channel 21 start register dma21_start dma + 0a9ch dma channel 21 interrupt status register dma21_intsta dma + 0aa0h dma channel 21 interrupt acknowledge register dma21_ackint dma + 0aa8h dma channel 21 bandwidth limiter register dma21_limiter dma + 0aach dma channel 21 programmable address register dma21_pgmaddr dma + 0ab0h dma channel 21 virtual fifo write pointer dma21_wrptr dma + 0ab4h dma channel 21 virtual fifo read pointer dma21_rdptr dma + 0ab8h dma channel 21 virtual fifo data count dma21_ffcnt dma + 0abch dma channel 21 virtual fifo status dma21_ffsta dma + 0ac0h dma channel 21 virtual fifo alert length dma21_altlen dma + 0ac4h dma channel 21 virtual fifo size dma21_ffsize dma + 0b10h dma channel 22 transfer count register dma22_count dma + 0b14h dma channel 22 control register dma22_con dma + 0b18h dma channel 22 start register dma22_start dma + 0b1ch dma channel 22 interrupt status register dma22_intsta free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 96 of 1535 dma + 0b20h dma channel 22 interrupt acknowledge register dma22_ackint dma + 0b28h dma channel 22 bandwidth limiter register dma22_limiter dma + 0b2ch dma channel 22 programmable address register dma22_pgmaddr dma + 0b30h dma channel 22 virtual fifo write pointer dma22_wrptr dma + 0b34h dma channel 22 virtual fifo read pointer dma22_rdptr dma + 0b38h dma channel 22 virtual fifo data count dma22_ffcnt dma + 0b3ch dma channel 22 virtual fifo status dma22_ffsta dma + 0b40h dma channel 22 virtual fifo alert length dma22_altlen dma + 0b44h dma channel 22 virtual fifo size dma22_ffsize dma + 0b90h dma channel 23 transfer count register dma23_count dma + 0b94h dma channel 23 control register dma23_con dma + 0b98h dma channel 23 start register dma23_start dma + 0b9ch dma channel 23 interrupt status register dma23_intsta dma + 0ba0h dma channel 23 interrupt acknowledge register dma23_ackint dma + 0ba8h dma channel 23 bandwidth limiter register dma23_limiter dma + 0bach dma channel 23 programmable address register dma23_pgmaddr dma + 0bb0h dma channel 23 virtual fifo write pointer dma23_wrptr dma + 0bb4h dma channel 23 virtual fifo read pointer dma23_rdptr dma + 0bb8h dma channel 23 virtual fifo data count dma23_ffcnt dma + 0bbch dma channel 23 virtual fifo status dma23_ffsta dma + 0bc0h dma channel 23 virtual fifo alert length dma23_altlen dma + 0bc4h dma channel 23 virtual fifo size dma23_ffsize dma + 0c10h dma channel 24 transfer count register dma24_count dma + 0c14h dma channel 24 control register dma24_con dma + 0c18h dma channel 24 start register dma24_start dma + 0c1ch dma channel 24 interrupt status register dma24_intsta dma + 0c20h dma channel 24 interrupt acknowledge register dma24_ackint dma + 0c28h dma channel 24 bandwidth limiter register dma24_limiter dma + 0c2ch dma channel 24 programmable address register dma24_pgmaddr dma + 0c30h dma channel 24 virtual fifo write pointer dma24_wrptr dma + 0c34h dma channel 24 virtual fifo read pointer dma24_rdptr dma + 0c38h dma channel 24 virtual fifo data count dma24_ffcnt dma + 0c3ch dma channel 24 virtual fifo status dma24_ffsta free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 97 of 1535 dma + 0c40h dma channel 24 virtual fifo alert length dma24_altlen dma + 0c44h dma channel 24 virtual fifo size dma24_ffsize table 8 dma controller register map 2.6.2 register definitions register programming tips: z start registers shall be cleared, when associated channels are being programmed. z pgmaddr, i.e. programmable address, only exists in half-size dma channel s. if dir in control register is high, pgmaddr represents destination address. conversely, if dir in control register is low, pgmaddr represents source address. z functions of ring-buffer and double-buffer memory data movement can be activated on either source side or destination side by programming dma_wppt & and dma_wpto, as well as setting wpen in dma_con register high. wpsd in dma_con register determines the activated side. dma+0000h dma global status register dma_glbsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name it16 run16 it15 run15 it14 run14 it13 run13 it12 run 12 it11 run11 it10 run10 it9 run9 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name it8 run8 it7 run7 it6 run6 it5 run 5 it4 run4 it3 run3 it2 run2 it1 run1 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma+0004h dma global status 2 register dma_glbsta2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name it24 run24 it23 run23 it22 run22 it21 run21 it20 run20 it19 run19 it18 run18 it17 run17 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register helps software program keep track of the global status of dma channels. run n dma channel n status 0 channel n is stopped or has completed the transfer already. 1 channel n is currently running. it n interrupt status for channel n 0 no interrupt is generated. 1 an interrupt is pending and waiting for service. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 98 of 1535 dma+0028h dma global band width limiter register dma_glblimit er bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name glblimiter type wo reset 0 please refer to the expression in dman_limiter for detailed note. the value of dma_glblimiter is set to all dma channels, from 1 to 15. dma+0080h dma channel 1 sour ce address register dma1_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src[15:0] type r/w reset 0 the above registers contain the base or current source address that the dma channel is currently operating on. writing to this register specifies the base address of transfer source for a dma channel. before programming these registers, the software program should make sure that str in dman_start is set to 0; that is, the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. reading this register returns the address value from which the dma is reading. tcm is not accessible by dma. the source addresses register for channel 1 to channel 8 are defined in registers listed in table 9 src src [31:0] specifies the base or current address of transfer source for a dma channel write base address of transfer source read address from which dma is reading register address register function acronym dma + 0080h dma channel 1 source address register dma1_src dma + 0100h dma channel 2 source address register dma2_src dma + 0180h dma channel 3 source address register dma3_src dma + 0200h dma channel 4 source address register dma4_src dma + 0280h dma channel 5 source address register dma5_src dma + 0300h dma channel 6 source address register dma6_src dma + 0380h dma channel 7 source address register dma7_src dma + 0400h dma channel 8 source address register dma8_src free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 99 of 1535 table 9 dma source address registers list dma+0084hh dma channel 1 destination address register dma1_dst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst[15:0] type r/w reset 0 the above registers contain the base or current destination address that the dma channel is currently operating on.. writing to this register specifies the base address of the transfer destination for a dma channel. before programming these registers, the software should make sure that str in dman_start is set to ?0?; that is, the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. reading this register returns the address value to which the dma is writing. tcm is not accessible by dma. the destination addresses registers for channel 1 to channel 8 are defined in registers listed in table 10 dst dst [31:0] specifies the base or current address of transfer destination for a dma channel, i.e. channel 1~8 write base address of transfer destination. read address to which dma is writing. register address register function acronym dma + 0084h dma channel 1 destination address register dma1_dst dma + 0104h dma channel 2 destination address register dma2_dst dma + 0184h dma channel 3 destination address register dma3_dst dma + 0204h dma channel 4 destination address register dma4_dst dma + 0284h dma channel 5 destination address register dma5_dst dma + 0304h dma channel 6 destination address register dma6_dst dma + 0384h dma channel 7 destination address register dma7_dst dma + 0404h dma channel 8 destination address register dma8_dst table 10 dma destination address registers list dma+0088h dma channel 1 wrap po int count register dma1_wppt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wppt[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 100 of 1535 reset 0 the above registers are to specify the transfer count required to perform before the jump point. this can be used to support ring buffer or double buffer style memory accesses. to enable this function, two control bits, wpen and wpsd, in dma control register must be programmed. see the following register description for more details. if the transfercounter in the dma engine matches this value, an address jump occurs, and the next address is the address specified in dman_wpto. before programming these registers, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. to enable this function, wpen in dma_con is set. note that the total size of data specify in the wrap point count in a dma channel is determined by len together with the size in dman_con, i.e. wppt x size. the wrap point addresses registers for channel 1 to channel 16 are defined in registers listed in table 11 wppt wppt [15:0] specifies the amount of the transfer count from start to jumping point for a dma channel, i.e. channel 1 ? 16. write wrap point transfer count. read value set by the programmer. register address register function acronym dma + 0088h dma channel 1 wrap point address register dma1_wppt dma + 0108h dma channel 2 wrap point address register dma2_wppt dma + 0188h dma channel 3 wrap point address register dma3_wppt dma + 0208h dma channel 4 wrap point address register dma4_wppt dma + 0288h dma channel 5 wrap point address register dma5_wppt dma + 0308h dma channel 6 wrap point address register dma6_wppt dma + 0388h dma channel 7 wrap point address register dma7_wppt dma + 0408h dma channel 8 wrap point address register dma8_wppt dma + 0488h dma channel 9 wrap point address register dma9_wppt dma + 0508h dma channel 10 wrap point address register dma10_wppt dma + 0588h dma channel 11 wrap point address register dma11_wppt dma + 0608h dma channel 12 wrap point address register dma12_wppt dma + 0688h dma channel 13 wrap point address register dma13_wppt dma + 0708h dma channel 14 wrap point address register dma14_wppt dma + 0788h dma channel 15 wrap point address register dma15_wppt dma + 0808h dma channel 16 wrap point address register dma16_wppt table 11 dma wrap point address registers list dma+0080c0h dma channel 1 wrap to address register dma1_wpto bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wpto[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 101 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wpto[15:0] type r/w reset 0 the above registers specify the address of the jump destination of a given dma transfer to support ring buffer or double buffer style memory accesses. to enable this function, set the two control bits, wpen and wpsd, in the dma control register . see the following register description for more details. before programming these registers, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. to enable this function, wpen in dma_con should be set. the wrap to addresses registers for channel 1 to channel 16 are defined in registers listed in table 12 wpto wpto [31:0] specifies the address of the jump point for a dma channel, i.e. channel 1 ? 16. write address of the jump destination. read value set by the programmer. register address register function acronym dma + 008ch dma channel 1 wrap to address register dma1_wpto dma + 010ch dma channel 2 wrap to address register dma2_wpto dma + 018ch dma channel 3 wrap to address register dma3_wpto dma + 020ch dma channel 4 wrap to address register dma4_wpto dma + 028ch dma channel 5 wrap to address register dma5_wpto dma + 030ch dma channel 6 wrap to address register dma6_wpto dma + 038ch dma channel 7 wrap to address register dma7_wpto dma + 040ch dma channel 8 wrap to address register dma8_wpto dma + 048ch dma channel 9 wrap to address register dma9_wpto dma + 050ch dma channel 10 wrap to address register dma10_wpto dma + 058ch dma channel 11 wrap to address register dma11_wpto dma + 060ch dma channel 12 wrap to address register dma12_wpto dma + 068ch dma channel 13 wrap to address register dma13_wpto dma + 070ch dma channel 14 wrap to address register dma14_wpto dma + 078ch dma channel 15 wrap to address register dma15_wpto dma + 080ch dma channel 16 wrap to address register dma16_wpto table 12 dma wrap to address registers list dma+00810h dma channel 1 transfer count register dma1_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 102 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name len type r/w reset 0 this register specifies the amount of total transfer count that the dma channel is required to perform. upon completion, the dma channel generates an interrupt request to the processor while iten in dman_con is set as ?1?. note that the total size of data being transferred by a dma channel is determined by len together with the size in dman_con, i.e. len x size. for virtual fifo dma, this register is used to configure the rx threshold and tx threshold. interrupt is triggered while fifo count >= rx threshold in rx path or fifo count =< tx threshold in tx path. note that iten bit in dma_con register shall be set, or no interrupt is issued. the transfer count registers for channel 1 to channel 24 are defined in registers listed in table 13 len the amount of total transfer count register address register function acronym dma + 0090h dma channel 1 transfer count address register dma1_count dma + 0110h dma channel 2 transfer count address register dma2_count dma + 0190h dma channel 3 transfer count address register dma3_count dma + 0210h dma channel 4 transfer count address register dma4_count dma + 0290h dma channel 5 transfer count address register dma5_count dma + 0310h dma channel 6 transfer count address register dma6_count dma + 0390h dma channel 7 transfer count address register dma7_count dma + 0410h dma channel 8 transfer count address register dma8_count dma + 0490h dma channel 9 transfer count address register dma9_count dma + 0510h dma channel 10 transfer count address register dma10_count dma + 0590h dma channel 11 transfer count address register dma11_count dma + 0610h dma channel 12 transfer count address register dma12_count dma + 0690h dma channel 13 transfer count address register dma13_count dma + 0710h dma channel 14 transfer count address register dma14_count dma + 0790h dma channel 15 transfer count address register dma15_count dma + 0810h dma channel 16 transfer count address register dma16_count dma + 0890h dma channel 17 transfer count address register dma17_count dma + 0910h dma channel 18transfer count address register dma18_count dma + 0990h dma channel 19 transfer count address register dma19_count dma + 0a10h dma channel 20 transfer count address register dma20_count dma + 0a90h dma channel 21 transfer count address register dma21_count dma + 0b10h dma channel 22 transfer count address register dma22_count dma + 0b90h dma channel 23 transfer count address register dma23_count free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 103 of 1535 dma + 0c10h dma channel 24 transfer count address register dma24_count table 13 dma transfer count registers list dma+00814h dma channel 1 co ntrol register dma1_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mas dir wpen wpsd type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iten burst b2w drq dinc sinc size type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 this register contains all the available control schemes for a dma channel that is ready for software programmer to configure. note that all these fields cannot be changed while dma transfer is in progress or an unexpected situation may occur. the transfer count registers for channel 1 to channel 24 are defined in registers listed in table 14 . size data size within the confine of a bus cycle per transfer. these bits confines the data transfer size between source and destination to the specified value for individual bus cycle. the size is in terms of byte and has maximum value of 4 bytes. it is mainly decided by the data width of a dma master. 00 byte transfer/1 byte 01 half-word transfer/2 bytes 10 word transfer/4 bytes 11 reserved sinc incremental source address. source addresses increase every transfer. if the setting of size is byte, source addresses increase by 1 every single transfer. if half-word, increase by 2; and if word, increase by 4. 0 disable 1 enable dinc incremental destination address. destination addresses increase every transfer. if the setting of size is byte, destination addresses increase by 1 every single transfer. if half-word, increase by 2; and iif word, increase by 4. 0 disable 1 enable dreq throttle and handshake control for dma transfer 0 no throttle control during dma transfer or transfers occurred only between memories 1 hardware handshake management the dma master is able to throttle down the transfer rate by way of request-grant handshake. b2w word to byte or byte to word transfer for the applications of transferring non-word-aligned-address data to word-aligned-address data. note that burst is set to 4-beat burst while enabling this function and the size is set to byte. no effect on channel 1 ? 8 & 17 - 24. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 104 of 1535 0 disable 1 enable burst transfer type. burst-type transfers have better bus efficiency. mass data movement is recommended to use this kind of transfer. however, note that burst-type transfer does not stop until all of the beats in a burst are completed or transfer length is reached. fifo threshold of peripherals must be configured carefully while being used to move data from/to the peripherals. what transfer type can be used is restricted by the size. if size is 00b, i.e. byte transfer, all of the four transfer types can be used. if size is 01b, i.e. half-word transfer, 16-beat incrementing burst cannot be used. if size is 10b, i.e. word transfer, only single and 4-beat incrementing burst can be used. no effect on channel 17 - 24. 000 single 001 reserved 010 4-beat incrementing burst 011 reserved 100 8-beat incrementing burst 101 reserved 110 16-beat incrementing burst 111 reserved iten dma transfer completi on interrupt enable. 0 disable 1 enable wpsd the side using address-wrapping function. only one side of a dma channel can activate address- wrapping function at a time. no effect on channel 17-24 0 address-wrapping on source. 1 address-wrapping on destination. wpen address-wrapping for ring buffer and double buffer. the next address of dma jumps to wrap to address when the current address matches wrap point count. no effect on channel 17-24 0 disable 1 enable dir directions of dma transfer for half-size and virtual fifo dma channels, i.e. channels 4~14. the direction is from the perspective of the dma masters. write means read from master and then write to the address specified in dma_pgmaddr, and vice versa. no effect on channel 1-8 0 read 1 write mas master selection. specifies which master occupies this dma channel. once assigned to certain master, the corresponding dreq and dack are connected. for half-size and virtual fifo dma channels, i.e. channels 9 ~ 15, a predefined address is assigned as well. 00000 sim2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 105 of 1535 00001 msdc1 00010 msdc2 00011 irda tx 00100 irda rx 00101 uart1 tx 00110 uart1 rx 00111 uart2 tx 01000 uart2 rx 01001 uart3 tx 01010 uart3 rx 01011 nfi tx 01100 nfi rx 01101 vfe 01110 i2c tx 01111 i2c rx 10000 uart4 tx 10001 uart4 rx 10010 msdc3 others reserved register address register function acronym dma + 0094h dma channel 1 control register dma1_con dma + 0114h dma channel 2 control register dma2_con dma + 0194h dma channel 3 control register dma3_con dma + 0214h dma channel 4 control register dma4_con dma + 0294h dma channel 5 control register dma5_con dma + 0314h dma channel 6 control register dma6_con dma + 0394h dma channel 7 control register dma7_con dma + 0414h dma channel 8 control register dma8_con dma + 0494h dma channel 9 control register dma9_con dma + 0514h dma channel 10 control register dma10_con dma + 0594h dma channel 11 control register dma11_con dma + 0614h dma channel 12 control register dma12_con dma + 0694h dma channel 13 control register dma13_con dma + 0714h dma channel 14 control register dma14_con dma + 0794h dma channel 15 control register dma15_con dma + 0814h dma channel 16 control register dma16_con dma + 0894h dma channel 17 control register dma17_con dma + 0914h dma channel 18control register dma18_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 106 of 1535 dma + 0994h dma channel 19 control register dma19_con dma + 0a14h dma channel 20 control register dma20_con dma + 0a94h dma channel 21 control register dma21_con dma + 0b14h dma channel 22 control register dma22_con dma + 0b94h dma channel 23 control register dma23_con dma + 0c14h dma channel 24 control register dma24_con table 14 dma control registers list dma+0098h dma channel 1 st art register dma1_start bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of a dma channel. when str is changed from 0 to 1, the dma channel starts to work. note that prior to setting str to ?1?, all the configurations should be done by giving proper value to the registers. note also that once the str is set to ?1?, the hardware does not clear it automatically no matter if the dma channel accomplishes the dma transfer or not. in other words, the value of str stays ?1? regardless of the completion of dma transfer. therefore, the software program should be sure to clear str to ?0? for starting another transfer for the same dma channel. if this bit is cleared to ?0? during dma transfer is active, software should polling dma_glbsta run n after this bit is cleared to ensure current dma transfer is terminated by dma engine. the dma start registers for channel 1 to channel 24 are defined in registers listed in table 15 str start control for a dma channel. 0 the dma channel is stopped. 1 the dma channel is started and running register address register function acronym dma + 0098h dma channel 1 start register dma1_start dma + 0118h dma channel 2 start register dma2_start dma + 0198h dma channel 3 start register dma3_start dma + 0218h dma channel 4 start register dma4_start dma + 0298h dma channel 5 start register dma5_start dma + 0318h dma channel 6 start register dma6_start dma + 0398h dma channel 7 start register dma7_start dma + 0418h dma channel 8 start register dma8_start dma + 0498h dma channel 9 start register dma9_start free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 107 of 1535 dma + 0518h dma channel 10 start register dma10_start dma + 0598h dma channel 11 start register dma11_start dma + 0618h dma channel 12 start register dma12_start dma + 0698h dma channel 13 start register dma13_start dma + 0718h dma channel 14 start register dma14_start dma + 0798h dma channel 15 start register dma15_start dma + 0818h dma channel 16 start register dma16_start dma + 0898h dma channel 17 start register dma17_start dma + 0918h dma channel 18start register dma18_start dma + 0998h dma channel 19 start register dma19_start dma + 0a18h dma channel 20 start register dma20_start dma + 0a98h dma channel 21 start register dma21_start dma + 0b18h dma channel 22 start register dma22_start dma + 0b98h dma channel 23 start register dma23_start dma + 0c18h dma channel 24 start register dma24_start table 15 dma start registers list . dma+009ch dma channel 1 interrupt status register dma1_intsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name int type ro reset 0 this register shows the interrupt status of a dma channel. it has the same value as dma_glbsta. the dma interrupt status registers for channel 1 to channel 24 are defined in registers listed in table 16 int interrupt status for dma channel 0 no interrupt requ est is generated. 1 one interrupt request is pend ing and waiting for service. register address register function acronym dma + 009ch dma channel 1 interrupt status register dma1_intsta dma + 011ch dma channel 2 interrupt status register dma2_intsta dma + 019ch dma channel 3 interrupt status register dma3_intsta dma + 021ch dma channel 4 interrupt status register dma4_intsta dma + 029ch dma channel 5 interrupt status register dma5_intsta free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 108 of 1535 dma + 031ch dma channel 6 interrupt status register dma6_intsta dma + 039ch dma channel 7 interrupt status register dma7_intsta dma + 041ch dma channel 8 interrupt status register dma8_intsta dma + 049ch dma channel 9 interrupt status register dma9_intsta dma + 051ch dma channel 10 interrupt status register dma10_intsta dma + 059ch dma channel 11 interrupt status register dma11_intsta dma + 061ch dma channel 12 interrupt status register dma12_intsta dma + 069ch dma channel 13 interrupt status register dma13_intsta dma + 071ch dma channel 14 interrupt status register dma14_intsta dma + 079ch dma channel 15 interrupt status register dma15_intsta dma + 081ch dma channel 16 interrupt status register dma16_intsta dma + 089ch dma channel 17 interrupt status register dma17_intsta dma + 091ch dma channel 18interrupt status register dma18_intsta dma + 099ch dma channel 19 interrupt status register dma19_intsta dma + 0a1ch dma channel 20 interrupt status register dma20_intsta dma + 0a9ch dma channel 21 interrupt status register dma21_intsta dma + 0b1ch dma channel 22 interrupt status register dma22_intsta dma + 0b9ch dma channel 23 interrupt status register dma23_intsta dma + 0c1ch dma channel 24 interrupt status register dma24_intsta table 16 dma interrupt status registers list dma+00a0h dma channel n interrupt acknowledge regist er dma1_ackint bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ack type wo reset 0 this register is used to acknowledge the current interrupt request associated with the completion event of a dma channel by software program. note that this is a write-only register, and any read to it returns a value of ?0?. the dma interrupt acknowledge registers for channel 1 to channel 24 are defined in registers listed in table 17 ack interrupt acknowledge for the dma channel 0 no effect 1 interrupt request is acknowledged and should be relinquished. register address register function acronym free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 109 of 1535 dma + 00a0h dma channel 1 interrupt acknowledge register dma1_ackint dma + 0120h dma channel 2 interrupt acknowledge register dma2_ackint dma + 01a0h dma channel 3 interrupt acknowledge register dma3_ackint dma + 0220h dma channel 4 interrupt acknowledge register dma4_ackint dma + 02a0h dma channel 5 interrupt acknowledge register dma5_ackint dma + 0320h dma channel 6 interrupt acknowledge register dma6_ackint dma + 03a0h dma channel 7 interrupt acknowledge register dma7_ackint dma + 0420h dma channel 8 interrupt acknowledge register dma8_ackint dma + 04a0h dma channel 9 interrupt acknowledge register dma9_ackint dma + 0520h dma channel 10 interrupt acknowledge register dma10_ackint dma + 05a0h dma channel 11 interrupt acknowledge register dma11_ackint dma + 0620h dma channel 12 interrupt acknowledge register dma12_ackint dma + 06a0h dma channel 13 interrupt acknowledge register dma13_ackint dma + 0720h dma channel 14 interrupt acknowledge register dma14_ackint dma + 07a0h dma channel 15 interrupt acknowledge register dma15_ackint dma + 0820h dma channel 16 interrupt acknowledge register dma16_ackint dma + 08a0h dma channel 17 interrupt acknowledge register dma17_ackint dma + 0920h dma channel 18interrupt acknowledge register dma18_ackint dma + 09a0h dma channel 19 interrupt acknowledge register dma19_ackint dma + 0a20h dma channel 20 interrupt acknowledge register dma20_ackint dma + 0aa0h dma channel 21 interrupt acknowledge register dma21_ackint dma + 0b20h dma channel 22 interrupt acknowledge register dma22_ackint dma + 0ba0h dma channel 23 interrupt acknowledge register dma23_ackint dma + 0c20h dma channel 24 interrupt acknowledge register dma24_ackint table 17 dma interrupt acknowledge registers list dma+00a4h dma channel 1 remaining length of current transfer dma1_rlct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rlct type ro reset 0 this register is to reflect the left count of the transfer . note that this value is tr ansfer count not the transfer data size. the dma remaining length of current transfer registers for channel 1 to channel 24 are defined in registers listed in table 18 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 110 of 1535 register address register function acronym dma + 00a4h dma channel 1 remaining length of current transfer register dma1_rlct dma + 0124h dma channel 2 remaining length of current transfer register dma2_rlct dma + 01a4h dma channel 3 remaining length of current transfer register dma3_rlct dma + 0224h dma channel 4 remaining length of current transfer register dma4_rlct dma + 02a4h dma channel 5 remaining length of current transfer register dma5_rlct dma + 0324h dma channel 6 remaining length of current transfer register dma6_rlct dma + 03a4h dma channel 7 remaining length of current transfer register dma7_rlct dma + 0424h dma channel 8 remaining length of current transfer register dma8_rlct dma + 04a4h dma channel 9 remaining length of current transfer register dma9_rlct dma + 0524h dma channel 10 remaining length of current transfer register dma10_rlct dma + 05a4h dma channel 11 remaining length of current transfer register dma11_rlct dma + 0624h dma channel 12 remaining length of current transfer register dma12_rlct dma + 06a4h dma channel 13 remaining length of current transfer register dma13_rlct dma + 0724h dma channel 14 remaining length of current transfer register dma14_rlct dma + 07a4h dma channel 15 remaining length of current transfer register dma15_rlct dma + 0824h dma channel 16 remaining length of current transfer register dma16_rlct dma + 08a4h dma channel 17 remaining length of current transfer register dma17_rlct dma + 0924h dma channel 18remaining length of current transfer register dma18_rlct dma + 09a4h dma channel 19 remaining length of current transfer register dma19_rlct dma + 0a24h dma channel 20 remaining length of current transfer register dma20_rlct dma + 0aa4h dma channel 21 remaining length of current transfer dma21_rlct free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 111 of 1535 register dma + 0b24h dma channel 22 remaining length of current transfer register dma22_rlct dma + 0ba4h dma channel 23 remaining length of current transfer register dma23_rlct dma + 0c24h dma channel 24 remaining length of current transfer register dma24_rlct table 18 dma remaining length of current transfer registers list dma+00a8h dma channel 1 bandwidth limiter register dma1_limiter bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limiter type r/w reset 0 this register is to suppress the bus utilization of the dma channel. the va lue is from 0 to 255. 0 means no limitation, and 255 means totally banned. the value between 0 and 255 means certain dma can have permission to use ahb every (4 x n) ahb clock cycles. note that it is not recommended to limit the bus utiliz ation of the dma channels because this increases the latency of response to the masters, and the transfer rate decreases as well. before using it, programmer must make sure that the bus masters have some protective mechanism to avoid entering the wrong states. the dma bandwidth limiter registers for channel 1 to channel 24 are defined in registers listed in table 19 limiter from 0 to 255. 0 means no limitation, 255 means totally banned, and others mean bus access permission every (4 x n) ahb clock. register address register function acronym dma + 00a8h dma channel 1 bandwidth limiter register dma1_limiter dma + 0128h dma channel 2 bandwidth limiter register dma2_limiter dma + 01a8h dma channel 3 bandwidth limiter register dma3_limiter dma + 0228h dma channel 4 bandwidth limiter register dma4_limiter dma + 02a8h dma channel 5 bandwidth limiter register dma5_limiter dma + 0328h dma channel 6 bandwidth limiter register dma6_limiter dma + 03a8h dma channel 7 bandwidth limiter register dma7_limiter dma + 0428h dma channel 8 bandwidth limiter register dma8_limiter dma + 04a8h dma channel 9 bandwidth limiter register dma9_limiter dma + 0528h dma channel 10 bandwidth limiter register dma10_limiter dma + 05a8h dma channel 11 bandwidth limiter register dma11_limiter dma + 0628h dma channel 12 bandwidth limiter register dma12_limiter free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 112 of 1535 dma + 06a8h dma channel 13 bandwidth limiter register dma13_limiter dma + 0728h dma channel 14 bandwidth limiter register dma14_limiter dma + 07a8h dma channel 15 bandwidth limiter register dma15_limiter dma + 0828h dma channel 16 bandwidth limiter register dma16_limiter dma + 08a8h dma channel 17 bandwidth limiter register dma17_limiter dma + 0928h dma channel 18bandwidth limiter register dma18_limiter dma + 09a8h dma channel 19 bandwidth limiter register dma19_limiter dma + 0a28h dma channel 20 bandwidth limiter register dma20_limiter dma + 0aa8h dma channel 21 bandwidth limiter register dma21_limiter dma + 0b28h dma channel 22 bandwidth limiter register dma22_limiter dma + 0ba8h dma channel 23 bandwidth limiter register dma23_limiter dma + 0c28h dma channel 24 bandwidth limiter register dma24_limiter table 19 dma bandwidth limiter registers list dma+04ach dma channel 9 pr ogrammable address register dma9_pgmad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pgmaddr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pgmaddr[15:0] type r/w reset 0 the above registers specify the address for a half-size dma channel. this address represents a source address if dir in dma_con is set to 0, and represents a destination address if dir in dma_con is set to 1. before being able to program these register, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. the dma programmable address registers for channel 1 to channel 24 are defined in registers listed in table 20 note that n is from 9 to 24 and pgmaddr can?t be tcm address. tcm is not accessible by dma. pgmaddr pgmaddr [31:0] specifies the addresses for a half-size or a virtual fifo dma channel, i.e. channel 9 ? 24. write base address of transfer source or destination according to dir bit. read current address of the transfer. register address register function acronym dma + 04ach dma channel 9 programmable address register dma9_pgmaddr dma + 052ch dma channel 10 programmable address register dma10_pgmaddr dma + 05ach dma channel 11 programmable address register dma11_pgmaddr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 113 of 1535 dma + 062ch dma channel 12 programmable address register dma12_pgmaddr dma + 06ach dma channel 13 programmable address register dma13_pgmaddr dma + 072ch dma channel 14 programmable address register dma14_pgmaddr dma + 07ach dma channel 15 programmable address register dma15_pgmaddr dma + 082ch dma channel 16 programmable address register dma16_pgmaddr dma + 08ach dma channel 17 programmable address register dma17_pgmaddr dma + 092ch dma channel 18 programmable address register dma18_pgmaddr dma + 09ach dma channel 19 programmable address register dma19_pgmaddr dma + 0a2ch dma channel 20 programmable address register dma20_pgmaddr dma + 0aach dma channel 21 programmable address register dma21_pgmaddr dma + 0b2ch dma channel 22 programmable address register dma22_pgmaddr dma + 0bach dma channel 23 programmable address register dma23_pgmaddr dma + 0c2ch dma channel 24 programmable address register dma24_pgmaddr table 205 dma programmable address registers list dma+08b0h dma channel 17 virtual fifo write pointer register dma17_wrptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wrptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrptr[15:0] type ro the dma virtual fifo write pointer registers for channel 17 to channel 24 are defined in registers listed in table 21 wrptr virtual fifo write pointer. register address register function acronym dma + 08b0h dma channel 17 virtual fifo write pointer register dma17_wrptr dma + 0930h dma channel 18 virtual fifo write pointer register dma18_wrptr dma + 09b0h dma channel 19 virtual fifo write pointer register dma19_wrptr dma + 0a30h dma channel 20 virtual fifo write pointer register dma20_wrptr dma + 0ab0h dma channel 21 virtual fifo write pointer register dma21_wrptr dma + 0b30h dma channel 22 virtual fifo write pointer register dma22_wrptr dma + 0bb0h dma channel 23 virtual fifo write pointer register dma23_wrptr dma + 0c30h dma channel 24 virtual fifo write pointer register dma24_wrptr table 21 dma virtual fifo write pointer registers list dma+08b4h dma channel 17 virtual fifo read pointer register dma17_rdptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 114 of 1535 name rdptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rdptr[15:0] type ro the dma virtual fifo read pointer registers for channel 17 to channel 24 are defined in registers listed in table 22 rdptr virtual fifo read pointer. register address register function acronym dma + 08b4h dma channel 17 virtual fifo read pointer register dma17_rdptr dma + 0934h dma channel 18 virtual fifo read pointer register dma18_rdptr dma + 09b4h dma channel 19 virtual fifo read pointer register dma19_rdptr dma + 0a34h dma channel 20 virtual fifo read pointer register dma20_rdptr dma + 0ab4h dma channel 21 virtual fifo read pointer register dma21_rdptr dma + 0b34h dma channel 22 virtual fifo read pointer register dma22_rdptr dma + 0bb4h dma channel 23 virtual fifo read pointer register dma23_rdptr dma + 0c34h dma channel 24 virtual fifo read pointer register dma24_rdptr table 227 dma virtual fifo read pointer registers list dma+08b8h dma channel 17 virtual fi fo data count register dma17_ffcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ffcnt type ro the dma virtual fifo data count registers for channel 17 to channel 24 are defined in registers listed in table 23 ffcnt to display the number of data stored in fifo. 0 means fifo empty, and fifo is full if ffcnt is equal to ffsize. register address register function acronym dma + 08b8h dma channel 17 virtual fifo data count register dma17_ffcnt dma + 0938h dma channel 18 virtual fifo data count register dma18_ffcnt dma + 09b8h dma channel 19 virtual fifo data count register dma19_ffcnt dma + 0a38h dma channel 20 virtual fifo data count register dma20_ffcnt dma + 0ab8h dma channel 21 virtual fifo data count register dma21_ffcnt dma + 0b38h dma channel 22 virtual fifo data count register dma22_ffcnt free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 115 of 1535 dma + 0bb8h dma channel 23 virtual fifo data count register dma23_ffcnt dma + 0c38h dma channel 24 virtual fifo data count register dma24_ffcnt table 23 dma virtual fifo data count registers list dma+08bch dma channel 17 virtual fifo status register dma17_ffsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt empt y full type ro ro ro reset 0 1 0 the dma virtual fifo status registers for channel 17 to channel 24 are defined in registers listed in table 24 full to indicate fifo is full. 0 not full 1 full empty to indicate fifo is empty. 0 not empty 1 empty alt to indicate fifo count is larger than altlen. dma issues an alert signal to uart to enable uart flow control. 0 not reach alert region. 1 reach alert region. register address register function acronym dma + 08bch dma channel 17 virtual fifo status register dma17_ffsta dma + 093ch dma channel 18 virtual fifo status register dma18_ffsta dma + 09bch dma channel 19 virtual fifo status register dma19_ffsta dma + 0a3ch dma channel 20 virtual fifo status register dma20_ffsta dma + 0abch dma channel 21 virtual fifo status register dma21_ffsta dma + 0b3ch dma channel 22 virtual fifo status register dma22_ffsta dma + 0bbch dma channel 23 virtual fifo status register dma23_ffsta dma + 0c3ch dma channel 24 virtual fifo status register dma24_ffsta table 24 dma virtual fifo status registers list dma+08c0h dma channel 17 virtua l fifo alert length register dma17_altle n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 116 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name altlen type r/w reset 0 the dma virtual fifo alert length registers for channel 17 to channel 24 are defined in registers listed in table 25 altlen specifies the alert length of virtual fifo dma. once the remaining fifo space is less than altlen, an alert signal is issued to uart to enable flow control. normally, altlen shall be larger than 16 for uart application. register address register function acronym dma + 08c0h dma channel 17 virtual fifo alert length register dma17_altlen dma + 0940h dma channel 18 virtual fifo alert length register dma18_altlen dma + 09c0h dma channel 19 virtual fifo alert length register dma19_altlen dma + 0a40h dma channel 20 virtual fifo alert length register dma20_altlen dma + 0ac0h dma channel 21 virtual fifo alert length register dma21_altlen dma + 0b40h dma channel 22 virtual fifo alert length register dma22_altlen dma + 0bc0h dma channel 23 virtual fifo alert length register dma23_altlen dma + 0c40h dma channel 24 virtual fifo alert length register dma24_altlen table 25 dma virtual fifo alert length registers list dma+08c4h dma channel 17 virtual fifo size register dma17_ffsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ffsize type r/w reset 0 the dma virtual fifo size registers for channel 17 to channel 24 are defined in registers listed in table 26 ffsize specifies the fifo size of virtual fifo dma. register address register function acronym dma + 08c4h dma channel 17 virtual fifo size register dma17_ffsize dma + 0944h dma channel 18 virtual fifo size register dma18_ffsize dma + 09c4h dma channel 19 virtual fifo size register dma19_ffsize dma + 0a44h dma channel 20 virtual fifo size register dma20_ffsize dma + 0ac4h dma channel 21 virtual fifo size register dma21_ffsize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 117 of 1535 dma + 0b44h dma channel 22 virtual fifo size register dma22_ffsize dma + 0bc4h dma channel 23 virtual fifo size register dma23_ffsize dma + 0c44h dma channel 24 virtual fifo size register dma24_ffsize table 26 dma virtual fifo size registers list 2.7 ap config register 2.7.1 apb bridge register map register address register name synonym 8000_1000h hardware version register hw_ver 8000_1004h software version register sw_ver 8000_1008h hardware code register hw_code 8000_1010h software misc. low register sw_misc_l 8000_1014h software misc. high register sw_misc_h 8000_1020h hardware misc. register hw_misc 8000_1100h arm9 frequency division register arm9_freq_div 8000_1204h sleep control register sleep_con 8000_1208h mcu clock control register mcuclk_con 8000_120ch emi clock control register emiclk_con 8000_1300h subsystem output isolation register iso_en 8000_1304h subsystem power down register pwr_off 8000_1308h apmcusys memory power down register mcu_mem_pdn 8000_130ch graph1sys memory power down register g1_mem_pdn 8000_1310h graph2sys memory power down register g2_mem_pdn 8000_1314h cevasys memory power down register ceva_mem_pdn 8000_1318h subsystem input isolation register in_iso_en 8000_131ch subsystem power ack register pwr_ack 8000_1320h subsystem ack clear register ack_clr 8000_1404h apb bus control register apb_con 8000_1408h security boot register security_reg 8000_1500h io driving control register 0 io_drv0 8000_1504h io driving control register 1 io_drv1 8000_1600h instruction cache size control register ic_size 8000_1604h data cache size control register dc_size 8000_1608h mdvcxo_off register mdvcxo_off free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 118 of 1535 2.7.2 register definitions 8000_1000h hardware version register hw_version bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extp majrev minrev type ro ro ro ro reset 8 a 0 0 this register is used by software to determine the hardware version of the chip. the register contains a new value whenever each metal fix or major step is performed. all values are incremented by a step of 1. minrev minor revision of the chip majrev major revision of the chip extp this field shows the existence of hardware code register that presents the hardware id while the value is other than zero. 8000_1004h software version register sw_version bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extp majrev minrev type ro ro ro ro reset 8 a 0 0 this register is used by software to determine the so ftware version used with this chip. all values are incremented by a step of 1. minrev minor revision of the software majrev major revision of the software extp this field shows the existence of hardware code register that presents the hardware id when the value is other than zero. 8000_1008h hardware code register hw_code bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name code3 code2 code1 code0 type ro ro ro ro reset 6 5 1 6 this register presents the hardware id. code1 & code0 can be programmed by efuse_dout[61:54]. 8000_1010h software misc low register sw_misc_l bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sw_misc_l type r/w reset 0 spare registers for software control. 8000_1014h software misc high register sw_misc_h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 119 of 1535 name sw_misc_h type r/w reset 0 spare registers for software control. 8000_1020h hardware misc register hw_misc bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md_b oot_ only nirq_ mask mask _gmc 2 mask _gmc 1 ceva dbg_ en nfi_s el sim2_ sel uart4 _sel uart3 _sel uart2 _sel uart1 _sel gmc_ auto cg usb_ sel type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 xcore 0 0 0 0 1 1 1 spare registers for platform control. usb_sel usb selection. 0 ap use the usb. 1 md use the usb. gmc_autocg hw automatic clock gating for gmc 0 disable 1 enable uartx_sel uart selection. 0 ap use the uartx. 1 md use the uartx. sim2_sel sim2 selection. 0 ap use the sim2. 1 md use the sim2. nfi_sel this bit is used to set which domain nfi can ac cess. ap and md still can control the nfi no matter what you set this register 0 nfi can access md domain. 1 nfi can access ap domain. cevadbg_en ceva debug request 0 disable 1 enable mask_gmc1 this bit is used to mask gmc clock gating bit in emi slow idle condition 0 un-mask gmc clock gating constraint. that is gmc clock must be gated before emi slow down. 1 mask gmc clock gating constraint. emi can directly enter the slow idle mode without gmc clock gating constraint. mask_gmc2 this bit is used to mask gmc clock gating bit in emi slow idle condition 0 un-mask gmc clock gating constraint. that is gmc clock must be gated before emi slow down. 1 mask gmc clock gating constraint. emi can directly enter the slow idle mode without gmc clock gating constraint. nirq_mask this bit is used to mask sleep controller?s wakeup signal, this signal is come from interrupt controller?s nirq signal. 0 un-mask free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 120 of 1535 1 mask md_boot_only this bit is used to let md standalone rise pll frequency without waking up ap side. 0 disable 1 enable this function 8000_1100h arm9 frequency division register arm9_freq_div bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arm9_freq_ div type r/w reset 0 arm9_freq_div 00 arm9 clock is divided by 1, i.e. 416 mhz 01 reserved 10 arm9 clock is divided by 2, i.e. 208 mhz 11 arm9 clock is divided by 4, i.e. 104 mhz note : 1. this register can be changed only if the source clock is switched to pll. 2. the clock rate may not change immediately after the software sets this register. for any case which needs to assure that the clock really changes, you can read this register and wait until it becomes to the value that you specify. 8000_1204h sleep control register sleep_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fmcu _2x_di v_en fmcu _div_ en f48m md_a ct_b ceva ddr ahb type r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 icor e 1 0 0 ahb stop the ahb bus clock to force the entire bus to enter sleep mode. ahb clock will be resumed as long as there is an interrupt request or system is reset. 0 ahb bus clock is running 1 ahb bus clock is stopped note: before entering bus sleep mode, you must ensure that ceva, graph1sys, and graph2sys are not active. ddr stop the ddr clock. 0 ddr clock is running 1 ddr clock is stopped ceva stop the ceva clock. 0 ceva clock is stopped 1 ceva clock is running md_act_b active md mcu. the system boots from ap mcu by default (icore = 1) . after ap mcu finish the initialization of the memory and system setting for md mcu. ap mcu can set the bit as free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 121 of 1535 ?0? to activate md mcu. the md mcu will boot from md_vector. md_vector is specified by ap and the value is store in emi. whenever md mcu access emi, and address issued to external bus is addr + md_vector. 0 active md mcu 1 disable md mcu. (md mcu clock stops) f48m stop the f48m clock. 0 f48m clock is running 1 f48m clock is stopped note: before switching the source clock to pll, you should set both fmcu_div_en and fmcu_2x_div_en to 1 first, and then keep polling the registers until these two bits became 1. this procedure is a safe way to inform arm9 to switch the clock ratio of cpu to bus clocks, otherwise it might cause cpu crash. fmcu_4x_ck mixedsys u_clock_switch mcu_switch p l l 26mhz 26/13 mhz fmcu_ck fmcu_2x_ck (emi_2x_ck) (arm7_ck, emi_1x_ck, ahb_ck, apb_ck) garm_ck (arm9_ck) mpll_sel fmcu_2x_div_en 1/2 fmcu_div_en 1/2 figure 1 clock scheme fmcu_div_en enable fmcu_ck frequency division 0 disable 1 enable fmcu_2x_div_en enable fmcu_2x_ck frequency division 0 disable 1 enable 8000_1208h mcu clock control register mcuclk_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mcu_fsel type r/w reset 7 mcu_fsel mcu clock frequency selection. this control register is used to control the output clock frequency of mcu dynamic clock manager. the clock frequency is from 13mhz to 104mhz. the waveforms of the output clock are shown below. this setting only takes effect when the bus has no any transaction and ahb bus clock has been stopped. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 122 of 1535 104mhz 52mhz 26mhz 13mhz figure 2 output of dynamic clock manager high speed bus low speed bus 0 13mhz 13mhz 1 26mhz 26mhz 2 reserved reserved 3 52mhz 52mhz 4 reserved reserved 5 reserved reserved 6 reserved reserved 7 104mhz 52mhz others reserved 8000_1 20ch emi clock control register emiclk_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name emiclk_con type r/w reset 0 emiclk_con[4:0] emi clock frequency selection 00000 3.25mhz 00001 6.5mhz 00011 13mhz 00111 26mhz 01111 52mhz 11111 104mhz others reserved this register takes effect only when the following conditions are all true. 1. ap and md ahb buses enter the sleep mode 2. gmc1, gmc2, and ceva are all clock gating note: before entering emi slow idle mode, you must ensure that ceva, graph1sys, and graph2sys are not active. 8000_1300h subsystem output isolation register iso_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_ iso_e n grap h2_is o_en grap h1_is o_en type r/w r/w r/w reset 0 0 0 sub-system output isolation control free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 123 of 1535 graph1_iso_en controls the graph1sys output signal isolation graph2_iso_en controls the graph2sys output signal isolation ceva_iso_en controls the cevasys output signal isolation 8000_1304h subsystem power down register pwr_off bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_ pdn grap h2_pd n grap h1_pd n type r/w r/w r/w reset 0 0 0 sub-system power down control graph1_pdn controls the graph1sys power down graph2_pdn controls the graph2sys power down ceva_pdn controls the cevasys power down 8000_1308h mcusys memory power down register mcu_mem_pd n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name l1_tc m l1_ca che md_s ysro m etb type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ccif usb ap_sy srom dtcm itcm mmu dc_16 kb dc ic_16k b ic type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 mcusys memory power down control ic controls the lower instruction cache memory power down ic_16kb controls the upper instruction cache memory power down, when the cache configuration is 16kb, you should power down this memory block. dc controls the lower data cache memory power down dc_16kb controls the upper data cache memory power down, when the cache configuration is 16kb, you should power down this memory block. mmu controls the mmu memory power down itcm controls the itcm memory power down dtcm controls the dtcm memory power down ap_sysrom controls the ap sysrom power down usb contorl the usb memory power down ccif control the ccif memory power down etb control the csdbg memory power down md_sysrom controls the md sysrom power down l1_cache controls the l1 cache memory power down free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 124 of 1535 l1_tcm controls the l1 tcm memory power down 8000_1 30ch graph1sys memory power down register g1_mem_pdn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam resz imgd ma tvc lcd wave asm afe dpi dsi type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 graph1sys memory power down control dsi controls the dsi memory power down dpi controls the dpi memory power down afe controls the afe memory power down asm controls the asm memory power down wave contorl the wave memory power down lcd control the lcd memory power down tvc control the tvc memory power down imgdma controls the imgdma memory power down resz controls the resz cache memory power down cam controls the cam memory power down 8000_1310h graph2sys memory power down register g2_mem_pdn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d type r/w reset 0 graph2sys memory power down control m3d controls the m3d memory power down 8000_1 314h cevasys memory power down register ceva_mem_pd n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ccif l2_mem_pdn l1_mem_pdn type r/w r/w r/w reset 0 0 0 cevasys memory power down control l1_mem_dn controls the l1 memory power down l2_mem_dn controls the l2 memory power down ccif controls the ccif memory power down 8000_1318h subsystem input isolation register in_iso_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_ in_iso grap h2_in_ iso grap h1_in_ iso type r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 125 of 1535 reset 0 0 0 sub-system output isolation control graph1_in_iso controls the graph1sys input signal isolation graph2_in_iso controls the graph2sys input signal isolation ceva_in_iso controls the cevasys in put signal isolation 8000_1 31ch subsystem power ack register pwr_ack bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _pwr _ack g1_p wr_a ck g2_p wr_a ck ceva _pwr _ack type ro ro ro ro reset 0 0 1 1 this register is used to indicate if the power down subsystem had powered up already. 8000_1320h clear subsystem power ack register ack_clr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _pwr _ack g1_p wr_a ck g2_p wr_a ck ceva _pwr _ack type wo wo wo wo reset 0 0 0 0 note: before using the power ack register to monitor the power ack of subsystems, you should clear powr ack registers first after powering down subsystems. writing to the corresponding ?clear? bit will perform a bit clear function. eg. if pwr_ack = 16?h000f, writing ack_clr = 16?000a will result in pwr_ack = 16?h0005 8000_1404h apb bus control register apb_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apbw 6 apbw 5 apbw 4 apbw 3 apbw 2 apbw 1 apbw 0 apbr6 apbr5 apbr4 apbr3 apbr2 apbr1 apbr 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used to control the timing of read cycle and write cycle on apb bus. apbr0-apbr6 read access time on apb bus 0 1-cycle access 1 2-cycle access apbw0-apbw6 write access time on apb bus 0 1-cycle access 1 2-cycle access free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 126 of 1535 8000_1408h security boot register security_boot bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name security_boot type r/w reset 0 this register is written by sw, and it is also readable for md side. 8000_1500h io driving control register io_drv0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cmpc lk nfi etm cd etm clock type r/w r/w r/w r/w reset 0 8 8 8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam dpi parallel lcd serial lcd type r/w r/w r/w r/w reset 8 8 8 8 serial lcd driving control of serial lcd io [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control parallel lcd driving control of parallel lcd io [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control dpi driving control of dpi io [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control cam driving control of camera io [0] smt control [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control etm clock driving control of etm clock [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control etm cd driving control of etm control and data signal [0] e8, add 8ma current free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 127 of 1535 [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control nfi driving control of nfi io [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control cmpclk cmpclk input smt trigger control 0 disable 1 enable 8000_1504h io driving control register io_drv1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i2c_2 i2c_1 i2c_0 type r/w r/w r/w reset 8 8 8 i2c_0 driving control of i2c_0 [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control i2c_1 driving control of i2c_1 [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control i2c_2 driving control of i2c_2 [0] e8, add 8ma current [1] e4, add 4ma current [2] e2, add 2ma current [3] slew rate control 8000_1600h arm926ejs instruction cache size register ic_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ic_siz e type r/w reset 0 this register is used to configure the instruction cache size of arm926ej-s. ic_size 0 32kb cache size 1 16kb cache size free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 128 of 1535 8000_1604h arm926ejs data cache size register dc_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_si ze type r/w reset 0 this register is used to configure the data cache size of arm926ej-s. dc_size 0 32kb cache size 1 16kb cache size 8000_1608h mdvcxo_off register mdvcxo_off bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mdvc xo_o ff type ro reset mdvcx o_off this register is used to monitor mdvcxo_off signal 2.7.3 mtcmos application note MT6516 implements mtcmos technology. the following subsystem can be powered off when no use: 1) graph1sys 2) graph2sys 3) cevasys 4) md2gsys the following figure lists all power regions. the gray region in figure can be powered down by proper procedure. the following table summarizes related control registers and power-on stable time. the following list summarizes which sections you can find the related mtcmos control registers. ap config register: in_iso_en(ap), iso_en(ap), pwr_off(ap), and sleep_con(ap). md config register: in_iso_en(md), iso_en(md), pwr_con(md), and sleep_con(md) reset generation unit(aprgu): rgu_usrst2, rgu_usrst3, rgu_usrst4, and rgu_usrst5 graph1sys config register: graph1sys_cg_set and graph1sys_cg_clr graph2sys config register: graph2sys_cg_set and graph2sys_cg_clr for safely powering on/down each subsystem, the following statements are our proposed power on/down procedure. /? power-on sequence y 1) enable subsystem software reset y 2) power-on subsystem free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 129 of 1535 y 3) wait for a power-on stable time y 4) disable input isolation y 5) enable clocks y 6) disable output isolation y 7) disable subsystem software reset /? power-down sequence y 1) enable output isolation y 2) disable clocks y 3) enable input isolation y 4) power-down subsystem 2.8 apmcusys config register in addition to the pause mode capability while in the standby state, the software program can also put each peripheral independently into power down mode while in the active state by gating off their clock. the typical logic implementation is depicted in figure 13 . for all configuration bits, 1 signifies that the function is in power down mode, and 0 means the function is in the active mode. clock power down testmode figure 13 power down control at block level register address register name synonym 8003_9300h clock gating control status register 0 apmcusys_pdn_con0 8003_9320h clock gating set register 0 apmcusys_pdn_set0 8003_9340h clock gating clear register 0 apmcusys_pdn_clr0 8003_9360h clock gating control status register 1 apmcusys_pdn_con1 8003_9380h clock gating set register 1 apmcusys_pdn_set1 8003_93a0h clock gating clear register 1 apmcusys_pdn_clr1 8003_9600h memory delsel control register 0 (used by hardware) apmcusys_delsel0 8003_9604h memory delsel control register 1 (used by hardware) apmcusys_delsel1 8003_9608h memory delsel control register 2 (used by apmcusys_delsel2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 130 of 1535 hardware) 8003_960ch memory delsel control register 3 (used by hardware) apmcusys_delsel3 8003_9700h arm9 monitor control register apmcusys_mon_con 8003_9704h arm9 monitor set register apmcusys_mon_set 8003_9708h arm9 monitor clear register apmcusys_mon_clr 8003_970ch arm9 performance register 1 apmcusys_mon_perf1 8003_9710h arm9 performance register 2 apmcusys_mon_perf2 8003_9714h arm9 performance register 3 apmcusys_mon_perf3 8003_9718h arm9 performance register 4 apmcusys_mon_perf4 8003_971ch arm9 performance register 5 apmcusys_mon_perf5 8003_9720h arm9 performance register 6 apmcusys_mon_perf6 8003_9724h arm9 performance register 7 apmcusys_mon_perf7 8003_9728h arm9 performance register 8 apmcusys_mon_perf8 8003_972ch arm9 performance register 9 apmcusys_mon_perf9 8003_9730h arm9 performance register 0 apmcusys_mon_perf10 8003_9734h arm9 performance register 11 apmcusys_mon_perf11 8003_9738h arm9 performance register 12 apmcusys_mon_perf12 8003_973ch arm9 performance register 13 apmcusys_mon_perf13 8003_9740h arm9 performance register 14 apmcusys_mon_perf14 8003_9744h arm9 performance register 15 apmcusys_mon_perf15 8003_9748h arm9 performance register 16 apmcusys_mon_perf16 8003_974ch arm9 performance register 17 apmcusys_mon_perf17 8003_9750h arm9 performance register 18 apmcusys_mon_perf18 8003_9754h arm9 performance register 19 apmcusys_mon_perf19 8003_9758h arm9 performance register 20 apmcusys_mon_perf20 8003_975ch arm9 performance register 21 apmcusys_mon_perf21 8003_9760h arm9 performance register 22 apmcusys_mon_perf22 table 27 apb bridge register map 2.8.1 register definitions 8003_9300h clock gating control status register 0 apmcusys_pdn_ con0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name onewi re msdc 3 uart4 xgpt tp auxa dc msdc 2 sim2 i2c irda i2c2 nfi swdb g type ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 0 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 131 of 1535 name msdc pwm3 pwm2 pwm1 pwm sim uart3 uart2 uart1 gpio kp gpt i2c3 sej usb dma type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 apmcu sub-system power down control status register (read only). value 1 represents power down. dma status of the ap dma controller power down usb status of the usb power down sej status of the sej power down. i2c3 status of the 3 rd i2c controller power down gpt status of the gpt timer power down. kp status of the keypad power down. gpio status of the gpio power down. uart1 status of the 1 st uart power down. uart2 status of the 2 nd uart power down. uart3 status of the 3 rd uart power down. sim status of the 1 st sim power down. pwm status of pwm module power down. set this bit to 1 would power down all 7 pwm (pwm0, pwm1,?,pwm6). pwm0 status of the pwm0 power down. pwm1 status of the pwm1 power down. pwm2 status of the pwm2 power down. msdc status of the 1 st msdc power down. swdbg status of the software debug power down. nfi status of the nfi power down. i2c2 status of the 2 nd i2c power down. irda status of the irda power down. i2c status of the 1 st i2c power down. sim2 status of the 2 nd sim power down. msdc2 status of the 2 nd msdc power down. auxadc status of the auxadc power down. tp status of the touch panel power down. xgpt status of the xgpt timer power down. uart4 status of the 4 th uart power down. msdc3 status of the 3 rd msdc power down. onewire status of the onewire power down. 8003_9320h clock gating control set register 0 apmcusys_pdn_s et0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name onewi re msdc 3 uart4 xgpt tp auxa dc msdc 2 sim2 i2c irda i2c2 nfi swdb g type wo wo wo wo wo wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 name msdc pwm3 pwm2 pwm1 pwm sim uart3 uart2 uart1 gpio kp gpt i2c3 sej usb dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 132 of 1535 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo apmcu sub-system power down set register, value 1 represents power down. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?h0f0f, writing pdn_ set0 = 16?f0f0 will result in pdn_con0 = 16?hffff. 8003_9340h clock gating control clear register 0 apmcusys_pdn_c lr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name onewi re msdc 3 uart4 xgpt tp auxa dc msdc 2 sim2 i2c irda i2c2 nfi swdb g type wo wo wo wo wo wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 name msdc pwm3 pwm2 pwm1 pwm uart3 uart2 uart1 gpio kp gpt i2c3 sej usb dma type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo apmcu sub-system power down clear register, value 1 represents power up. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?hf fff, writing pdn_clr0 = 16?f0f0 will result in pdn_con0 = 16?h0f0f. usb please be noticed that there?s programming constraints for usb. the difference between usb and others is usb has its registers accessed through ahb instead of apb. what makes this fact serious is the power up operation and usb register access are two distinct paths in hardware, the apb and the ahb. we must first power up the usb to un-gate its ahb clock otherwise we cannot access its registers. then look at the example below: instruction 1: apb write to power up usb instruction 2: ahb access to usb register instruction 3: ? the instruction 1 is to un-gate the ahb clock of the usb. there?re chances that the un-gated ahb clock has not yet propagated to usb when instruction 2 arrives usb and consequently the register access of instruction 2 failed. to get rid of the potential problem, we suggested the below programming codes: instruction 1: apb write to power up usb loop 1-a:read usb register 0x8010061b and loop until the return value is 0x80 instruction 2: ahb access to usb register instruction 3: ? the loop 1-a guarantees that the clock propagation reaches usb because the returned data will be zeros if the ahb clock of usb is still gated. 8003_9360h clock gating control status register 1 apmcusys_ pdn_ con1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 133 of 1535 name pwm0 csdb g type ro ro reset 1 1 apmcu sub-system power down direct status, value 1 represents power down. csdbg status of the csdbg power down. this status takes effect immediately. pwm0 status of the pwm0 power down. this status takes effect immediately. 8003_9380h clock gating set register 1 apmcusys_pdn_s et1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm0 csdb g type wo wo apmcu sub-system power down set register, value 1 represents power down. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?h0f0f, writing pdn_ set0 = 16?f0f0 will result in pdn_con0 = 16?hffff. 8003_93a0h clock gating clear register 1 apmcusys_pdn_ clr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm0 csdb g type wo wo mdmcu sub-system power down clear register, value 1 represents power up. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?hffff, writing pdn_clr0 = 16?f0f0 will result in pdn_con0 = 16?h0f0f. 8003_9600h memory delsel control register 0 apmcusys_dels el0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name arm9 type rw reset 01 01 01 01 01 01 01 01 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name usb etb ccif ccif_ceva type rw r/w r/w r/w reset 0011 0001 0010 0001 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 134 of 1535 8003_9604h- 8003_9608h memory delsel control register 1-2 apmcusys_dels el1 - apmcusys_dels el2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name arm9 type rw reset 01 01 01 01 01 01 01 01 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arm9 type rw reset 01 01 01 01 01 01 01 01 8003_960ch memory delsel control register 3 apmcusys_dels el21 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csdbg apsysrom type rw rw reset 10 11 00 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apsysrom arm9 type rw rw reset 11 10 01 01 01 01 01 01 8003_9700h arm9 monitor control register apmcusys_m on_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dahb_sel iahb_ clr dahb_ clr iext_ clr dext_ clr icp_ clr dcp_ clr type ro ro ro ro ro ro ro reset 0 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name itlb_ clr dtlb_ clr activ e_clr icm_c lr dcm_ clr iahb_ en dahb _en iext_ en dext_ en icp_e n dcp_e n itlb_e n dtlb_ en activ e_en icm_e n dcm_ en type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 dcm_en enable the miss rate monitor of data cache icm_en enable the miss rate monitor of instruction cache active_en enable arm9 active counter dtlb_en enable the data tlb penalty counter of mmu itlb_en enable the instruction tlb penalty counter of mmu dcp_en enable the penalty counter of data cache icp_en enable the penalty counter of instruction cache dext_en enable the penalty counter of data external write buffer free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 135 of 1535 iext_en enable the penalty counter of instruction external write buffer dahb_en enable the penalty counter of arm9 data ahb bus iahb_en enable the penalty counter of arm9 instruction ahb bus dcm_clr clear the miss rate counter of data cache (active low) icm_clr clear the miss rate counter of instruction cache (active low) active_clr clear arm9 active counter (active low) dtlb_clr clear the data tlb penalty counter of mmu (active low) itlb_clr clear the instruction tlb penalty counter of mmu (active low) dcp_clr clear the penalty counter of data cache (active low) icp_clr clear the penalty counter of in struction cache (active low) dext_clr clear the penalty counter of data external write buffer (active low) iext_clr clear the penalty counter of instructi on external write buffer (active low) dahb_clr clear the penalty counter of data ahb bus (active low) iahb_clr clear the penalty counter of instruction ahb bus (active low) dahb_sel this control register is used to select which the data address range is monitored. it is taken effect when you enable the penalty counter of arm9 data ahb bus. 0 external memory: 0x0000_0000 ~ 0x3fff_ffff 1 internal memory: 0x4000_0000 ~ 0x4fff_ffff 2 apb register: 0x8000_0000 ~ 0xffff_ffff 3 reserved 8003_9704h arm9 monitor set register apmcusys_mon_ set for monitor control register listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding mon_con register. eg. if mon_con = 16?h0f0f, writing mon_set = 16?f0f0 will result in mon_con = 16?hffff. 8003_9708h arm9 monitor clear register apmcusys_mon_ clr for monitor control register listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding mon_con register. eg. if mon_con = 16?hffff, writing mon_clr = 16?f0f0 will result in mon_con = 16?h0f0f. 8003_970ch arm9 performance register 1 apmcusys_m on_perf1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 136 of 1535 name dc_read_req type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_read_req type ro reset 0 8003_9710h arm9 performance register 2 apmcusys_m on_perf2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dc_write_req type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_write_req dc_read_req type ro ro reset 0 0 8003_9714h arm9 performance register 3 apmcusys_m on_perf3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dc_read_miss type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_write_req type ro reset 0 8003_9718h arm9 performance register 4 apmcusys_m on_perf4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dc_write_miss dc_read_miss type ro ro reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_read_miss type ro reset 0 8003_971ch arm9 performance register 5 apmcusys_m on_perf5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dc_write_miss type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_write_miss type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 137 of 1535 8003_9720h arm9 performance register 6 apmcusys_m on_perf6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ic_read_req type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ic_read_req type ro reset 0 8003_9724h arm9 performance register 7 apmcusys_m on_perf7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ic_read_miss type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ic_read_miss ic_read_req type ro ro reset 0 0 8003_9728h arm9 performance register 8 apmcusys_m on_perf8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name arm9_active type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ic_read_miss type ro reset 0 8003_972ch arm9 performance register 9 apmcusys_m on_perf9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dtlb_penalty arm9_active type ro ro reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arm9_active type ro reset 0 8003_9730h arm9 performance register 10 apmcusys_m on_perf10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dtlb_penalty type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 138 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dtlb_penalty type ro reset 0 8003_9734h arm9 performance register 11 apmcusys_m on_perf11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name itlb_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name itlb_penalty type ro reset 0 8003_9738h arm9 performance register 12 apmcusys_m on_perf12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dc_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_penalty itlb_penalty type ro ro reset 0 0 8003_973ch arm9 performance register 13 apmcusys_m on_perf13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ic_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dc_penalty type ro reset 0 8003_9740h arm9 performance register 14 apmcusys_m on_perf14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dext_penalty ic_penalty type ro ro reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ic_penalty type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 139 of 1535 8003_9744h arm9 performance register 15 apmcusys_m on_perf15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dext_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dext_penalty type ro reset 0 8003_9748h arm9 performance register 16 apmcusys_m on_perf16 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iext_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iext_penalty type ro reset 0 8003_974ch arm9 performance register 17 apmcusys_m on_perf17 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dahb_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dahb_penalty iext_penalty type ro ro reset 0 0 8003_9750h arm9 performance register 18 apmcusys_m on_perf18 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dahb_req type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dahb_penalty type ro reset 0 8003_9754h arm9 performance register 19 apmcusys_m on_perf19 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iahb_penalty dahb_req type ro ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 140 of 1535 reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dahb_req type ro reset 0 8003_9758h arm9 performance register 20 apmcusys_m on_perf20 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iahb_penalty type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iahb_penalty type ro reset 0 8003_975ch arm9 performance register 21 apmcusys_m on_perf21 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iahb_req type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iahb_req type ro reset 0 8003_9760h arm9 performance register 22 apmcusys_m on_perf22 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iahb_req type ro reset 0 for all register addresses listed above, each counter register is 40-bit width. the 40-bit monitor can record about 43.98 minutes when arm9 runs at 416mhz, that is ?clock period x 2 counter bit width = 2.4ns x 2 40 = 43.98 mins?. dc_read_req total read requests of the data cache dc_write_req total write requests of the data cache dc_read_miss total read misses of the data cache, read miss rate = total read misses / total read requests. dc_write_miss total write misses of the data cache, write miss rate = total write misses / total write requests. ic_read_req total read requests of the instruction cache free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 141 of 1535 ic_read_miss total read misses of the instruction cache, read miss rate = total read misses / total read requests. arm9_active arm9 total active count, it only counts when arm9 is active. dtlb_penalty it counts arm9 stall cycles caused by data tlb. itlb_penalty it counts arm9 stall cycles caused by instruction tlb. dc_penalty it counts arm9 stall cycles caused by data cache. ic_penalty it counts arm9 stall cycles caused by instruction cache. dext_penalty it counts arm9 stall cycles caused by data external write buffer (dext). iext_penalty it counts arm9 stall cycles caused by instruction external write buffer (iext) dahb_penalty this counter will count the penalty caused by the external bus (data ahb bus), and this counter will be influenced by the dahb_sel register, if you set dahb_sel as 0x1, the penalty monitored by the counter will only has the internal memory access penalty not the total penalty. with this functionality, we can further analyze the penalty source with the same monitor. dahb_req total request number of the arm9 data bus. iahb_penalty this counter will count the penalty caused by the external bus (instruction ahb bus). iahb_req total request number of the arm9 instruction bus. 2.9 ap extended gpt 2.9.1 general description ap-domain extended general purpose timer (apxgpt). channels 1 & 2 are based on 13,000,000hz (13mhz) clock and channels 3 to 7 are based on 32768hz clock. 2.9.2 register definitions xgpt+0000h apxgpt irq enable xgpt_irqen bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ien7 ien6 ien5 ien4 ien3 ien2 ien1 type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 ienn enable the interrupt of each xgpt channel. when the counter is equal to compare and mode is not freerun. 0 interrupt of channel n is disabled. 1 interrupt of channel n is enabled. xgpt+0004h apxgpt irq status xgpt_irqsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 142 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ist7 ist6 ist5 ist4 ist3 ist2 ist1 type ro ro ro ro ro ro ro reset istn interrupt status for channel n 0 no interrupt is generated 1 an interrupt is pending and waiting for service xgpt+0008h apxgpt irq status acknowledge xgpt_irqack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iack7 iack6 iack5 iack4 iack3 iack2 iack1 type wo wo wo wo wo wo wo reset iackn interrupt acknowledge for the apxgpt channel 0 no effect 1 interrupt request is acknowledged and should be relinquished. xgpt+00n0h apxgpt channel n control xgptn_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mode clr en type r/w wo r/w reset 0 0 n=1 to 7 en enable the xgpt channel n. 0 xgpt channel n is disabled. 1 xgpt channel n is enabled. clr clear the countn to 0. mode the operation mode of channel n 00 one-shot mode. 01 repeat mode. 10 keepgo mode. 11 freerun mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 143 of 1535 auto stop interrupt increase when en=1 and ? if countn = comparen example: reset to 0 and compare = 2 ( bold means interrupt .) one-shot yes yes stopped when countn equals to comparen en is reset to 0 0,1, 2 ,2,2,2,2,2,2,2,2,? repeat no yes count is reset to 0 0,1, 2 ,0,1, 2 ,0,1, 2 ,0,1, 2 ,0,?. keepgo no yes reset to 0 when overflow 0,1, 2 ,3,4,5,6,7,8,9,? freerun no no reset to 0 when overflow 0,1,2,3,4,5,6,7,8,9,? mode xgpt+00n4h apxgpt channel n prescaler xgptn_presc aler bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler type r/w reset 0 n=1 to 7 prescale xgpt channel n input clock. clock (hz) prescale 1 to 2 3 to 7 000 13m 32768 001 6.5m 16384 010 3.25m 8192 011 1.625m 4096 100 812.5k 2048 101 406.25k 1024 110 203.125k 512 111 101.5625k 256 channel note: m=1,000,000; k=1,000. xgpt+00n8h apxgpt channel n count xgptn_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count[15:0] type ro reset 0 n=1 to 7 count the current count of channel n. when en=1, the count increases according prescaler. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 144 of 1535 xgpt+00nch apxgpt channel n compare value xgptn_compa re bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name compare[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name compare[15:0] type r/w reset 0 n=1 to 7 compare the compared value of channel n. when (en=1) and (mode is not freerun) and (count is equal to compare) and (ien=1), an interrupt happened. 2.10 auxiliary adc unit the auxiliary adc unit is used to monitor the status of the battery and charger, to identify the plugged peripheral, and to perform temperature measurement. 9 input channels allow diverse applications in this unit. figure 14 auxadc architecture each channel can operate in one of two modes: immediate mode and timer-triggered mode. the mode of each channel can be individually selected through register auxadc_con0 . for example, if the flag syn0 in free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 145 of 1535 the register auxadc_con0 is set, channel 0 is set in the timer-triggered mode. otherwise, the channel operates in the immediate mode. in the immediate mode, the a/d converter samples the value once only when the flag in the auxadc_con1 register has been set. for example, if the flag imm0 in auxadc_con1 is set, the a/d converter samples the data for channel 0. the imm flags must be cleared and set again to initiate another sampling. the value sampled for channel 0 is stored in register auxadc_dat0 , the value for channel 1 is stored in register auxadc_dat1 , etc. if the autoset flag in the register auxadc_con3 is set, the auto-sampling function is enabled. the a/d converter samples the data for the channel on which the corresponding data register has been read. for example, in the case where the syn1 flag is not set, the autoset flag is set, when the data register auxadc_dat0 has been read, the a/d converter samples the next value for channel 1 immediately. if multiple channels are selected at the same time, the task is performed sequentially on every selected channel. for example, if auxadc_con1 is set to 0x1ff, that is, all the 9 channels are selected, the state machine in the unit starts sampling from channel 8 to channel 0, and saves the values of each input channel in its corresponding register. the same process also applies to the timer-triggered mode. in the timer-triggered mode, the a/d converter samples the value for the channels in which the corresponding syn flags are set when the tdma timer counts to the value specified in the register tdma_auxev1 , which is placed in the tdma timer. for example, if auxadc_con0 is set to 0x1ff, all the 9 channels are selected the timer-triggered mode. the state machine samples all the 9 channels sequentially and saves the values in registers from auxadc_dat0 to auxadc_dat8 , as it does in the immediate mode. there is a dedicated timer-triggered scheme for channel 0. this scheme is enabled by setting the syn9 flag in the register auxadc_con2 . the timing offset for this event is stored in the register tdma_auxev0 in the tdma timer. the sampled data triggered by this specific event is stored in the register auxadc_dat9 . it is used to separate the results of two individual soft ware routines that perform actions on the auxiliary adc unit. the autoclr n in the register auxadc_con3 is set when it is intended to sample only once after setting the timer-triggered mode. if autoclr1 flag has been set, after the data for the channels in the timer- triggered mode has been stored, the syn n flags in the register auxadc_con0 are cleared. if autoclr0 flag has been set, after the data for the channel 0 has been stored in the register auxadc_dat9 , the syn9 flag in the register auxadc_con2 is cleared. the usage of the immediate mode and timer-triggered mode are mutually exclusive in each individual channel. the puwait_en bit in the registers auxadc_con3 is used to power up the analog port in advance. this ensures that the power has ramped up to the stable state before a/d converter starts the conversion. the analog part is automatically powered down after the conversion is completed. touch panel: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 146 of 1535 vdd vdd _ + vdd _ + _ + figure 15 touch panel circuit structure besides the normal sampling of the external input voltage, auxadc includes the sampling of the touch panel function. for the specified axis, sw should program aux_ts_cmd first, and then trigger touch panel?s sample in the register aux_ts_con . the touch panel sampling waveform is shown as follows. after sw polls status bit in the register auxadc_con3 to know that the touch panel sample is finished. sw can read back the specified axis value from the register aux_ts_dat0 . figure 16 touch panel sampling waveform s: start bit a2~a0: addressing bits mode: 10-bit or 8-bit se/df: single end or differential mode 4 " " " .0%& 4&%' 1% 1% *c *c % % % % % % $4# %$-, %*/ 41- #vtz %065 % free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 147 of 1535 pd1~0: power down command these values are defined in the register aux_ts_cmd . in the following table, it shows the relationship between aux_ts_cmd and touch panel control signals. table 28 relationship between commands and touch panel control signals background detection: in order to monitor at ap sleep mode, auxadc adds the background detection function to monitor the pre-defined channel. if the expected times is achieved, higher or lower than expected voltage, auxadc will issue lowbat interrupt to ap interrupt controller to wake up the ap. besides ap sleep mode, this background detection is not recommended to be used in the normal mode. in the normal mode, sw is recommended to regularly measure battery voltage. the lo wbat interrupt id refers to ap interrupt controller. moreover, lowbat waking up ap needs to set enable bit in the sleep controller and please refer to ap sleep controller to enable it before entering the sleep mode. power up/down adc procedure: 4&%'# " " " /05& :1ptjujpo :1ptjujpo 91ptjujpo 91ptjujpo ; 1ptjujpo ; 1ptjujpo ; 1ptjujpo ; 1ptjujpo 9:%sjwfs 9:1btt 4&- */ */ */ */ "--0'' 5#% 5#% 5#% 5#% 99pgg ::po "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' 99po ::pgg 99pgg ::po 99po ::pgg 9:pgg :9po 9:pgg :9po 9:pgg :9po 9:pgg :9po "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' "--0'' 99pgg ::po 99po ::pgg 9:pgg :9po 9:pgg :9po free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 148 of 1535 power up adc immediate trigger autoset mode sync mode read adc value set sync channel wait for ready disable autoset read adc value mode select anthoer sample power down adc y n check sta is busy y n autoset mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 149 of 1535 2.10.1 register definitions register address register function acronym 0x8003d000 auxiliary adc cont rol register 0 auxadc_con0 0x8003d004 auxiliary adc cont rol register 1 auxadc_con1 0x8003d008 auxiliary adc cont rol register 2 auxadc_con2 0x8003d010 auxiliary adc channel 0 data register auxadc_dat0 0x8003d014 auxiliary adc channel 1 data register auxadc_dat1 0x8003d018 auxiliary adc channel 2 data register auxadc_dat2 0x8003d01c auxiliary ad c channel 3 data register auxadc_dat3 0x8003d020 auxiliary adc channel 4 data register auxadc_dat4 0x8003d024 auxiliary adc channel 5 data register auxadc_dat5 0x8003d028 auxiliary adc channel 6 data register auxadc_dat6 0x8003d02c auxiliary ad c channel 7 data register auxadc_dat7 0x8003d030 auxiliary adc channel 8 data register auxadc_dat8 0x8003d034 auxiliary adc channel 0 data register for tdma event 0 auxadc_dat9 0x8003d050 touch screen debounce time aux_ts_debt 0x8003d054 touch screen sample command aux_ts_cmd 0x8003d058 touch screen control aux_ts_con 0x8003d060 auxadc background voltage threshold aux_det_volt 0x8003d064 auxadc background detected channel aux_det_sel 0x8003d068 auxadc background detection period auxadc_det_period 0x8003d06c auxadc background detection debounce aux_det_debt table 29 auxadc registers 0x8003d000 auxiliary adc contro l register 0 auxadc_con0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name syn8 syn7 syn6 syn5 syn4 syn3 syn2 syn1 syn0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 syn n these 9 bits define whether the corresponding channel is sampled or not in timer-triggered mode. it is associated with timing offset register tdma_auxev1 . it supports multiple flags. the flags can be automatically cleared after those channel have been sampled if autoclr1 in the register auxadc_con3 is set. 0 the channel is not selected. 1 the channel is selected. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 150 of 1535 0x8003d004 auxiliary adc contro l register 1 auxadc_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name imm8 imm7 imm6 imm5 imm4 imm3 imm2 imm1 imm0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 imm n these 7 bits are set individually to sample the data for the corresponding channel. it supports multiple flags. 0 the channel is not selected. 1 the channel is selected. 0x8003d008 auxiliary adc contro l register 2 auxadc_con2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name syn9 type r/w reset 0 syn9 this bit is used only for channel 0 and is to be associated with timing offset register tdma_auxev0 in the tdma timer in timer-triggered mode. the flag can be automatically cleared after channel 0 has been sampled if autoclr0 in the register auxadc_con3 is set. 0 the channel is not selected. 1 the channel is selected. 0x8003d00c auxiliary adc contro l register 3 auxadc_con3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto set puwai t_en auto clr1 auto clr0 sta type r/w r/w r/w r/w ro reset 0 0 0 0 0 autoset this field defines the auto-sample mode of the module. in auto-sample mode, each channel with its sample register being read can start sampling immediately without configuring the control register auxadc_con1 again. puwait_en thus field enables the power warm-up period to ensure power stability before the sar process takes place. it is recommended to activate this field. 0 the mode is not enabled. 1 the mode is enabled. autoclr1 the field defines the auto-clear mode of the module for event 1. in auto-clear mode, each timer-triggered channel gets samples of the specified channels once the syn n bit in the register auxadc_con0 has been set. the syn n bits are automatically cleared and the channel is not enabled again by the timer event except when the syn n flags are set again. 0 the automatic clear mode is not enabled. 1 the automatic clear mode is enabled. autoclr0 the field defines the auto-clear mode of the module for event 0. in auto-clear mode, the timer-triggered channel 0 gets the sample once the syn9 bit in the register auxadc_con2 has free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 151 of 1535 been set. the syn9 bit is automatically cleared and the channel is not enabled again by the timer event 0 except when the syn9 flag is set again. 0 the automatic clear mode is not enabled. 1 the automatic clear mode is enabled. sta the field defines the state of the module. 0 this module is idle. 1 this module is busy. 0x8003d010 auxiliary adc channel 0 register auxadc_dat0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dat type ro reset 0 the register stores the sampled data for the channel 0. there are 8 registers of the same type for the corresponding channel . the overall register definition is listed in table 30 . register address register function acronym 0x8003d010 auxiliary adc channel 0 data register auxadc_dat0 0x8003d014 auxiliary adc channel 1 data register auxadc_dat1 0x8003d018 auxiliary adc channel 2 data register auxadc_dat2 0x8003d01c auxiliary adc channel 3 data register auxadc_dat3 0x8003d020 auxiliary adc channel 4 data register auxadc_dat4 0x8003d024 auxiliary adc channel 5 data register auxadc_dat5 0x8003d028 auxiliary adc channel 6 data register auxadc_dat6 0x8003d02c auxiliary adc channel 7 data register auxadc_dat7 0x8003d030 auxiliary adc channel 8 data register auxadc_dat8 0x8003d034 auxiliary adc channel 0 data register for tdma event 0 auxadc_dat9 table 30 auxiliary adc data register list 0x8003d050 touch screen debounce time aux_ts_debt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name debounce time type r/w reset 0 debounce time while the analog touch screen irq signal is from high to low level, auxadc will issue an interrupt after the debounce time. 0x8003d054 touch screen sample command aux_ts_cmd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name address mode se/df pd type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 152 of 1535 address define which x or y or z data will be sampled. 001 y position 011 z1 position 100 z2 position 101 x position others reserved mode select the samp le resolution 0 10-bit resolution 1 8-bit resolution se/df mode selection 0 differential mode 1 single-end mode pd power down control for analog irq signal and touch screen sample control signal 00 turn on y-_drive signal and pdn_sh_ref 01 turn on pdn_irq and pdn_sh_ref 10 reserved 11 turn on pdn_irq 0x8003d058 touch screen control aux_ts_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name st spl type r r/w reset 0 0 spl touch screen sample trigger 0 no action 1 while sw writes 1?b1, auxadc will trigger the touch screen process. after the sample process of touch screen finishes, this bit will be disserted. st touch screen status 0 touch screen is idle. 1 touch screen is touched. 0x8003d05c touch screen sample data aux_ts_dat0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dat type ro reset 0 this register stores the touch screen sample data. 0x8003d060 auxadc background voltage threshold aux_det_vol t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name inv volt type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 153 of 1535 reset 0 0 0 0 0 0 0 inv while the battery voltage is high or lower than pre-defined voltage (volt), the interrupt will be issued to ap. 0 lower 1 higher volt pre-defined voltage threshold 0x8003d064 auxadc background detected channel aux_det_sel bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name det_ch type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 det_ch which a channel will be sa mpled in the background 0x8003d068 auxadc backgro und detection period auxadc_det_ period bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name det_period type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 det_period background sample period. while this value is not zero, the background detection will be activated automatically. (use 32k clock as unit) 0x8003d06c auxadc backgro und detection debounce aux_det_deb t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name debounce time type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 debounce_time while the number of that the detected channel is 2.11 coresight 2.11.1 general description coresight is one set of debug ip tool kit provided by arm. it supports mcu & bus real-time trace, multi-core debug, and cross trigger feature. in MT6516 coresight system comprises of 1 dap (debug access port), 1 etm (embedded trace macrocell), 1 tpiu (trace port interface unit), 1 etb (embedded trace buffer), 1 ctm (cross trigger matrix), and 3 cti (cross trigger interface). etm can be categorized as trace source, whereas tpiu and etb are trace sink. trace source records cpu activities and produces trace data. through atb (amba trace bus), trace sink collects these trace data to external debugger by tpiu or to internal storage (etb). dap is the gateway transmitting information between external debugger and dual core system through jtag interface. dap can control arm7ejs, arm926ejs and all coresight components through single jtag port. etm records real-time arm926ejs operations, compresses, and transfers these trace data to atb. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 154 of 1535 replicator is a device which dispatches trace data to two different types of trace sink. tpiu and etb both are used to store trace, while tpiu transfers to external debugger and etb stores internally. ctm and cti control cross triggering that transmit trigger event from one device to another. the description above is not exhaustive. about the detailed information, programmer?s model, and so on, please refer to coresight technical reference manual on arm website. figure 17 shows an overview of the coresight system in MT6516. cross trigger interface arm 9 dap corss trigger interface arm 7 amba axi/ahb cross trigger matrix debug bus (apb v3) etm 9cs trace bus (atb) trace port buffer replicator cross trigger interface figure 17 overview of MT6516 coresight system 2.11.2 project-dependent specification some coresight specifications are project-dependent. the following features are only in MT6516. ? tpiu trace port : trace data port + trace control port + trace clock port = 16 + 1 + 1 = 18 bits ? trace clock : 52mhz ? etb size : 4kb ? cross trigger feature figure 2 shows an overview of cross trigger in MT6516 coresight system. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 155 of 1535 cti_a7 arm 7 dbgack dbgrq trigin[3] trigout[4] trigoutack[4] etb cti_tb full trigin trigin[3] trigin[4] trigout[5] trigoutack[5] tpiu triginack trigin triginack etm 9cs cti_a9 arm 9 dbgack dbgrq trigout trigoutack trigin[4] trigout[3] trigoutack[3] trigin[5] triginack[5] figure 2 cross trigger overview for example, if cti_a7 enables trigin[3] and cti_a9 enables trigout[3], once arm7 enters debug mode, dbgack will be asserted. this assertion will be transferred through cti_a7 ? ctm ? cti_a9 ? arm9 dbgrq signal and force arm 9 also enters debug mode. this scenario achieves that one arm core state influences the other one. there are several scenarios in MT6516 cross trigger function. 1. arm7 & arm9 enter debug mode in turn. 2. etb full forces arm7 & arm9 to enter debug mode. 3. etm_a9 issue trigger event and cause tpiu & etb to stop tracing. cross trigger operational procedure in trace32 (take the above case for example) data.set dap:8004302c %l 0x1 // enable cti_a7 trigin[3] and assign to channel 0 data.set dap:80043000 %l 0x1 // enable cti_a7 data.set dap:800440ac %l 0x1 // enable cti_a9 trigout[3] and assign to channel 0 data.set dap:80044000 %l 0x1 // enable cti_a9 2.11.3 register definitions table 31 summarizes the base address of coresight components. base address coresight component acronym 80040000h debug access port dap 80041000h embedded trace macrocell ? arm 9 etm9 80042000h trace port interface unit tpiu 80043000h cross trigger interface ? arm 7 ctia7 80044000h cross trigger interface ? arm 9 ctia9 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 156 of 1535 80045000h embedded trace buffer etb 80046000h cross trigger interface ? tpiu & etb ctitb table 31 base address of coresight components coresight technical reference manual has detailed register definition. please download these documents from arm?s website : www.arm.com . here only introduce the newly-added features. tpiu+040h trace clock delay chain control register tpiu_dlychn bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name delay select setting type r/w reset 1 delay select setting trace port has three types of signals : traceclk, tracedata, tracectl, and need to connect to external debugger. traceclk needs flexibility to adjust timing to sample correct trace data. this setting decides how much delay traceclk pin will pass through. only sets one bit at a time, such as 16?h1, 16?h2, 16?h4, etc. the larger this setting is, the more delay traceclk passes through. default value is 16?h1, which passes one tap of delay cell. tpiu+080h trace clock positive negative control register tpiu_tckpn bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pn type r/w reset 1 pn traceclk is generated by one double-frequency clock : traceclkin. this bit decides to sample at positive or negative edge to create traceclk. default uses negative edge to sample. 2.11.4 application note clock of coresight system is controlled by power down bit. if using trace32 to connect coresight (pad icoresight = 1), coresight system will be powered up by default. if using software to control coresight (pad icoresight = 0), clear coresight power down bit is required. *apmcusys_pdn_clr1 (0x800393a0) = 0x1 also, because trace port 18 signals are muxed with gpio, please configure gpio mode register to switch to trace port first. *gpio_mode13 (0x800026c0) = *gpio_mode13 & 0xf0 | 0xff0f *gpio_mode14 (0x800026d0) = *gpio_mode14 & 0xfff0 | 0xf *gpio_mode18 (0x80002710) = *gpio_mode18 & 0x3 | 0x5554 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 157 of 1535 *gpio_mode19 (0x80002720) = *gpio_mode19 & 0xffc0 | 0x15 2.12 cpu-cpu interface (ccif) 2.12.1 general description and features ccif is designed for communication between two cpus. message from any one cpu can be sent to another cpu efficiently. the functional block diagram of ccif is shown in fig. 1. and the operation flow of ccif is shown in fig. 2. fig. 1 fig. 2 the flow of ccif protocol can be summarized as: z transmission side: set busy of channel #n z transmission side: move data to channel #n z transmission side: write channel number to fifo ( start of channel #n will be set automatically) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 158 of 1535 z interrupt issued to reception side automatically z reception side: read channel number from fifo z reception side: move data and ack z busy and start is cleared automatically the main features of the ccif are: z two ccif sides can have different clock frequency z two different arbitration modes are supported (sequential mode or arbitration by mcu) z one internal 256 byte dual port sram z 16 channels are provided (8 channels ap ? md, 8 channels md ? ap) z support 1t/2t apb read/write 2.12.2 register definitions of apmcu side table 1 is the ap cpu-cpu interface (ccif) register mapping table that summarizes the ap ccif register address mapping on apb bus and function description. note: the ceva ccif base address of the ap side is 0xb1001000 , other offset registers of ceva ccif is same as the following. apb address register function acronym 8003_6000h ap ccif control register con 8003_6004h ap ccif busy register busy 8003_6008h ap ccif start register start 8003_600ch ap ccif transmit channel number register tchnum 8003_6010h ap ccif receive channel number register rchnum 8003_6014h ap ccif acknowledge register ack 8003_6100h -- 8003_61ffh ap ccif channel data register chdata table 1 the ap ccif register mapping 8003_6000h ap ccif control register apccif_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arb type r/w reset 0 arb enable arbitration mechanism for apmcu to decide which channel wants to be read. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 159 of 1535 0 use sequential mechanism to decide which channel needs to be read firstly. rchnum represents the number of channel need to be processed by apmcu in advance. only use three bits ([2:0]) in rchnum. the processing order of channels is only in time sequence. rchnum[2:0] having data in which channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 1 apmcu decides to read which channel by arbitration. the bit value of rchnum ([7:0]) represents which channels need to be processed respectively. rchnum[0] have data in channel 0? 0 no 1 yes rchnum[1] have data in channel 1? 0 no 1 yes rchnum[2] have data in channel 2? 0 no 1 yes rchnum[3] have data in channel 3? 0 no 1 yes rchnum[4] have data in channel 4? 0 no 1 yes rchnum[5] have data in channel 5? 0 no 1 yes rchnum[6] have data in channel 6? 0 no 1 yes rchnum[7] have data in channel 7? 0 no 1 yes free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 160 of 1535 8003_6004h ap ccif busy register apccif_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy type r/w reset 0 this register provides the status of channel 7-0 busy. busy indicate which channel operation is in process. it will de-assert when mdmcu finishes fetching channel data and then writes acknowledge for according channel. busy [7] represents the busy status of channel 7, and so on. 8003_6008h ap ccif start register apccif_start bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start type r reset 0 this register provides the status of channel 7-0 start. it is only for debugging usage. start indicate the state of finishing transmitting channe l number but not receiving acknowledge. it will de-assert when writing acknowledge for according channel by mdmcu. start [0] represents the start status of channel 0, and so on. 8003_600ch ap ccif transmit channel number register apccif_tchnu m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tchnum type w reset 0 this register specifies the transmitted channel number set by apmcu. tchnum the 3-bit channel number represents which channel (channel 7-0) is to be used for transmitting data to mdmcu. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 161 of 1535 8003_6010h ap ccif receive channel number register apccif_rchn um bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rchnum type r reset 0 this register provides the received channel number read-out by apmcu. rchnum the 3-bit channel number represents which channel (channel 7-0) is to be used for receiving data from mdmcu. 8003_6014h ap ccif acknowledge register apccif_ack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ack type w reset 0 this register specifies acknowledge when finishing one channel receiving. ack acknowledge. it is write-cleared and set by apmcu for clearing interrupt status and busy/start states of mdmcu cpu-cpu interface according channel. writing ack is the latest step for ending one channel transfer. 8003_6100h ap ccif channel data register apccif_chdat a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w this register specifies the data port for channel data accessing. data the 32-bit channel data read from one 256 bytes dual-port sram. this sram can also be accessed by mdmcu subsystem. total 256 bytes of channel data are read/written from address: apccif+0100h to address: apccif+01ffh by apmcu. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 162 of 1535 2.12.3 register definitions of mdmcu side table 1 is the md cpu-cpu interface (ccif) register mapping table that summarizes the md ccif register address mapping on apb bus and function description. apb address register function acronym 8116_0000h md ccif control register con 8116_0004h md ccif busy register busy 8116_0008h md ccif start register start 8116_000ch md ccif transmit channel number register tchnum 8116_0010h md ccif receive channel number register rchnum 8116_0014h md ccif acknowledge register ack 8116_0100h -- 8116_01ffh md ccif channel data register chdata table 1 the md ccif register mapping 8116_0000h md ccif control register mdccif_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arb type r/w reset 0 arb enable arbitration mechanism for mdmcu to decide which channel wants to be read. 0 use sequential mechanism to decide which channel needs to be read firstly. rchnum represents the number of channel need to be processed by mdmcu in advance. only use three bits ([2:0]) in rchnum. the processing order of channels is only in time sequence. rchnum[2:0] having data in which channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 1 mdmcu decides to read which channel by arbitration. the bit value of rchnum ([7:0]) represents which channels need to be processed respectively. rchnum[0] have data in channel 0? free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 163 of 1535 0 no 1 yes rchnum[1] have data in channel 1? 0 no 1 yes rchnum[2] have data in channel 2? 0 no 1 yes rchnum[3] have data in channel 3? 0 no 1 yes rchnum[4] have data in channel 4? 0 no 1 yes rchnum[5] have data in channel 5? 0 no 1 yes rchnum[6] have data in channel 6? 0 no 1 yes rchnum[7] have data in channel 7? 0 no 1 yes 8116_0004h md ccif busy register mdccif_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy type r/w reset 0 this register provides the status of channel 7-0 busy. busy indicate which channel operation is in process. it will de-assert when apmcu finishes fetching channel data and then writes acknowledge for according channel. busy [7] represents the busy status of channel 7, and so on. 8116_0008h md ccif start register mdccif_start bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 164 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start type r reset 0 this register provides the status of channel 7-0 start. it is only for debugging usage. start indicate the state of finishing transmitting channe l number but not receiving acknowledge. it will de-assert when writing acknowledge for according channel by apmcu. start [0] represents the start status of channel 0, and so on. 8116_000ch md ccif transmit channel number register mdccif_tchn um bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tchnum type w reset 0 this register specifies the transmitted channel number set by mdmcu. tchnum the 3-bit channel number represents which channel (channel 7-0) is to be used for transmitting data to apmcu. 8116_0010h md ccif receive channel number register mdccif_rchn um bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rchnum type r reset 0 this register provides the received channel number read-out by mdmcu. rchnum the 3-bit channel number represents which channel (channel 7-0) is to be used for receiving data from apmcu. 8116_0014h md ccif acknowle dge register mdccif_ack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ack free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 165 of 1535 type w reset 0 this register specifies acknowledge when finishing one channel receiving. ack acknowledge. it is write-cleared and set by mdmcu for clearing interrupt status and busy/start states of apmcu cpu-cpu interface according channel. writing ack is the latest step for ending one channel transfer. 8116_0100h md ccif channel data register mdccif_chda ta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w this register specifies the data port for channel data accessing. data the 32-bit channel data read from one 256 bytes dual-port sram. this sram can also be accessed by apmcu subsystem. total 256 bytes of channel data are read/written from address: mdccif+0100h to address: mdccif+01ffh by mdmcu. 2.13 efuse controller (efusec) 2.13.1 general description there are some efuse macros in the chip. efuse macro is a one-time-programming non-volatile memory. we usually use it as storage of sensitive and important data. efuse controller delivers efuse status and re-initializes efuse macro. you can program the efuse via efuse controller with proper configuration and sequences. 2.13.2 register definitions efusec+0000 h efuse control efusec_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name esel wsel rd busy v ld type r/w r/w wo ro ro reset 0 0 0 0 0 vld indicate if efuse data are valid or not. efusec will initialize all efuse macros automatically. after finishing the initialization, this bi t will change to 1 from 0. in other case, if you initialize efuse macros by write rd=1 manually, the vld will go to low. af ter rd process done, vld will go to high again. busy efuse controller is busy. you can write efusec control registers only when busy is low. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 166 of 1535 rd initialize efuse macros manually. the busy is 1 and vld is 0 while efusec re-initialize all efuse macros. after finishing the initialization, busy changes to 0 and vld changes to 1. please perform read and write operations when pll is off. wsel efuse word selection. there are 2 words in each efuse macro. you should decide which word you will program esel efuse macro selection. there are 6 efuse macros in the system. you should decide which macro you will program esel wsel efuse_dx 011 0 efuse_d0 011 1 efuse_d1 100 0 efuse_d2 100 1 efuse_d3 101 0 efuse_d4 101 1 efuse_d5 110 0 efuse_d6 110 1 efuse_d7 111 0 efuse_d8 111 1 efuse_d9 efusec+0004 h efuse write data efusec_wda t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wdat[31:16] type r/w reset n/a bit 15 14 13 12 11 109876543 2 10 name wdat [ 15:0 ] type r/w reset n/a wdat after setting the efuse_sel and wsel, you can write wdat with values you want to program. once you write efusec_wdat, efusec starts blowing efuse operation. the busy flag rises. after the efusec finished the blowing process, the busy flag lowers. you can follow the guidelines below: 1. wait until busy is 0 2. set vfsource=2.8v from ground 3. set esel and wsel. 4. write efusec_wdat with your prefer value. 5. wait until busy is 0 6. if you want to blow other efuse macro, jump step 1 7. set vfsource= ground 8. write rd = 1. wait busy=0 and valid=1. check the efuse contents you blew. note1: each bit valued 1 in wdat means a blowing operation. blown bits can not be blown again. such that the final efuse content should be the original efuse content or wdat. note2: please perform read and write operations when pll is off. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 167 of 1535 efusec+0008 h efuse programming time efusec_pgmt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 109876543 2 10 name pgmt [ 14:0 ] type wo reset 0x82 pgmt this value defines the programming time. efusec+0010 h efuse data out efuse_d0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d0 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d0 type r/w reset 0 efusec+0014 h efuse data out efuse_d1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d1 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d1 type r/w reset 0 efusec+0018 h efuse data out efuse_d2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d2 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d2 type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 168 of 1535 efusec+001c h efuse data out efuse_d3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d3 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d3 type r/w reset 0 efusec+0020 h efuse data out efuse_d4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d4 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d4 type r/w reset 0 efusec+0024 h efuse data out efuse_d5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d5 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d5 type r/w reset 0 efusec+0028 h efuse data out efuse_d6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d6 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d6 type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 169 of 1535 efusec+002c h efuse data out efuse_d7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d7 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d7 type r/w reset 0 efusec+0030 h efuse data out efuse_d8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name efuse_d8 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d8 type r/w reset 0 efusec+0034 h efuse data out efuse_d9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name d89w p d67wp d45w p efuse_d9 type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name efuse _ d9 type r/w reset 0 efuse_d x efuse output data d xy wp write protection bit for efuse_d x and efuse_d y 0 efuse_d x and efuse_d y can be blown. 1 efuse_d x and efuse_d y can not be blown. 2.14 external memory interface 2.14.1 general description MT6516 incorporates a powerful and flexible memory controller, external memory interface, to connect with a variety of memory components. this controller provides one generic access scheme for flash memory, sram, psram and. up to 4 memory banks can be supported simultaneously, bank0-bank3, with a maximum size of 128mb each. this controller also provides another access scheme for dram (sdr/ddr), and 4 banks can be supported for simultaneous access, with a maximum size of 256mb of each bank. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 170 of 1535 the software program can treat different components by simply specifying certain predefined parameters. all these parameters are based on cycle time of system clock. the interface definition based on such scheme is listed in table 32 . note that, this interface always operates data in little endian format for all types of accesses. signal name type description xadmux i define admux or not in nor flash / psram ewait i wait signal input ed[31:0] i/o data bus ea[26:0] i/o address bus edqs[3:0] i/o data strobe in ddr ecs# [3:0] o bank3~bank0 selection signal ewr# o write enable strobe erd# o read enable strobe edqm[3:0]# o data mask eadv# o burst mode flash memory address latch signal eras# o row address latch signal (sdr/ddr) ecas# o column address latch signal (sdr/ddr) ecke# o dram clock enable signal (sdr/ddr) ec_clk o burst mode flash/psram memory clock signal ed_clk o dram clock signal ed_clk_b o dram clock invert signal (for ddr) table 32 external memory interface of MT6516 register address register name synonym emi + 0000h psram controller register for bank0 emi_cona emi + 0008h psram controller register for bank1 emi_conb emi + 0010h psram controller register for bank2 emi_conc emi + 0018h psram controller register for bank3 emi_cond emi + 0020h psram controller register for bank0 emi_cone emi + 0028h psram controller register for bank1 emi_conf emi + 0030h psram controller register for bank2 emi_cong emi + 0038h psram controller register for bank3 emi_conh emi + 0040h dram mr/emr emi_coni emi + 0048h dram controller timing configuration i emi_conj emi + 0050h dram controller timing configuration ii emi_conk emi + 0058h dram controller read data path configuration emi_conl emi + 0060h emi digital dll control emi_conm free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 171 of 1535 emi + 0068h dram controller function configuration emi_conn emi + 0070h emi general control register a emi_gena emi + 0078h emi general control register b emi_genb emi + 0080h emi general control register c emi_genc emi + 0088h emi general control register d emi_gend emi + 0090h modem side offset address emi_gene emi + 0098h emi in/out delay line control emi_dela emi + 00a0h emi in/out delay line control emi_delb emi + 00a8h emi in/out delay line control emi_delc emi + 00b0h emi in/out delay line control emi_deld emi + 00b8h emi in/out delay line control emi_dele emi + 00c0h emi in/out delay line control emi_delf emi + 00c8h emi in/out delay line control emi_delg emi + 00d0h emi in/out delay line control emi_delh emi + 00d8h emi in/out delay line control emi_deli emi + 00e0h emi in/out delay line control emi_delj emi + 00e8h mpu address set (region_0) emi_mpua emi + 00f0h mpu address set (region_1) emi_mpub emi + 00f8h mpu address set (region_2) emi_mpuc emi + 0100h mpu address set (region_3) emi_mpud emi + 0108h mpu address set (region_4) emi_mpue emi + 0110h mpu address set (region_5) emi_mpuf emi + 0118h mpu address set (region_6) emi_mpug emi + 0120h mpu address set (region_7) emi_mpuh emi + 0128h mpu region access configuration emi_mpui emi + 0130h mpu region access configuration emi_mpuj emi + 0138h mpu status emi_mpuk emi + 0140h mpu status emi_mpul emi + 0148h mpu error address emi_mpum emi + 0150h mpu error ap irq emi_mpun emi + 0158h mpu error md irq emi_mpuo emi + 0160h emi bus monitor enable emi_bmen emi + 0168h emi bus cycle counter emi_bcnt emi + 0170h emi transaction counter for all masters emi_tact emi + 0178h emi transaction counter for selected masters emi_tsct emi + 0180h emi double word counter for all masters emi_wact emi + 0188h emi double word counter for selected masters emi_wsct free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 172 of 1535 emi + 0190h emi bus-busy counter for all masters emi_bact emi + 0198h emi bus-busy counter for selected masters emi_bsct emi + 01a0h emi dummy read controls emi_drct emi + 01b0h dqsi auto-tracking control for cs[0] emi_dqsa emi + 01b8h dqsi auto-tracking control for cs[1] emi_dqsb emi + 01c0h dqsi auto-tracking control for cs[2] emi_dqsc emi + 01c8h dqsi auto-tracking control for cs[3] emi_dqsd emi + 01d0h dqsi auto-tracking calibrating delay value emi_dqsv emi + 01e0h modem side control register emi_mdcl table 33 external memory interface register map free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 173 of 1535 2.14.2 registers +0000h~0018h asynchronous psram and flash control registers emi_cona~d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name psize admu x asrd aswr aprd as_adv as_set ap_set as_cs_end type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w de_rese t 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 ad_rese t 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ap_wait_1 st ar_wait aw_wait as_hold adve n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w de_rese t 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 ad_rese t 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 +00020h ~0038h synchronous/asynchronous psram and flash control registers emi_cone~h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rd_w ait_e n wr_w ait_e n sy_rd sy_w r sy_set sy_rd_wait sy_hold sy_cs_end type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wplo wrps lss sram _a_la t /sram _rdpt r_to g rd_del_sel rd_x wait_ n_en wr_x wait_ n_en rd_x wait_ p_en wr_x wait_ p_en sy_wr_wait admu x_2t_ dv demu x_2t_ dv type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psize page size for ap_rd (page read mode), sy_rd (synchronous read mode) and sy_wr (synchronous write mode) 00 01 10 psize 8 byte 16 byte 32 byte admux admux/ad-demux memory selection 0 non admux type memory 1 admux type memory as_rd enable asynchronous read (only one of as_rd, ap_rd and sy_rd can be set to 1, others must be 0) 0 turn off asynchronous read 1 turn on asynchronous read free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 174 of 1535 as_wr enable asynchronous write (only one of as_wr, and sy_wr can be set to 1, others must be 0) 0 turn off asynchronous write 1 turn on asynchronous write ap_rd enable asynchronous page read (only one of as_rd, ap_rd and sy_rd can be set to 1, others must be 0) 0 turn off asynchronous page read (burst-page read) 1 turn on asynchronous page read (burst-page read) as_adv adjust adv time in every transaction of asynchronous mode. as_adv is only adjustable at as_wr/as_rd mode and adven = 1. (unit: cycle, default 0: 0t, 1:1t ??) ---- fig-1 as_set adjust init set up time in every transaction of asynchronous read/write mode. (unit: cycle, the set value must > 1, 1:2t, 2:3t??) ---- fig-2 ap_set adjust init set up time in every transaction of asynchronous page read mode. (unit: cycle, the set value must > 1, 1:2t, 2:3t??) ---- fig-4 as_cs_end adjust cs disable time in the end of every transaction in asynchronous mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-2 ap_wait_1st adjust first wait time in every transaction of page read mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-4 ar_wait adjust wait time in every transaction of asynchronous read mode. (unit: cycle, the set value must > 1, 1:2t, 2:3t??) ---- fig-3 aw_wait adjust wait time in every transaction of asynchronous wait mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-2 as_hold adjust hold time in every transaction of asynchronous mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-2 adven adv control in asynchronous read / write 0 disable 1 enable adv_out wave form timing fig-1 as_wr wave form timing free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 175 of 1535 fig-2 as_rd wave form timing $4@# 3%@# 8jeui "4@4&5 8jeui "3@8"*5 8jeui "4@$4@&/% %r@jo %bub fig-3 ap_rd wave form timing $4@# 3%@# 8jeui "1@4&5 8jeui "1@8"*5@tu 8jeui "4@$4@&/% "%%3@065 "%%3@ "%%3@ "%%3@ "%%3@ 8jeui "3@8"*5 8jeui "3@8"*5 8jeui "3@8"*5 %r@jo %bub@ %bub@ %bub@ %bub@ fig-4 rd_wait_en monitor xwait signal from external memory to emi controller at read 0 not monitor 1 monitor wr_wait_en monitor xwait signal from external memory to emi controller at write 0 not monitor 1 monitor sy_rd enable synchronous (burst) read (only one of as_rd, ap_rd and sy_rd can be set to 1, others must be 0) 0 disable 1 enable sy_wr enable synchronous (burst) write (only one of as_wr, and sy_wr can be set to 1, others must be 0) 0 disable 1 enable sy_set adjust init set up time in every transaction of synchronous mode. (unit: cycle, the set value must > 1, 1:2t, 2:3t?) ---- fig-5 sy_rd_wait adjust wait time in every transaction of synchronous read mode, after wait time passed the controller start to check input xwait signal (skip xwait unstable at the beginning). (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-5 sy_hold adjust hold time in every transaction of synchronous mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 176 of 1535 sy_cs_end adjust cs disable time in the end of every transaction in synchronous mode. (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-5 sy_wr_wait adjust wait time in every transaction of synchronous write mode, after wait time passed the controller start to check input xwait signal (skip xwait unstable at the beginning). (unit: cycle, default 0: 1t, 1:2t ??) ---- fig-6 sy_rd wave form timing &$@$-, $4@# 3%@# "%7@# 8jeui 4:@$4@&/% 8jeui 4:@4&5 8jeui 4:@3%@8"*5 98"*5 fig-5 sy_wr wave form timing &$@$-, $4@# 83@# 8jeui 4:@$4@&/% 8jeui 4:@4&5 8jeui 4:@83@8"*5 98"*5 8jeui 4:@)0-% fig-6 wpol enable xwait polarity change 0 disable 1 enable wrps access psram by wrap mode. (must be set to 1) lss access psram by half speed mode. if this bit is turned on, the output wave form timing will be doubled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 177 of 1535 &$@$-, $4@# 83@# 8jeui 4:@$4@&/% 8jeui 4:@4&5 8jeui 4:@83@8"*5 98"*5 8jeui 4:@)0-% sram_a_lat / sram_rdptr_tog sram_a_lat: sampling sram input data by internal adjustable clock first in synchronous read mode. (1t input data valid window when demux_2t_dv = 0 or admux_2t_dv = 0) sram_rd_ptr_tog: sram input data select (2t input data valid window when sram_2t_dv = 1). refer to the ?data_in_sel? signal as the following figure. 0 do not toggle (default) 1 to g g l e ebub@jo<> % % % % ebub@jo@dml ebub@jo@qus 'sffsvo sgg@ebub@jo<> % % '8efufdutuifgjstuebubmpdbujpo sgg@ebub@jo<> % % '8efufdutuifgjstuebubmpdbujpo ebub@jo@tfm'sffsvo xs@qus@di@e % % % % rd_del_sel the input data latency to internal read fifo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 178 of 1535 00 no delay 01 delay 1t latch 10 delay 2t latch 11 reserved note that under the asynchronous/page read mode, rd_del_sel must be set to ?h01. rd_xwait_n_en sampling input xwait signal by bus clock negative edge first in synchronous read mode. wr_xwait_n_en sampling input xwait signal by bus clock negative edge first in synchronous write mode. rd_xwait_p_en sampling input xwait signal by bus clock positive edge synchronous read mode. wr_xwait_p_en sampling input xwait signal by bus clock positive edge synchronous write mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 179 of 1535 (read/write mode use separate xwait controller circuit ) sy_wr_wait adjust wait time in every transaction of synchronous write mode. (0: 1clk, 1: 2clk ??) admux_2t_dv input data valid window of admux psram 0 1t (default) 1 2t (suggest to enable at high-speed synchronous read, and psram is set to the fixed latency mode) demux_2t_dv input data valid window of ad-demux psram 0 1t (default) 1 2t (suggest to enable at high-speed synchronous read, and psram is set to the fixed latency mode) +0040h dram mode register set control registers emi_coni bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mba1 mba0 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eba1 eba0 eba12 eba11 eba10 eba9 eba8 eba7 eba6 eba5 eba4 eba3 eba2 eba1 eba0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mba1~0 dram bank address setting when load mode register to dram ma12~0 dram mode register value eba1~0 dram bank address setting when load extended mode register to dram ea12~0 dram extended mode register value +0048h dram ac timing control 1 registers emi_conj bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pral_cyc ref_cyc exit_sref_cyc ldmr_cyc type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name act_rc_cyc trc_cyc rtw_cyc wr_wait_cy c rd_wait_c yc type r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 180 of 1535 reset 0 0 0 0 0 pral_cyc dram pre-charge cycle time (trp) (unit: cycle, de fault 0: 2t, 1:3t ?, relative wave form please reference to dram spec) ref_cyc dram refresh cycle time (trfc) (unit: cycle, default 0: 2t, 1:3t?, relative wave form please reference to dram spec) exit_sref_cyc dram exit self refresh to first valid comman d cycle time (txsr) (unit: cycle, default 0: 2t, 1:3t ..., relative wave form please reference to dram spec) ldmr_cyc dram load mode/extended-mode register cycle time (tmrd) (unit: cycle, default 0: 1t, 1:2t ?, relative wave form please reference to dram spec) act_rc_cyc dram active to read/write command delay cycle time (trcd) (unit: cycle, the set value must >= 2, 2:3t, 3:4t?, relative wave form please reference to dram spec) trc_cyc dram active to active command (same bank) delay cycle time (trc) (unit: cycle, the set value must 0:2t , 2:4t, 3:5t?, relative wave form please reference to dram spec) rtw_cyc read to write data turn-around time (under inter-bank access) for preventing from contention of dram data bus. (unit: cycle, 0/1/2/3 for delay 0/1/2/3t) $pnnboe 3fbe "$5 13& 8sjuf %bub 3% 3% 3% 8% 8% 8% %bubuvsobspvoeujnf 358@$:$<>
wr_wait_cyc dram write recovery cycle time (twr). (unit: cycle, default 0: 2t/0t, 1:3t/1t ? for sdr/ddr, relative wave form please reference to sdr/ddr dram spec) rd_wait_cyc dram read command to pre-charge delay cycle time (adjust the final read command to pre- charge command delay cycle time) (unit: cycle, default 0: 1t, 1:2t ?) +0050h dram ac timing control 2 registers emi_conk bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name refp_cyc type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 181 of 1535 name sdr_rd0_psel type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 refp_cyc auto refresh period cycle time (tref). note that refp_cyc value must be larger than ref_cyc value (emi_conj[27:24]). unit: cycle: default 0: 1t, 1:2t ? when ref_cnt_en (emi_conn[1]) = 1 & ref_fix_ck (emi_conn[2]) = 0 default 0: 0t, 1:1t ? when ref_fix_ck (emi_conn[2]) = 1, relative waveform please reference to dram spec. for example: if one external dram having 8192 rows needs to do refresh at 64ms, thus the average refresh period is 64ms/8192 = 7.8us ? if (ref_cnt_en = 1 & ref_fix_ck = 0): (refp_cyc +1)* (clock period) must < 7.8us ? if ref_fix_ck = 1: (refp_cyc)* (1/3.25mhz) must < 7.8us, to satisfy the dram refresh spec sdr_rd0_psel read phase delay for sdr input data bit [31:0] --- > 1 tape (0.1~0.2 ns) sdr_rdx_psel is not adjustable at sdr_a_lat = 0 and sdr_2t_dv = 0. $mpdl hfo %- %- %- 4fm<> 4fm<> *g tfm<>
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"ekvtu dmpdl +0058h dram ac timing control 3 registers emi_conl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pd_cyc type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ras_min_cyc sdr_2 t_dv sdr_a _lat / sdr_r dptr_ tog rd_del_sel type r/w r/w r/w r/w reset 0 0 0 0 0 pd_cyc enter and exit dram power down state cycle time (enter: 0/1/2?/7 = 1t/2t/3t?/8t, exit: 0/1/2?/7 = 1t/1t/2t?/7t) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 182 of 1535 &%@$-, &oufsesbn1%/tubuf $-,@%*4 &yjuesbn1%/tubuf $,& 8jeui 1%@$:$ 8jeui 1%@$:$ ras_min_cyc active to pre-charge minimum cycle time (unit: cycle, default 0: 2t, 1:3t ?, relative wave form please reference to dram spec) sdr_2t_dv input data valid window of sdr psram 0 1t (default) 1 2t (suggest to enable at high-speed read) sdr_a_lat / sdr_rdptr_tog sdr_a_lat: sampling sdr sram input data by internal adjustable clock first in synchronous read mode. (1t input data valid window when sdr_2t_dv = 0) sdr dram input data (2t valid window, sdr_2t_dv = 1) selection 0 do not toggle (default) 1 to g g l e rd_del_sel the delay time cycles from read command for input read data to be sampled at rd_fifo. (include cas latency, io pad delay, pcb delay) (unit: cycle, default 0: 1t, 1:2t ?, 7:8t) +0060h digital dll offset registers emi_conm bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name digital_dll_offset_3 digital_dll_offset_2 digital_dll_offset_1 digital_dll_offset_0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name digital_dll_cal_value type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 digital_dll_offset_3 digital dll offset value for adding an offset delay on dqs_3 1/5 t delay path digital_dll_offset_2 digital dll offset value for adding an offset delay on dqs_2 1/5 t delay path digital_dll_offset_1 digital dll offset value for adding an offset delay on dqs_1 1/5 t delay path digital_dll_offset_0 digital dll offset value for adding an offset delay on dqs_0 1/5 t delay path digital_dll_cal_value digital dll locking value for 1/5 t delay +0068h dram mode register set and refresh control registers emi_conn bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pral_ en aref1 _en aref2 _en ldmr _en ldem r_en addr _swa p addr_type dram_type type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 183 of 1535 name dqsi_cal_mo n cal_d one cal_e n sref_ st pdn_s t sref_ en pdn_e n ref_f ix_ck ref_c nt_en dra m_en type r/w r r/w r r r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 five dram initialize steps must be executed step by step : pral_en single pre-charge all enable (for dram initialize) arf1_en single auto-refresh-1 enable (for dram initialize) arf2_en single auto-refresh-2 enable (for dram initialize) ldmr_en single load mode register en able (for dram initialize) ldem_en single load extended mode register enable (for dram initialize) addr_swap swap msb of dram row address and ba[1] for partial array self refresh (pasr) 0 disable 1 enable 1iztjdbmbeesftt 3pxbeesftt #bolbeesftt $pmvno beesftt %%3 " %%3@5:1& (c
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addr_type dram address type addr_type row address bit bank d column dd sdr (ddr) 16 sdr (ddr) 32 010 12 2 8 64mb 128mb 011 12 2 9 128mb 256mb 100 13 2 9 256mb 512mb 101 13 2 10 512mb 1gb 110 14 2 10 1gb 2gb (others are reserved) dram_type dram type selection (sdr/ddr, data bus width 16/32 bits) 00 sdr-16 01 sdr-32 10 ddr-16 11 ddr-32 dqsi_cal_mon select cs dqs calibrating value for f/w read out free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 184 of 1535 00 select cs[0] dqs calibrati ng value for f/w read out 01 select cs[1] dqs calibrati ng value for f/w read out 10 select cs[2] dqs calibrati ng value for f/w read out 11 select cs[3] dqs calibrati ng value for f/w read out cal_done digital dll calibration status 0 not finish or calibration is disabled 1 done cal_en enable digital dll calibration circuit 0 disable 1 enable sref_st dram self refresh status 0 exit self refresh status 1 in self refresh status pdn_st dram power down status 0 exit power down status 1 in power down status sref_en dram self-refresh enable by ap side. both sref_en and sref_en_md (emi_mdcl[0]) should be enabled for entering self-refresh mode. 0 force dram to enter self refresh 1 force dram to exit self refresh pdn_en enable dram to enter power down mode when dram controller is idle (the controller will exit power down mode, and exercise auto refresh step to keep data correctness in dram, if the refresh time is reached) 0 disable 1 enable ref_fix_ck enable auto refresh with a fixed clock source (3.25mhz) for the refresh counter. note that ref_cnt_en (emi_conn[1]) is ignored when this bit is enabled! 0 refresh counter is by hclk_ck 1 refresh counter is by a fixed clock 3.25mhz (thus the clock switching will not affect the refresh rate to dram!) ref_cnt_en enable auto refresh to dram. note that this bit is ignored when ref_fix_ck (emi_conn[2]) is enabled! 0 disable 1 enable dram_en enable dram controller 0 disable 1 enable +0070h emi general control registers a emi_gena bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sw_psel sr_psel type r/w r/w reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 185 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hi_pio tras_ inter _dis sclk_ en dclk_ en hclk x2_ck _on cre_e n cre_v alue activ e_wr _dis activ e_rd_ dis paus e_str _en rwwr _inte r_dis rm1 rm0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sw_psel define emi output clock to psram phase select sw_psel[7:0] : adjust phase delay --- > 1 tape (0.1~0.2 ns) sw_psel is only adjustable at sw_default = 0 $mpdl hfo %- %- %- 4fm<> 4fm<> *g tfm<>
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"ekvtu dmpdl sr_psel define emi internal adjustable clock to sample (admux & ad-demux) psram input data sr_psel[7:0] : adjust phase delay --- > 1 tape (0.1~0.2 ns) sr_psel is not adjustable at data_a_lat = 0 and demux_2t_dv = 0 (admux_2t_dv = 0) $mpdl hfo %- %- %- 4fm<> 4fm<> *g tfm<>
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"ekvtu dmpdl hi_pio arbitration high priority for ahb 6 ~ 3 (ahb6~5 from ceva, ahb4~3 from md) 0 disable 1 enable tras_inter_dis dram inter-bank access is affected by the ras_min_cyc condition 0 not affected 1 affected sclken sram controller clock out enable 0 disable 1 enable dclken dram controller clock out enable 0 disable 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 186 of 1535 hclkx2_ck_on emi delay-line input hclkx2_ck enable. note that this bit must be enabled under burst-mode psram/nor and dram. 0 disable 1 enable cre_en assign ea26 as gpio function for psram cre 0 disable 1 enable cre_value assign cre output value active_wr_dis dram inter-bank access for write 0 enable 1 disable active_rd_dis dram inter-bank access for read 0 enable 1 disable &%@$-, %3".dpnnboe sfbe
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jg"$5*7&@83@%*4 13&@ /01 /01 /01 $"4@ pause_str_en emi dram controller enters self-refresh controlled by bus pause-start signal. when pause-start signal is asserted, emi dram controller automatically enters self-refresh mode. when pause- start signal is de-asserted, emi dram controller automatically exits self-refresh mode. pause-start signal is asserted only when ap side and md side sleep controller are both activated. 0 disable 1 enable rwwr_inter_dis dram inter-bank access for read to write and write to read 0 enable 1 disable rm1 booting control 0 internal boot 1 external boot when internal boot (rm1 = 0) is selected, arm will fetch 2 fixed instructions from emi and jump into the boot rom area. during the boot rom execution, rm1 must be set to 1 before burst transactions to emi! rm0 chip select remapping control free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 187 of 1535 0 cs[0]/cs[1] not change 1 cs[0]/cs[1] change +0078h emi io control registers b emi_genb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dqs_s mt dq_s mt dqs_p u dqs_p d dq_p u dq_p d dqs3s r dqs3e 2 dqs3e 4 dqs3e 8 dqs20 sr dqs2e 2 dqs2e 4 dqs2 e8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dqs1s r dqs1e 2 dqs1e 4 dqs1e 8 dqs0s r dqs0e 2 dqs0e 4 dqs0e 8 dcks r dcke2 dcke4 dcke8 scks r scke2 scke4 scke 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 home dqs_smt enable dqs input control by schmitt-trigger 0 disable 1 enable dq_smt enable dq input control by schmitt-trigger 0 disable 1 enable dqs_pu enable dqs pad pull up control 0 disable 1 enable dqs_pd enable dqs pad pull down control 0 disable 1 enable dq_pu enable dq pad pull up control 0 disable 1 enable dq_pd enable dq pad pull down control dqs3sr : dqs3 pad slew rate control 0 fast 1 slow dqs3ex dqs3 pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. dqs2sr dqs2 pad slew rate control 0 fast 1 slow dqs2ex dqs2 pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 188 of 1535 if all bits (e2~e8) = 0, the pad has basic 2ma driving. dqs1sr dqs1 pad slew rate control 0 fast 1 slow dqs1ex dqs1 pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. dqs0sr dqs0 pad slew rate control 0 fast 1 slow dqs0ex dqs0 pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. dcksr dck pad slew rate control 0 fast 1 slow dckex dck pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. scksr sck pad slew rate control 0 fast 1 slow sckex sck pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. +0080h emi io control registers c emi_genc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name easr eae2 eae4 eae8 edsr ede2 ede4 ede8 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 9 8 7 6 4 3 2 1 0 name ecss r ecse2 ecse4 ecse8 erws r erwe 2 erwe 4 erwe 8 eadv sr eadv e2 eadv e4 eadv e8 ercsr erce2 erce4 erce 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 easr address pad slew rate control 0 fast 1 slow eaex address pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 189 of 1535 edsr data pad slew rate control 0 fast 1 slow edex data pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. ecssr cs pad slew rate control 0 fast 1 slow ecsex cs pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. erwsr rd/wr pad slew rate control 0 fast 1 slow erwex rd/wr pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. eadvsr adv pad slew rate control 0 fast 1 slow eadvex adv pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. ercsr ras/cas pad slew rate control 0 fast 1 slow ercex ras/cas pad driving control e2: add 2ma, e4: add 4ma, e8: add 8ma. if all bits (e2~e8) = 0, the pad has basic 2ma driving. +0088h emi bank select registers emi_gend bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dram_cs_en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sram_cs_en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 dram_cs_en from bank_3 to bank _0 (all banks can be turned on, except the banks assigned to sram) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 190 of 1535 0 disable 1 enable sram_cs_en from bank _3 to bank _0 (all banks can be turned on, except the banks assigned to dram) 0 disable 1 enable +0090h modem side master address offset registers emi_gene bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md_addr_offset type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 md_addr_offset modem side master offset address +0098h emi delay control registers a emi_dela bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq31_out_del dq30_out_del dq29_out_del dq28_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq27_out_del dq26_out_del dq25_out_del dq24_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00a0h emi delay control registers b emi_delb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq23_out_del dq22_out_del dq21_out_del dq20_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq19_out_del dq18_out_del dq17_out_del dq16_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00a8h emi delay control registers c emi_delc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq15_out_del dq14_out_del dq13_out_del dq12_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq11_out_del dq10_out_del dq9_out_del dq8_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 191 of 1535 +00b0h emi delay control registers d emi_deld bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq7_out_del dq6_out_del dq5_out_del dq4_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq3_out_del dq2_out_del dq1_out_del dq0_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00b8h emi delay control registers e emi_dele bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq31_in_del dq30_in_del dq29_in_del dq28_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq27_in_del dq26_in_del dq25_in_del dq24_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00c0h emi delay control registers f emi_delf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq23_in_del dq22_in_del dq21_in_del dq20_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq19_in_del dq18_in_del dq17_in_del dq16_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00c8h emi delay control registers g emi_delg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq15_in_del dq14_in_del dq13_in_del dq12_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq11_in_del dq10_in_del dq9_in_del dq8_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00d0h emi delay control registers h emi_delh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dq7_in_del dq6_in_del dq5_in_del dq4_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dq3_in_del dq2_in_del dq1_in_del dq0_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 192 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00d8h emi delay control registers i emi_deli bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dqs3_out_del dqs2_out_del dqs1_out_del dqs0_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dqs3_in_del dqs2_in_del dqs1_in_del dqs0_in_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00e0h emi delay control registers j emi_delj bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dqs_i n_add 4 edclk_out_del ra_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dqm3_out_del dqm2_out_del dqm1_out_del dqm0_out_del type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dqs_in_add4 when 1/5t dll locked value ( emi_conm [3:1]) is 3?b111, dqsx_in_del[2] ( emi_deli ) values would set to 1. thus the dqsx_in_del values would add 4 if their original dqsx_in_del[2] is 0. 0 disable 1 enable dqx_out_del (31~0) ddr output data delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance dqx_in_del (31~0) ddr input data delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance dqsx_out_del (3~0) ddr output data strobe delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance dqsx_in_del (3~0) ddr input data strobe delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance. note that when dqs_in_add4 ( emi_delj [28]) is enabled and digital_dll_cal_value[3:1] ( emi_conm [3:1]) is locked to full (3?b111), dqsx_in_d el[3:0] values will add 4 if their original dqsx_in_del[2] is 0. the modified values of dqsx_in_del can also be read out by sw. edclk_out_del dram output clock delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance ra_out_del ddr output address delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance dqmx_out_del (3~0) ddr output data mask delay balance select (1tap: 0.1~0.2ns), for substrate or pcb skew balance free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 193 of 1535 +00e8h memory protect unit control registers a emi_mpua bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00f0h memory protect unit control registers b emi_mpub bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +00f8h memory protect unit control registers c emi_mpuc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0100h memory protect unit control registers d emi_mpud bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_3 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_3 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0108h memory protect unit control registers e emi_mpue bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 194 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0110h memory protect unit control registers f emi_mpuf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_5 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_5 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0118h memory protect unit control registers g emi_mpug bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0120h memory protect unit control registers h emi_mpuh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_start_addr_7 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_stop_addr_7 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_start_addr_x memory protect region x start address. {mpu_start_addr_x, 14?b0}, total 30-bit mpu_stop_addr_x memory protect region x stop address. {mpu_stop_addr_x, 14?b0}, total 30-bit +0128h memory protect unit control registers i emi_mpui bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name md_r7 md_r 6 md_r 5 md_r 4 md_r 3 md_r 2 md_r 1 md_r 0 md_ w7 md_ w6 md_ w5 md_ w4 md_ w3 md_ w2 md_ w1 md_ w0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ap_r 7 ap_r 6 ap_r 5 ap_r 4 ap_r 3 ap_r 2 ap_r 1 ap_r 0 ap_w 7 ap_w 6 ap_w 5 ap_w 4 ap_w 3 ap_w 2 ap_w 1 ap_ w0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 195 of 1535 +0130h memory protect unit control registers j emi_mpuj bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m7_e n m6_e n m5_e n m4_e n m3_e n m2_e n m1_e n m0_e n type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cv_r 7 cv_r 6 cv_r 5 cv_r 4 cv_r 3 cv_r 2 cv_r 1 cv_r 0 cv_w 7 cv_w 6 cv_w 5 cv_w 4 cv_w 3 cv_w 2 cv_w 1 cv_ w0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 md_rx memory protect region_x (7~0) forbid md-side read. 0 disable 1 enable md_wx memory protect region_x (7~0) forbid md-side write. 0 disable 1 enable ap_rx memory protect region_x (7~0) forbid ap-side read. 0 disable 1 enable ap_wx memory protect region_x (7~0) forbid ap-side write. 0 disable 1 enable mx_en memory protect region_x (7~0) interrupt . 0 disable 1 enable cv_rx memory protect region_x (7~0) forbid ceva-side read. 0 disable 1 enable cv_wx memory protect region_x (7~0) forbid ceva -side write. 0 disable 1 enable +0138h memory protect unit control registers k (ap & md can read) emi_mpuk bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name md_r 7v md_r 6v md_r 5v md_r 4v md_r 3v md_r 2v md_r 1v md_r 0v md_ w7v md_ w6v md_ w5v md_ w4v md_ w3v md_ w2v md_ w1v md_ w0v type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ap_r 7v ap_r6 v ap_r 5v ap_r 4v ap_r 3v ap_r 2v ap_r 1v ap_r 0v ap_w 7v ap_w 6v ap_w 5v ap_w 4v ap_w 3v ap_w 2v ap_w 1v ap_ w0v type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 196 of 1535 +0140h memory protect unit control registers l (ap & md can read) emi_mpul bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_error_master[6:0] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cv_r 7v cv_r6 v cv_r 5v cv_r 4v cv_r 3v cv_r 2v cv_r 1v cv_r 0v cv_w 7v cv_w 6v cv_w 5v cv_w 4v cv_w 3v cv_w 2v cv_w 1v cv_ w0v type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_error_master memory protect error master 6 ~ 0 md_rx memory protect region_x (7~0) md-side read violate. md_wx memory protect region_x (7~0) md-side write violate. ap_rx memory protect region_x (7~0) ap-side read violate. ap_wx memory protect region_x (7~0) ap-side write violate. cv_rx memory protect region_x (7~0) ceva-side read violate. cv_wx memory protect region_x (7~0) ceva-side write violate. +0148h memory protect unit control registers m (ap & md can read) emi_mpum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mpu_error_address type r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpu_error_address type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_error_address memory protecting error address +0150h memory protect unit control registers n (ap & md can read) emi_mpun bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cv_ir q ap_ir q type wc wc reset 0 0 ap_irq memory protect error interrupt to ap side (write clear only by ap). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 197 of 1535 cv_irq memory protect error interrupt to ceva side (write clear only by ap). note: 1. ap accesses protected area: (a) issue interrupts to inform ap, md, ceva (b) ap & ceva interrupts are cleared by ap (c) md interrupt is cleared by md 2. md accesses protected area: (a) issue interrupts to inform md, ap (b) md interrupt is cleared by md (c) ap interrupt is cleared by ap 3. ceva accesses protected area: (a) issue interrupts to inform ceva, ap (b) both interrupts are cleared by ap +0158h memory protect unit control registers o (ap & md can read) emi_mpuo bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md_ir q type wc reset 0 md_irq memory protect error interrupt to md side (write clear only by md). note: 1. ap accesses protected area: (a) issue interrupts to inform ap, md, ceva (b) ap & ceva interrupts are cleared by ap (c) md interrupt is cleared by md 2. md accesses protected area: (a) issue interrupts to inform md, ap (b) md interrupt is cleared by md (c) ap interrupt is cleared by ap 3. ceva accesses protected area: (a) issue interrupts to inform ceva, ap (b) both interrupts are cleared by ap +0160h emi bus monitor co ntrol registers emi_bmen bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sel_master type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 198 of 1535 name sel_s ame_ bank sel_id le_tr ans sel_i nter_ ref sel_i nter_ bank sel_d iff_c s sel_d ram_i dle bc_o verr un bus_mon_r w bus_ mon_ paus e bus_ mon_ en type r/w r/w r/w r/w r/w r/w r r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 sel_master monitor the selected masters (master 0 ~ master 11) emi_bmen[16]: dcache emi_bmen[17]: ap dma emi_bmen[18]: icache emi_bmen[19]: md l1 cache emi_bmen[20]: md dma emi_bmen[21]: ceva1 emi_bmen[22]: ceva2 emi_bmen[23]: gmc1 1 (from graph1) emi_bmen[24]: gmc1 2 (from graph1) emi_bmen[25]: gmc2 1 (from graph2) emi_bmen[26]: gmc2 2 (from graph2) emi_bmen[27]: dummy read sel_same_bank select word_all_cnt/same_bank_cnt when 0/1 sel_idle_trans select word_cnt/idle_trans_cnt when 0/1 sel_inter_ref select busy_all_cnt/inter_ref_cnt when 0/1 sel_inter_bank select busy_cnt/inter_bank_cnt when 0/1 sel_diff_cs select buscyc_cnt/diff_cs_cnt when 0/1 note that trans_all_cnt = same_bank_cnt + idle_trans_cnt + inter_ref_cnt + inter_bank_cnt + diff_cs_cnt sel_dram_idle select trans_cnt/dram_idle_cnt when 0/1 bc_overrun bus counter (buscyc_cnt[31:0]) overrun, and it is cleared by (bus_mon_en = 0) bus_mon_rw bus monitor for read/write 00 monitor both read/write transactions 01 monitor only read transactions 10 monitor only write transactions 11 monitor both read/write transactions bus_mon_pause pause the monitor circuit bus_mon_en enable the monitor circuit. when disabl e, all monitor counters will be cleared free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 199 of 1535 +0168h emi bus cycle counters emi_bcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buscyc_cnt [31:16] / diff_cs_cnt[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buscyc_cnt [15:0] / diff_cs_cnt[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 buscyc_cnt / diff_cs_cnt bus cycle counter, and will keep to maximum when reach / counters for number of different cs transa ction, and will keep to maximum wh en reach. the counter selection is by emi_bmen [11] (sel_diff_cs). +0170h emi total transaction counters emi_tact bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name trans_all_cnt [31:16] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trans_all_cnt [15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trans_all_cnt counter for transactions of all masters (master 0 ~ master 11), and will keep to maximum when reach +0178h emi transaction counters emi_tsct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name trans_ cnt [31:16] / dram_idle_cnt[31:16] type r 8bjubqfsjpe 4fu 4&-@."45&3<> #64@.0/@38<> 4fu #64@.0/@&/ 4fu #64@.0/@1"64& $ifdl #$@07&336/ $mfbs #64@.0/@&/ 3fbecvtdzdmf usbotbdujpo xpseboe cvtzcvtzdpvoufst 3ftvmu bddvnvmbufe $mfbs #64@.0/@1"64& $mfbs #64@.0/@&/ :ft /p :ft /p free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 200 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trans_ cnt [15:0] / dram_idle_cnt[15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trans_cnt / dram_idle_cnt counter for transactions of selected masters (master 0 ~ master 11), and will keep to maximum when reach / counters for id le cycles of dram data bus, and will keep to maximum when reach. the counter selection is by emi_bmen [10] (sel_dram_busy). +0180h emi total word counters emi_wact bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name word_all_cnt [31:16] / same_bank_cnt[31:16] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name word_all_cnt [15:0] / same_bank_cnt[15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word_all_cnt / same_bank_cnt counter for access amount (unit: double words, 8-byte) to emi of all masters (master 0 ~ master 11), and will keep to maximum when reach / counters for number of same-bank transaction, and will keep to maximum when reach. the counter selection is by emi_bmen [15] (sel_same_bank). +0188h emi word counters emi_wsct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name word_ cnt [31:16] / idle_trans_cnt[31:16] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name word_ cnt [15:0] / idle_trans_cnt[15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word_cnt / idle_trans_cnt counter for access amount (unit: double words, 8-byte) to emi of selected masters (master 0 ~ mast er 11), and will keep to maximum when reach / counters for number of idle to read/write transaction, and will keep to maximum when reach. the counter selection is by emi_bmen [14] (sel_idle_trans). +0190h emi total access cycle counters emi_bact bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name busy_all_cnt [31:16] / inter_ref_cnt[31:16] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy_all_cnt [15:0] / inter_ref_cnt[15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 201 of 1535 busy_all_cnt / inter_ref_cnt counter for access cycles to emi of all masters (master 0 ~ master 11), and will keep to maximum when reach / counters for number of inter-bank access blocked by refresh cycles, and will keep to maximum when reach. the counter selection is by emi_bmen [13] (sel_inter_ref). +0198h emi access cycle counters emi_bsct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name busy_cnt [31:16] / inter_bank_cnt[31:16] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy_cnt [15:0] / inter_bank_cnt[15:0] type r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 busy_cnt / inter_bank_cnt counter for access cycles to emi of selected masters (master 0 ~ master 11) / counters for number of inter-bank transactions to dram bus, and will keep to maximum when reach. the counter selection is by emi_bmen [12] (sel_inter_bank) +01a0h emi dummy read co ntrol registers emi_drct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dummy_rd_addr type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dummy_rd_p eriod dummy_rd_burst dummy_rd_ size dr_te st_m ode dr_cs _tog gle dum my_r d_en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 dummy_rd_addr dummy read address {dummy_rd_addr[29:16], 16?b0}. the cs address addr[29:28] will be sequentially toggled if dr_cs_toggle is enabled. dummy_rd_period when dr_test_mode is disabled, the dummy read period, 0/1/2/3 = 1.288/2.576/5.152/10.304 seconds when emi clock is 104mhz. note that when dr_cs_toggle is enabled, the dummy read will issue to each installed rank ( emi_gend [19:16], dram_sc_en) sequentially according to this period setting. thus the dummy read period to each rank will be exte nded if multiple ra nks are installed! dummy_rd_burst burst type of ahb protocol for dummy read (?b001 incr is not supported!) 000 single 001 reserved 010 wrap 4 (suggest) 011 incr 4 100 wrap 8 101 incr 8 110 wrap 16 111 incr 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 202 of 1535 dummy_rd_size transfer size of ahb protocol for dummy read 00 1-byte 01 2-byte 10 4-byte (suggest) 11 8-byte dr_test_mode when enabled, the dummy read period (dummy_rd_period) is reduced to 0/1/2/3 = 10.24/20.48/40.96/81.92 us when emi clock is 104mhz dr_cs_toggle toggle dram cs for dummy read transaction 0 dummy read cs address is by dummy_rd_addr 1 dummy read cs address will sequenti ally issue to installed dram cs?s ( emi_gend [19:16], dram_sc_en) dummy_rd_en enable the dummy read function. when emi enters self-refresh mode, dummy read function is automatically disabled. manually turn off emi_drct[0]: dummy_rd_en before enter self-refresh mode is unnecessary. +01b0h ~ 01c8 emi dqs auto tracking control registers emi_dqsa ~ d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dqsi3 _cal_ enab le dqsi3_dlysel dqsi2 _cal_ enab le dqsi2_dlysel type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dqsi1 _cal_ enab le dqsi1_dlysel dqsi0 _cal_ enab le dqsi0_dlysel type r/w r/w r/w r/w reset 0 0 0 0 emi_dqsa for cs[0], emi_dqsb for cs[1], emi_dqsc for cs[2] and emi_dqsd for cs[3] dqsix_cal_enable enable auto-tracking function for input dqs[x] dqsix_dlysel[6:0] delay selection of auto-trackin g function for input dqs[x] dqsix_dlysel[6:5]: 00/01/10/11 = delay 0t/1t/2t/3t of hclk_ck (1x clock) dqsix_dlysel[4]: 0/1 = delay 0t/1t of hclkx2_ck (2x clock) dqsix_dlysel[3]: 0/1 = delay 0t/0.5t of hclkx2_ck (2x clock) dqsix_dlysel[2:0]: delay 0.3ns/1tap at typical case +01d0h emi dqs auto tracking value registers emi_dqsv bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name 0 dqsi3_dlysel_cal 0 dqsi2_dlysel_cal type r r r r reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 0 dqsi1_dlysel_cal 0 dqsi0_dlysel_cal free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 203 of 1535 type r r r r reset 0 0 0 0 dqsix_dlysel_cal[6:0] calibrating delay value of auto-tra cking function for input dqs[x], the corresponding cs is selected by emi_conn[15:14] (dqsi_cal_mon) dqsix_dlysel_cal[6:5]: 00/01/10/11 = delay 0t/1t/2t/3t of hclk_ck (1x clock) dqsix_dlysel_cal [4]: 0/1 = delay 0t/1t of hclkx2_ck (2x clock) dqsix_dlysel_cal [3]: 0/1 = delay 0t/0.5t of hclkx2_ck (2x clock) dqsix_dlysel_cal [2:0]: delay 0.3ns/1tap at typical case +01e0h emi modem side control registers emi_mdcl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sref_ st_md sref_ en_m d type r r/w reset 0 0 sref_st_md dram self refresh status by md read 0 not in self refresh 1 in self refresh sref_en_md dram self-refresh enable by modem side. both sref_en ( emi_conn [5]) and sref_en_md should be enabled for entering self-refresh mode. 0 force dram to exit self refresh 1 force dram to enter self refresh 2.14.3 1.1 emi ahb & gmc bus monitor in order to evaluate MT6516 system performance, this emi ahb & gmc bus monitor is added to observe emi front-end ahb & gmc bus behavior and record some useful data, such as latency, data amount, and so on. this monitor locates at stage2 in the following figure. emi ahb bus totally has 7 ports, including 3 ports from apmcusys, 2 ports from mdmcusys, and 2 ports from cevasys, while gmc bus has four ports. this monitor only can observe one port at a time. figure1. MT6516 performance monitor overview register address register name synonym 8003_7000h emi bus monitor enable register emimon_en 8003_7004h emi bus monitor latch register emimon_latch 8003_7008h emi bus monitor latch clear register emimon_latch_clr 8003_700ch emi bus monitor read/write selection register emimon_rw free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 204 of 1535 8003_7010h emi bus monitor cp/dp selection register emimon_max_sel 8003_7014h emi bus monitor idle mode selection register emimon_isel 8003_7018h emi bus monitor source selection register emimon_srcsel 8003_701ch emi bus monitor cycle count register emimon_cyccnt 8003_7020h emi bus monitor max latency register emimon_maxlat 8003_7024h emi bus monitor max command/data phase register emimon_maxcpdp 8003_7028h emi bus monitor command phase accumulation register emimon_cp 8003_702ch emi bus monitor data phase accumulation register emimon_dp 8003_7030h emi bus monitor idle cycle count register emimon_idle 8003_7034h emi bus monitor request number register emimon_req 8003_7038h emi bus monitor data beat register emimon_dbt 8003_703ch emi bus monitor data byte register emimon_dbyte 8003_7040h emi bus monitor ultra request count register emimon_ultra 8003_7044h emi bus monitor clear register emimon_clr table 34 apb register map 2.14.4 1.1.1 register definition 8003_7000h emi bus monitor enable register emimon_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bus_ mon_ en type r/w reset 0 bus_mon_en : enable emi bus monitor 8003_7004h emi bus monitor latch register emimon_latch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name latch type wc free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 205 of 1535 reset 0 latch : write this register no matter what value will perform latch operation to store counter value into register 8003_7008h emi bus monitor latch clear register emimon_latch _clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name latch _clr type r/w reset 0 latch_clr : indicate while latch command is performed also clear counter value 8003_700ch emi bus monitor read/write selection register emimon_rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rw_ind type r/w reset 0 rw_ind : indicate read or write or both command is monitored 3?b011 : read 3?b100 : write 3?b001 : read & write 8003_7010h emi bus monitor cp/dp selection register emimon_max_s el bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cpdp type r/w reset 0 cpdp : indicate command phase or data phase maximal duration should recorded 0 : data phase 1 : command phase free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 206 of 1535 8003_7014h emi bus monitor idle mode selection register emimon_isel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isel type r/w reset 0 isel : indicate data phase should be counted in idle mode or not 0 : count in 1 : not count in 8003_7018h emi bus monitor source selection register emimon_srcse l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srcsel type r/w reset 0 srcsel : indicate which emi port is selected 12?h1 : ap arm9 d bus 12?h2 : ap dma bus 12?h4 : ap arm9 i bus 12?h8 : md arm7 i/d bus 12?h10 : md dma bus 12?h20 : ceva ahb1 bus 12?h40 : ceva ahb2 bus 12?h80 : first gmc1 bus 12?h100 : second gmc1 bus 12?h200 : first gmc2 bus 12?h400 : second gmc2 bus 12?h800 : combined first and second gmc1 bus 12?h1000 : combined first and second gmc2 bus 8003_701ch emi bus monitor cycle count register emimon_cycc nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cyccnt[31:16] type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 207 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cyccnt[15:0] type ro reset 1 cyccnt : bus cycle count in monitor window from start to end. if reach maximal value (32?hffffffff), this register keeps maximal value. 8003_7020h emi bus monitor max latency register emimon_maxl at bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name maxlat[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name maxlat[15:0] type ro reset 0 ahb : gmc : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 208 of 1535 max_latency : this register records maximal latency in one single bus transaction within monitor window. if reach maximal value (32?hffffffff), this register w ill hold maximal value. latency definition is shown below. latency = command phase + data phase + data beat command phase : the cycle count from master starts to issue request to slave accepts command data phase : the cycle count from slave accepts command to slave accepts or returns data data beat : always 1 in ahb. each ahb transaction handles one data. in gmc, data beat equals to burst type 8003_7024h emi bus monitor max command/data phase register emimon_maxc pdp bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name maxcpdp[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name maxcpdp[15:0] type ro reset 0 maxcpdp : this register records maximal command phase or data phase duration within monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. 8003_7028h emi bus monitor command phase accumulation register emimon_cp bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cp[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cp[15:0] type ro reset 0 cp : this register records total command phase cycles of all transactions within monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 209 of 1535 8003_702ch emi bus monitor data phase accumulation register emimon_dp bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dp[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dp[15:0] type ro reset 0 dp : this register records total data phase cycles of all transactions within monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. 8003_7030h emi bus monitor idle cycle count register emimon_idle bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name idle_cnt[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name idle_cnt[15:0] type ro reset 0 idle_cnt : this register records total idle cycles within monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. idle cycle means there are no transactions on the bus as shown in the following figure. whether data phase counts in idle cycle or not depends on emimon_isel setting. ahb : hclk_ck hsel hready read phase write phase hwrite idle phase mode 0 idle phase mode 0 idle phase mode 1 gmc : 8003_7034h emi bus monitor request number register emimon_req bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name req_cnt[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name req_cnt[15:0] type ro reset 0 req_cnt : this register records total re quest counts within monitor window. if reach maximal value (32?hffffffff), free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 210 of 1535 this register will hold maximal value. burst request only counts once though there are more than one transactions in ahb. this figure is a simple example that 3 requests transmit on the ahb bus. 1 23 hclk_ck hsel hready 8003_7038h emi bus monitor data beat register emimon_dbt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dbt_cnt[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dbt_cnt[15:0] type ro reset 0 dbt_cnt : this register records total data beat counts wi thin monitor window. if reaches maximal value (32?hffffffff), this register will hold maximal value. this value equals to transaction burst type summation. 8003_703ch emi bus monitor data byte register emimon_dbyt e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dbyte_cnt[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dbyte_cnt[15:0] type ro reset 0 dbyte_cnt : this register records total data byte counts wi thin monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. 8003_7040h emi bus monitor ultra request count register emimon_ultr a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ultra_cnt[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ultra_cnt[15:0] type ro reset 0 ultra_cnt : this register records gmc ultra request count within monitor window. if reach maximal value (32?hffffffff), this register will hold maximal value. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 211 of 1535 8003_7044h emi bus monitor clear register emimon_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clr type r/w reset 0 clr : while assert, clear all counter value 8003_7800h emi bus monitor arm liniter emimon_limiter bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name limit_req type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limit_req limit_cyc limit_ en type r/w r/w r/w reset 0 0 0 limit the corresponding target mom_srcsel==0 => arm9d mom_srcsel==5 => ceva mom_srcsel==6 => ceva it will limit target?s request number must be less t han {limit_req,7?b0} every {limit_cyc,12?b0} cycles 2.15 general purpose inputs/outputs MT6516 offers 147 general-purpose i/o pins. by setting the control registers, mcu software can control the direction, the output value, and read the input values on these pins. these gpios and are multiplexed with other functionalities to reduce the pin count. figure 18 gpio block diagram gpios at reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 212 of 1535 upon a hardware reset (sysrst#), gpios are all configured as inputs and the following alternative usages of the gpio pins are enabled. these gpios are used to latch the inputs upon reset to memorize the desired configuration to ensure that the system restarts or boots up in the right mode. 2.15.1 register definitions 8000_2000h gpio direction control register 1 gpio_dir1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2010h gpio direction control register 2 gpio_dir2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2020h gpio direction control register 3 gpio_dir3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2030h gpio direction control register 4 gpio_dir4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2040h gpio direction control register 5 gpio_dir5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2050h gpio direction control register 6 gpio_dir6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 213 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2060h gpio direction control register 7 gpio_dir7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2070h gpio direction control register 8 gpio_dir8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2080h gpio direction control register 9 gpio_dir9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2090h gpio direction control register 10 gpio_dir10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset 0 0 0 gpio n gpio direction control 0 gpios are configured as input 1 gpios are configured as output 8000_2100h gpio pull-up/pull-d own enable register 1 gpio_pullen 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 8000_2110h gpio pull-up/pull-d own enable register 2 gpio_pullen 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 214 of 1535 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2120h gpio pull-up/pull-d own enable register 3 gpio_pullen 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2130h gpio pull-up/pu ll-down enable regi ster 4 gpio_pullen4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2140h gpio pull-up/pu ll-down enable regi ster 5 gpio_pullen5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2150h gpio pull-up/pu ll-down enable regi ster 6 gpio_pullen6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2160h gpio pull-up/pu ll-down enable regi ster 7 gpio_pullen7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8000_2170h gpio pull-up/pu ll-down enable regi ster 8 gpio_pullen8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 215 of 1535 8000_2180h gpio pull-up/pu ll-down enable register 9 gpio_ pullen 9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 8000_2190h gpio pull-up/pu ll-down enable regist er 10 gpio_ pullen 10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset 1 1 1 gpio n gpio pull-up/pull-down control 8000_2200h gpio pull-up/pull-down selection register 1 gpio_pullsel 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2210h gpio pull-up/pull-down selection register 2 gpio_pullsel 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2220h gpio pull-up/pull-down selection register 3 gpio_pullsel 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 216 of 1535 8000_2230h gpio pull-up/pull-down selection register 4 gpio_pullsel 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2240h gpio pull-up/pull-down selection register 5 gpio_pullsel 5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2250h gpio pull-up/pull-down selection register 6 gpio_pullsel 6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2260h gpio pull-up/pull-down selection register 7 gpio_pullsel 7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2270h gpio pull-up/pull-down select ion register 8 gpio_pullsel8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 217 of 1535 8000_2280h gpio pull-up/pull-down select ion register 9 gpio_ pullsel9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd 8000_2290h gpio pull-up/pull-down selection register 10 gpio_ pullsel10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset 0 0 0 note pd pd pd gpio n gpio pull-up/pull-down selection control 0 gpios pull-down 1 gpios pull-up 8000_2300h gpio data inversion control register 1 gpio_dinv1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2310h gpio data inversion control register 2 gpio_dinv2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2320h gpio data inversion control register 3 gpio_dinv3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2330h gpio data inversion control register 4 gpio_dinv4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 218 of 1535 8000_2340h gpio data inversion control register 5 gpio_dinv5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2350h gpio data inversion control register 6 gpio_dinv6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2360h gpio data inversion control register 7 gpio_dinv7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2370h gpio data inversion control register 8 gpio_dinv8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2380h gpio data inversion control register 9 gpio_ dinv9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2390h gpio data inversion control register 10 gpio_ dinv10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset 0 0 0 gpion gpio inversion control 0 gpios data inversion disable 1 gpios data inversion enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 219 of 1535 8000_2400h gpio data output register 1 gpio_dout1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2410h gpio data output register 2 gpio_dout2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2420h gpio data output register 3 gpio_dout3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2430h gpio data output register 4 gpio_dout4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2440h gpio data output register 5 gpio_ dout5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2450h gpio data output register 6 gpio_dout6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2460h gpio data output register 7 gpio_dout7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 220 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2470h gpio data output register 8 gpio_dout8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2480h gpio data output register 9 gpio_ dout9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000_2490h gpio data output register 10 gpio_ dout10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset 0 0 0 gpion gpio data output control 0 gpios data output 0 1 gpios data output 1 8000_2500h gpio data input register 1 gpio_din1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 5 gpio1 4 gpio1 3 gpio1 2 gpio1 1 gpio1 0 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2510h gpio data input register 2 gpio_din2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 1 gpio3 0 gpio2 9 gpio2 8 gpio2 7 gpio2 6 gpio2 5 gpio2 4 gpio2 3 gpio2 2 gpio2 1 pgio2 0 gpio1 9 gpio1 8 gpio1 7 gpio1 6 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2520h gpio data input register 3 gpio_din3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio4 7 gpio4 6 gpio4 5 gpio4 4 gpio4 3 gpio4 2 gpio4 1 gpio4 0 gpio3 9 gpio3 8 gpio3 7 gpio3 6 gpio3 5 gpio3 4 gpio3 3 gpio3 2 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 221 of 1535 reset x x x x x x x x x x x x x x x x 8000_2530h gpio data input register 4 gpio_din4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio6 3 gpio6 2 gpio6 1 gpio6 0 gpio5 9 gpio5 8 gpio5 7 gpio5 6 gpio5 5 gpio5 4 gpio5 3 gpio5 2 gpio5 1 gpio5 0 gpio4 9 gpio4 8 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2540h gpio data input register 5 gpio_ din5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7 9 gpio7 8 gpio7 7 gpio7 6 gpio7 5 gpio7 4 gpio7 3 gpio7 2 gpio7 1 gpio7 0 gpio6 9 gpio6 8 gpio6 7 gpio6 6 gpio6 5 gpio6 4 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2550h gpio data input register 6 gpio_din6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio9 5 gpio9 4 gpio9 3 gpio9 2 gpio9 1 gpio9 0 gpio8 9 gpio8 8 gpio8 7 gpio8 6 gpio8 5 gpio8 4 gpio8 3 gpio8 2 gpio8 1 gpio8 0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2560h gpio data input register 7 gpio_din7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 11 gpio1 10 gpio1 09 gpio1 08 gpio1 07 gpio1 06 gpio1 05 gpio1 04 gpio1 03 gpio1 02 gpio1 01 gpio1 00 gpio9 9 gpio9 8 gpio9 7 gpio9 6 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset x x x x x x x x x x x x x x x x 8000_2570h gpio data input register 8 gpio_din8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 27 gpio1 26 gpio1 25 gpio1 24 gpio1 23 gpio1 22 gpio1 21 gpio1 20 gpio1 19 gpio1 18 gpio1 17 gpio1 16 gpio1 15 gpio1 14 gpio1 13 gpio1 12 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset x x x x x x x x x x x x x x x x 8000_2580h gpio data input register 9 gpio_ din9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio1 43 gpio1 42 gpio1 41 gpio1 40 gpio1 39 gpio1 38 gpio1 37 gpio1 36 gpio1 35 gpio1 34 gpio1 33 gpio1 32 gpio1 31 gpio1 30 gpio1 29 gpio1 28 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset x x x x x x x x x x x x x x x x 8000_2590h gpio data input register 10 gpio_ din10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 222 of 1535 name gpio1 46 gpio1 45 gpio1 44 type r/w r/w r/w reset x x x gpion gpios data input 8000_2600h gpio mode control register 1 gpio_mode1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio7_m gpio6_m gpio5_m gpio4_m gpio3_m gpio2_m gpio1_m gpio0_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio0_m gpio mode selection 00 configured as gpio function 01 o: pwm4 10 o: clk_out0 11 reserved gpio1_m gpio mode selection 00 configured as gpio function 01 i: eadmux 10 o: clk_out1 11 i: external interrupt input 15 (eint15) gpio2_m gpio mode selection 00 configured as gpio function 01 reserved 10 i2s_ws 11 reserved gpio3_m gpio mode selection 00 configured as gpio function 01 reserved 10 i2s_clk 11 reserved gpio4_m gpo mode selection 00 configured as gpio function 01 reserved 10 i2s_dat 11 reserved gpio5_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio6_m gpio mode selection 00 configured as gpio function free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 223 of 1535 01 reserved 10 reserved 11 reserved gpio7_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved 8000_2610h gpio mode control register 2 gpio_mode2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio15_m gpio14_m gpio13_m gpio12_m gpio11_m gpio10_m gpio9_m gpio8_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio8_m gpio mode selection 00 configured as gpio function 01 reserved 10 o: clk_out2 11 reserved gpio9_m gpio mode selection 00 configured as gpio function 01 reserved 10 o: clk_out3 11 reserved gpio10_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio11_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio12_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio13_m gpio mode selection 00 configured as gpio function 01 i: ceva_tck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 224 of 1535 10 reserved 11 reserved gpio14_m gpio mode selection 00 configured as gpio function 01 i: ceva_tms 10 reserved 11 reserved gpio15_m gpio mode selection 00 configured as gpio function 01 i: ceva_tdi 10 reserved 11 reserved 8000_2620h gpio mode control register 3 gpio_mode3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio23_m gpio22_m gpio21_m gpio20_m gpio19_m gpio18_m gpio17_m gpio16_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio16_m gpio mode selection 00 configured as gpio function 01 ceva_tdo 10 reserved 11 reserved gpio17_m gpio mode selection 00 configured as gpio function 01 o: cmos sensor reset control signal (cmrst) 10 o: dsp2_gpo3 11 o: master dsp task id bit 0 (d1_tid0) gpio18_m gpio mode selection 00 configured as gpio function 01 o: cmos sensor power down control signal (cmpdn) 10 o: dsp2_gpo2 11 o: master dsp task id bit 1 (d1_tid1) gpio19_m gpio mode selection 00 configured as gpio function 01 i: cmvref 10 o: dsp_gpo3 11 o: tdma debug (tbtxen) gpio20_m gpio mode selection 00 configured as gpio function 01 i: cmhref 10 o: dsp_gpo2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 225 of 1535 11 o: tdma debug (tbtxfs) gpio21_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 8 (eint8) 10 o: dsp_gpo1 11 o: tdma debug (tbrxen) gpio22_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 9 (eint9) 10 o: dsp_gpo0 11 o: tdma debug (tbrxfs) gpio23_m gpio mode selection 00 configured as gpio function 01 keyboard row 5 (krow5) 10 o: dsp2_gpo1 11 reserved 8000_2630h gpio mode control register 4 gpio_mode4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio31_m gpio30_m gpio29_m gpio28_m gpio27_m gpio26_m gpio25_m gpio24_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio24_m gpio mode selection 00 configured as gpio function 01 o: pwm6 10 o: dsp2_gpo0 11 reserved gpio25_m gpio mode selection 00 configured as gpio function 01 i2s_ws 10 i: master dsp ice clk (d1ick) 11 o: usb_probe_out[7] gpio26_m gpio mode selection 00 configured as gpio function 01 i2s_clk 10 master dsp ice data (d1id) 11 o: usb_probe_out[6] gpio27_m gpio mode selection 00 configured as gpio function 01 i2s_dat 10 i: master dsp ice mode select (d1ims) 11 o: usb_probe_out[5] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 226 of 1535 gpio28_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 5 (kcol5) 10 i: slave dsp ice clk (d2ick) 11 o: usb_probe_out[4] gpio29_m gpio mode selection 00 configured as gpio function 01 camera strobe (cam_strobe) 10 slave dsp ice data (d2id) 11 o: usb_probe_out[3] gpio30_m gpio mode selection 00 configured as gpio function 01 o: cam_mechsh0 (camera) 10 i: slave dsp ice model select (d2ims) 11 o: usb_probe_out[2] gpio31_m gpio mode selection 00 configured as gpio function 01 o: cam_mechsh1 (camera) 10 o: slave dsp task id bit 0 (d2_tid0) 11 o: usb_probe_out[1] 8000_2640h gpio mode control register 5 gpio_mode5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio39_m gpio38_m gpio37_m gpio36_m gpio35_m gpio34_m gpio33_m gpio32_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio32_m gpio mode selection 00 configured as gpio function 01 o: usb_drvvbus 10 reserved 11 reserved gpio33_m gpio mode selection 00 configured as gpio function 01 o: cmos sensor flash control signal (cmflash) 10 o: slave dsp task id bit 2 (d2_tid2) 11 reserved gpio34_m gpio mode selection 00 configured as gpio function 01 i2c clock signal (scl) 10 o: slave dsp task id bit 3 (d2_tid3) 11 reserved gpio35_m gpio mode selection free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 227 of 1535 00 configured as gpio function 01 i2c data signal (sda) 10 o: slave dsp task id bit 4 (d2_tid4) 11 reserved gpio36_m gpio mode selection 00 configured as gpio function 01 o: pwm2 10 o: slave dsp task id bit 5 (d2_tid5) 11 reserved gpio37_m gpio mode selection 00 configured as gpio function 01 o: pwm3 10 o: slave dsp task id bit 6 (d2_tid6) 11 ceva_gpio31 gpio38_m gpio mode selection 00 configured as gpio function 01 i: mc2wp 10 mc0da4 11 reserved gpio39_m gpio mode selection 00 configured as gpio function 01 o: mc2pwron 10 mc0da5 11 reserved 8000_2650h gpio mode control register 6 gpio_mode6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio47_m gpio46_m gpio45_m gpio44_m gpio43_m gpio42_m gpio41_m gpio40_m type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio40_m gpio mode selection 00 configured as gpio function 01 mc2cm 10 mc0da6 11 reserved gpio41_m gpio mode selection 00 configured as gpio function 01 i: mc2ins 10 mc0da7 11 reserved gpio42_m gpio mode selection 00 configured as gpio function free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 228 of 1535 01 o: serial lcd clock signal (lsck) 10 o: tdma timer debug port clock output (tdma_ck) 11 reserved gpio43_m gpio mode selection 00 configured as gpio function 01 o: serial lcd address signal (lsa0) 10 o: tdma timer debug port data output 1 (tdma_d1) 11 o: tdma timer debug (tdtirq) gpio44_m gpio mode selection 00 configured as gpio function 01 serial lcd data signal (lsda) 10 o: tdma timer debug port data output 0 (tdma_d0) 11 o: tdma timer debug (tctirq2) gpio45_m gpio mode selection 00 configured as gpio function 01 o: lsce0b 10 o: tdma timer debug port frame sync signal (tdma_fs) 11 o: tdma timer debug (tctirq1) gpio46_m gpio mode selection 00 configured as gpio function 01 o: lsce1b 10 o: lpce2b 11 o: tdma timer debug (tevtval) gpio47_m gpio mode selection 00 configured as gpio function 01 o: lpce1b 10 o: d2_tid1 11 o: usb_probe_out[0] 8000_2660h gpio mode control register 7 gpio_mode7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio55 gpio54 gpio53 gpio52 gpio51 gpio50 gpio49 gpio48 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio48_m gpio mode selection 00 configured as gpio function 01 i: jtrst_b 10 o: clk_out6 11 reserved gpio49_m gpio mode selection 00 configured as gpio function 01 i: jtck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 229 of 1535 10 o: clk_out7 11 reserved gpio50_m gpio mode selection 00 configured as gpio function 01 i: jtdi 10 reserved 11 reserved gpio51_m gpio mode selection 00 configured as gpio function 01 i: jtms 10 reserved 11 reserved gpio52_m gpio mode selection 00 configured as gpio function 01 jtdo 10 reserved 11 reserved gpio53_m gpio mode selection 00 configured as gpio function 01 jrtck 10 reserved 11 reserved gpio54_m gpio mode selection 00 configured as gpio function 01 o: pwm0 10 i: external interrupt input 16 (eint16) 11 reserved gpio55_m gpio mode selection 00 configured as gpio function 01 o: pwm1 10 i: bsi_rfin 11 i: external interrupt input 17 (eint17) 8000_2670h gpio mode control register 8 gpio_mode8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio63 gpio62 gpio61 gpio60 gpio59 gpio58 gpio57 gpio56 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio56_m gpio mode selection 00 configured as gpio function 01 o: vcxo enable output signal (srclkena) 10 i: external interrupt input 18 (eint18) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 230 of 1535 11 reserved gpio57_m gpio mode selection 00 configured as gpio function 01 o: vcxo enable output signal low active (srclkenan) 10 i: external interrupt input 19 (eint19) 11 reserved gpio58_m gpio mode selection 00 configured as gpio function 01 i: vcxo enable input signal (srclkenai) 10 i: external interrupt input 20 (eint20) note: this external interrupt only can be used by md side, ap side can?t use this interrupt. 11 reserved gpio59_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 0 (eint0) 10 reserved 11 ceva_gpio18 gpio60_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 1 (eint1) 10 reserved 11 ceva_gpio19 gpio61_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 2 (eint2) 10 reserved 11 ceva_gpio20 gpio62_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 3 (eint3) 10 reserved 11 ceva_gpio21 gpio63_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 4 (eint4) 10 reserved 11 ceva_gpio22 8000_2680h gpio mode control register 9 gpio_mode9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio71 gpio70 gpio69 gpio68 gpio67 gpio66 gpio65 gpio64 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 231 of 1535 gpio64_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 5 (eint5) 10 reserved 11 ceva_gpio23 gpio65_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 6 (eint6) 10 reserved 11 ceva_gpio24 gpio66_m gpio mode selection 00 configured as gpio function 01 i: external interrupt input 7 (eint7) 10 reserved 11 ceva_gpio25 gpio67_m gpio mode selection 00 configured as gpio function 01 i: urxd3 10 i: uart4 cts signal (ucts4) 11 reserved gpio68_m gpio mode selection 00 configured as gpio function 01 o: utxd3 10 o: uart4 rts signal (urts4) 11 reserved gpio69_m gpio mode selection 00 configured as gpio function 01 i: urxd4 10 i: uart3 cts signal (ucts3) 11 reserved gpio70_m gpio mode selection 00 configured as gpio function 01 o: utxd4 10 o: uart3 rts signal (urts3) 11 reserved gpio71_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 7 (kcol7) 10 o: clk_out4 11 ceva_gpio14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 232 of 1535 8000_2690h gpio mode control register 10 gpio_mode10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio79 gpio78 gpio77 gpio76 gpio75 gpio74 gpio73 gpio72 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio72_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 6 (kcol6) 10 o: clk_out5 11 ceva_gpio15 gpio73_m gpio mode selection 00 configured as gpio function 01 keyboard row 7 (krow7) 10 o: clk_out6 11 ceva_gpio16 gpio74_m gpio mode selection 00 configured as gpio function 01 keyboard row 6 (krow6) 10 o: clk_out7 11 ceva_gpio17 gpio75_m gpio mode selection 00 configured as gpio function 01 o: digital audio interface pcm clock output (daiclk) 10 reserved 11 ceva_gpio26 gpio76_m gpio mode selection 00 configured as gpio function 01 o: digital audio interface pcm data output (daipcmout) 10 reserved 11 ceva_gpio27 gpio77_m gpio mode selection 00 configured as gpio function 01 i: digital audio interface pcm data input (daipcmin) 10 reserved 11 ceva_gpio28 gpio78_m gpio mode selection 00 configured as gpio function 01 i: digital audio interface reset signal (dairst) 10 o: clk_out5 11 ceva_gpio29 gpio79_m gpio mode selection free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 233 of 1535 00 configured as gpio function 01 o: digital audio interface sync signal (daisync) 10 reserved 11 ceva_gpio30 8000_26a0h gpio mode control register 11 gpio_mode11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio87 gpio86 gpio85 gpio84 gpio83 gpio82 gpio81 gpio80 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio80_m gpio mode selection 00 configured as gpio function 01 o: spi_cs_n 10 i: irda rxd signal (irda_rxd) 11 o: bsi_cs1 gpio81_m gpio mode selection 00 configured as gpio function 01 o: spi_sck 10 o: irda txd signal (irda_txd) 11 reserved gpio82_m gpio mode selection 00 configured as gpio function 01 o: spi_mosi 10 o: irda power down control signal (irda_pdn) 11 mc2da2 gpio83_m gpio mode selection 00 configured as gpio function 01 i: spi_miso 10 i: mirq 11 mc2da3 gpio84_m gpio mode selection 00 configured as gpio function 01 i: irda rxd signal (irda_rxd) 10 ceva_gpio0 11 i: mfiq gpio85_m gpio mode selection 00 configured as gpio function 01 o: irda txd signal (irda_txd) 10 ceva_gpio1 11 reserved gpio86_m gpio mode selection 00 configured as gpio function free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 234 of 1535 01 o: irda power down control signal (irda_pdn) 10 ceva_gpio2 11 reserved gpio87_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 0 (kcol0) 10 ceva_gpio3 11 i: external interrupt input 10 (eint10) 8000_26b0h gpio mode control register 12 gpio_mode12 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio95 gpio94 gpio93 gpio92 gpio91 gpio90 gpio89 gpio88 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio88_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 1 (kcol1) 10 ceva_gpio4 11 i: external interrupt input 11 (eint11) gpio89_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 2 (kcol2) 10 ceva_gpio5 11 i: external interrupt input 12 (eint12) gpio90_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 3 (kcol3) 10 ceva_gpio6 11 i: external interrupt input 13 (eint13) gpio91_m gpio mode selection 00 configured as gpio function 01 i: keyboard column 4 (kcol4) 10 ceva_gpio7 11 i: external interrupt input 14 (eint14) gpio92_m gpio mode selection 00 configured as gpio function 01 i: btdmp_din1 10 ceva_gpio8 11 reserved gpio93_m gpio mode selection 00 configured as gpio function 01 btdmp_fsp1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 235 of 1535 10 ceva_gpio9 11 o: phy_clk gpio94_m gpio mode selection 00 configured as gpio function 01 btdmp_clk1 10 ceva_gpio10 11 o: line_state0 gpio95_m gpio mode selection 00 configured as gpio function 01 o: btdmp_dout_2 10 ceva_gpio11 11 o: line_state1 8000_26c0h gpio mode control register 13 gpio_mode13 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio103 gpio102 gpio101 gpio100 gpio99 gpio98 gpio97 gpio96 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio96_m gpio mode selection 00 configured as gpio function 01 btdmp_fsp2 10 ceva_gpio12 11 o: tracedata14 gpio97_m gpio mode selection 00 configured as gpio function 01 btdmp_clk2 10 ceva_gpio13 11 o: tracedata15 gpio98_m gpio mode selection 00 configured as gpio function 01 ceva_rtck 10 reserved 11 reserved gpio99_m gpio mode selection 00 configured as gpio function 01 o: pwm5 10 reserved 11 reserved gpio100_m gpio mode selection 00 configured as gpio function 01 i: j2trst_b 10 reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 236 of 1535 11 o: tracedata8 gpio101_m gpio mode selection 00 configured as gpio function 01 i: j2tck 10 reserved 11 o: tracedata9 gpio102_m gpio mode selection 00 configured as gpio function 01 i: j2tdi 10 reserved 11 o: tracedata10 gpio103_m gpio mode selection 00 configured as gpio function 01 i: j2tms 10 reserved 11 o: tracedata11 8000_26d0h gpio mode control register 14 gpio_mode14 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio111 gpio110 gpio109 gpio108 gpio107 gpio106 gpio105 gpio104 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio104_m gpio mode selection 00 configured as gpio function 01 j2tdo 10 reserved 11 o: tracedata12 gpio105_m gpio mode selection 00 configured as gpio function 01 j2rtck 10 reserved 11 o: tracedata13 gpio106_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio107_m gpio mode selection 00 configured as gpio function 01 hdq 10 reserved 11 reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 237 of 1535 gpio108_m gpio mode selection 00 configured as gpio function 01 o: urts2 10 reserved 11 reserved gpio109_m gpio mode selection 00 configured as gpio function 01 i: ucts2 10 reserved 11 reserved gpio110_m gpio mode selection 00 configured as gpio function 01 keyboard row 0 (krow0) 10 reserved 11 reserved gpio111_m gpio mode selection 00 configured as gpio function 01 keyboard row 1 (krow1) 10 reserved 11 reserved 8000_26e0h gpio mode control register 15 gpio_mode15 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio119 gpio118 gpio117 gpio116 gpio115 gpio114 gpio113 gpio112 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio112_m gpio mode selection 00 configured as gpio function 01 keyboard row 2 (krow2) 10 reserved 11 reserved gpio113_m gpio mode selection 00 configured as gpio function 01 keyboard row 3 (krow3) 10 reserved 11 reserved gpio114_m gpio mode selection 00 configured as gpio function 01 keyboard row 4 (krow4) 10 reserved 11 reserved gpio115_m gpio mode selection free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 238 of 1535 00 configured as gpio function 01 o: clk_out0 10 reserved 11 reserved gpio116_m gpio mode selection 00 configured as gpio function 01 o: clk_out1 10 reserved 11 reserved gpio117_m gpio mode selection 00 configured as gpio function 01 o: clk_out2 10 reserved 11 reserved gpio118_m gpio mode selection 00 configured as gpio function 01 o: clk_out3 10 reserved 11 reserved gpio119_m gpio mode selection 00 configured as gpio function 01 o: clk_out4 10 reserved 11 reserved 8000_26f0h gpio mode control register 16 gpio_mode16 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio127 gpio126 gpio125 gpio124 gpio123 gpio122 gpio121 gpio120 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio120_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio121_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio122_m gpio mode selection 00 configured as gpio function free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 239 of 1535 01 reserved 10 reserved 11 reserved gpio123_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio124_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio125_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio126_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio127_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved 8000_2700h gpio mode control register 17 gpio_mode17 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio135 gpio134 gpio133 gpio132 gpio131 gpio130 gpio129 gpio128 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio128_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio129_m gpio mode selection 00 configured as gpio function 01 reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 240 of 1535 10 reserved 11 i: ucts4 gpio130_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 o: urts4 gpio131_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 i: ucts3 gpio132_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 o: urts3 gpio133_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio134_m gpio mode selection 00 configured as gpio function 01 reserved 10 reserved 11 reserved gpio135_m gpio mode selection 00 configured as gpio function 01 scl2 10 reserved 11 reserved 8000_2710h gpio mode control register 18 gpio_mode18 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio143 gpio142 gpio141 gpio140 gpio139 gpio138 gpio137 gpio136 type r/w r/w r/w r/w r/w r/w r/w r/w reset 01 01 01 01 01 01 01 01 gpio136_m gpio mode selection 00 configured as gpio function 01 sda2 10 reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 241 of 1535 11 reserved gpio137_m gpio mode selection 00 configured as gpio function 01 o: traceclk 10 reserved 11 reserved gpio138_m gpio mode selection 00 configured as gpio function 01 o: tracectl 10 reserved 11 reserved gpio139_m gpio mode selection 00 configured as gpio function 01 o: tracedata0 10 reserved 11 reserved gpio140_m gpio mode selection 00 configured as gpio function 01 o: tracedata1 10 reserved 11 reserved gpio141_m gpio mode selection 00 configured as gpio function 01 o: tracedata2 10 reserved 11 reserved gpio142_m gpio mode selection 00 configured as gpio function 01 o: tracedata3 10 reserved 11 reserved gpio143_m gpio mode selection 00 configured as gpio function 01 o: tracedata4 10 reserved 11 reserved 8000_2720h gpio mode control register 19 gpio_mode19 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio146 gpio145 gpio144 type r/w r/w r/w reset 01 01 01 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 242 of 1535 gpio144_m gpio mode selection 00 configured as gpio function 01 o: tracedata5 10 reserved 11 reserved gpio145_m gpio mode selection 00 configured as gpio function 01 o: tracedata6 10 reserved 11 reserved gpio146_m gpio mode selection 00 configured as gpio function 01 o: tracedata7 10 reserved 11 reserved 8000_2900h clk_out0 setting clk_out0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out0 type r/w reset 0 clk_out0 select the clock output source of clk_out0 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2910h clk_out1 setting clk_out1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out1 type r/w reset 0 clk_out1 select the clock output source of clk_out1 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 243 of 1535 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2920h clk_out2 setting clk_out2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out2 type r/w reset 0 clk_out2 select the clock output source of clk_out2 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2930h clk_out3 setting clk_out3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out3 type r/w reset 0 clk_out3 select the clock output source of clk_out3 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2940h clk_out4 setting clk_out4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out4 type r/w reset 0 clk_out4 select the clock output source of clk_out4 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 244 of 1535 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2950h clk_out5 setting clk_out5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out5 type r/w reset 0 clk_out5 select the clock output source of clk_out5 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2960h clk_out6 setting clk_out6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out6 type r/w reset 0 clk_out6 select the clock output source of clk_out6 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 8000_2970h clk_out7 setting clk_out7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_out7 type r/w reset 0 clk_out7 select the clock output source of clk_out7 0 apmcusys bus clock (ahmclk_ck) 1 dsp1io_ck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 245 of 1535 2 f13m_ck 3 f65m_ck 4 f48m_ck 5 f32k_ck 6 f26m_ck 7 mdmcusys bus clock (mhmclk_ck) 2.16 general purpose timer (ap) 2.16.1 general description three general-purpose timers are provided. the timers are 16 bits long and run independently of each other, although they share the same clock source. two timers can operate in one of two modes: one-shot mode and auto-repeat mode; the other is a free running timer. in one-shot mode, when the timer counts down and reaches zero, it is halted. in au to-repeat mode, when the timer reaches ze ro, it simply resets to countdown initial value and repeats th e countdown to zero; this loop repeats until the disable signal is set to 1. regardless of the timer?s mode, if the countdown initial value (i.e. apgpt1_dat for apgpt1 or apgpt_dat2 for apgpt2) is written when the timer is running, the new initial value does not take effect until the next time the timer is restarted. in auto-repeat mode, the new countdown start value is used on the next countdown iteration. therefore, before enabling the general purpose timer, the desired values for apgpt_dat and the apgpt_prescaler registers must first be set. 2.16.2 register definitions apgpt+0000h gpt1 control register apgpt1_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en mode type r/w r/w reset 0 0 mode this register controls gpt1 to count repeatedly (in a loop) or just one-shot. 0 one-shot mode is selected. 1 auto-repeat mode is selected. en this register controls gpt1 to start counting or to stop. 0 gpt1 is disabled. 1 gpt1 is enabled. apgpt+0004h gpt1 time-out in terval register apgpt1_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt [15:0] type r/w reset ffffh cnt [15:0] initial counting value. gpt1 counts down from gpt1_dat. when gpt1 counts down to zero, a gpt1 interrupt is generated. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 246 of 1535 apgpt+0008h gpt2 control register apgpt2_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en mode type r/w r/w reset 0 0 mode this register controls gpt2 to count repeatedly (in a loop) or just one-shot. 0 one-shot mode is selected 1 auto-repeat mode is selected en this register controls gpt2 to start counting or to stop. 0 gpt2 is disabled. 1 gpt2 is enabled. apgpt+000c h gpt2 time-out interval register apgpt2_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt [15:0] type r/w reset ffffh cnt [15:0] initial counting value. gpt2 counts down from gpt2_dat. when gpt2 counts down to zero, a gpt2 interrupt is generated. apgpt+0010h gpt status register apgpt_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpt2 gpt1 type rc rc reset 0 0 this register illustrates the gptimer timeout status. each flag is set when the corresponding timer countdown completes, and can be cleared when the cpu reads the status register. apgpt+0014h gpt1 prescaler register apgpt1_presca ler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b prescaler this register controls the counting clock for gptimer1. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 100 1024 hz 101 512 hz free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 247 of 1535 110 256 hz 111 128 hz apgpt+0018h gpt2 prescaler register apgpt2_presca ler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b prescaler this register controls the counting clock for gptimer2. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 100 1024 hz 101 512 hz 110 256 hz 111 128 hz apgpt+001c h gpt3 control register apgpt3_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en type r/w reset 0 en this register controls gpt3 to start counting or to stop. 0 gpt3 is disabled. 1 gpt3 is enabled. apgpt+0020h gpt3 time-out in terval register apgpt3_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt[15:0] type ro reset 0 cnt [15:0] if en=1, gpt3 is a free running timer . software reads this register for the countdown start value for gpt3. apgpt+0024h gpt3 prescaler register apgpt3_presca ler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 248 of 1535 prescaler this register controls the counting clock for gptimer3. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 100 1024 hz 101 512 hz 110 256 hz 111 128 hz 2.17 graph1sys clock ma nagement register confg_base = 0x80092000 register address register name synonym confg_base + 300h clock gating control status register graph1sys_cg_con confg_base + 320h clock gating set register graph1sys_cg_set confg_base + 340h clock gating clear register graph1sys_cg_clr table 35 apb bridge register map 2.17.1 register definitions confg_base + 300h clock gating control status register graph1sys_c g_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 0 graph1 sub-system clock gating control status register (read only), value 1 represents clock gating. gmc1 status of the gmc1 clock gating. g2d status of the g2d clock gating. gcmq status of the gcmq clock gating. bls status of the bls clock gating. imgdma0 status of the imgdma0 clock gating. png status of the png clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 249 of 1535 dsi status of the dsi clock gating. tve status of the tve clock gating. tvc status of the tvc clock gating. isp status of the isp clock gating. ipp status of the ipp clock gating. prz status of the prz clock gating. crz status of the crz clock gating. drz status of the drz clock gating. wt status of the wt clock gating. afe status of the afe clock gating. spi status of the spi clock gating. asm status of the asm clock gating. resz_lb status of the resz_lb clock gating. lcd status of the lcd clock gating. dpi status of the dpi clock gating. g1fake status of the g1fake clock gating. confg_base + 320h clock gating set register graph1sys_c g_set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo graph1 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_cond registers. eg. if pdn_cond = 16?h0f0f, writing pdn_cond = 16?f0f0 will result in pdn_cond = 16?hffff. gmc1 set gmc1 clock gating. g2d set g2d clock gating. gcmq set gcmq clock gating. bls set bls clock gating. imgdma0 set imgdma0 clock gating. png set png clock gating. dsi set dsi clock gating. tve set tve clock gating. tvc set tvc clock gating. isp set isp clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 250 of 1535 ipp set ipp clock gating. prz set prz clock gating. crz set crz clock gating. drz set drz clock gating. wt set wt clock gating. afe set afe clock gating. spi set spi clock gating. asm set asm clock gating. resz_lb set resz_lb clock gating. lcd set lcd clock gating. dpi set dpi clock gating. g1fake set g1fake clock gating. confg_base + 340h clock gating clear register graph1sys_c g_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo graph1 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_cond registers. eg. if pdn_cond = 16?hffff, writing pdn_cond = 16?f0f0 will result in pdn_cond = 16?h0f0f. gmc1 clear gmc1 clock gating. g2d clear g2d clock gating. gcmq clear gcmq clock gating. bls clear bls clock gating. imgdma0 clear imgdma0 clock gating. png clear png clock gating. dsi clear dsi clock gating. tve clear tve clock gating. tvc clear tvc clock gating. isp clear isp clock gating. ipp clear ipp clock gating. prz clear prz clock gating. crz clear crz clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 251 of 1535 drz clear drz clock gating. wt clear wt clock gating. afe clear afe clock gating. spi clear spi clock gating. asm clear asm clock gating. resz_lb clear resz_lb clock gating. lcd clear lcd clock gating. dpi clear dpi clock gating. g1fake clear g1fake clock gating. 2.18 graph2sys clock ma nagement register confg_base = 0x800a7000 register address register name synonym confg_base + 000h clock gating control status register graph2sys_cg_con confg_base + 004h clock gating set register graph2sys_cg_set confg_base + 008h clock gating clear register graph2sys_cg_clr confg_base + 010h memory delsel control regsiter 0 graph2sys_delsel0 confg_base + 014h memory delsel control regsiter 1 graph2sys_delsel1 confg_base + 018h memory delsel control regsiter 2 graph2sys_delsel2 table 36 apb bridge register map 2.18.1 register definitions confg_base + 000h clock gating control status register graph2sys_c g_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 type ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 0 graph2 sub-system clock gating control status register (read only), value 1 represents clock gating. gmc2 status of the gmc2 clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 252 of 1535 image_dma_1 status of the image_dma_1 clock gating. prz status of the prz clock gating. m3d status of the m3d clock gating. h264 status of the h264 clock gating. dct status of the dct clock gating. jpeg status of the jpeg clock gating. mp4 status of the mp4 clock gating. mp4_deblk status of the mp4_deblk clock gating. confg_base + 004h clock gating set register graph2sys_c g_set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 type w/o wo wo wo wo wo wo wo wo graph2 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con = 16?h0f0f, writing cg_set = 16?f0f0 will result in cg_con = 16?hffff. gcu set the gcu controller power down. gmc2 set the gmc2 clock gating. image_dma_1 set the image_dma_1 clock gating. prz set the prz clock gating. m3d set the m3d clock gating. h264 set the h264 clock gating. dct set the dct clock gating. jpeg set the jpeg clock gating. mp4 set the mp4 clock gating. mp4_deblk set the mp4_deblk clock gating. confg_base + 008h clock gating clear register graph2sys_c g_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 253 of 1535 type wo wo wo wo wo wo wo wo wo graph2 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con = 16?hffff, writing cg_clr = 16?f0f0 will result in cg_con = 16?h0f0f. gcu clear the gcu controller power down. gmc2 clear the gmc2 clock gating. image_dma_ clear the image_dma_1 clock gating. prz clear the prz clock gating. m3d clear the m3d clock gating. h264 clear the h264 clock gating. dct clear the dct clock gating. jpeg clear the jpeg clock gating. mp4 clear the mp4 clock gating. mp4_deblk clear the mp4_deblk clock gating. 2.19 hdq/1-wire 2.19.1 general description the hdq/1-wire design comprises the following blocks: ? hdq finite state machine (hdq_fsm) ? hdq register (hdq_reg) ? hdq interrupt controller (hdq_int) hdq is a point to point communication. it uses a single wire to communication between master and slave. the protocol is an asynchronous return-to-one mechanism referenced to vss. the protocol is byte access between master and slave. in a typical write to slave (or read from slave), one byte command will be sent by master, and then another byte data will be sent to slave (or be read from slave). some slave also support for two bytes access which can be wrote or read 16 bits data with a master command. hdq pin is an open-drain device. it means that the hdq bus need an external pull-up resistance to vss. 1-wire interface is a point to multi-point communication. it is also a single wire to communication between master and slave. and it also an asynchronous return-to-one mechanism referenced to vss. each slave has a 64 bit net address as follow: in additional to search net address command, each 1-wire communication is formed by 1) one byte command only, 2) one byte command with 16 bit data read/write, 3) one byte command with 8 bit data read/write, or 4) one byte command with 64 bit net address read/write. command read/write data + when the master send a search net address command, the slave might return two bit, and then the master shall return one bit to select the device. sw can just read two bits data from slave by setting 0x04[11:10]. and we can return the select bit as a one bit command by setting 0x04[9]. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 254 of 1535 2.19.2 address map for hdq/1-wire register address register name common control registers hdq + 0000h hdq/1-wire tx command hdq + 0004h hdq/1-wire control hdq + 0008h 1-wire control hdq + 000ch hdq div contol hdq + 0010h 1-wire status (read-only) hdq + 0014h hdq/1-wire interrupt enable hdq + 0018h hdq/1-wire interrupt clear (write-only) hdq + 001ch hdq/1-wire interrupt (read-only) hdq + 0020h ~ 002ch hdq/1-wire data write hdq + 0030h ~ 003ch hdq/1-wire data read (read-only) hdq + 0040h ~ 004ch hdq timing parameter hdq + 0050h ~ 0064h 1-wire timing parameter blue for r/w, yellow for read only, gyay for reserved. green for write only bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 tx_command[7:0] 4 sw_rst no_comman d wr_rd_data_type[2:0] one_bit_comma nd overdrive 5 hdq_1-wire_en hdq_1-wire_wr rate_fix[1:0] gobit hdq16_en break hdq_en 8 onewire_sample_time[15:8] c div[7:0] 10 rx_always_hig h 1- wire_presenc e_short 1- wire_presence_l ong rx_always_low 14 1- wire_alarm_en 1- wire_presenc e_en 1- wire_presence _timeout_en hdq_rx_timeou t_en hdq_break_i ntr_en hdq_rx_done_e n hdq_tx_done_e n 18 1-wire_alarm_clr 1- wire_presenc e_clr 1- wire_presence _timeout_clr hdq_rx_timeou t_clr hdq_break_i ntr_clr hdq_rx_done_cl r hdq_tx_done_c lr 1c 1- wire_alarm_intr 1- wire_presenc e_intr 1- wire_presence _timeout_intr hdq_rx_timeou t_intr hdq_break_i ntr hdq_rx_done_in tr hdq_tx_done_i ntr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 255 of 1535 20~2f hdq_tx_data[63:0] 30~3f hdq_rx_data[63:0] 40 hdq_tb[7:0] 41 hdq_tbreak[7:0] 44 hdq_cych[7:0] 45 hdq_tsp[7:0] 48 hdq_thw0[7:0] 49 hdq_thw1[7:0] 4c hdq_rxto[7:0] 50 onewire_tpdl_min[7:0] 51 onewire_tpdl_max[7:0] 54 onewire_tint1_min[7:0] 55 onewire_tint1_max[7:0] 58 onewire_tpdh [7:0] 59 onewire_trstl [7:0] 5c onewire_tmslot [7:0] 5d onewire_tsslot_max [7:0] 60 onewire_tlow0 [7:0] 61 onewire_tlow1 [7:0] 64 onewire_tdri [7:0] 65 onewire_trsth [7:0] 2.19.3 register definitions hdq+0000h hdq/1-wire tx command hdq_com bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_tx_command type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 hdq_tx_command[7:0] 8-bits tx command. it will be sent when the gobit (0x04[11]) is set. in the search net address sequence, sw might send 1-bit response data into hdq_tx_comand to select slave device. hdq+0004h hdq/1-wire control hdq_ctrl bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sw_r st no_c omma nd data_type 1bit_ comm and over drive hdq_1 wire_ en hdq_1 wire_ tx rate_fix gobit hdq16 _en brea k hdq_ en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w wo r/w r/w r/w reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 sw_rst software can reset hardware state machine and interrupt by setting this bit to 1. apb registers in free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 256 of 1535 this document will not be reset by sw_rst. remember to set this bit to 0 after finishing sw reset. no_command it will be allowed that the data will be sent or received without sent any command in front of it if this bit is set. 1bit_command (0x04[9]) will be ig nored when this bit is set, and data_type (0x04[12:10]) just can be 0, 1, or 3 when this bit is set. this bit is only used for 1-wire bus (0x04[0]=0). data_type[2:0] the type of the wr/rd data following after command. it only used for 1-wire bus (0x04[0]=0). 3?b000: 2 bytes data. 3?b001: 8 bytes data 3?b010: 2 bit data 3?b011: 1 byte data 3?b100: no data is following others are reserved to define. 1 bit command this bit is used only when enabling 1-wire bus (0x04[0]=0). when this bit is set to 0, 8-bit tx command in 0x00 will be sent when gobit (0x04[3]) is set to 1?b1. otherwire, only 0x00[0] will be sent when gobit is set. the 1-bit command is used for search net address sequence. overdrive this bit is used only when enabling 1-wire bus (0x04[0]=0). when this bit is set to 0, the 1-wire bus is in the standard mode. otherwise, the 1-wire bus is in overdrive mode. hdq_1wire_en this bit is used to enable the hdq/1-wire bus function. when this bit is set to 1?b0, the hdq/1-wire will be disabled. hdq_1wire_tx when this bit is set to 1?b1, it means that t he data following the command will be writen into the slave. otherwire, the following data is read from slave. rate_fix[1:0] when rate_fix is set to 2?b10, it means that the device is operated when f13m_en is enable. when rate_fix is set to 2?b11, it means that the device is operated when f26m_en is enable. otherwire, the device is operated with the input clock. when the device is operated for 1-wire bus, the clock into the design shall be 13mhz, or the rate_fix shall be set to 13mhz. gobit when this bit is set to 1?b1, the command will be sent and then the data might be sent or received if the break bit (0x04[1]) is set to 0. if the break is set to 1?b1 and we setting the gobit, 1) a break signal will be sent when hdq_en (0x04[0]) is set to 1, or 2) a reset signal will be sent from master and the slave shall response a presence signal to master. this gobit is write-only an d it will auto be reset after the signal is sent. hdq16_en this bit is only used for hdq bus (0x04[0]=1). when this bit is set to 1?b1, the wr/rd data following the command is 16-bit. otherwise, the data will be 8-bit. break when the device is used for hdq bus (0x04[0]=1), a break signal will be sent when this bit is set to 1 and the gobit (0x04[3]) is set to 1. when the device is used for 1-wire bus (0x04[0]=0), a reset signal will be sent from master and the slave shall response a presence signal to master when this bit is set to 1 and the gobit (0x04[3]) is set to 1. hdq_en when this bit is set to 1?b1, it means that device is used for hdq bus. otherwise, the device is used for 1-wire bus. when you use this as a 1-wire device, a pull-u p resistance must be added in the hdq inout port . hdq+0008h 1-wire control 1wire_ctrl bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 1wire_sample_time[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1wire_sample_time[15:0] this register is only used for 1-wire bu s. this value is the sample time after the negtive edge in the bus when data is read from slave. each step is about 76.92ns (1/13mhz). hdq+000ch hdq div register hdq_div bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_div[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 257 of 1535 reset 0 0 0 0 1 0 1 1 hdq_div[7:0] this register is only used for hdq bus. when the clock input into design is 52mhz, this value shall set to 52. if the clock is 26mhz or the rate_fix is set to operate. for 26mhz, this value shall set to 26. if the clock is 13mhz or the rate_fix is set to operated for 13mhz, this value shall set to 13. hdq+0010h 1wire status register 1wire_stat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_al ways _high 1wire _pres ence_ shor t 1wire _pres ence_ long rx_al ways _low type ro ro ro ro reset 0 0 0 0 rx_always_high when this bit is set to 1, it means that the device the bus is always high even if we send 0 to the bus. 1wire_presence_short when this bit is set to 1, it means that the presence signal from slave is shorter than we expect. 1wire_presence_long when this bit is set to 1, it means that the presence signal from slave is longer than we expect. rx_always_low when this bit is set to 1, it means that the device the bus is always low when we don?t drive the bus. hdq+0014h hdq/1-wire intr enable hdq_int_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 1wire _alar m_en 1wire _pres ence_ en 1wire _pres ence_ timeo ut_en hdq_ rx_ti meou t_en hdq_ brea k_en hdq_ rx_d one_e n hdq_ tx_do ne_en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1wire_alarm_en when this bit is set to 1, the alarm interrupt will be occurred if an alarm signal is detected. it is only used for 1-wire bus. 1wire_presence_en when this bit is set to 1, the presence interrupt will be occurred if a presence signal is detected. it is only used for 1-wire bus. 1wire_presence_timeout_en when this bit is set to 1, the presence timeout interrupt will be occurred if no presence signal is received from slave after sending the reset signal. it is only used for 1-wire bus. hdq_rx_timeout_en when this bit is set to 1, the hdq rx ti meout interrupt will be occurred if the slave does not response anything after we send a read command. it is only used for hdq bus. hdq_break_en when this bit is set to 1, the hdq break in terrupt will be occurred after the master send the break signal to slave. it is only used for hdq bus. hdq_rx_done_en when this bit is set to 1, the hdq/1-wire rx done interrupt will be occurred after the master send the read command to slave and then receive the data from slave. it is used for both hdq and 1- wire bus. hdq_tx_done_en when this bit is set to 1, the hdq/1-wire tx done interrupt will be occurred after the master send the read command and the data to the slave. it is used for both hdq and 1-wire bus. hdq+0018h hdq/1-wire intr clear hdq_int_clr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 258 of 1535 name 1wire _alar m_cl r 1wire _pres ence_ clr 1wire _pres ence_ timeo ut_cl r hdq_ rx_ti meou t_clr hdq_ brea k_clr hdq_ rx_d one_ clr hdq_ tx_do ne_cl r type wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 1wire_alarm_clr when this bit is set to 1, the alarm interrupt will be cleared. it is only used for 1-wire bus. and it will auto be reset by hw. 1wire_presence_clr when this bit is set to 1, the presence interrupt will be cleared. it is only used for 1-wire bus. and it will auto be reset by hw. 1wire_presence_timeout_clr when this bit is set to 1, the pres ence timeout interrupt will be cleared. it is only used for 1-wire bus. and it will auto be reset by hw. hdq_rx_timeout_clr when this bit is set to 1, the hdq rx timeout interrupt will be cleared. it is only used for hdq bus. and it will auto be reset by hw. hdq_break_clr when this bit is set to 1, the hdq break interrupt will be cleared. and it will auto be reset by hw. hdq_rx_done_clr when this bit is set to 1, the hdq/1-wire rx done interrupt will be cleared. it is used for both hdq and 1-wire bus. and it will auto be reset by hw. hdq_tx_done_clr when this bit is set to 1, the hdq/1-wire tx done interrupt will be cleared. it is used for both hdq and 1-wire bus. and it will auto be reset by hw. hdq+001ch hdq/1-wire intr hdq_intr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 1wire _alar m_int r 1wire _pres ence_ intr 1wire _pres ence_ timeo ut_in tr hdq_ rx_ti meou t_int r hdq_ brea k_int r hdq_ rx_d one_i ntr hdq_ tx_do ne_in tr type ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 1wire_alarm_intr this is the slave alarm interrupt. when this bit is set to 1, sw shall read the status register of the slave to check the alarm item. it is only used for 1-wire bus. 1wire_presence_intr when this bit is set to 1, it means that the master had sent a reset signal and then received a presence signal from slave. it is only used for 1-wire bus. 1wire_presence_timeout_intr when this bit is set to 1, it means that the master had sent a reset signal, but no presence is detected from the bus. it is only used for 1-wire bus. hdq_rx_timeout_intr when the interrupt is occurred, it means that the the master had sent a read command, but no data is responded from slave. it is only used for hdq bus. hdq_break_intr when this bit is set to 1, it means that the master had sent a break signal to the slave. it is only used for hdq bus. hdq_rx_done_intr when this bit is set to 1, it means that the hdq/1-wire master had sent a read command to the slave, and then received the data sent by slave. it is used for both hdq and 1-wire bus. hdq_tx_done_intr when this bit is set to 1, it means that the hdq/1-wire master had sent a write command and data to the slave. it is used for both hdq and 1-wire bus. hdq +0020h hdq tx data hdq_tx_data bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 259 of 1535 name hdq_tx_data[63:48] type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 name hdq_tx_data[47:32] type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hdq_tx_data[31:16] type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_tx_data[15:0] type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hdq_tx_data[63:0] 64 bit tx data. the lsb will be sent first. for example, if the tx data is 16 bit, hdq_tx_data[15:0] will be sent to the slave. hdq +0030h hdq rx data hdq_rx_data bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 name hdq_rx_data[63:48] type ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 name hdq_rx_data[47:32] type ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hdq_rx_data[31:16] type ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_rx_data[15:0] type ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hdq_rx_data[63:0] 64 bit rx data from slave. the lsb will be received first. for example, if the rx data is 16 bit, the receiving da ta from slave will be put in hdq_rx_data[15:0]. hdq+0040h hdq para_1 hdq_para_1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_tbreak[7:0] hdq_tb[7:0] type r/w r/w reset 8?d230 8?d190 hdq_tbreak[7:0] this register is defined the total hdq break time as the diagram in 1.4.1. for example, if the value is 8?d230 as default, the time in hdq break will be 230 us. hdq_tb[7:0] this register is defined the hdq break low time as the diagram in 1.4.1. for example, if the value is 8?d190 as default, the low time in hdq break will be 190 us. hdq+0044h hdq para_2 hdq_para_2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 260 of 1535 name hdq_tsp[7:0] hdq_cych[7:0] type r/w r/w reset 8?d65 8?d190 hdq_tsp[7:0] this register is defined the hdq sample point as the diagram in 1.4.1. for example, if the value is 8?d65 as default, the hdq sample point will be 65 us. hdq_cych[7:0] this register is defined the hdq tx bit cycle time as the diagram in 1.4.1. for example, if the value is 8?d190 as default, the tx bit cycle time in hdq will be 230 us. hdq+0048h hdq para_3 hdq_para_3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_thw1[7:0] hdq_thw0[7:0] type r/w r/w reset 8?d40 8?d130 hdq_thw1[7:0] this register is defined the low duration on the bus when hdq send a ?1? to slave as the diagram in 1.4.1. for example, if the value is 8?d4 00 as default, the hdq sample point will be 40 us. hdq_thw0[7:0] this register is defined the low duration on the bus when hdq send a ?0? to slave as the diagram in 1.4.1. for example, if the value is 8?d1 30 as default, the hdq sample point will be 130 us. hdq+004ch hdq para_4 hdq_para_4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdq_rxto[7:0] type r/w reset 8?d130 hdq_rxto[7:0] this register is defined the hdq rx timeout value. if the hdq bus is not driven to 0 (by slave) for more than this setting value, the hdq rx timeout interrupt will be set. the timeout time will be (2 * hdq_rxto) us. for example, if this register is 8?d130 as default, the hdq rx timeout time will be 130*2=260us. hdq+0050h 1-wire para_1 1wire_para_1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_tpdl_max[7:0] onewire_tpdl_min[7:0] type r/w r/w reset 8?d195 8?d195 onewire_tpdl_max[7:0] this register is defined the 1-wire bus presense max. time as the diagram in 1.4.2. the max. presense time will be (16 * onewire_tpdl_min * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the max. presense time will be (16*195*0.07692)=240us. be careful, (onewire_tint1_max*256) need to be larger than (onewire_tpdl_max*16)! onewire_tpdl_min[7:0] this register is defined the 1-wire bus presense min. time as the diagram in 1.4.2. the min. presense time will be (4 * onewire_tpdl_min * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the min. presense time will be (4*195*0.07692)=60us. be careful, (onewire_trsth*32) need to be larger than (onewire_tpdl_min*4). hdq+0054h 1-wire para_2 1wire_para_2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_tint1_max[7:0] onewire_tint1_min[7:0] type r/w r/w reset 8?d220 8?d195 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 261 of 1535 onewire_tint1_max[7:0] this register is defined the 1-wire bus max. interrupt duration time as the diagram in 1.4.3. the max. interrupt duration time will be (256 * onewire_tint1_max * input_clock_period). for example, if this register is 8?d220 as default and the input clock is 13mhz (76.92ns), the max. interrupt duration time will be (256*220*0.07692)=4332 us. be care ful, (onewire_tint1_max*256) need to be larger than (onewire_tpdl_max*16)! onewire_tint1_min[7:0] this register is defined the 1-wire bus min. interrupt duration time as the diagram in 1.4.3. the min. interrupt duration time will be (64 * onewire_tint1_min * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the min. interrupt duration time will be (64*195*0.07692)=960 us. be careful, (onewire_tint1_min*64) need to be larger than (onewire_trstl*32)! hdq+0058h 1-wire para_3 1wire_para_3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_trtsl[7:0] onewire_tpdh[7:0] type r/w r/w reset 8?d203 8?d195 onewire_trtsl[7:0] this register is defined the 1-wire bus reset low duration time as the diagram in 1.4.2. the reset low duration time will be (32 * onewire_trtsl * input_clock_period). for example, if this register is 8?d203 as default and the input clock is 13mhz (76.92ns), the 1-wire bus reset low duration time will be (32*203*0.07692)=500 us. be careful, (onewire_tint1_min*64) need to be larger than (onewire_trstl*32)! onewire_tpdh[7:0] this register is defined the duration time from reset to presense as the diagram in 1.4.2. the the duration time from reset to presense will be (4 * onewire_tpdh * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the duration time from reset to presense will be (4*195*0.07692)=60 us. hdq+005ch 1-wire para_4 1wire_para_4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_tsslot_max[7:0] onewire_tmslot[7:0] type r/w r/w reset 8?d195 8?d163 onewire_tsslot_max[7:0] this register is defined the 1-wire bus slave tx max. bit duration as the diagram in 1.4.2. the slave tx max bit duration time will be (8 * onewire_tsslot_max * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the slave tx max bit duration time will be (8*195*0.07692)=120 us. onewire_tmslot[7:0] this register is defined the 1-wire bus master tx bit duration as the diagram in 1.4.2. the master tx bit duration time from reset to presense will be (8 * onewire_tmslot * input_clock_period). for example, if this register is 8?d163 as default and the input clock is 13mhz (76.92ns), the min. presense time will be (8*163*0.07692)=100 us. hdq+0060h 1-wire para_5 1wire_para_5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_tlow1[7:0] onewire_tlow0[7:0] type r/w r/w reset 8?d170 8?d130 onewire_tlow1[7:0] this register is defined the bus driven low duration when the master send a bit ?1? to slave, as the diagram in 1.4.2. the bus driven low duration time when the master send a bit ?1? to slave will be (1 * onewire_tlow1 * input_clock_period). for example, if this register is 8?d170 as default and the input clock is 13mhz (76.92ns), the slave tx max bit duration time will be (1*170*0.07692)=13 us. onewire_tlow0[7:0] this register is defined the bus driven low duration when the master send a bit ?0? to slave, as the diagram in 1.4.2. the bus driven low duration time when the master send a bit ?0? to slave will free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 262 of 1535 be (8 * onewire_tlow0 * input_clock_period). for example, if this register is 8?d130 as default and the input clock is 13mhz (76.92ns), the slave tx max bit duration time will be (8*130*0.07692)=80 us. hdq+0064h 1-wire para_6 1wire_para_6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onewire_trsth[7:0] onewire_tdri[7:0] type r/w r/w reset 8?d195 8?d17 onewire_trsth[7:0] this register is defined the presense process duration after master send the reset signal, as the diagram in 1.4.2. this duration will be (32 * on ewire_trsth * input_clock_period). for example, if this register is 8?d195 as default and the input clock is 13mhz (76.92ns), the slave tx max bit duration time will be (32*195*0.07692)=480 us. be careful, (onewire_trsth*32) need to be larger than (onewire_tpdl_min*4). onewire_tdri[7:0] this register is defined the master driving low duration when receiving the rx data from slave, as the diagram in 1.4.2. the duration time will be (1 * onewire_tdri * input_clock_period). for example, if this register is 8?d17 as default and the input clock is 13mhz (76.92ns), the slave tx max bit duration time will be (1*17*0.07692)=1.3 us. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 263 of 1535 2.19.4 hdq/1-wire timing requirement 2.19.4.1 hdq timing requirement parameter max (us) type (us) mi(us) t b 190 t break 230 t hw1 40 t hw0 130 t cych 190 t dw1 60 10 t dw0 160 70 t cycd 260 190 t sp 65 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 264 of 1535 2.19.4.2 1-wire timing requirement : master driving : slave driving t rstl t rsth t pdl t pdh presence: master tx: t mslot t t low0 t low1 t rec slave tx: t sslot t sslot t sp t sp t dri mslot parameter standard max (us) standard min (us) overdrive max(us) overdrive min(us) t rstl 500 50 t pdh 60 6 t pdl 240 60 24 8 t rsth 480 48 t mslot 100 100 t low1 13 1.3 t low0 80 8 t rec 15 15 15 15 t sslot 120 16 t dri 1.3 1.3 t sp 110 2 14 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 265 of 1535 2.19.4.3 1-wire alarm timing reset presence presence interrupt t int1 reset presence presence interrupt t int2 1 for slave but 0 for master reset presence t int3 : master driving : slave driving parameter standard max (us) standard min (us) overdrive max(us) overdrive min(us) t int1 4332 960 433 96 t int2 4080 1020 408 102 t int3 4820 960 482 96 2.20 i2c / sccb controller 2.20.1 special notes MT6516 has 3 sets of i2c controller: i2c controller 1 (i2c), i2c controller 2 (i2c2), i2c controller 3 (i2c3). the 3 controllers are defined as the table below shows: apb address mapping pin name gpio mux i2c_base (8003_0000h) scl1 sda1 scl1 (gpio 34) sda1 (gpio 35) i2c2_base (8003_5000h) scl0 sda0 none none i2c3_base (8002_e000h) scl2 sda2 scl2 (gpio free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 266 of 1535 135) sda2 (gpio 136) since only controller 2 has dma support, all the following descriptions that refers to dma mode will only be applicable to controller 2. 2.20.2 general description i2c (inter-ic) /sccb (serial camera control bus) is a two-wire serial interface. the two signals are scl and sda. scl is a clock signal that is driven by the master. sda is a bi-directional data signal that can be driven by either the master or the slave. this generic controller supports the master role and conforms to the i2c specification. 2.20.2.1 feature support i2c compliant master mode operation adjustable clock speed for ls/fs mode operation. 7bit/10 bit addressing support. high speed mode support. slave clock extension support. start/stop/repeated start condition manual/dma transfer mode multi write per transfer (up to 8 data bytes for non dma mode and 255 data bytes for dma mode) multi read per transfer (up to 8 data bytes for non dma mode and 255 data bytes for dma mode) multi transfer per transaction (up to 256 write transfers or 256 read transfers with dma mode) dma mode with fifo flow control and bus signal holding combined format transfer with length change capability. active drive / wired-and i/o configuration 2.20.2.2 manual/dma transfer mode the controller offers 2 types of transfer mode, manual and dma. when manual mode is selected, in addition to the slave address register, the controller has a built-in 8byte deep fifo which allows mcu to prepare up to 8 bytes of data for a write transfer, or read up to 8 bytes of data for a read transfer. when dma mode is enabled, the data to and from the fifo is controlled via dma transfer and can therefore support up to 255 bytes of consecutive read or write, with the data read from or write to another memory space. when dma mode is enabled, flow control mechanism is also implemented to hold the bus clk when fifo underflow or overflow condition is encountered. 2.20.2.3 transfer format support this controller has been designed to be as generic as possible in order to support a wide range of devices that may utilize different combinations of transfer formats. here are the transfer format types that can be supported through different software configuration: (wording convention note: transfer = anything encapsulated within a start and stop or repeated start. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 267 of 1535 transfer length = the number of bytes within the transfer. transaction = this is the top unit. everything combined equals 1 transaction. transaction length = the number of transfers to be conducted. ) .btufsuptmbwfejs 4mbwfupnbtufsejs single byte access 4mbwf"eesftt " 4 %"5" " 1 4mbwf"eesftt " 4 %"5" o" 1 4johmf#zuf8sjuf 4johmf#zuf3fbe multi byte access 4mbwf"eesftt " 4 %"5" " 1 /czuftbdl 4mbwf"eesftt " 4 %"5" " o" 1 /czuftbdlobl .vmuj#zuf8sjuf .vmuj#zuf3fbe multi byte transfer + multi transfer (same direction) 4mbwf "eesftt " %"5" " 4 1 4mbwf "eesftt " %"5" " o" 4 1 /czuftbdlobl /czuftbdlobl .vmuj#zuf8sjuf.vmuj5sbotgfs .vmuj#zuf3fbe.vmuj5sbotgfs 9usbotgfst xbjuujnf 9usbotgfst xbjuujnf multi byte transfer + multi transfer w rs (same direction) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 268 of 1535 4mbwf "eesftt " %"5" " 4 3 4mbwf "eesftt " %"5" " o" 4 3 /czuftbdlobl /czuftbdlobl .vmuj#zuf8sjuf.vmuj5sbotgfs3fqfbufe4ubsu .vmuj#zuf3fbe.vmuj5sbotgfs3fqfbufe4ubsu 9usbotgfst 9usbotgfst 1 1 combined write/read with repeated start (direction change) (note: only supports write and then read sequence. read and then write is not supported) 4mbwf "eesftt " 4 %"5" " 3 / czuftbdlobl 4mbwf "eesftt " %"5" " 1 . czuftbdlobl $pncjofe.vmuj#zuf8sjuf.vmuj#zuf3fbe 2.20.3 programming examples common transfer programmable parameters 4mbwf "eesftt " %"5" " 4 1 34 usbotgfs@mfo 1sphsbnnbcmf1bsbnfufst usbotbd@mfo %"5" " st@tupq tmbwf@bees 4mbwf "eesftt " %"5" " 4 1 34 %"5" " efmbz@mfo usbotgfs@mfobvyusbotgfs@mfo tmbwf@beesejsdibohf output waveform timing programmable parameters free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 269 of 1535 tbnqmf@dou@ejw .i[
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4bnqmfxjeui 2.20.4 register definitions i2creg+0000 h data port register data_port bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data type r/w reset 0 data_port[7:0] this is the fifo access port. during master write sequences (slave_addr[0] = 0), this port can be written by apb, and during master read sequences (slave_addr[0] = 1), this port can be read by apb. (note) slave_addr must be set correctly before accessing the fifo. (debug only) if the fifo_apb_debug bit is set, then the fifo can be read and write by the apb i2creg+0004 h slave address register slave_addr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slave_addr type r/w reset 0 slave_addr [7:0] this specifies the slave address of the device to be accessed. bit 0 is defined by the i2c protocol as a bit that indicates the direction of transfer. 1 = master read, 0 = master write. i2creg+0008 h interrupt mask register intr_mask bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name debu g hs_na cker acke rr tran sac_ comp type r.w r/w r/wr/w reset 1 1 1 1 this register provides masks for the corresponding interrupt sources as indicated in intr_stat register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 270 of 1535 1 = allow interrupt 0 = disable interrupt note: while disabled, the corresponding interrupt will not be asserted, however the intr_stat will still be updated with the status. ie. mask does not affect intr_stat register values. i2creg+000c h interrupt status register intr_stat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hs_na cker r acke rr tran sac_ comp type w1c w1cw1c reset 0 0 0 when an interrupt is issued by i2c controller, this regist er will need to be read by mcu to determine the cause for the interrupt. after this status has been read and appropriate actions are taken, the corresponding interrupt source will need to be write 1 cleared. hs_nackerr this status is asserted if hs master code nack error detection is enabled. if enabled, hs master code nack err will cause transaction to end and stop will be issued. ackerr this status is asserted if ack error detection is enabled. if enabled, ackerr will cause transaction to end and stop will be issued. transac_comp this status is asserted when a transaction has completed successfully. i2creg+0010 h control register control bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tran sfer_ len_c hang e acke rr_de t_en dir_c hang e clk_e xt en dma_ en rs_st op type r/w r/w rw rw rw rw r/w reset 0 0 0 0 0 0 0 transfer_len_change this options specifies whether or not to change the transfer length after the fist transfer completes. if enabled, the transfers after the first transfer will use the transfer_len_aux parameter. ackerr_det_en this option enables slave ack error detection. when enabled, if slave ack error is detected, the master shall terminate the transaction by issuing a stop condition and then asserts ackerr interrupt. mcu shall handle this case appropriately and then resets the fifo address before reissuing transaction again. if this option is disabled, the controller will ignore slave ack error and keep on scheduled transaction. 0 disable 1 enable dir_change this option is used for combined transfer format, where the direction of transfer is to be changed from write to read after the first rs condition. note: when set to 1, the transfers after the direction change will be based on the transfer_len_aux parameter. 0 disable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 271 of 1535 1 enable clk_ext_en i2c spec allows slaves to hold the scl lin e low if it is not yet ready for further processing. therefore, if this bit is set to 1, master controller will enter a high wait state until the slave releases the scl line. dma_en by default, this is disabled, and fifo data shall be manually prepared by mcu. this default setting should be used for transfer sizes of less than 8 data bytes and no multiple transfer is configured. when enabled, dma requests are turned on, and the fifo data should be prepared in memory. rs_stop in ls/fs mode, this bit affects multi-transfer transaction only. it controls whether or not repeated-start condition is used between transfers. the last ending transfer always ends with a stop. in hs mode, this bit must be set to 1. 0 use stop 1 use repeated-start i2creg+0014 h transfer length register (number of bytesper transfer) transfer_le n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name transfer_len_aux transfer_len type r/w r/w reset ?h1 ?h1 transfer_len_aux[4:0] this field is valid only when dir_change is set to 1. this indicates the number of data bytes to be transferred in 1 transfer unit (excluding slave address byte) for the transfers following the direction change. i.e., if dir_change =1, then the first write transfer length depends on transfer_len, while the second read transfer length depend on transfer_len_aux. dir change is always after the first transfer. (note) the value must be set greater than 1, otherwise no transfer will take place. transfer_len[7:0] this indicates the number of data bytes to be transferred in 1 transfer unit (excluding slave address byte) (note) the value must be set greater than 1, otherwise no transfer will take place. i2creg+0018 h transaction length register (number of transfers per transaction) transac_len bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name transac_len type r/w reset ?h1 transac_len[7:0] this indicates the number of transfers to be transferred in 1 transaction (note) the value must be set greater than 1, otherwise no transfer will take place. i2creg+001c h inter delay length register delay_len bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name delay_len free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 272 of 1535 type r/w reset ?h2 delay_len[3:0] this sets the wait delay between consecutive transfers when rs_stop bit is set to 0. (the unit is same as the half pulse width) i2creg+0020 h timing control register timing bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data read adj data_read_time sample_cnt_div step_cnt_div type r/w r/w r/w r/w reset ?h0 ?h1 ?h3 ?h3 ls/fs only. this register is used to control the output waveform timing. each half pulse width (ie. each high or low pulse) is equal to = step_cnt_div * (sample_cnt_div * 1/13mhz) sample_cnt_div[2:0] used for ls/fs only. this adjusts the width of each sample. (sample width = sample_cnt_div * 1/13mhz) step_cnt_div[5:0] this specifies the number of samples per half pulse width (ie. each high or low pulse) data_read_adj when set to 1, data latch in sampling time during master reads are adjusted according to data_read_time value. otherwise, by default, data is latched in at half of the high pulse width point. this value must be set to less or equal to half the high pulse width. data_read_time[2:0] this value is valid only when data_read_adj is set to 1. this can be used to adjust so that data is latched in at earlie r sampling points (assum ing data is settled by then) i2creg+0024 h start register start bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start type r/w reset 0 start this register starts the transaction on the bus. it is auto deasserted at the end of the transaction. i2creg+0030 h fifo status register fifo_stat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rd_addr wr_addr fifo_offset wr_f ull rd_e mpty type ro ro ro ro ro reset 0 0 0 0 0 0 0 rd_addr[3:0] the current rd address pointer. (only bit [2:0] has physical meaning) wr_addr[3:0] the current wr address pointer. (only bit [2:0] has physical meaning) fifo_offset[3:0] wr_addr[3:0] ? rd_addr[3:0] wr_full this indicates that the fifo is full. rd_empty this indicates that the fifo is empty. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 273 of 1535 i2creg+0034 h fifo thresh register fifo_thresh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx_trig_thresh rx_trig_thresh type rw r/w reset ?h7 ?h0 debug only. by default, these values do not need to be adjusted. note! for rx, no timeout mechanism is implemented. therefore, rx_trig_thresh must be left at 0, or there would be data left in the fifo that is not fetched by dma controller. tx_trig_thresh[2:0] when tx fifo level is below this value, tx dma request is asserted. rx_trig_thresh[2:0] when rx fifo level is above this value, rx dma request is asserted. i2creg+0038 h fifo address clear register fifo_addr_cl r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_ addr _cr type wo reset 0 fifo_addr_clr when written with a 1?b1, a 1 pulse fifo_addr_clr is generated to clear the fifo address to back to 0. i2creg+0040 h io config register io_config bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name io sync en sda_i o_co nfig scl_i o_co nfig type r/w r/wr/w reset 0 0 0 this register is used to configure the i/o for the sda and scl lines to select between normal i/o mode, or open- drain mode to support wired-and bus. io_sync_en debug only: when set to 1, scl and sda inputs will be first dual synced by bclk_ck. this should not be needed. only reserved for debugging. sda_io_config 0 normal tristate io mode 1 open-drain mode scl_io_config 0 normal tristate io mode 1 open-drain mode i2creg+0044 h reserved debug register debug bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/wr/w reset 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 274 of 1535 note: this register is for debug only. the bits are r/w, do not change the values from the default value. i2creg+0048 h high speed mode register hs bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hs_sample_cnt div hs_step_cnt_div master_code hs_na cker r_det _en hs_e n type r/w r/w r/w r/w r/w reset 0 1 0 1 0 this register contains options for supporting high speed operation features each hs half pulse width (ie. each high or low pulse) is equal to = step_cnt_div * (sample_cnt_div * 1/13mhz) hs_sample_cnt_div[2:0] when high speed mode is entered after the master code transfer has been completed, the sample width becomes dependent on this parameter. hs_step_cnt_div[2:0] when high speed mode is entered after the master code transfer has been completed, the number of samples per half pulse width becomes dependent on this value. master_code[2:0] this is the 3 bit programmable value for the master code to be transmitted. hs_nackerr_det_en this enables nackerr detection during the master code transmission. when enabled, if nack is not received after master code has been transmitted, the transaction will terminated with a stop condition. hs_en this enables the high speed transaction. (note: rs_stop must be set to 1 as well) i2creg+0050 h soft reset register softreset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name soft_ reset type wo reset 0 soft_reset when written with a 1?b1, a 1 pulse soft reset is used as synchronous reset to reset the i2c internal hardware circuits. i2creg+0064 h debug status register debugstat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bus_b usy mast er_w rite mast er_re ad master_state type ro ro ro ro reset 0 1 0 0 bus_busy debug only: valid when bus_detect_en is 1. bus_busy = 1 indicates a start transaction has been detected and no stop condition has been detected yet. master_write debug only: 1 = current transfer is in the master write dir master_read debug only: 1 = current transfer is in the master read dir master_state[3:0] debug only: reads back the current master_state. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 275 of 1535 i2creg+0068h debug cont rol register debugctrl bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apb_d ebug _rd fifo_ apb_ debu g type wor/w reset 0 0 apb_debug_rd this bit is only valid when fifo_apb_debug is set to 1. writing to this register will generate a 1 pulsed fifo apb rd signal for reading the fifo data. fifo_apb_debug this is used for trace32 debug purposes. when using trace32, and the memory map is shown, turning this bit on will block the normal apb read access. apb read access to the fifo is then enabled by writing to apb_debug_rd. 0 disable 1 enable 2.21 irda framer 2.21.1 general description irda framer is implemented to reduce the cpu loading for irda transmissions by performing all the physical level protocol framing in hardware. from a software perspective, the framer need only prepare and process the raw data for transmission and reception. generic dma is required to move the data between irda framer?s internal fifo and software-designated memory. the irda framer supports irda sir, mir, and fir modes of operation. sir mode includes operation from 9600bps ~ 115200bps, mir includes operation at 567000bps or 1152000bps, and fir mode includes operation at 4mbps. 2.21.2 register definitions irda+0000h tx buf and rx buf buf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf[7:0] type r/w reset 0 buf irda framer transmit or receive data. a write to this register writes into the internal tx fifo. a read from this register reads from the internal rx fifo. irda+0004h tx buf and rx buf clear signal buf_clear bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clear type r/w reset 0 clear sir mode only . when clear=1, both the tx and rx fifo are cleared. this is used primarily for debug purpose. normal operation does not require this. this control signaled can only be issued under sir mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 276 of 1535 irda+0008h maximum turn around time max_t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max_t [13:0] type r/w reset 3e80h max_t the maximum time that a station can hold the p/f bit. this parameter along with the baud rate parameter dictates the maximum number of bytes that a station can transmit before passing the line to another station by transmitting a frame with the p/f bit. this parameter is used by one station to indicate the maximum time the other station can send before it must turn the link around. for baud rates less than 115200 kbps, 500 ms is the only valid value. the default value is 500 ms. irda+000ch minimum turn around time min_t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name min_t [15:0] type r/w reset fde8h min_t minimum turn around time, the default value is 10 ms. the minimum turn around time parameter deals with the time needed for a receiver to recover following saturation by transmission from the same device. this parameter corresponds to the required time delay between the last byte of the last frame sent by a station and the point at which it is ready to receive the first byte of a frame from another station, i.e. the latency for a transmit to complete and be ready to receive. irda+0010h number of additional bofs pr efixed to the beginning of a frame bofs bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type bofs [6:0] type r/w r/w reset 0 1011b bofs for sir mode : the additional bofs parameter indicates the number of additional flags needed at the beginning of every frame. the main purpose for the additional bofs is to provide a delay at the beginning of each frame for devices with a long interrupt latency. for mir mode : this parameter indicates the number of double sta?s to transmit in the beginning. this value should be set to 0 (for default 2 sta?s) for mir mode, unless more are required. for fir mode : this parameter has no effect. type sir mode only . additional bofs type. 1 bof = c0h 0 bof = ffh irda+0014h baud rate divisor div bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name div[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 277 of 1535 reset 55h div transmit or receive rate divider. rate = system clock frequency / div/ 16. the default value is 55h when in contention mode. this divisor is also used to determine the rx fifo timeout threshold. irda+0018h transmit frame size tx_frame_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx_frame_size[11:0] type r/w reset 40h tx_frame_size transmit frame size; the default value is 64 when in contention mode. irda+001ch receiving frame1 size rx_frame1_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_frame1_size[11:0] type ro reset 0 rx_frame1_size reports the number of byte received. includes only the a+c+i fields. irda+0020h transmit abort indication abort bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name abor t type r/w reset 0 abort sir mode only . when set 1, the framer transmits an abort sequence and closes the frame without an fcs field or an ending flag. note: tx abort can be achieved in mir and fir by simply disabling the tx_en signal. irda+0024h irda framer transmit enable signal tx_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx_on e txinve rt mode tx_en type r/w r/w r/w r/w reset 0 0 0 0 tx_en transmit enable. mode sir mode only . modulation type selection. 0 3/16 modulation 1 1.61us txinvert invert the transmit signal. 0 transmit signal is not inverted. 1 transmit signal is inverted. tx_one: controls the transmit enable signal is one or not. 0 tx_en is not de-asserted until software programs a so. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 278 of 1535 1 tx_en is de-asserted (i.e. transmit disabled) automatically after one frame has been sent. irda+0028h irda framer receive enable signal rx_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_on e rxinve rt rx_e n type r/w r/w r/w reset 0 0 0 rx_en receive enable. rxinvert invert the receive signal. 0 receive signal is not inverted . 1 receive signal is inverted . rx_one disable receive when get one frame. 0 rx_en is not de-asserted until software programs so. 1 rx_en is de-asserted (i.e. transmit disabled) automatically after one frame has been sent. irda+002ch fifo trigger level indication trigger bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_trig[ tx_trig type r/w r/w reset 0 0 tx_trig tx fifo interrupt trigger threshold. when the amount of data in the tx fifo is less than the specified amount, dma req is asserted. (when tx_trig = 03, dma req is always asserted as long as fifo is not full.) 00 0 byte 01 1 byte 02 8 byte 03 16 byte rx_trig rx fifo interrupt trigger threshold. when the amount of data in rx fifo is above the specified amount, dma req is asserted. 00 1 byte 01 2 byte 02 3 byte irda+0030h irq enable signal irq_enable bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 2ndrx _com p rxre start thres htime out fifoti meou t txabo rt rxabo rt maxti meou t minti meou t rxco mplet e txco mplet e erro r rxth res txth res type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 txres transmit data reaches the threshold level. (for debug only. should be set to 0.) 0 no interrupt is generated. 1 interrupt is generated when transmit fifo size reaches threshold. rxres receive data reaches the threshold level. (for debug only. should be set to 0.) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 279 of 1535 0 no interrupt is generated. 1 interrupt is generated when receive fifo size reaches threshold. error error status interrupt enable. 0 no interrupt is generated. 1 interrupt is generated when one of the error statuses occurs. txcomplete transmit one frame completely. 0 no interrupt is generated. 1 interrupt is generated when transmitting one frame completely. rxcomplete receive one frame completely. 0 no interrupt is generated. 1 interrupt is generated when receiving one frame completely. mintimeout minimum time timeout. 0 no interrupt is generated. 1 interrupt is generated when minimum timer is timed out. maxtimeout maximum time timeout. 0 no interrupt is generated. 1 interrupt is generated when maximum timer is timed out. rxabort receiving aborting frame. 0 no interrupt is generated. 1 interrupt is generated when receiving aborting frame. txabort sir mode only . transmitting aborting frame. 0 no interrupt is generated. 1 interrupt is generated when transmitting aborting frame. fifotimeout fifo timeout. 0 no interrupt is generated. 1 interrupt is generated when fifo timeout. threshtimeout threshold time timeout. 0 no interrupt is generated. 1 interrupt is generated when threshold timer is timed out. rxrestart sir mode only . receiving a new frame before one frame is received completely. 0 no interrupt is generated. 1 interrupt is generated when receiving a new frame before one frame is received completely. 2ndrx_comp receiving second frame and get p/f bit. 0 no interrupt is generated. 1 interrupt is generated when receiving second frame and get p/f bit completely. irda+0034h interrupt status irq_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 2ndrx _com p rxre start thres htime out fifoti meou t txabo rt rxabo rt maxti meou t minti meou t rxco mplet e txco mplet e erro r rxtre s txtre s type rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 280 of 1535 txfifo transmit fifo reaches threshold. (for debug only. not recommended for normal usage.) rxfifo receive fifo reaches threshold. (for debug only. not recommended for normal usage.) error generated when any of status in error status register occurs. once the source of an interrupt is determined to be caused by an error (bit 2), the error status register should be read. once read, both the error status register and the interrupt source are read-cleared. if the error status register indicates either a frame 1 or frame 2 error, the corresponding frame status register should be read. txcomplete transmitting one frame completely. rxcomplete receiving one frame completely. mintimeout minimum turn around time timeout. maxtimeout maximum turn around time timeout. rxabort receiving aborting frame. txabort transmitting aborting frame. fifotimeout fifo is timeout. threshtimeout threshold time timeout. rxrestart receiving a new frame before one frame is received completely. 2ndrx_comp receiving second frame and get p/f bit completely. irda+0038h error status register err_status bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx fifo underr un frame 2 data err frame 1 data err reser ved2 reser ved over run rxsiz e type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 rxsize receive frame size error. overrun frame overrun. reserved reserved for future use. reserved2 reserved for future use. frame1 data err indicates that an error condition occurred in rx frame1. must check the rx frame1 status. frame2 data err indicates that an error condition occurred in rx frame2. must check the rx frame2 status. tx fifo underrun mir and fir mode only . tx fifo underrun has occurred. data transmission is aborted. software must reset the tx_en signal. irda+003ch transceiver power on/off control. transceiver mode select. transceiver_pd n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txcvr config tx manual trans_ pdn type r/w r/w r/w reset 0 0 0 transceiver_pdn used for power on/off control for external irda transceiver. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 281 of 1535 tx_manual when txcvr config is set to 1, this bit can be used to select the operation mode of the external irda transceiver (some transceivers require selection between high speed and low speed operating modes), by software programming the desired sequence to transmit through the irda_txd pin. txcvr config 0 irda_txd comes from core logic. 1 irda_txd depends on tx_manual value. irda+0040h maximum number of receiving frame size rx_frame_max bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max_rx_frame_size_ type r/w reset 0 rx_frame_max receive frame i field max size, when actual receiving frame size is larger than rx_frame_max, rxsize is asserted. the maximum allowed i field size is 2048. irda+0044h threshold time thresh_t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name disconnect_time[15:0] type r/w reset bb8h threshold time threshold time; used to control the time a station waits without receiving a valid frame before disconnecting the link. associated with this is the time a station waits without receiving a valid frame before sending a status indication to the service user layer. irda+0048h counter enab le signal count_enable bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thresh _en min_e n max_ en type r/w r/w r/w reset 0 0 0 count_enable counter enable signals. irda+004ch indication of system clock rate clock_rate bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clock_rate type r/w reset 0 clock_rate sir mode only indication of the system clock rate. 0 26 mhz 1 52 mhz 2 13 mhz irda+0050h system clock rate fix rate_fix bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 282 of 1535 name mir timing tune crc repor t sir framin g set rate_ fix type r/w r/w r/w r/w reset 0 0 0 0 rate_fix sir mode only fix the irda framer sample base clock rate as 13 mhz. 0 clock rate based on clock_rate selection. 1 clock rate fixed at 13 mhz. sir framing set sir mode only . framing error check condition. 0 ignore the stop bit of the last byte of a frame. 1 check the stop bit of the last byte of a frame. crc report when set to 1, crc error is reported via error status register and error interrupt. mir timing tune[1:0] mir mode only . for some transceivers, in mir 0.576mbps mode, the rx output pulse does not conform to irda specification. therefore, this option is used to detect the rx output from those transceivers correctly. 0 for transceivers that conform to spec. 1 for transceivers that do not conform to spec, and the rx output pulse is half of that specified. 2 for transceivers that do not conform to spec, and the rx output pulse is quarter of that specified. irda+0054h rx frame1 status frame1_status bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fir sto err fir 4ppm err mir hdlc err unkno w_erro r pf_dete ct crc_fai l frame_ error type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 frame_error sir mode only . framing error, i.e. stop bit = 0. 0 no framing error 1 framing error occurred crc_fail crc check fail 2 crc check successfully 3 crc check fail pf_detect p/f bit detect 0 not a p/f bit frame 1 detected p/f bit in this frame unknown_error sir mode only . receiving error data, i.e. escape character is followed by a character that is not an esc, bof, or eof character. 0 data received correctly. 1 unknown error occurred. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 283 of 1535 mir hdlc err mir mode only . mir hdlc encoding error 0 no error 1 error fir 4ppm err fir mode only . fir 4ppm encoding error 0 no error 1 error fir sto err fir mode only . fir sto sequence error 0 no error 1 error irda+0058h rx frame2 status frame2_status bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fir sto err fir 4ppm err mir hdlc err unkno w_erro r pf_dete ct crc_fai l frame_ error type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 frame_error sir mode only. framing error, i.e. stop bit = 0 0 no framing error. 1 framing error occurred. crc_fail crc check fail. 0 crc check successfully. 1 crc check fail. pf_detect p/f bit detect. 0 not a p/f bit frame. 1 detected p/f bit in this frame. unknown_error sir mode only . receiving error data, i.e. escape character is followed by a character that is not an esc, bof, or eof character. 0 data receiving correctly. 1 unknown error occurred. mir hdlc err mir mode only . mir hdlc encoding error. 0 no error 1 error fir 4ppm err fir mode only .fir 4ppm encoding error 0 no error 1 error fir sto err fir mode only .fir sto sequence error 0 no error 1 error irda+005ch receiving frame2 size rx_frame2_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_frame2_size[11:0] type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 284 of 1535 reset 0 rx_frame2_size reports the number of byte received. includes only the a+c+i fields. irda+0060h irda mode select irda_mode bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mir speed irda mode type r/w r/w reset 0 00 irda mode selects the irda operating mode. note: this mode selection cannot be issued while transmitting or receiving. 00 ir mode 01 mir mode 10 fir mode mir speed select the mir speed. 0 0.576 mbps 1 1.152 mbps irda+0064h fifo status fifo_stat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx fifo hold tx fifo wr full tx fifo rd empty rx fifo wr full rx fifo rd empty type ro ro ro ro ro reset 0 0 1 0 1 this register indicates the real time fifo status, for monitoring purposes. 2.22 keypad scanner 2.22.1 general description the keypad can be divided into two parts: one is the keypad interface including 8 columns and 8 rows with one dedicated power-key, as shown in fig. 3 ; the other is the key detection block which provides key pressed, key released and de-bounce mechanisms. each time the key is pressed or released, i.e. something different in the 8 x 8 matrix or power-key, the key detection block senses the change and recognizes if a key has been pressed or released. whenever the key status changes and is stable, a keypad irq is issued. the mcu can then read the key(s) pressed directly in kp_mem1, kp_mem2, kp_mem3, kp_mem4 and kp_mem5 registers. to ensure that the key pressed information is not missed, the status register in keypad is not read- cleared by apb read command. the status register can only be changed by the key-pressed detection fsm. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 285 of 1535 this keypad can detect one or two key-pressed simultaneously with any combination. fig. 4 shows one key pressed condition. fig. 5 (a) and fig. 5 (b) illustrate two keys pressed case s. since the key press detection depends on the high or low level of the external keypad interface, if keys are pressed at the same time and there exists a key that is on the same column and the same row with the other keys, the pressed key cannot be correctly decoded. for example, if there are three ke y presses: key1 = (x1, y1), key2 = (x2, y2), and key3 = (x1, y2), then both key3 and key4 = (x2, y1) are detected, and therefore they cannot be distinguished correctly. hence, the keypad can detect only one or two keys pressed simultaneously at any combination. more than two keys pressed simultaneously in a specific pattern retrieve the wrong information. this keypad can detect more than two key-presses simultaneously with some special combination. this limitation is any two or more simultaneous keys can?t be the same row or column. as shown in fig.4 , two key- presses has exists in the keypad matrix and we do the 3 rd key-press, key_a or kye_b. in this case, key_a is valid and can be detected correctly because its position is not in the row or column of the two existing key- press. however keypad circuit can?t detect key_b correctly. if three or more simultaneous key-press is necessary, the positions of these special keys need to be arranged carefully. d edicated for pow er-key (8x8 + one power-key) key m atrix row 0 row 1 row 2 row 3 row 4 baseband pm ic integrated bb chip col1 col2 col3 col4 col5 col6 pm ic col0 col7 pw r_key 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 row 5 row 6 row 7 fig. 3 8x8 matrix with one power-key free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 286 of 1535 key-pressed st at us de-bounce t ime de-bounce time key pressed kp_ irq key_ press_ irq key_ release_ irq fig. 4 . one key pressed with de-bounce mechanism denoted key1 pressed key2 pressed status irq key1 pressed key2 pressed key1 released key2 released key1 pressed key2 pressed status irq key1 pressed key2 pressed key2 released key1 released (a) (b) key1 pressed key2 pressed status irq key1 pressed key2 pressed key1 released key2 released key1 pressed key2 pressed status irq key1 pressed key2 pressed key2 released key1 released (a) (b) fig. 5. (a) two keys pressed, case 1 (b) two keys pressed, case 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 287 of 1535 dedicated for power-key (8x8 + one power-key) key matrix row0 row1 row2 row3 row4 baseband pmic integrated bb chip col1 col2 col3 col4 col5 col6 pmic col0 col7 pwr_key 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 row5 row6 row7 0 key a key b fig. 6. simultaneous three key support example. 2.22.2 register definitions kp +0000h keypad status kp_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sta type ro reset 0 sta this register indicates the keypad status. the register is not cleared by the read operation. 0 no key pressed 1 key pressed kp +0004h keypad scanning output register kp_mem1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key 15 key 14 key 13 key 12 key 11 key 10 key 9 key 8 key 7 key 6 key 5 key 4 key 3 key 2 key 1 key 0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 the register shows up the key-press status of key0(lsb)~key15. please reference table 37. kp +0008h keypad scanning output register kp_mem2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 288 of 1535 name key 31 key 30 key 29 key 28 key 27 key 26 key 25 key 24 key 23 key 22 key 21 key 20 key 19 key 18 key 17 key 16 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 the register shows up the key-press status of key16(lsb)~key31. please reference table 37. kp +000ch keypad scanning output register kp_mem3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key 47 key 46 key 45 key 44 key 43 key 42 key 41 key 40 key 39 key 38 key 37 key 36 key 35 key 34 key 33 key 32 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 the register shows up the key-press status of key32(lsb)~key47. please reference table 37. kp +0010h keypad scanning output register kp_mem4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key 63 key 62 key 61 key 60 key 59 key 58 key 57 key 56 key 55 key 54 key 53 key 52 key 51 key 50 key 49 key 48 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 the register shows up the key-press status of key48(lsb)~key63. please reference table 37. kp +0014h keypad scanning output register kp_mem5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key 71 key 70 key 69 key 68 key 67 key 66 key 65 key 64 type ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 the register shows up the key-press status of key64(lsb)~key71. please reference table 37. these five registers list the status of 72 keys on the keypad but key[8], key[17], key[26], key[35], key[44] , key[53] , key[62] , key[71] is dedicated for power key. when the mcu receives the keypad irq, both two registers must be read. if any key is pressed, the relative bit is set to 0. if some keys can be use because their col or row is use as gpio, these corresponding bit will be tie to high. keys status list of the 72 keys. kp +00018h de-bounce period setting kp_debounce bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name debounce [13:0] type r/w reset 400h free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 289 of 1535 this register defines the waiting period before key press or release events are considered stale. if debounce setting is too small, keypad will be too sensitive and detect too many unexpected key-press. the suitable debounce time setting must be adjust for the user?s habit. debounce de-bounce time = kp_debounce*(1/32k) sec. 32 khz is the working clock frequency of keypad module. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 290 of 1535 col0 col1 col2 col3 col4 col5 col6 col7 pwrkey row7 63 64 65 66 67 68 69 70 71 row6 54 55 56 57 58 59 60 61 62 row5 45 46 47 48 49 50 51 52 53 row4 36 37 38 39 40 41 42 43 44 row3 27 28 29 30 31 32 33 34 35 row2 18 19 20 21 22 23 24 25 26 row1 9 10 11 12 13 14 15 16 17 row0 0 1 2 3 4 5 6 7 8 table 37 key?s order number in col/row matrix. revision date author comments 2008/7/18 sj yang add clock rate switching notes 2.23 memory stick and sd memory card controller 2.23.1 introduction the controller fully supports the memory stick bus protocol as defined in format specification version 2.0 of memory stick standard (memory stick pro) and the sd memory card bus protocol as defined in sd memory card specification part 1 physical layer specificatio n version 2.0 as well as the multimediacard (mmc) bus protocol as defined in mmc system specification version 4.1. since sd memory card bus protocol is backward compatible to mmc bus protocol, the controller is capable of working well as the host on mmc bus under control of proper firmware. furthermore, the controller also support sdio card specification version 1.0 partially. however, the controller can only be configured as either the host of memory stick or the host of sd/mmc memory card at one time. hereafter, the cont roller is also abbreviated as ms/sd controller. the following are the main features of the controller. z interface with mcu by apb bus z 16/32-bit access on apb bus z 16/32-bit access for control registers z 32-bit access for fifo z shared pins for memory stick and sd/mmc memory card z built-in 32 bytes fifo buffers for transmit and re ceive, fifo is shared for transmit and receive z built-in crc circuit z crc generation can be disabled z dma supported free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 291 of 1535 z interrupt capabilities z automatic command execution capability wh en an interrupt from memory stick z data rate up to 26 mbps in serial mode, 26x4 mbps (26x8 mbps if 8-bit data line for sd/mmc card is configured) in parallel model, the module is targeted at 26 mhz operating clock z serial clock rate on ms/sd/mmc bus is programmable z card detection capabilit ies during sleep mode z controllability of po wer for memory card z not support spi mode for ms/sd/mmc memory card z not support multiple sd memory cards 2.23.2 overview 2.23.2.1 pin assignment since the controller can only be configured as either the host of memory stick or the host of sd/mmc memory card at one time, pins for memory stick and sd/mmc memory card are shared in order to save pin counts. the following lists pins required for memory stick and sd/mmc memory card. table 38 shows how they are shared. in table 38 , all i/o pads have embedded both pull up and pull down resistor because they are shared by both the memory stick and sd/mmc memory card. pins 2,4,5,8 are only useful for sd/mmc memory card. pull down resistor for these pins can be used for power saving. all embedded pull-up and pull- down resistors can be disabled by programming the corresponding control registers if optimal pull-up or pull- down resistors are required on the system board. the pin vddpd is used for power saving. power for memory stick or sd/mmc memory card can be shut down by programming the corresponding control register. the pin wp (write protection) is only valid when the controller is configured for sd/mmc memory card. it is used to detect the status of write protection switch on sd/mmc memory card. no. name t y pe mmc sd ms mspro description 1 sd_clk o clk clk sclk sclk clock 2 sd_dat3 i/o/pp cd/dat3 dat3 data line [bit 3] 3 sd_dat0 i/o/pp dat0 dat0 sdio dat0 data line [bit 0] 4 sd_dat1 i/o/pp dat1 dat1 data line [bit 1] 5 sd_dat2 i/o/pp dat2 dat2 data line [bit 2] 6 sd_cmd i/o/pp cmd cmd bs bs command or bus state 7 sd_pwron o vdd on/off 8 sd_wp i write protection switch in sd 9 sd_ins i vss2 vss2 ins ins card detection table 38 sharing of pins for memory stick and sd/mmc memory card controller 2.23.2.2 card detection for memory stick, the host or connector should provide a pull up resistor on the signal ins. therefore, the signal ins will be logic high if no memory stick is on line. the scenario of card detection for memory stick is shown in figure 19 . before memory stick is inserted or powered on, on host side sw1 shall be closed and sw2 shall be opened for card detection. it is the default setting when the controller is powered on. upon insertion of memory stick, the signal ins will have a transi tion from high to low. hereafter, if memory stick is free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 292 of 1535 removed then the signal ins will return to logic high. if card insertion is intended to not be supported, sw1 shall be opened and sw2 closed always. for sd/mmc memory card, detection of card insertion/removal by hardware is also supported. because a pull down resistor with about 470 k ? resistance which is impractical to embed in an i/o pad is needed on the signal cd/dat3, and it has to be capable of being connected or disconnected dynamically onto the signal cd during initialization period, an additional i/o pad is needed to switch on/off the pull down resistor on the system board. the scenario of card detection for sd/mmc memory card is shown in figure 20 . before sd/mmc memory card is inserted or powered on, sw1 and sw2 shall be opened for card detection on the host side. meanwhile, pull down resistor r cd on system board shall attach onto the signal cd/dat3 by the output signal rcden. in addition, sw3 on the card is default to be closed. upon insertion of sd/mmc memory card, the signal cd/dat3 will have a transition from low to high. if sd/mmc memory card is removed then the signal cd/dat3 will return to logic low. after the card identification process, pull down resistor r cd on system board shall disconnect with the signal cd/dat3 and sw3 on the card shall be opened for normal operation. since the scheme above needs a mechanical switch such as a relay on system board, it is not ideal enough. thus, a dedicated pin ?ins? is used to perform card insertion and removal for sd/mmc. the pin ?ins? will connect to the pin ?vss2? of a sd/mmc connector. then the scheme of card detection is the same as that for ms. it is shown in figure 19 . */4 3 16 1"% 48 3 1% 48 %"5065 $%%"5*/ )045 $"3% pvuqvufobcmf figure 19 card detection for memory stick free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 293 of 1535 3 16 1"% 48 3 1% 48 %"5065 $%%"5*/ )045 $"3% , 48 pvuqvufobcmf pvuqvufobcmf ,pin 3$%&/ 1"% figure 20 card detection for sd/mmc memory card free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 294 of 1535 2.23.3 register definitions for mt6253, msdc base address is 0x81110000. register address register name synonym msdc + 0000h ms/sd memory card controller configuration register msdc_cfg msdc + 0004h ms/sd memory card controller status register msdc_sta msdc + 0008h ms/sd memory card controller interrupt register msdc_int msdc + 000ch ms/sd memory card controller data register msdc_dat msdc + 00010h ms/sd memory card pin status register msdc_ps msdc + 00014h ms/sd memory card controller io control register msdc_iocon msdc + 0020h sd memory card controller configuration register sdc_cfg msdc + 0024h sd memory card controller command register sdc_cmd msdc + 0028h sd memory card controller argument register sdc_arg msdc + 002ch sd memory card controller status register sdc_sta msdc + 0030h sd memory card controller response register 0 sdc_resp0 msdc + 0034h sd memory card controller response register 1 sdc_resp1 msdc + 0038h sd memory card controller response register 2 sdc_resp2 msdc + 003ch sd memory card controller response register 3 sdc_resp3 msdc + 0040h sd memory card controller command status register sdc_cmdsta msdc + 0044h sd memory card controller data status register sdc_datsta msdc + 0048h sd memory card status register sdc_csta msdc + 004ch sd memory card irq mask register 0 sdc_irqmask0 msdc + 0050h sd memory card irq mask register 1 sdc_irqmask1 msdc + 0054h sdio configuration register sdio_cfg msdc + 0058h sdio status register sdio_sta msdc + 0060h memory stick controller configuration register msc_cfg msdc + 0064h memory stick controller command register msc_cmd msdc + 0068h memory stick controller auto command register msc_acmd msdc + 006ch memory stick controller status register msc_sta table 39 ms/sd controller register map free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 295 of 1535 2.23.3.1 global register definitions msdc+0000h ms/sd memory card controller configuration register msdc_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifothd prcfg2 prcfg1 prcfg0 vddp d rcde n dirqe n pinen dmae n inten type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0001 01 01 10 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sclkf sclk on cred stdby clks rc rst nocr c msdc type r/w r/w r/w r/w r/w w r/w r/w reset 00000000 0 0 1 0 0 0 0 the register is for general configuration of the ms/sd controller. note that msdc_cfg[31:16] can be accessed by 16-bit apb bus access. msdc the register bit is used to configure the controller as the host of memory stick or as the host of sd/mmc memory card. the default value is to configure the controller as the host of memory stick. 0 configure the controller as the host of memory stick 1 configure the controller as the host of sd/mmc memory card nocrc crc disable. a ?1? indicates that data transfer without crc is desired. for write data block, data will be transmitted without crc. for read data bl ock, crc will not be checked. it is for testing purpose. 0 data transfer with crc is desired. 1 data transfer without crc is desired. rst software reset. writing a ?1? to the register bi t will cause internal synchronous reset of ms/sd controller, but does not reset register settings. 0 otherwise 1 reset ms/sd controller clksrc the register bit specifies which clock is used as the source clock of the memory card. if the mcu clock is used, the fastest clock rate the memory ca rd is 122/4=30.5mhz. instead, if the mcpll clock is used, the fastest clock rate of the memory card is 91/2=45.5mhz. 0 use mcu clock as the source clock of the memory card. 1 use mcpll clock as the source clock of the memory card. stdby standby mode. if the module is powered down, operating clock to the module will be stopped. at the same time, clock to card detection circuitry will also be stopped. if detection of memory card insertion and removal is desired, write ?1? to the register bit. if interrupt for detection of memory card insertion and removal is enabled, interrupt will take plac e whenever memory is inserted or removed. 0 standby mode is disabled. 1 standby mode is enabled. red rise edge data. the register bit is used to determ ine that serial data input is latched at the falling edge or the rising edge of serial clock. the defaul t setting is at the rising edge. if serial data has free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 296 of 1535 worse timing, set the register bit to ?1?. when memory card has worse timing on return read data, set the register bit to ?1?. 0 serial data input is latched at the rising edge of serial clock. 1 serial data input is latched at the falling edge of serial clock. sclkon serial clock always on. it is for debugging purpose. 0 not to have serial clock always on. 1 to have serial clock always on. sclkf the register field controls clock frequency of serial clock on ms/sd bus. denote clock frequency of ms/sd bus serial clock as f slave and clock frequency of the ms/sd controller as f host which is 104 or 52 mhz. then the value of the register field is as follows. note that the allowable maximum frequency of f slave is 26mhz . while changing clock rate, it needs ? 1t clock period before change + 1t clock period after change? for hw signal to re-synchronize. 00000000b f slave =(1/2) * f host 00000001b f slave = (1/(4*1)) * f host 00000010b f slave = (1/(4*2)) * f host 00000011b f slave = (1/(4*3))* f host ? 00010000b f slave = (1/(4*16))* f host ? 11111111b f slave = (1/(4*255)) * f host inten interrupt enable. note that if interrupt capability is disabled then application software must poll the status of the register msdc_sta to check for any interrupt request. 0 interrupt induced by various conditions is disabled, no matter the controller is configured as the host of either sd/mmc memory card or memory stick. 1 interrupt induced by various conditions is enabled, no matter the controller is configured as the host of either sd/mmc memory card or memory stick. dmaen dma enable. note that if dma capability is disabled then application software must poll the status of the register msdc_sta for checking any data transfer request. if dma is desired, the register bit must be set before command register is written. 0 dma request induced by various conditions is disabled, no matter the controller is configured as the host of either sd/mmc memory card or memory stick. 1 dma request induced by various conditions is enabled, no matter the controller is configured as the host of either sd/mmc memory card or memory stick. pinen pin interrupt enable. the register bit is used to control if the pin for card detection is used as an interrupt source. 0 the pin for card detection is not used as an interrupt source. 1 the pin for card detection is used as an interrupt source. dirqen data request interrupt enable. the register bit is used to control if data request is used as an interrupt source. 0 data request is not used as an interrupt source. 1 data request is used as an interrupt source. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 297 of 1535 rcden the register bit controls the output pin rcden that is used for card identification process when the controller is for sd/mmc memory card. its output will control the pull down resistor on the system board to connect or disconnect with the signal cd/dat3. 0 the output pin rcden will output logic low. 1 the output pin rcden will output logic high. vddpd the register bit controls the output pin vddpd that is used for power saving. the output pin vddpd will control power for memory card. 0 the output pin vddpd will output logic low. the power for memory card will be turned off. 1 the output pin vddpd will output logic high. the power for memory ca rd will be turned on. prcfg0 pull up/down register configuration for the pin wp . the default value is 10 . 00 pull up resistor and pull down resistor in the i/o pad of the pin wp are all disabled. 01 pull down resistor in the i/o pad of the pin wp is enabled. 10 pull up resistor in the i/o pad of the pin wp is enabled. 11 use keeper of io pad. prcfg1 pull up/down register configuration for the pin cmd/bs. the default value is 0b01. 00 pull up resistor and pull down resistor in the i/o pad of the pin cmd/bs are all disabled. 01 pull down resistor in the i/o pad of the pin cmd/bs is enabled. 10 pull up resistor in the i/o pad of the pin cmd/bs is enabled. 11 use keeper of io pad. prcfg2 pull up/down register configuration for the pins dat0, dat1, dat2, dat3. the default value is 0b01. 00 pull up resistor and pull down resistor in the i/o pads o the pins dat0, dat1, dat2, dat3. are all disabled. 01 pull down resistor in the i/o pads of the pins dat0, dat1, dat2, dat3 and wp. is enabled. 10 pull up resistor in the i/o pads of the pins dat0, dat1, dat2, dat3. is enabled. 11 use keeper of io pad. fifothd fifo threshold. the register field determines when to issue a dma request. for write transactions, dma requests will be as serted if the number of free entries in fifo are larger than or equal to the value in the register field. for read transactions, dma requests will be asserted if the number of valid entries in fifo are larger than or eq ual to the value in the register field. the register field must be set according to the setting of data transfer count in dma burst mode. if single mode for dma transfer is used, the register field shall be set to 0b0001. 0000 invalid. 0001 threshold value is 1. 0010 threshold value is 2. ? 1000 threshold value is 8. others invalid free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 298 of 1535 msdc+0004h ms/sd memory card controller status register msdc_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy fifoc lr fifocnt int drq be bf type r w ro ro ro ro ro reset 0 - 0000 0 0 0 0 the register contains the status of fifo, interrupts and data requests. bf the register bit indicates if fifo in ms/sd controller is full. 0 fifo in ms/sd controller is not full. 1 fifo in ms/sd controller is full. be the register bit indicates if fifo in ms/sd controller is empty. 0 fifo in ms/sd controller is not empty. 1 fifo in ms/sd controller is empty. drq the register bit indicates if any data transfer is required. while any data transfer is required, the register bit still will be active even if the register bit dirqen in the register msdc_cfg is disabled. data transfer can be achieved by dma channel alleviating mcu loading, or by polling the register bit to check if any data transfer is requested. while the register bit dirqen in the register msdc_cfg is disabled, the second method is used. 0 no dma request exists. 1 dma request exists. int the register bit indicates if any interrupt exists. while any interrupt exists, the register bit still will be active even if the register bit inten in the register msdc_cfg is disabled. ms/sd controller can interrupt mcu by issuing interrupt request to interrupt controller, or software/application polls the register endlessly to check if any interrupt request exists in ms/sd controller. while the register bit inten in the register msdc_cfg is disabled, the second method is used. for read commands, it is possible that timeout error takes place. software can read the status register to check if timeout error takes place without os time tick support or data request is asserted. note that the register bit will be cleared when reading the register msdc_int. 0 no interrupt request exists. 1 interrupt request exists. fifocnt fifo count. the register field shows how many valid entries are in fifo. 0000 there is 0 valid entry in fifo. 0001 there is 1 valid entry in fifo. 0010 there are 2 valid entries in fifo. ? 1000 there are 8 valid entries in fifo. others invalid fifoclr clear fifo. writing ?1? to the register bit will caus e the content of fifo clear and reset the status of fifo controller. 0 no effect on fifo. 1 clear the content of fifo clear and reset the status of fifo controller. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 299 of 1535 busy status of the controller. if the controller is in busy state, the register bit will be ?1?. otherwise ?0?. 0 the controller is in busy state. 1 the controller is in idle state. msdc+0008h ms/sd memory card controller interrupt register msdc_int bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sdioi rq sdr1b irq msifir q sdmci rq sdda tirq sdcm dirq pinir q dirq type rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 the register contains the status of interrupts. note that the register still show status of interrupt even though interrupt is disabled, that is, the register bit inten of the register msdc_cfg is set to ?0. it implies that software interrupt can be implemented by polling the register bit int of the register msdc_sta and this register. however, if hardware interrupt is desired, remember to clear the register before setting the register bit inten of the register msdc_cfg to ?1?. or undesired hardware interrupt arisen from previous interrupt status may take place. dirq data request interrupt. the register bit indicates if any interrupt for data request exists. whenever data request exists and data request as an interrupt source is enabled, i.e., the register bit dirqen in the register msdc_cfg is se t to ?1?, the register bit will be active . it will be reset when reading it. for software, data requests can be recognized by polling the register bit drq or by data request interrupt. data request interrupts will be generated every fifothd data transfers. 0 no data request interrupt. 1 data request interrupt occurs. pinirq pin change interrupt. the register bit indicates if any interrupt for memory card insertion/removal exists. whenever memory card is inserted or removed and card detection interrupt is enabled, i.e., the register bit pinen in the register msdc_cfg is set to ?1?, the register bit will be set to ?1?. it will be reset when the register is read. 0 otherwise. 1 card is inserted or removed. sdcmdirq sd bus cmd interrupt. the register bit indicates if any interrupt for sd cmd line exists. whenever interrupt for sd cmd line exists, i.e., any bit in the register sdc_cmdsta is active, the register bit will be set to ?1? if interrupt is enabled. it will be reset when the register is read. 0 no sd cmd line interrupt. 1 sd cmd line interrupt exists. sddatirq sd bus dat interrupt. the register bit indicates if any interrupt for sd dat line exists. whenever interrupt for sd dat line exists, i.e., any bit in the register sdc_ datsta is active, the register bit will be set to ?1? if interrupt is enabled. it will be reset when the register is read. 0 no sd dat line interrupt. 1 sd dat line interrupt exists. sdmcirq sd memory card interrupt. the register bit in dicates if any interrupt for sd memory card exists. whenever interrupt for sd memory card exists, i.e., any bit in the register sdc_csta is active, the register bit will be set to ?1? if interrupt is enabled. it will be reset when the register is read. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 300 of 1535 0 no sd memory card interrupt. 1 sd memory card interrupt exists. msifirq ms bus interface interrupt. the register bit indicates if any interrupt for ms bus interface exists. whenever interrupt for ms bus interface exists, i.e., any bit in the register msc_sta is active, the register bit will be set to ?1? if interrupt is enabled. it will be reset when the register msdc_sta or msc_sta is read. 0 no ms bus interface interrupt. 1 ms bus interface interrupt exists. sdr1birq sd/mmc r1b response interrupt. the register bit will be active when a sd/mmc command with r1b response finishes and the dat0 line has transition from busy to idle state. single block write commands with r1b response will cause the interrupt when the command completes no matter successfully or with crc error. however, multi-block write commands with r1b response do not cause the interrupt because multi-block write commands are always stopped by stop_trans commands. stop_trans commands (with r1b response) behind multi-block write commands will cause the interrupt. single block read command with r1b response will cause the interrupt when the command completes but multi-block read commands do not. note that stop_trans commands (with r1b response) behind multi-block read commands will cause the interrupt. 0 no interrupt for sd/mmc r1b response. 1 interrupt for sd/mmc r1b response exists. sdioirq sdio interrupt. the register bit indicates if any interrupt for sdio exists . whenever interrupt for sdio exists, i.e., the register bit will be set to ?1? if interrupt is enabled. it will be reset when the register is read. 0 no sdio interrupt. 1 sdio card interrupt exists. msdc+000ch ms/sd memory card controller data register msdc_dat bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w the register is used to read/write data from/to fifo inside ms/sd controller. data access is in unit of 32 bits. msdc+0010h ms/sd memory card pin status register msdc_ps bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cmd dat type ro ro reset - - bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cddebounce pinch g pin0 poen0 pien0 cden free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 301 of 1535 type rw rc ro r/w r/w r/w reset 0000 0 1 0 0 0 the register is used for card detection. when the memory card controller is powered on, and the system is powered on, the power for the memory card is st ill off unless power has been supplied by the pmic. meanwhile, pad for card detection defaults to pull down when the system is powered on. the scheme of card detection for ms is the same as that for sd/mmc. for detecting card insertion, first pull up ins pin, and then enable card detection and input pin at the same time. after 32 cycles of controller clock, status of pin changes will emerge. for detecting card removal, just keep enabling card detection and input pin. cden card detection enable. the register bit is used to enable or disable card detection. 0 card detection is disabled. 1 card detection is enabled. pien0 the register bit is used to control input pin for card detection. 0 input pin for card detection is disabled. 1 input pin for card detection is enabled. poen0 the register bit is used to control output of input pin for card detection. 0 output of input pin for card detection is disabled. 1 output of input pin for card detection is enabled. pin0 the register shows the value of input pin for card detection. 0 the value of input pin for card detection is logic low. 1 the value of input pin for ca rd detection is logic high. pinchg pin change. the register bit indicates the status of card insertion/removal. if memory card is inserted or removed, the register bit will be set to ?1? no matter pin change interrupt is enabled or not. it will be cleared when the register is read. 0 otherwise. 1 card is inserted or removed. cddebounce the register field specifies the time interval for card detection de-bounce. its default value is 0. it means that de-bounce interval is 32 cycle time of 32khz. the interval will extend one cycle time of 32khz by increasing the counter by 1. dat memory card data lines. cmd memory card command lines. msdc+0014h ms/sd memory card controller io control register msdc_iocon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dlt crcdis cmdsel intlh dsw type r/w r/w r/w r/w r/w reset 00000010 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cmdr e prcfg3 srcf g1 srcf g0 odccfg1 odccfg0 type r/w r/w r/w r/w r/w r/w reset 0 10 1 1 000 011 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 302 of 1535 the register specifies output driving capability and slew rate of io pads for msdc. the reset value is suggestion setting. if output drivin g capability of the pins dat0, dat1, dat2 and dat3 is too large, it?s possible to arise ground bounce and thus result in glitch on sclk. the actual driving current will depend on the pad type selected for the chip. odccfg0 output driving capability the pins cmd/bs and sclk 000 4ma 010 8ma 100 12ma 110 16ma odccfg1 output driving capability the pi ns dat0, dat1, dat2 and dat3 000 4ma 010 8ma 100 12ma 110 16ma srcfg0 output driving capability the pins cmd/bs and sclk 0 fast slew rate 1 slow slew rate srcfg1 output driving capability the pi ns dat0, dat1, dat2 and dat3 0 fast slew rate 1 slow slew rate prcfg3 pull up/down register configuration for the pin ins . the default value is 10 . 00 pull up resistor and pull down resistor in the i/o pad of the pin ins are all disabled. 01 pull down resistor in the i/o pad of the pin ins is enabled. 10 pull up resistor in the i/o pad of the pin ins is enabled. 11 use keeper of io pad. cmdre the register bit is used to determine whether the host should latch response token (which is sent from card on cmd line ) at rising edge or falling edge of serial clock. 0 host latches response at rising edge of serial clock 1 host latches response at falling edge of serial clock dsw the register bit is used to determine whether the host should latch data with 1-t delay or not. for sd card, this bit is suggest to be 0. for ms /mspro cards, it is suggested to be 1. note that this field is added after mt6268 and MT6516. ( tk6516 not support yet ) 0 host latches the data with 1-t delay 1 host latches the data without 1-t delay intlh this field is used to select the latch ti ming for sdio multi-b lock read interrupt. note that this field is added after mt6268 and MT6516. ( tk6516 not support yet ) 00 host latches int at the second backend clock after the end bit of current data block from card is received. (this is the default setting) 01 host latches int at the first backend clock after the end bit of current data block from card is received. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 303 of 1535 10 host latches int at the second backend clock after the end bit of current data block from card is received. 11 host latches int at the third backend clock after the end bit of current data block from card is received. cmdsel the register bit is used to determine whether the host should delay 1-t to latch response from card. note that this field is added after mt6268 and MT6516. ( tk6516 not support yet ) 0 host latches response without 1-t delay. 1 host latches response with 1-t delay. crcdis the register bit is used to switch-off the data crc check for sd/mmc read data. note that this field is added after mt6268 and MT6516. ( tk6516 not support yet ) 0 crc check is on. 1 crc check is off. dlt data latch timing. the register is used for sw to select the latch timing on data line. figure 3 illustrates the data line la tch timing. sclk_out is the serial clock output to card. div_clk is the internal clock used for generating divided clock. the number ?1 2 1 2? means the current sclk_out is divided from div_clk by a ratio of 2. data_in is the output data from card, and latched_data(r)/(f) is the rising/falling edge latche d data inside the host (configured by red in msdc_cfg). in this example, sclkf(in msdc_cfg) is set to 8?b0 which means the division ratio is 2, and dlt is set to 1. note that the value of dlt cannot be set as 0 and its value should not exceed the division ratio ( in the example, the division ratio is 2). also note that, the latching time will be one div_clk later than the indicated dlt value and the falling edge is always half div_clk ahead from rising edge. the default value of dlt is set to 8?b2. figure 3 illustration of data line latch timing 2.23.3.2 sd memory card controller register definitions msdc+0020h sd memory card controller configuration register sdc_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dtoc wdod sdio mdlw 8 mdle n sien type r/w r/w r/w r/w r/w r/w reset 00000000 0000 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 304 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsydly blklen type r/w r/w reset 1000 00000000000 the register is used for configuring the ms/sd memory card controller when it is configured as the host of sd memory card. if the controller is configured as the host of memory stick, the contents of the register have no impact on the operation of the controller. note that sdc_cfg[31:16] can be accessed by 16-bit apb bus access. blklen it refers to block length. the register field is used to define the length of one block in unit of byte in a data transaction. the maximal value of block length is 2048 bytes. 000000000000 reserved. 000000000001 block length is 1 byte. 000000000010 block length is 2 bytes. ? 011111111111 block length is 2047 bytes. 100000000000 block length is 2048 bytes. bsydly the register field is only valid for the commands with r1b response. if the command has a response of r1b type, ms/sd controller must monitor the data line 0 for card busy status from the bit time that is two serial clock cycles after the command end bit to check if operations in sd/mmc memory card have finished. the register field is used to expand the time between the command end bit and end of detection period to detect card busy status. if time is up and there is no card busy status on data line 0, then the controller will abandon the detection. 0000 no extend. 0001 extend one more serial clock cycle. 0010 extend two more serial clock cycles. ? 1111 extend fifteen more serial clock cycle. sien serial interface enable. it should be enabled as soon as possible before any command. 0 serial interface for sd/mmc is disabled. 1 serial interface for sd/mmc is enabled. mdlw8 eight data line enable. the register works when mdlen is enabled. the register can be enabled only when multimediacard 4. 0 is applied and detected by software application. 0 4-bit data line is enabled. 1 8-bit data line is enabled. sdio sdio enable. 0 sdio mode is disabled 1 sdio mode is enabled mdlen multiple data line enable. the register can be enabled only when sd memory card is applied and detected by software application. it is the responsibility of the application to program the bit correctly when an multimediacard is applied. if an multimediacard is ap plied and 4-bit data line is enabled, then 4 bits will be output every serial clock. therefore, data integrity will fail. 0 4-bit data line is disabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 305 of 1535 1 4-bit data line is enabled. wdod write data output delay. the period from finish of the response for the initial host write command or the last write data block in a multiple block write operation to the start bit of the next write data block requires at least two serial clock cycles. the register field is used to extend the period (write data output delay) in unit of one serial clock. 0000 no extend. 0001 extend one more serial clock cycle. 0010 extend two more serial clock cycles. ? 1111 extend fifteen more serial clock cycle. dtoc data timeout counter. the period from finish of the initial host read command or the last read data block in a multiple block read operation to the start bit of the next read data block requires at least two serial clock cycles. the counter is used to extend the period (read data access time) in unit of 65,536 serial clock. see the register field description of the register bit rdint for reference. 00000000 extend 65,536 more serial clock cycle. 00000001 extend 65,536x2 more serial clock cycle. 00000010 extend 65,536x3 more serial clock cycle. ? 11111111 extend 65,536x 256 more serial clock cycle. msdc+0024h sd memory card controller command register sdc_cmd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cmdf ail type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name intc stop rw dtype idrt rsptyp brea k cmd type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 00 0 000 0 000000 the register defines a sd memory card command and its attribute. before ms/sd controller issues a transaction onto sd bus, application shall specify other relative setting such as argument for command. after application writes the register, ms/sd controller will issu e the corresponding transaction onto sd serial bus. if the command is go_idle_state, the controller will have serial clock on sd/mmc bus run 128 cycles before issuing the command. cmd sd memory card command. it is totally 6 bits. break abort a pending mmc go_irq_mode command. it is only valid for a pending go_irq_mode command waiting for mmc interrupt response. 0 other fields are valid. 1 break a pending mmc go_irq_mode command in the controller. other fields are invalid. rsptyp the register field defines response type for the command. for commands with r1 and r1b response, the register sdc_csta (not sdc_sta) will update after response token is received. this free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 306 of 1535 register sdc_csta contains the status of the sd /mmc and it will be used as response interrupt sources. note that if cmd7 is used with all 0?s rca then rsptyp must be ?000?. and the command ?go_to_idle? also have rsptyp=?000?. 000 there is no response for the command. for instance, broadcast command without response and go_inactive_state command. 001 the command has r1 response. r1 response token is 48-bit. 010 the command has r2 response. r2 response token is 136-bit. 011 the command has r3 response. even though r3 is 48-bit response, but it does not contain crc checksum. 100 the command has r4 response. r4 response token is 48-bit. (only for mmc) 101 the command has r5 response. r5 response token is 48-bit. (only for mmc) 110 the command has r6 response. r6 response token is 48-bit. 111 the command has r1b response. if the command has a response of r1b type, ms/sd controller must monitor the data line 0 for card busy status from the bit time that is two or four serial clock cycles after the command end bit to check if operations in sd/mmc memory card have finished. there are two cases for detection of card busy status. the first case is that the host stops the data transmission during an active write data transfer. the card will assert busy signal after the stop transmission command end bit followed by four serial clock cycles. the second case is that the card is in idle state or under a scenario of receiving a stop transmission command between data blocks when multiple block write command is in progress. the register bit is valid only when the command has a response token. idrt identification response time. the register bit indicates if the command has a response with n id (that is, 5 serial clock cycles as defined in sd me mory card specification part 1 physical layer specification version 1.0) response time. the register bit is valid only when the command has a response token. thus the register bit must be set to ?1? for cmd2 (all_send_cid) and acmd41 (sd_app_op_cmd). 0 otherwise. 1 the command has a response with n id response time. dtype the register field defines data token type for the command. 00 no data token for the command 01 single block transaction 10 multiple block transaction. that is, the command is a multiple block read or write command. 11 stream operation. it only shall be used when an multimediacard is applied. rw the register bit defines the command is a read command or write command. the register bit is valid only when the command will cause a transaction with data token. 0 the command is a read command. 1 the command is a write command. stop the register bit indicates if the command is a stop transmission command. 0 the command is not a stop transmission command. 1 the command is a stop transmission command. intc the register bit indicates if the command is go_irq_state. if the command is go_irq_state, the period between command token and response token will not be limited. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 307 of 1535 0 the command is not go_irq_state. 1 the command is go_irq_state. msdc+0028h sd memory card controller argument register sdc_arg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name arg [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arg [15:0] type r/w the register contains the argument of the sd/mmc memory card command. msdc+002ch sd memory card controller status register sdc_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wp fedat busy fecm dbus y beda tbusy becm dbus y besd cbus y type r ro ro ro ro ro reset - 0 0 0 0 0 the register contains various status of ms/sd controller as the controller is configured as the host of sd memory card. besdcbusy the register field indicates if ms/sd controller is busy, that is, any transmission is going on cmd or dat line on sd bus. this bit shows backend controller?s sdc busy state. the busy state is sync from card clock domain to bus clock domain. 0 backend ms/sd controller is idle. 1 backend ms/sd controller is busy. becmdbusy the register field indicates if any transmission is going on cmd line on sd bus. this bit shows backend controller?s cmd busy state. the busy state is sync from card clock domain to bus clock domain. 0 backend ms/sdc controller gets the info that no transmission is going on cmd line on sd bus. 1 backend ms/sdc controller gets the info that there exists transmission going on cmd line on sd bus. bedatbusy the register field indicates if any transmission is going on dat line on sd bus. 0 backend ms/sdc controller gets the info that no transmission is going on dat line on sd bus. 1 backend ms/sdc controller gets the info that there exists transmission going on dat line on sd bus. feccmdbusy the register field indicates if any transmission is going on cmd line on sd bus. this bit indicates directly the cmd line at card clock domain. 0 no transmission is going on cmd line on sd bus. 1 there exists transmission going on cmd line on sd bus. fedatbusy the register field indicates if any transmission is going on dat line on sd bus. this bit indicates directly the cmd line at card clock domain. for those commands without data but still involving dat line, the register bit is useless. for example, if an erase command is issued, free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 308 of 1535 then checking if the register bit is ?0? before issuing next command with data would not guarantee that the controller is idle. in this situation, use the register bit besdcbusy. 0 no transmission is going on dat line on sd bus. 1 there exists transmission going on dat line on sd bus. wp it is used to detect the status of write protection switch on sd memory card. the register bit shows the status of write protection switch on sd memory card. there is no default reset value. the pin wp (write protection) is also only useful while the controller is configured for sd memory card. 1 write protection switch on. it means that memory card is desired to be write-protected. 0 write protection switch off. it means that memory card is writable. msdc+0030h sd memory card controller response register 0 sdc_resp0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name resp [31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name resp [15:0] type ro the register contains parts of the last sd/mmc memory card bus response. see description for the register field sdc_resp3. msdc+0034h sd memory card controller response register 1 sdc_resp1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name resp [63:48] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name resp [47:32] type ro the register contains parts of the last sd/mmc memory card bus response. see description for the register field sdc_resp3. msdc+0038h sd memory card controller response register 2 sdc_resp2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name resp [95:80] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name resp [79:64] type ro the register contains parts of the last sd/mmc memory card bus response. see description for the register field sdc_resp3. msdc+003ch sd memory card controller response register 3 sdc_resp3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name resp [127:112] type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 309 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name resp [111:96] type ro the register contains parts of the last sd/mmc memory card bus response. the register fields sdc_resp0, sdc_resp1, sdc_resp2 and sdc_resp3 compose the last sd/mmc memory card bus response. for response of type r2, that is, response of the command all_send_cid, send_csd and send_cid, only bit 127 to 0 of response token is stored in the register field sdc_resp0, sdc_resp1, sdc_resp2 and sdc_resp3. for response of other types, only bit 39 to 8 of response token is stored in the register field sdc_resp0. msdc+0040h sd memory card controller command status register sdc_cmdsta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mmcir q rspc rcer r cmdt o cmdr dy type rc rc rc rc reset 0 0 0 0 the register contains the status of ms/sd controller during command execution and that of ms/sd bus protocol after command execution when ms/sd controller is configured as the host of sd/mmc memory card. the register will also be used as interrupt sources. the register will be cleared when reading the register. meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. cmdrdy for command without response, the register bit will be ?1? once the command completes on sd/mmc bus. for command with response, the register bit will be ?1? whenever the command is issued onto sd/mmc bus and its corresponding response is received without crc error . 0 otherwise. 1 command with/without response finish successfully without crc error. cmdto timeout on cmd detected. a ?1? indicates that ms/sd controller detected a timeout condition while waiting for a response on the cmd line. 0 otherwise. 1 ms/sd controller detected a timeout condition wh ile waiting for a response on the cmd line. rspcrcerr crc error on cmd detected. a ?1? indicates that ms/sd controller detected a crc error after reading a response from the cmd line. 0 otherwise. 1 ms/sd controller detected a crc error after reading a response from the cmd line. mmcirq mmc requests an interrupt. a ?1? indicates that a mmc supporting command class 9 issued an interrupt request. 0 otherwise. 1 a ?1? indicates that a mmc supporting command class 9 issued an interrupt request. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 310 of 1535 msdc+0044h sd memory card controller data status register sdc_datsta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name datc rcer r datt o blkd one type rc rc rc reset 0 0 0 the register contains the status of ms/sd controller during data transfer on dat line(s) when ms/sd controller is configured as the host of sd/mmc memo ry card. the register also will be used as interrupt sources. the register will be cleared when reading the register. meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. blkdone the register bit indicates the status of data block transfer. 0 otherwise. 1 a data block was successfully transferred. datto timeout on dat detected. a ?1? indicates that ms/sd controller detected a timeout condition while waiting for data token on the dat line. 0 otherwise. 1 ms/sd controller detected a timeout condition wh ile waiting for data token on the dat line. datcrcerr crc error on dat detected. a ?1? indicates that ms/sd controller detected a crc error after reading a block of data from the dat line or sd/mmc signaled a crc error after writing a block of data to the dat line. 0 otherwise. 1 ms/sd controller detected a crc error after reading a block of data from the dat line or sd/mmc signaled a crc error after writing a block of data to the dat line. msdc+0048h sd memory card status register sdc_csta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csta [31:16] type rc reset 0000000000000000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csta [15:0] type rc reset 0000000000000000 after commands with r1 and r1b response this register contains the status of the sd/mmc card and it will be used as response interrupt sources. in all register fields, logic high indicates error and logic low indicates no error. the register will be cleared when reading the register. meanwhile, if interrupt is enabled and thus interrupt caused by the register is generated, reading the register will deassert the interrupt. csta31 out_of_range . the command?s argument was out of the allowed range for this card. csta30 address_error . a misaligned address that did not match the block length was used in the command. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 311 of 1535 csta29 block_len_error . the transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. csta28 erase_seq_error . an error in the sequence of erase commands occurred. csta27 erase_param . an invalid selection of write-blocks for erase occurred. csta26 wp_violation . attempt to program a write-protected block. csta25 reserved. return zero. csta24 lock_unlock_failed . set when a sequence or password error has been detected in lock/unlock card command or if there was an attempt to access a locked card. csta23 com_crc_error . the crc check of the previous command failed. csta22 illegal_command . command not legal for the card state. csta21 card_ecc_failed . card internal ecc was applied but failed to correct the data. csta20 cc_error . internal card controller error. csta19 error . a general or an unknown error occurred during the operation. csta18 underrun . the card could not sustain data transfer in stream read mode. csta17 overrun . the card could not sustain data programming in stream write mode. csta16 cid/csd_overwrite . it can be either one of the following errors: 1. the cid register has been already written and cannot be overwritten 2. the read only section of the csd does not match the card. 3. an attempt to reverse the copy (set as original) or permanent wp (unprotected) bits was made. csta[15:4] reserved. return zero. csta3 ake_seq_error . error in the sequence of authentication process csta[2:0] reserved. return zero. msdc+004ch sd memory card irq mask register 0 sdc_irqmask 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irqmask [31:16] type r/w reset 0000000000000000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqmask [15:0] type r/w reset 0000000000000000 the register contains parts of sd memory card interrupt mask register. see the register description of the register sdc_irqmask1 for reference. the register will mask interrupt sources from the register sdc_cmdsta and sdc_datsta. irqmask[15:0] is for sdc_cmdsta and irqmask[31:16] for sdc_datsta. a ?1? in some bit of the register will mask the corresponding interrupt source with the same bit position. for example, if irqmask[0] is ?1? then interrupt source from the register field cmdrdy of the register sdc_ cmdsta will be masked. a ?0? in some bit will not cause interrupt mask on the corresponding interrupt source from the register sdc_cmdsta and sdc_datsta. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 312 of 1535 msdc+0050h sd memory card irq mask register 1 sdc_irqmask 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irqmask [63:48] type r/w reset 0000000000000000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqmask [47:32] type r/w reset 0000000000000000 the register contains parts of sd memory card interrupt mask register. the registers sdc_irqmask1 and sdc_irqmask0 compose the sd memory card interrupt mask register. the register will mask interrupt sources from the register sdc_csta. a ?1? in some bit of the register will mask the corresponding interrupt source with the same bit position. for example, if irqmask[63] is ?1? then interrupt source from the register field out_of_range of the register sdc_ csta will be masked. a ?0? in some bit will not cause interrupt mask on the corresponding interrupt source from the register sdc_ csta. msdc+0054h sdio configuration register sdio_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsbs el intse l inten type r/w r/w r/w reset 0 0 0 the register is used to configure functionality for sdio. inten interrupt enable for sdio. 0 disable 1 enable intsel interrupt signal selection 0 use data line 1 as interrupt signal 1 use data line 5 as interrupt signal dsbsel data block start bit selection. 0 use data line 0 as start bit of data block and other data lines are ignored. 1 start bit of a data block is received only when data line 0-3 all become low. msdc+0058h sdio status register sdio_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 313 of 1535 name sdioi rq type ro reset 0 sdioirq sdio interrupt. the register bit indicates if any interrupt for sdio exists . whenever interrupt for sdio exists, i.e., the register bit will be set to ?1? if interrupt is enabled. 0 no sdio interrupt. 1 sdio card interrupt exists. memory stick controller register definitions msdc+0060h memory stick controller configuration register msc_cfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pmod e pred busycnt sien type r/w r/w r/w r/w reset 0 0 101 0 the register is used for memory stick controller configuration when ms/sd controller is configured as the host of memory stick. sien serial interface enable. it should be enabled as soon as possible before any command. 0 serial interface for memory stick is disabled. 1 serial interface for memory stick is enabled. busycnt rdy timeout setting in unit of serial clock cycle. the register field is set to the maximum busy timeout time (set value x 4 +2) to wait until the rdy signal is output from the card. rdy timeout error detection is not performed when busycnt is set to 0. the initial value is 0x5. that is, busy signal exceeding 5x4+2=22 serial clock cycles causes a rdy timeout error. 000 not detect rdy timeout 001 busy signal exceeding 1x4+2=6 serial clock cycles causes a rdy timeout error. 010 busy signal exceeding 2x4+2=10 serial clock cycles causes a rdy timeout error. ? 111 busy signal exceeding 7x4+2=30 serial clock cycles causes a rdy timeout error. pred parallel mode rising edge data. the register field is only valid in parallel mode, that is, mspro mode. in parallel mode, data must be driven and latched at the fa lling edge of serial clock on ms bus. in order to mitigate hold time issue, the register can be set to ?1? such that write data is driven by msdc at the rising edge of serial clock on ms bus. 0 write data is driven by msdc at the falling edge of serial clock on ms bus. 1 write data is driven by msdc at the rising edge of serial clock on ms bus. pmode memory stick pro mode. 0 use memory stick serial mode. 1 use memory stick parallel mode. msdc+0064h memory stick controller command register msc_cmd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 314 of 1535 name pid datasize type r/w r/w reset 0000 0000000000 the register is used for issuing a transaction onto ms bus. transaction on ms bus is started by writing to the register msc_cmd. the direction of data transfer, that is, read or write transaction, is extracted from the register field pid. 16-bit crc will be transferred for a write transaction even if the register field datasize is programmed as zero under the condition where the register field nocrc in the register msdc_cfg is ?0?. if the register field nocrc in the register msdc_cfg is ?1 ? and the register field datasize is programmed as zero, then writing to the register msc_cmd will not induce transaction on ms bus. the same applies for when the register field rdy in the register msc_sta is ?0?. datasize data size in unit of byte for the current transaction. 0000000000 data size is 0 byte. 0000000001 data size is one byte. 0000000010 data size is two bytes. ? 0111111111 data size is 511 bytes. 1000000000 data size is 512 bytes. pid protocol id. it is used to derive transfer protocol code (tpc). the tpc can be derived by cascading pid and its reverse version. for example, if pid is 0x1, then tpc is 0x1e, that is, 0b0001 cascades 0b1110. in addition, the direction of the bus transaction can be determined from the register bit 15, that is, pid[3]. msdc+0068h memory stick controller auto command register msc_acmd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apid adatasize acen type r/w r/w r/w reset 0111 0000000001 0 the register is used for issuing a transaction onto ms bus automatically after the ms command defined in msc_cmd completed on ms bus. auto command is a function used to automatically execute a command like get_int or read_reg for checking status after set_cmd ends. if auto command is enabled, the command set in the register will be executed once the int signal on ms bus is detected. after auto command is issued onto ms bus, the register bit acen will become disabled automatically. note that if auto command is enabled then the register bit rdy in the register msc_sta caused by the command defined in msc_cmd will be suppressed until auto command completes. note that the register field adatasize cannot be set to zero, or the result will be unpredictable. acen auto command enable. 0 auto command is disabled. 1 auto command is enabled. adatasize data size in unit of byte for auto command. initial value is 0x01. 0000000000 data size is 0 byte. 0000000001 data size is one byte. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 315 of 1535 0000000010 data size is two bytes. ? 0111111111 data size is 511 bytes. 1000000000 data size is 512 bytes. apid auto command protocol id. it is used to derive transfer protocol code (tpc). initial value is gset_int(0x7). msdc+006ch memory stick controller status register msc_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cmdn k breq err ced hsrd y crce r toer sif rdy type r r r r ro ro ro ro ro reset 0 0 0 0 0 0 0 0 1 the register contains various status of memory stick controller, that is, ms/sd controller is configured as memory stick controller. these statuses can be used as interrupt sources. reading the register will not clear it. the register will be cl eared whenever a new co mmand is written to the register msc_cmd. rdy the register bit indicates the status of transaction on ms bus. the register bit will be cleared when writing to the command register msc_cmd. 0 otherwise. 1 a transaction on ms bus is ended. sif the register bit indicates the status of serial interface. if an interrupt is active on ms bus, the register bit will be active. note the difference between the signal rdy and sif. when parallel mode is enabled, the signal sif will be active whenever any of the signal ced, err, breq and cmdnk is active. in order to separate interrupts caused by the signals rdy and sif, the register bit sif will not become active until the register msdc_int is read once. that is, the sequence for detecting the register bit sif by polling is as follows: 1. detect the register bit rdy of the register msc_sta 2. read the register msdc_int 3. detect the register bit sif of the register msc_sta bs bs0 bs1 bs2 bs3 bs0 sdio command execution command finished int irq rdy irq clear sif irq clear 0 otherwise. 1 an interrupt is active on ms bus free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 316 of 1535 toer the register bit indicates if a busy signal timeout error takes place. when timeout error occurs, the signal bs will become logic low ?0?. the register bit will be cleared when writing to the command register msc_cmd. 0 no timeout error. 1 a busy signal timeout error takes place. the register bit rdy will also be active. crcer the register bit indicates if a crc error occurs wh ile receiving read data. the register bit will be cleared when writing to the command register msc_cmd. 0 otherwise. 1 a crc error occurs while receiving read data. the register bit rdy will also be active. hsrdy the register bit indicates the status of handshaking on ms bus. the register bit will be cleared when writing to the command register msc_cmd. 0 otherwise. 1 a memory stick card responds to a tpc by rdy. ced the register bit is only valid when parallel mode is enabled. in fact, it?s value is from dat[0] when serial interface interrupt takes place. see format specification version 2.0 of memory stick standard (memory stick pro) for more details. 0 command does not terminate. 1 command terminates normally or abnormally. err the register bit is only valid when parallel mode is enabled. in fact, it?s value is from dat[1] when serial interface interrupt takes place. see format specification version 2.0 of memory stick standard (memory stick pro) for more details. 0 otherwise. 1 indicate memory access error during memory access command. breq the register bit is only valid when parallel mode is enabled. in fact, it?s value is from dat[2] when serial interface interrupt takes place. see format specification version 2.0 of memory stick standard (memory stick pro) for more details. 0 otherwise. 1 indicate request for data. cmdnk the register bit is only valid when parallel mode is enabled. in fact, it?s value is from dat[3] when serial interface interrupt takes plac e. see format specification version 2.0 of memory stick standard (memory stick pro) for more details. 0 otherwise 1 indicate non-recognized command. 2.23.4 application notes 2.23.4.1 initialization procedures after power on disable power down control for msdc module remember to power on msdc module before starting any operation to it. 2.23.4.2 card detection procedures the pseudo code is as follows: msdc_cfg.prcfg0 = 2?b10 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 317 of 1535 msdc_ps = 2?b11 msdc_cfg.vddpd = 1 if(msdc_ps.pinchg) { // card is inserted . . . } the pseudo code segment perform the following tasks: 1. first pull up cd/dat3 (ins) pin. 2. enable card detection and input pin at the same time. 3. turn on power for memory card. 4. detect insertion of memory card. 2.23.4.3 notes on commands for ms, check if msc_sta.rdy is ?1? before issuing any command. for sd/mmc, if the command desired to be issued involves data line, for example, commands with data transfer or r1b response, check if sdc_sta.sdcbusy is ?0? before issuing. if the command desired to be issued does not involve data line, only chec k if sdc_sta.cmdbusy is ?0? before issuing. 2.23.4.4 notes on data transfer z for sd/mmc, if multiple-block-write command is issued then only issue stop_trans command inter-blocks instead of intra-blocks. z once sw decides to issue stop_trans commands, no more data transfer from or to the controller. 2.23.4.5 notes on frequency change before changing the frequency of serial clock on ms/sd/mmc bus, it is necessary to disable serial interface of the controller. that is, set the register bit sien of the register sdc_cfg to ?0? for sd/mmc controller, and set the register bit sien of the register msc_cfg to ?0? for memory stick controller. serial interface of the controller needs to be enabled again before starting any operation to the memory card. 2.23.4.6 notes on response timeout if a read command doest not receive response, that is, it terminates with a timeout, then register sdc_datsta needs to be cleared by reading it. the register bit ?datto? should be active. however, it may take a while before the register bit becomes active. the alternative is to send the stop_trans command. however, this method will receive response with illegal-command information. also, remember to check if the register bit sdc_sta.cmdbusy is active before issuing the stop_trans command. the procedure is as follows: 1. read command => response time out 2. issue stop_trans command => get response 3. read register sdc_datsta to clear it free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 318 of 1535 2.23.4.7 source or destination address is not word-aligned it is possible that the source address is not word-alig ned when data move from memory to msdc. similarly, destination address may be not word-aligned when data move from msdc to memory. this can be solved by setting dma byte-to-word functionality. 1. dman_con.size=0 2. dman_con.btw=1 3. dman_con.burst=2 (or 4) 4. dman_count=byte number instead of word number 5. fifo threshold setting must be 1 (or 2), depending on dman_con.burst note n=4 ~ 11 2.23.4.8 miscellaneous notes z siemens mmc card: when a write command is issued and followed by a stop_trans command, siemens mmc card will de-assert busy status even though flash programming has not yet finished. software must use ?get status? command to make sure that flash programming finishes. 2.24 nand flash interface figure 21 block diagram of nand flash interface MT6516 provides nand flash interface (for slc & mlc). the nand flash interface support features as follows: z ecc (bch code) acceleration capable of 12 bit error correction. (with ecc engine) z programmable page size and spare size free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 319 of 1535 z programmable fdm data size and protected fdm data size. z word/byte access through apb bus. z ahb for massive data transfer. z latch sensitive interrupt to indicate ready state for read, program, erase operation. z programmable wait states, command/address setup and hold time, read enable hold time, and write enable recovery time. z support 2 chip select for nand flash parts. z support 8/16 bits i/o interface. the nfi and ecc engine (in nfi mode) can automatically generate ecc syndrome bits when programming or reading the device. if the user approves the way it stores the syndrome bits in the spare area for each page, the hw_ecc mode can be used. otherwise, the user can prepare the data (may contains operating system information or ecc syndrome bits) for the spare area with another arrangement. in the former case, the nfi and ecc engine (in nfi mode) can check the syndrome bits when reading from the device. the ecc module features the bch code, which is capable of correcting 4/6/12 bit errors within one sector. 2.24.1 general description 2.24.1.1 input and output interface 2.24.1.1.1 ecc engine signal name direction function auto_fmt_en output nfi automatic append fdm data and encode or decode by hw ecc engine b16en output 8/16 bits i/o data cur_sec_num output read or write sector number as using ahb ecc_str output ecc start trigger for each sector sec_str_addr output start address of ahb for each sector ecc_rdy input ecc data request ecc_valid output ecc data valid ack data[15:0] output data for ecc par_req output parity request to ecc par_rdy input parity ack from ecc parity[15:0] input parity table 40 2.24.1.1.2 nli arbiter and nand flash device signal name direction function egrant input nli bus grant indication eready input nli bus ready indication free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 320 of 1535 eready_nfi output nfi ready indication for nli bus ready ebusreq output nli bus request ndi input nand data input ndo output nand data output ndoe output nana data output enable nrb output nand flash ready/busy nce[1:0] output nand flash chip enable nwr output nand flash write enable nre output nand flash read enable ncle output nand flash command latch enable nale output nand flash address latch enable table 2 2.24.1.1.3 mcu signal name direction function nfi_irq_b output interrupt for mcu table 41 2.24.1.1.4 ahb arbiter signal name direction function write output read or write address output ahb address wdata[31:0] output write data bus rdata[31:0] input input data bus byte_data output byte data or 4-byte data ahb_req output ahb request ahb_ack input ahb ack table 2 2.24.1.1.5 apb signal name direction function paddr[15:0] input 16 lsb of the arm address bus pwrite input write control penable input enable interface psel input transmitter interface select pwdata[31:0] input 32 bits of the arm writer data bus prdata[31:0] output 32 bits of the arm read data bus free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 321 of 1535 table 3 2.24.2 registers memory map 2.24.2.1 registers memory map software responsibility an d controllable functions register address acronym register function nfi +0000h nfi_cnfg nfi configuration nfi +0004h nfi_pagefmt nfi page format control nfi +0008h nfi_con nfi control nfi +000ch nfi_acccon nand flash access control nfi +0010h nfi_intr_en nfi interrupt enable nfi +0014h nfi_intr nfi interrupt status nfi +0020h nfi_cmd nfi command nfi +0030h nfi_addrnob nfi address length nfi +0034h nfi_coladdr nfi column address nfi +0038h nfi_rowaddr nfi row address nfi +0040h nfi_strdata nfi data transfer start trigger nfi +0050h nfi_dataw write data buffer nfi +0054h nfi_datawb write data buffer for byte access nfi +0054h nfi_datar read data buffer nfi +005ch nfi_datarb read data buffer for byte access nfi +0060h nfi_sta nfi status nfi +0064h nfi_fifosta nfi fifo status nfi +0068h nfi_locksta nfi lock status nfi +0070h nfi_addrcntr nand flash page address counter nfi +0080h nfi_straddr ahb start address nfi +0084h nfi_bytelen ahb byte length i/o pin control nfi +0090h nfi_csel nand flash device select nfi +0094h nfi_iocon nfi io control fdm data content free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 322 of 1535 nfi +00a0h nfi_fdm0l nfi least fdm data for sector 0 nfi +00a4h nfi_fdm0m nfi significant fdm data for sector 0 nfi +00a8h nfi_fdm1l nfi least fdm data for sector 1 nfi +00ach nfi_fdm1m nfi significant fdm data for sector 1 nfi +00b0h nfi_fdm2l nfi least fdm data for sector 2 nfi +00b4h nfi_fdm2m nfi significant fdm data for sector 2 nfi +00b8h nfi_fdm3l nfi least fdm data for sector 3 nfi +00bch nfi_fdm3m nfi significant fdm data for sector 3 nfi +00c0h nfi_fdm4l nfi least fdm data for sector 4 nfi +00c4h nfi_fdm4m nfi significant fdm data for sector 4 nfi +00c8h nfi_fdm5l nfi least fdm data for sector 5 nfi +00cch nfi_fdm5m nfi significant fdm data for sector 5 nfi +00d0h nfi_fdm6l nfi least fdm data for sector 6 nfi +00d4h nfi_fdm6m nfi significant fdm data for sector 6 nfi +00d8h nfi_fdm7l nfi least fdm data for sector 7 nfi +00dch nfi_fdm7m nfi significant fdm data for sector 7 flash lock nfi +0100h nfi_lock nfi lock enable nfi +0104h nfi_lockcon nfi lock contorl nfi +0108h nfi_lockanob nfi address format for lock nfi +0110h nfi_lock00add row start address for lock set 00 nfi +0114h nfi_lock00fmt row address format for lock set 00 nfi +0118h nfi_lock01add row start address for lock set 01 nfi +011ch nfi_lock01fmt row address format for lock set 01 nfi +0120h nfi_lock02add row start address for lock set 02 nfi +0124h nfi_lock02fmt row address format for lock set 02 nfi +0128h nfi_lock03add row start address for lock set 03 nfi +012ch nfi_lock03fmt row address format for lock set 03 nfi +0130h nfi_lock04add row start address for lock set 04 nfi +0134h nfi_lock04fmt row address format for lock set 04 nfi +0138h nfi_lock05add row start address for lock set 05 nfi +013ch nfi_lock05fmt row address format for lock set 05 nfi +0140h nfi_lock06add row start address for lock set 06 nfi +0144h nfi_lock06fmt row address format for lock set 06 nfi +0148h nfi_lock07add row start address for lock set 07 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 323 of 1535 nfi +014ch nfi_lock07fmt row address format for lock set 07 nfi +0150h nfi_lock08add row start address for lock set 08 nfi +0154h nfi_lock08fmt row address format for lock set 08 nfi +0158h nfi_lock09add row start address for lock set 09 nfi +015ch nfi_lock09fmt row address format for lock set 09 nfi +0160h nfi_lock10add row start address for lock set 10 nfi +0164h nfi_lock10fmt row address format for lock set 10 nfi +0168h nfi_lock11add row start address for lock set 11 nfi +016ch nfi_lock11fmt row address format for lock set 11 nfi +0170h nfi_lock12add row start address for lock set 12 nfi +0174h nfi_lock12fmt row address format for lock set 12 nfi +0178h nfi_lock13add row start address for lock set 13 nfi +017ch nfi_lock13fmt row address format for lock set 13 nfi +0180h nfi_lock14add row start address for lock set 14 nfi +0184h nfi_lock14fmt row address format for lock set 14 nfi +0188h nfi_lock15add row start address for lock set 15 nfi +018ch nfi_lock15fmt row address format for lock set 15 debug register nfi +0190h nfi_fifodata0 nfi fifo data 0 nfi +0194h nfi_fifodata1 nfi fifo data 1 nfi +0198h nfi_fifodata2 nfi fifo data 2 nfi +019ch nfi_fifodata3 nfi fifo data 3 table 5 registers memory map table 2.24.2.2 register definition nfi +0000h nfi configuration nfi_cnfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name op_mode auto_ fmt_e n hw_e cc_en byte_ rw read _mod e ahb_ mode type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 the register controls the nfi functions. for all enable fields, setting to be logic-1 represents enabled, while 0 represents disabled. ahb_mode this field is used to control the operation mode. 0 mcu mode. all data (include read or write) move by mcu through apb access. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 324 of 1535 1 ahb mode. all data (include read or write) move by hw automation through ahb bus. read_en this field is used to control the activity of read or write transfer. 0 write operation of ahb or mcu. 1 read operation of ahb or mcu. byte_rw enable byte access . the valid bytes read from nfi_datar and nfi_dataw is only dr0 and dw0 if byte_rw is enabled. hw_ecc_en this field is used to enable encoding or decoding operation of hw ecc engine. auto_fmt_en automatic hw ecc encode or decode enable. if enabled, the ecc parity from hw ecc engine and fdm data from register are written automatically to the spare area. if disable, the spare data all comes from mcu or ahb as main area data. auto_fmt_en hw_ecc_en nfi function 0 0 data, fdm, parity all come from mcu or ahb ecc interface turn off 0 1 data, fdm, parity all come from mcu or ahb ecc interface turn on 1 0 data comes from mcu or ahb, fdm comes from register and parity forces 0xff ecc interface turn off 1 1 data comes from mcu or ahb, fdm comes from register and parity comes from ecc engine ecc interface turn on op_mode the field control the operating process flow of fsm for nfi.. 000 idle state. 001 read process. recommend for basic read operation. 010 single read process. recommend for read id and read status. 011 program process. recommend for basic program operation. 100 erase process. recommend for basic erase operation. 101 reset process. recommend for basic reset operation. 110 custom process. recommend for all advance operation. others reserved nfi +0004h nfi page format co ntrol register nfi_pagefmt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fdm_ecc_num fdm_num spare_size dbyte _en page_size type r/w r/w r/w r/w r/w reset 0 0 0 0 0 this register manages the page format of the device. it includes the bus width selection, the page size, the associated address format, and the spare format. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 325 of 1535 page_size page size. the field specifies the size of one page for the device. some most widely used page size are supported. 0 the page size is 512 bytes (including 512 bytes data area and (spare_size*1) bytes spare area). 1 the page size is 2k bytes (including 2048 bytes data area and (spare_size*4) bytes spare area). 2 the page size is 4k bytes (including 4096 bytes data area and (spare_size*8) bytes spare area). 3 reserved. dbyte_en 16 bits i/o bus interface enable. spare_size spare size per 512 bytes main area. 512 byte main area with spare size means one sector. 0 16 bytes. 1 26 bytes. 2 27 bytes. 3 28 bytes. fdm_num the fdm data number for each spare area. the valid number of bytes are from 0 to 8. fdm_ecc_num the number of each fdm data for hw ecc protection. the valid number of bytes ranges are from 0 to 8. nfi +0008h nfi operation co ntrol register nfi_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sec_num bwr brd nob srd nfi_r st fifo_ flus h type r/w r/w r/w w/r wo wo wo reset 0 0 0 0 0 0 0 this is recommended to reset the state machine, data fifo and flush the data fifo before starting a new command nfi_rst reset the state machine, data fifo (0x0000) and fdm data (0xffff) . fifo_flush flush the data fifo. this following register controls the burst mode and the single of the data access. in burst mode, the core supposes there are one or more than one page of data to be accessed. on the contrary, in single mode, the core supposes there are only less than 4 bytes of data to be accessed. srd setting to be logic-1 initializes the one-shot data read operation. it?s mainly used for read id and read status command, which requires no more than 4 read cycles to retrieve data from the device. it used when fifo is empty or after reset nficore nob the field represents the number of bytes to be retrieved from the device in single mode, and the number of bytes per apb transaction in both single and burst mode. if device is 16-bit io, the read bytes number will double 0 read 8 bytes from the device. (16 byte for 16-bit io) 1 read 1 byte from the device. (2 byte for 16-bit io) 2 read 2 bytes from the device. (4 byte for 16-bit io) 3 read 3 bytes from the device. (6 byte for 16-bit io) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 326 of 1535 4 read 4 bytes from the device. (8 byte for 16-bit io) 5 read 5 byte from the device. (10 byte for 16-bit io) 6 read 6 bytes from the device. (12 byte for 16-bit io) 7 read 7 bytes from the device. (14 byte for 16-bit io) brd burst read mode . setting this field to be logic-1 enables the data read operation. the nfi core will issue read cycles to retrieve data from the device when the data fifo is not full or the device is not in the busy state. the nfi core supports consecutive page reading. bwr burst write mode . setting to be logic-1 enables the data burst write operation. sec_num the field represents the sector number to be retrieved from the device or ahb. the valid number ranges from 1 to 8. nfi+000ch nand flash access timi ng control register nfi_acccon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lcd2nand precs c2r type r/w r/w r/w reset f 0f 3f bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w2r wh wst rlt type r/w r/w r/w r/w reset f f f f this is the timing access control register for the nand flash interface. in order to accommodate operations for different system clock frequency ranges from 13mhz to 61.44mhz, wait states and setup/hold time margin can be configured in this register. c2r the field represents the minimum required time from nceb low to nreb low (in step of 2t). w2r the field represents the minimum required time from nweb high to nreb low. it?s in unit of 2t. so the actual time ranges from 2t to 8t in step of 2t. wh write-enable hold-time. the field specifies the hold time of nale, ncle, nceb signals relative to the rising edge of nweb. this field is associated with wst to expand the write cycle time, and is associated with rlt to expand the read cycle time. rlt read latency time the field specifies how many wait states to be inserted to meet the requirement of the read access time for the device. 00 no wait state. 01 1t wait state. 10 2t wait state. 11 3t wait state. wst write wait state the field specifies the wait states to be inserted to meet the requirement of the pulse width of the nweb signal. 00 no wait state. 01 1t wait state. 10 2t wait state. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 327 of 1535 11 3t wait state. precs the field represents the minimum required time for cs pre-pulling down before any access to device (in step of 8t). lcd2nand arbitration wait state the field specifies the wait states to be inserted for the apb arbitrator when bus user changes. notes1 : c2r ? 2*c2r + 1 w2r ? 2*w2r + 3 wh/rlt/wst ? wh/rlt/wst + 1 precs ? 8*precs + 1 when prece>0 precs ? 0 when prece=0 83 "-& 8& 3% 83@dpvoufs 8) $-&"-& 8& 8)@dpvoufs '4. xt xf xdi xdb 8) $-&"-& 8& 8)@dpvoufs '4. xt xf xdi xdb 8) $-&"-& 8& 8)@dpvoufs '4. xt xf xdi xdi xdb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 328 of 1535 notes2 : the nli_arbiter behavior need be taken care. for example, in MT6516 the clock of nli_arbiter is 104mhz, and it will sample all nfi signal, such that the rlt must larger than 0. notes3 : rlt-1(for nli_arbiter with 104mhz) > max(trea, trp) + {nre to pad_nre delay} + max({pad_io to ndi delay}) + {pad_nre to nand input delay} + max({nand data outpu to pad_io delay}) take MT6516 & k9f2g08u0a 3.3v for example: max(trea, trp) = 20ns {nre to pad_nre delay} = 7ns max({pad_io to ndi delay}) = 3.4ns nfi +0010h nfi interrupt enable register nfi_intr_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ahb_ done _en acce ss_lo ck_en busy_ retu rn_en eras e_do ne_en reset _don e_en wr_d one_e n rd_ done _en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 this register controls the activity for the interrupt sources. these enable should be turned on only while sw expects the corresponding interrupt will occur. rd_done_en the single page read completion interrupt enable. wr_done_en the single page write completion interrupt enable. reset_done_en the reset completion interrupt enable. erase_done_en the erase completion interrupt enable. busy_return_en the busy return interrupt enable. access_lock_en the access lock interrupt enable. ahb_done_en the done interrupt enable for ahb mode. nfi +0014h nfi interrupt status register nfi_intr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ahb_ done acce ss_lo ck busy_ retu rn eras e_do ne reset _don e wr_d one rd _don e type rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 the register indicates the status of all the interrupt sources. read this register will clear all interrupts. rd_complete indicates that the single page read operation is completed. wr_complete indicates that the write operation is completed. reset_complete indicates that the reset operation is completed. erase_complete indicates that the erase operation is completed. busy_return indicates that the device state returns from busy by inspecting the r/b# pin. access_lock indicates that the operation is invalid and the address range is locked. ahb_done indicates that the ahb operation is completed. notes : access_lock & ahb_done will be reset when issue nfi_reset. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 329 of 1535 nfi +0020h nfi command register nfi_cmd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cmd type r/w reset 0 this is the command input register. the user should write this register to issue a command. please refer to device datasheet for the command set. before write the command, please check out the settings for register nfi_con . cmd command word. nfi +0030h nfi address length register nfi_addrnob bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name row_addr_nob col_addr_nob type r/w r/w reset 0 0 this register represents the number of bytes corresponding to current command. the each valid number of bytes ranges from 0 to 4. the address format depends on what device to be used and what commands to be applied. the nfi core is made transparent to those different situations except that the user has to define the number of bytes. the user should write the target address to the address register nfi_coladdr and nfi_rowaddr before programming this register. col_addr_nob number of bytes for the column address row_addr_nob number of bytes for the row address notes : when lock_en is turn on, these number will be automatic set to pre-defined value as command is 0x6x or 0x8x. nfi +0034h nfi column address register nfi_coladdr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name col_addr3 col_addr2 type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name col_addr1 col_addr0 type r/w r/w reset 0 0 this defines the 4 bytes of the column address field to be applied to the device. since the device bus width is 1 byte, the nfi core arranges the order of address data to be least significant byte first. the user should put the first address byte in the field addr0 , the second byte in the field addr1 , and so on. col_addrn the n-th column address byte. nfi +0038h nfi row address register nfi_rowaddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row_addr3 row _addr2 type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 330 of 1535 reset 0 0 bit 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 name row _addr1 row _addr0 type r/w r/w reset 0 0 this defines the 4 bytes of the row address field to be applied to the device. since the device bus width is 1 byte, the nfi core arranges the order of address data to be least significant byte first. the user should put the first address byte in the field addr0 , the second byte in the field addr1 , and so on. row_addrn the n-th row address byte. nfi +0040h nfi data transfer star t trigger register nfi_strdata bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str_ data type wo reset 0 this register controls the activity for the interrupt sources. str_data this signal triggers the data transfer for read or write. it only takes effect as custom operation mode nfi +0050h nfi write data buffer nfi_dataw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dw3 dw2 type wo wo reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dw1 dw0 type wo wo reset 0 0 this is the write port of the data fifo. it supports word access. the least significant byte dw0 is to be programmed to the device first, then dw1 , and so on. dw3 write data byte 3. dw2 write data byte 2. dw1 write data byte 1. dw0 write data byte 0. nfi +0054h nfi read data buffer nfi_datar bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dr3 dr2 type ro ro reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dr1 dr0 type ro ro reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 331 of 1535 this is the read port of the data fifo. it supports word access. the least significant byte dr0 is the first byte read from the device, then dr1 , and so on. dr3 read data byte 3. dr2 read data byte 2. dr1 read data byte 1. dr0 read data byte 0. nfi +0060h nfi status nfi_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name nand_fsm nfi_fsm type ro ro reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name read_ empt y busy2 read y busy acce ss_lo ck data w data r addr cmd type ro ro ro ro ro ro ro ro reset 1 0 0 0 0 0 0 0 this register represents the nfi core control status including command mode, address mode, data program and read mode. the user should poll this register for the end of those operations. *the value of busy/nand_busy bit depends on the gpio configuration. if gpio is configured for nand flash application, the reset value should be 0, which represents that nand flash is in idle status. when the nand flash is busy, the value will be 1. busy synchronized busy signal from the nand flash. it?s read-only. this signal is sampled from nfi busy2ready it?s read-only. this signal indicates nand from busy to ready state and it will be reset after nfi_reset or write command/address. notes: device busy duration must larger than 2/nfi_bclk_ck dataw the nfi core is in data write mode. datar the nfi core is in data read mode. addr the nfi core is in address mode. cmd the nfi core is in command mode. access_lock the access range is locked for erase or program . read_empty empty page indication during read operation, include all data, fdm and parity for all sectors nfi_fsm the field represents the state of nfi internal fsm. 0000 idle. 0001 reset. reset command to ready 0010 read busy. 0011 read data. 0100 program busy 0101 program data. input data command to program command 1000 erase busy. erase command to ready 1001 erase data. erase command 1 to erase command 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 332 of 1535 1111 custom mode 1110 custom mode for data access others reserved nand_fsm the field represents the state of nand interface fsm. 00000 idle. idle. 11100 pre_cs. pre cs state. 00101 cmd_wrst. command write set up 00110 cmd_wr. command write enable. 00111 cmd_wrhd. command write hold. 00100 cmd_wrrdy 01001 addr_wrst. address write set up 01010 addr_wr. address write enable 01011 addr_wrhd. address write hold 01000 addr_wrrdy. 01100 ca2dext. command address write extension. 10001 data_rdst. data read set up. 10010 data_rd. data read enable. 10011 data_rdhd. data read hold. 11000 data_wrrdy. 11001 data_wrst. data write set up. 11010 data_wr. data write enable. 11011 data_wrhd. data write hold. others reserved nfi +0064h nfi fifo status nfi_fifosta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wr_f ull wr_e mpty wr_remain rd_fu ll rd_e mpty rd_remain type ro ro ro ro ro ro reset 0 1 0 0 1 0 the register represents the status of the data fifo. the fifo top and bottom pointer of read & write will be reset when issue ?command? to nand flash wr_full data fifo full in burst write mode. wr_empty data fifo empty in burst write mode. rd_full data fifo full in burst read mode. rd_empty data fifo empty in burst read mode. rd_remain data fifo remaining byte number in burst read mode. wr_remain data fifo remaining byte number in burst write mode. nfi +0068h nfi lock status nfi_locksta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 333 of 1535 name acce ss_lo ck15 acces s_loc k14 acce ss_lo ck13 acce ss_lo ck12 acce ss_lo ck11 acce ss_lo ck10 acce ss_lo ck09 acce ss_lo ck08 acce ss_lo ck07 acce ss_lo ck06 acce ss_lo ck05 acce ss_lo ck04 acce ss_lo ck03 acce ss_lo ck02 acce ss_lo ck01 acce ss_l ock0 0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register represents the lock status for each lock range. if any access_lockxx happens, the nfi core will automatic issue a reset (0xff) command to nand device. access_lockn the access command violates the locking range n nfi+0070h nfi page address co unter register nfi_addrcntr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sec_cntr sec_addr type ro ro reset 0 0 the register represents the current read/write address with respect to initial address input. it counts in unit of byte. in page read and page program operation, the address should be the same as that in the state machine in the target device. sec_addr the address count of 512 main data and spare data for each sector. sec_cntr the sector count. nfi+0080h nfi ahb start address register nfi_straddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name str_addr type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str_addr type r/w reset 0 the register represents the start address for ahb to access emi. these memory from the start address is used to put read data from nand or write data to nand in ahb mode str_addr the start address of emi for both read or write in ahb mode. this address must be 4- byte aligned. notes : if start address of any sector data is not 4-byte aligned (especially disable auto_fmt_en and spare size is not 16 bytes), it must be 1-byte access for ahb mode (set byte_rw for 1- byte access) whether nfiecc or auto-correction is used or not. nfi+0084h nfi ahb byte length register nfi_bytelen bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name byte_len type ro reset 0 the register represents the current length for ahb to access emi. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 334 of 1535 byte_len the current length of emi for both read or write in ahb mode. (byte unit) notes : this register is used for polling ahb activity nfi+0090h nfi device select register nfi_csel bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csel type r/w reset 0 the register is used to select the target device. it decides which ceb pin to be functional. this is useful while using the high-density device. csel chip select. the value defaults to 0. 0 device 1 is selected. 1 device 2 is selected. notes : this register is latched as issue cmd nfi+0094h nfi io control register nfi_iocon bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name nld_p d type r/w reset 0 data bus pull down when no use. nld_pd data bus pull down when no use. 0 disable. 1 enable. nfi +00a0h nfi least fdm data fo r sector 0 register nfi_fdm0l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fdm0_3 fdm0_2 type r/w r/w reset ff ff bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fdm0_1 fdm0_0 type r/w r/w reset ff ff this register represents the least fdm data for the sector 0. since the device bus width is 1 byte, the nfi core arranges the order of address data to be least significant byte first. the user should put the first address byte in the field fdm0_0 , the second byte in the field fdm0_1 , and so on. it will be reset to 0xff when issue nfi_reset . fdm0_n the n-th fdm byte data for sector 0. nfi +00a4h nfi most fdm data for sector 0 register nfi_fdm0m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fdm0_7 fdm0_6 type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 335 of 1535 reset ff ff bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fdm0_5 fdm0_4 type r/w r/w reset ff ff this register represents the most fdm data for the sector 0. since the device bus width is 1 byte, the nfi core arranges the order of address data to be least significant byte first. the user should put the first address byte in the field fdm0_4 , the second byte in the field fdm0_7 , and so on. it will be reset to 0xff when issue nfi_reset . fdm0_n the n-th fdm byte data for sector 0. register address register function acronym nfi +00a8h nfi least fdm data for sector 1 nfi_fdm1l nfi +00ach nfi most fdm data for sector 1 nfi_fdm1m nfi +00b0h nfi least fdm data for sector 2 nfi_fdm2l nfi +00b4h nfi most fdm data for sector 2 nfi_fdm2m nfi +00b8h nfi least fdm data for sector 3 nfi_fdm3l nfi +00bch nfi most fdm data for sector 3 nfi_fdm3m nfi +00c0h nfi least fdm data for sector 4 nfi_fdm4l nfi +00c4h nfi most fdm data for sector 4 nfi_fdm4m nfi +00c8h nfi least fdm data for sector 5 nfi_fdm5l nfi +00cch nfi most fdm data for sector 5 nfi_fdm5m nfi +00d0h nfi least fdm data for sector 6 nfi_fdm6l nfi +00d4h nfi most fdm data for sector 6 nfi_fdm6m nfi +00d8h nfi least fdm data for sector 7 nfi_fdm7l nfi +00dch nfi most fdm data for sector 7 nfi_fdm7m table 42 nfi fdm data register table nfi +0100h nfi lock enable register nfi_lock bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lock _on type r/w1 reset 0 this register enable the lock function of nfi . these setting can only be set once after reset chip . lock_on enable the lock checking process for any lock set. 0 disable lock checking process. 1 enable lock checking process. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 336 of 1535 nfi +0104h nfi lock control register nfi_lock bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lock 15_cs lock 15_en lock1 4_cs lock1 4_en lock1 3_cs lock1 3_en lock1 2_cs lock1 2_en lock1 1_cs lock1 1_en lock1 0_cs lock1 0_en lock0 9_cs lock0 9_en lock0 8_cs lock 08_en type r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lock 07_cs lock 07_en lock0 6_cs lock0 6_en lock0 5_cs lock0 5_en lock0 4_cs lock0 4_en lock0 3_cs lock0 3_en lock0 2_cs lock0 2_en lock0 1_cs lock0 1_en lock0 0_cs lock 00_en type r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 r/w1 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register control the lock function of nfi . these setting can only be set once after reset chip . lockn_en enable the lock checking process of lock set n. before it takes effect, the lock_on must be turned on. 0 disable lock range check for set n. 1 enable lock range check for set n. lockn_cs indicate the lock checking process of lock set.n for cs0 or cs1 0 lock range check of set n for cs0. 1 lock range check of set n for cs1. nfi +0108h nfi address format for lock register nfi_lockanob bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prog_radd_nob prog_cadd_nob erase_radd_nob erase_cadd_nob type r/w1 r/w1 r/w1 r/w1 reset 0 0 0 0 this register represents the number of bytes corresponding to erase and program command. the each valid number of bytes ranges from 0 to 4. the address format depends on what device to be used and what commands to be applied. the nfi core will force these setting during some command operation(8x or 6x). these setting can only be set once after reset chip . erase_cadd_nob number of bytes for the column address for erase operation (command is 8?h6x) erase_radd_nob number of bytes for the row address for erase operation (command is 8?h6x) prog_cadd_nob number of bytes for the column address for program operation (command is 8?h8x) prog_radd_nob number of bytes for the row address for program operation (command is 8?h8x) nfi +0110h nfi row start address for lock set00 register nfi_lock00add bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lock00_row3 lock00_row2 type r/w1 r/w1 reset 0 0 bit 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 name lock00_row1 lock00_row0 type r/w1 r/w1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 337 of 1535 reset 0 0 this defines the 4 bytes of the row start address field to be locked range for the device. these setting can only be set once after reset chip . lock00_rown the n-th row start address byte to be locked for lock set 0. nfi +0114h nfi row address format for lock set00 register nfi_lock00fmt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lock00_fmt3 lock00_ fmt 2 type r/w1 r/w1 reset 0 0 bit 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 name lock00_ fmt 1 lock00_ fmt 0 type r/w1 r/w1 reset 0 0 this defines the 4 bytes format of the row address field to be locked range for the device. these setting can only be set once after reset chip. the msb unused range must be set to 0 for lockxxfmt. lock00_fmtn the n-th row address format byte to be locked for lock set 0. notes : the real lock range ? lock0_rown && lock0_fmtn register address register function acronym nfi +0118h nfi row start address for lock set 01 nfi_lock01add nfi +011ch nfi row address format for lock set 01 nfi_lock01fmt nfi +0120h nfi row start address for lock set 02 nfi_lock02add nfi +0124h nfi row address format for lock set 02 nfi_lock02fmt nfi +0128h nfi row start address for lock set 03 nfi_lock03add nfi +012ch nfi row address format for lock set 03 nfi_lock03fmt nfi +0130h nfi row start address for lock set 04 nfi_lock04add nfi +0134h nfi row address format for lock set 04 nfi_lock04fmt nfi +0138h nfi row start address for lock set 05 nfi_lock05add nfi +013ch nfi row address format for lock set 05 nfi_lock05fmt nfi +0140h nfi row start address for lock set 06 nfi_lock06add nfi +0144h nfi row address format for lock set 06 nfi_lock06fmt nfi +0148h nfi row start address for lock set 07 nfi_lock07add nfi +014ch nfi row address format for lock set 07 nfi_lock07fmt nfi +0150h nfi row start address for lock set 08 nfi_lock08add nfi +0154h nfi row address format for lock set 08 nfi_lock08fmt nfi +0158h nfi row start address for lock set 09 nfi_lock09add nfi +015ch nfi row address format for lock set 09 nfi_lock09fmt nfi +0160h nfi row start address for lock set 10 nfi_lock10add free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 338 of 1535 nfi +0164h nfi row address format for lock set 10 nfi_lock10fmt nfi +0168h nfi row start address for lock set 11 nfi_lock11add nfi +016ch nfi row address format for lock set 11 nfi_lock11fmt nfi +0170h nfi row start address for lock set 12 nfi_lock12add nfi +0174h nfi row address format for lock set 12 nfi_lock12fmt nfi +0178h nfi row start address for lock set 13 nfi_lock13add nfi +017ch nfi row address format for lock set 13 nfi_lock13fmt nfi +0180h nfi row start address for lock set 14 nfi_lock14add nfi +0184h nfi row address format for lock set 14 nfi_lock14fmt nfi +0188h nfi row start address for lock set 15 nfi_lock15add nfi +018ch nfi row address format for lock set 15 nfi_lock15fmt table 43 nfi lock range set register table nfi +0190h nfi fifo content data 0 nfi_fifodata0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_data0 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_data0 type ro reset 0 this register represents the content data 0 of fifo. nfi +0194h nfi fifo content data 1 nfi_fifodata1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_data1 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_data1 type ro reset 0 this register represents the content data 1 of fifo. nfi +0198h nfi fifo content data 2 nfi_fifodata2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_data2 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_data2 type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 339 of 1535 this register represents the content data 2 of fifo. nfi +019ch nfi fifo cont ent data 3 nfi_fifodata3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_data3 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_data3 type ro reset 0 this register represents the content data 3 of fifo. 2.24.3 device programming sequence this section lists the program sequences for the nand flash operations. 2.24.3.1 block erase *nfi_con = 0x3; // reset nfi core *nfi_intr_en = 0x8; // enable erase complete interrupt *nfi_cnfg = 0x4000; // erase operation *nfi_cmd = 0x60; // erase first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_cmd = 0xd0; // erase second cycle command // then, wait for the erase complete interrupt. 2.24.3.2 page program *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_fdmxx = all fdm data; // fdm data content *nfi_intr_en = 0x2; // enable write complete interrupt *nfi_cnfg = 0x3340; // program operation *nfi_cmd = 0x80; // page program first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_con = 0x8200; // set burst write mode // after mcu / ahb writing a page of bytes, *nfi_cmd = 0x10; // page program second cycle command free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 340 of 1535 // then, wait for the page pr ogram complete interrupt. 2.24.3.3 page read *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_intr_en = 0x1; // enable read complete *nfi_cnfg = 0x1342; // read operation *nfi_cmd = 0x0; // page read command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_cmd = 0x30; // page read second cycle command *nfi_con = 0x8100; // set burst write mode // then, use mcu / ahb to read a page of bytes, 2.24.3.4 read id / read status *nfi_cmd = 0x70; // read status command *nfi_con = cycle number; // set single word read for n byte while(*nfi_sta == 0); // wait for the command to be programmed status = *nfi_datar; // read the single byte of status 2.24.3.5 reset *nfi_intr_en = 0x4; // enable reset complete *nfi_cmd = 0xff; // reset command // then, wait for the reset complete interrupt. 2.24.3.6 multi block erase *nfi_con = 0x3; // reset nfi core *nfi_intr_en = 0x10; // enable ready busy interrupt *nfi_cnfg = 0x6000; // custom operation *nfi_cmd = 0x60; // erase first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_cmd = 0x60; // erase first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 341 of 1535 *nfi_cmd = 0xd0; // erase second cycle command // then, wait for the ready busy interrupt. 2.24.3.7 multi page with data cache program *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_fdmxx = all fdm data; // fdm data content *nfi_intr_en = 0x10; // enable ready busy interrupt *nfi_cnfg = 0x6340; // custom operation *nfi_cmd = 0x80; // page program first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_con = 0x8200; // set burst write mode *nfi_strdata = 0x1; // start data transfer // after mcu / ahb writing a page of bytes, *nfi_cmd = 0x11; // page program second cycle command // then, wait for the read y busy complete interrupt. *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_fdmxx = all fdm data; // fdm data content *nfi_intr_en = 0x10; // enable ready busy interrupt *nfi_cnfg = 0x6340; // custom operation *nfi_cmd = 0x80; // page program first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_con = 0x8200; // set burst write mode *nfi_strdata = 0x1; // start data transfer // after mcu / ahb writing a page of bytes, *nfi_cmd = 0x15; // page program second cycle command // then, wait for the read y busy complete interrupt. *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_fdmxx = all fdm data; // fdm data content *nfi_intr_en = 0x10; // enable ready busy interrupt *nfi_cnfg = 0x6340; // custom operation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 342 of 1535 *nfi_cmd = 0x80; // page program first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_con = 0x8200; // set burst write mode *nfi_strdata = 0x1; // start data transfer // after mcu / ahb writing a page of bytes, *nfi_cmd = 0x11; // page program second cycle command // then, wait for the read y busy complete interrupt. *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_fdmxx = all fdm data; // fdm data content *nfi_intr_en = 0x10; // enable ready busy interrupt *nfi_cnfg = 0x6340; // custom operation *nfi_cmd = 0x80; // page program first cycle command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_con = 0x8200; // set burst write mode *nfi_strdata = 0x1; // start data transfer // after mcu / ahb writing a page of bytes, *nfi_cmd = 0x10; // page program second cycle command // then, wait for the read y busy complete interrupt. 2.24.3.8 multi page with data cache read *nfi_con = 0x3; // reset nfi core *nfi_pagefmt = page format; // device page format *nfi_intr_en = 0x10; // enable ready busy complete *nfi_cnfg = 0x6342; // custom operation *nfi_cmd = 0x0; // page read command *nfi_coladdr = address; // address *nfi_rowaddr = address; // address *nfi_addrnob = cycle number;// number of page address while(*nfi_sta == 0); // wait for the address to be programmed *nfi_cmd = 0x30; // page read second cycle command // then, wait for the read y busy complete interrupt. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 343 of 1535 intr_status = *nfi_intr; // read the interrupt status *nfi_cmd = 0x31; // page read with data cache command // then, wait for the read y busy complete interrupt. intr_status = *nfi_intr; // read the interrupt status *nfi_con = 0x8100; // set burst write mode *nfi_strdata = 0x1; // start data transfer // then, use mcu / ahb to read a page of bytes, *nfi_con = 0x3; // reset nfi core *nfi_intr_en = 0x10; // enable ready busy complete *nfi_cnfg = 0x6342; // custom operation *nfi_cmd = 0x31; // page read command // then, wait for the read y busy complete interrupt. *nfi_con = 0x8100; // set burst write mode *nfi_strdata = 0x1; // start data transfer // then, use mcu / ahb to read a page of bytes, *nfi_con = 0x3; // reset nfi core *nfi_intr_en = 0x10; // enable ready busy complete *nfi_cnfg = 0x6342; // custom operation *nfi_cmd = 0x3f; // page read command // then, wait for the read y busy complete interrupt. *nfi_con = 0x8100; // set burst write mode *nfi_strdata = 0x1; // start data transfer // then, use mcu / ahb to read a page of bytes, 2.24.4 control and timing 2.24.4.1 timing diagram nre / nwr ecc_en busgnt ecc_req data_ack data figure 22 data interface free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 344 of 1535 data / io auto_ecc_en (encode) fdm_num ecc_fdm_num sec_num data_ack sym_req sym_ack data_str ahb/mcu req ahb addr figure 23 write for encoding data / io auto_ecc_en (decode) fdm_num ecc_fdm_num sec_num data_ack data_req data_str ahb/mcu req ahb addr figure 24 read for decoding free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 345 of 1535 2.24.4.2 finite state machine diagram idle read_busy read_data erase_data erase_busy reset program_data program_busy custom nrnb nrnb erase mode program mode read mode custom mode reset mode nrnb flash lock flash lock read mode rw_data flash lock figure 25 nfi core control free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 346 of 1535 2.24.4.3 device timing control idle cmd_wrst cmd_wr cmd_wrrdy cmd_wrhd ca2dext addr_wrst addr_wr addr_wrrdy addr_wrhd data_rdst data_rd data_rdhd data_wrst data_wr data_wrhd data_wr figure 26 nand flash interface signal timing contorl this section illustrates the timing diagram. the ideal timing for write access is listed as listed in table 44 . parame ter description timing specification timing at 13mhz (wst, wh) = (0,0) timing at 26mhz (wst, wh) = (0,0) timing at 52mhz (wst, wh) = (1,0) t wc1 write cycle time 3t + wst + wh 230.8ns 105.4ns 76.9ns t wc2 write cycle time 2t + wst + wh 153.9ns 76.9ns 57.7ns t ds write data setup time 1t + wst 76.9ns 38.5ns 38.5ns t dh write data hold time 1t + wh 76.9ns 38.5ns 19.2ns t wp write enable time 1t + wst 76.9ns 38.5ns 38.5ns t wh write high time 1t + wh 76.9ns 38.5ns 19.2ns t cls command latch enable setup time 1t 76.9ns 38.5ns 19.2ns t clh command latch enable hold time 1t + wh 76.9ns 38.5ns 19.2ns t als a ddress latch enable setup time 1t 76.9ns 38.5ns 19.2ns t alh a ddress latch enable hold time 1t + wh 76.9ns 38.5ns 19.23ns free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 347 of 1535 f wc write data rate 1 / t wc2 6.5mbytes/s 13mbytes/s 17.3mbytes/s table 44 write access timing wst t cls, t als t clh, t alh t wp t dh hclk ncle nweb nld nceb t ces t ceh t ds nale command t wc1 figure 27 command input cycle (1 wait state). wst t als t alh t wp t dh hclk nale nweb nld t wh oe (internal) nceb t ces t ceh ncle t cls t clh t dh t wh t dh t wp t wp wst wst a0 a1 a2 t wc2 t wc1 figure 28 address input cycle (1 wait state) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 348 of 1535 wst t als t alh t wp t dh hclk nale nweb nld t wh oe (internal) nceb t ces t ceh ncle t cls t clh t dh t wh t dh t wp t wp wst wst d0 d526 d527 t wc2 t wc1 t wc2 figure 29 consecutive data write cycles (1 wait state, 0 hold time extension) wst t als t alh t wp hclk nale nweb nld t wh wh wh oe (internal) nceb t ces t ceh t dh t dh ncle t cls d0 d527 wst t wp t clh t wc2 t wc1 figure 30 consecutive data write cycles (1 wait state, 1 hold time extension) the ideal timing for read access is as listed in table 6 . parame ter description timing specification timing at 13mhz (rlt, wh) = (0,0) timing at 26mhz (rlt, wh) = (1,0) timing at 52mhz (rlt, wh) = (2,0) t rc1 read cycle time 3t + rlt + wh 230.8ns 153.8ns 96.2ns t rc2 read cycle time 2t + rlt + wh 153.9ns 115.4ns 76.9ns t ds read data setup time 1t + rlt 76.9ns 76.9ns 57.7ns t dh read data hold time 1t + wh 76.9ns 38.5ns 19.2ns free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 349 of 1535 t rp read enable time 1t + rlt 76.9ns 76.9ns 57.7ns t rh read high time 1t + wh 76.9ns 38.5ns 19.2ns t cls command latch enable setup time 1t 76.9ns 38.5ns 19.2ns t clh command latch enable hold time 1t + wh 76.9ns 38.5ns 19.2ns t als a ddress latch enable setup time 1t 76.9ns 38.5ns 19.2ns t alh a ddress latch enable hold time 1t + wh 76.9ns 38.5ns 19.2ns f rc write data rate 1 / t rc2 6.5mbytes/s 8.7mbytes/s 13mbytes/s table 45 read access timing rlt t als t clh , t alh t wp hclk nale nreb nld t wh wh wh oe (internal) nceb t ces t ceh t dh t dh ncle t cls d0 d527 rlt figure 31 serial read cycle (1 wait state, 1 hold time extension) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 350 of 1535 rlt t cls t clh t wp t dh hclk ncle nweb nld nceb t ces t ceh t ds nale 70h t als t alh nreb status t whr t rp rlt oe (internal) w2r figure 32 status read cycle (1 wait state) t cls t clh t wp t dh hclk ncle nweb nld nceb t ces t ceh t ds nale 90h t als t alh nreb 01h, 06h t whr t rp oe (internal) t wp 00h t dh t ds figure 33 id and manufacturer read (0 wait state) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 351 of 1535 2.25 nand flash ecc figure 34 block diagram of nand flash ecc. bch codes are usually referred to as (n,k,t) codes, where n is the number of symbols in a code block, k is the number of data symbols and the t is maximum number of correctable symbol errors in a block. the bch codec module is implemented in gf(2 13 ) defined by primitive polynomial x 13 +x 4 +x 3 +x+1. z ecc (bch code) acceleration is capable of 4/6/8/10/12 bits correction in one full or shorten ecc coded block size which is less than 8192 (<8192bits) z support data input in 8/16 bits in nfi mode and 32 bits in ahb mode and works in 104mhz. z support encoder and decoder work separately and automatic error correction. 2.25.1 general description 2.25.1.1 input and output interface 2.25.1.1.1 nfi interface signal directio n width description nfi_str input 1 start to encode or decode in nfi mode. nfi_di_rdy output 1 the signal is high when ecc is ready to receive data. nfi_di input 16 data input port. when nfi_dbyte_en is equal to 0, the valid bits of input data is eight and is filled into the lowest eight bits ([7:0]). the lsb (bit 0) indicates the highest power of input data which will be encoded and decoded first. otherwise, when nfi_dbyte_en is equal to 1, the valid bits of input data is sixteen bits ([15:0]). nfi_di_valid input 1 the signal is high when input data is valid. nfi_str_addr input 32 the memory address indicates the decoding source data address, used only in the decoding processing of nfi mode. nfi_fdm_mod input 1 the signal indicates the fdm data location. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 352 of 1535 e nfi_sec_num input 3 the signal indicates the sector number of input decoding data. nfi_dbyte_en input 1 the signal informs the valid bit of input data, 0 for 8 bits and 1 for16 bits. nfi_par_req input 1 the signal indicates the data has been read and the ecc module will output next data. nfi_lbyte_en input 1 the signal informs the 16 bits of i nput data, only valid in lower location byte. [7:0] nfi_mbyte_en input 1 the signal informs the 16 bits of output data, only valid in higher location byte. [15:8] nfi_par_rdy output 1 the signal asserts when parity output is re ady in nfi_do port. nfi_parity output 16 encoding data output port. valid bit-width is same as input bit-width. table 1 nfi interface 2.25.1.1.2 memory access interface signal direction width description enc_rreq output 1 encoder block read request to ahb arbiter. enc_rack input 1 encoder block read acknowledge signal from ahb arbiter. enc_raddr output 32 encoder block read address to ahb arbiter. enc_rdata input 32 encoder block read data from memory. syn_rreq output 1 syndrome block read request to ahb arbiter. syn_rack input 1 syndrome block read acknowledge signal from ahb arbiter. syn_raddr output 32 syndrome block read address to ahb arbiter. syn_rdata input 32 syndrome block read data from memory. autoc_req output 1 auto-correction block request to ahb arbiter. autoc_ack input 1 auto-correction block acknowledge signal from ahb arbiter. autoc_addr output 32 auto-correction block address to ahb arbiter. autoc_write output 1 auto-correction block write or read indication to ahb arbiter. autoc_wdata output 32 auto-correction block write data from decoder. autoc_rdata input 32 auto-correction block read data from memory. table 2 memory access interface 2.25.1.1.3 apb interface signal direction width description bclk_ck input 1 module clock pclk_ck input 1 apb clock preset_rstb input 1 system reset penable input 1 apb enable psel input 1 apb select of nfiecc free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 353 of 1535 pwrite input 1 apb read or write command paddr [15:0] input 16 apb address of nfiecc pwdata [31:0] input 32 apb write data of nfiecc prdata [31:0] output 32 apb read data of nfiecc table 3 apb interface 2.25.1.1.4 interrupt signal direction width description nfiecc_irq_b output 1 inform encoder or decoder is done. active low signal table 4 interrupt 2.25.2 registers memory map 2.25.2.1 registers memory map software responsibility an d controllable functions register address acronym register function nfiecc +0000h nfiecc_encon encoder control nfiecc +0004h nfiecc_enccnfg encoder configure nfiecc +0008h nfiecc _encdiaddr encoder input data address nfiecc +000ch nfiecc _encidle encoder idle nfiecc +0010h nfiecc_encpar0 encoder parity output bit. nfiecc +0014h nfiecc_encpar1 encoder parity output bit. nfiecc +0018h nfiecc_encpar2 encoder parity output bit. nfiecc +001ch nfiecc_encpar3 encoder parity output bit. nfiecc +0020h nfiecc_encpar4 encoder parity output bit. nfiecc +0024h nfiecc_encsta encoder status report nfiecc +0028h nfiecc_encirqen encoder irq mask. nfiecc +002ch nfiecc_encirqsta encoder irq status report nfiecc +0100h nfiecc_deccon decoder control. nfiecc +0104h nfiecc_deccnfg decoding configuration. nfiecc +0108h nfiecc_decdiaddr decoder input data address nfiecc +010ch nfiecc_decidle decoder start status report nfiecc +0110h nfiecc_decfer decoder stop status report nfiecc +0114h nfiecc_decenum decoder stop status report nfiecc +0118h nfiecc_decdone decoder stop status report nfiecc +011ch nfiecc_decel0 decoder error location 0 report free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 354 of 1535 nfiecc +0120h nfiecc_decel1 decoder error location 1 report nfiecc +0124h nfiecc_decel2 decoder error location 2 report nfiecc +0128h nfiecc_decel3 decoder error location 3 report nfiecc +012ch nfiecc_decel4 decoder error location 4 report nfiecc +0130h nfiecc_decel5 decoder error location 5 report nfiecc +0134h nfiecc_decirqen decoder irq mask. nfiecc +0138h nfiecc_decirqsta decoder irq status report nfiecc +013ch nfiecc_fdmaddr first fdm data register address. nfiecc +0140h nfiecc_decfsm decoder fsm of all stage and sec_num. nfiecc +0144h nfiecc_synsta syndrome status. nfiecc +0148h nfiecc_nfidi nfi input data. nfiecc +014ch nfiecc_syn0 nfi syndrome data. table 5 registers memory map table 2.25.2.2 register definition timing definition z immediate(immd) ? no buffering of the parameter, update any time when the register is accessed. z ts y n ? update when syndrome process is finished of an encoding or decoding processor. z te l ? update when chien search is finished of a decoding processor. z tc o r r ? update when a error correction processor has done. z tdone ? update when a decoding processor has done. nfiecc+0000h nfiecc encoder co ntrol register nfiecc_enccon bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_ en type r/w reset 0 timing immd this register is for encoder control. enc_en indicates the enable in nfi mode and start to work in ahb mode. in ahb mode, parity bits is remained in the par0~par4 regist er field until the enc_en is deasserted to 0. 0 means disable the encode block. 1 means enable the encode block. in ahb mode, the encoder starts to fetch data when the register changes from 0 to 1 . in nfi mode, the register enables the encode block, and then the encoder module waits start signal and data from nfi. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 355 of 1535 nfiecc+0004h nfiecc configur e register nfiecc_enccnfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_ms type r/w reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_nf i_mode enc_tnum type r/w r/w reset 0 0 timing immd immd this register is for nfiecc encoder configuration. enc_tnum indicates the correct capability in one block size. 0 means the nfiecc is capable of correct 4 bits in one block size. 1 means the nfiecc is capable of correct 6 bits in one block size. 2 means the nfiecc is capable of correct 8 bits in one block size. 3 means the nfiecc is capable of correct 10 bits in one block size. 4 means the nfiecc is capable of correct 12 bits in one block size. enc_nfi_mode indicates the data source from access through ahb bus or from nfi. 0 means source data from access through ahb bus. 1 means source data from nfi module. enc_ms indicates the total bit size of message block including main data and control(fdm) data in the nfi mode . the spare_ecc_num parameter in old version has been merged into the message block_size parameter. if the block_size is equal to zero, the nfiecc do nothing. the acceptable coded block size, which includes data and parity bits size, is 1~8191bits. different enc_tnum results in different parity bits, and also results in different maximum message block size. the relationship shows in table 6. t maximum (enc_ms) parity bit number 4 8191-52 =8139 4*13=52 6 8191-78 =8113 6*13=78 8 8191-104 =8087 8*13=104 10 8191-130 =8061 10*13=130 12 8191-156 =8035 12*13=156 table 6 parity bit number and maximum message block size table the figure shows the defined block_size. the area of oblique line is the data that need to protect. the parity block is generated by encoder. the dec_cs in nfiecc_deccnfg should include parity bits, thus the enc_ms and dec_cs has relationship as : dec_cs = enc_ms + t*13 . t indicates the correct capability. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 356 of 1535 figure 2 the relationship of block size in nfi mode. nfiecc+0008h nfiecc encoder di memory address register nfiecc_encdiad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_diaddr type r/w reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_diaddr type r/w reset 0 timing immd the register indicates the data start address of input data to the encoder ahb mode. enc_diaddr indicates the memory address of input data to encoder block in ahb mode. ( 4-byte align ) nfiecc+000ch nfiecc encoder idle status register nfiecc_encidle bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_i dle type r reset 0 timing immd this register is for nfiecc encoder idle status. enc_idle indicates the encode block in idle state and ready for new message block. 0 means the encode block is under working. 1 means the encode block is in idle state and available for new message block. nfiecc+0010h nfiecc parity0 register nfiecc_encpar0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_par0 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_par0 type r reset 0 timing immd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 357 of 1535 the register indicates the highest order of parity bits enc_par0 indicates the highest order of output parity bits and the bit 0 is the highest order of parity bit. the par0~par4 register is remain the last message block parity bits until enc_en is deasserted. the parity bits should append after main data by order of {par0[31:0], par1[31:0], par2[31:0], par3[31:0], par4[31:4], 4?b0}, the redundant bit of parity bit will be padded by 0. nfiecc+0014h nfiecc parity1 register nfiecc_encpar1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_par1 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_par1 type r reset 0 timing immd the register indicates the parity bits enc_par1 indicates the parity bits and the bit 0 is the highest order of parity bit. nfiecc+0018h nfiecc parity2 register nfiecc_encpar2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_par2 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_par2 type r reset 0 timing immd the register indicates the parity bits enc_par2 indicates the parity bits and the bit 0 is the highest order of parity bit. nfiecc+001ch nfiecc parity3 register nfiecc_encpar3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_par3 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_par3 type r reset 0 timing immd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 358 of 1535 the register indicates the parity bits enc_par3 indicates the parity bits and the bit 0 is the highest order of parity bit. nfiecc+0020h nfiecc parity4 register nfiecc_encpar4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name enc_par4 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_par4 type r reset 0 timing immd the register indicates the parity bits enc_par4 indicates the parity bits and the 31 is the highest order of parity bit. nfiecc+0024h nfiecc encoder st atus register nfiecc_encsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count_ms type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count_ps enc_fsm type r r reset 0 0 timing immed immed this register is for nfiecc encoder status for sw polling. enc_fsm indicates encoder finite state machine state.. 6?d0 idle 6?d1 waitin 6?d2 busy 6?d4 parout count_ps indicates the parity bits that have not read out from nfi. count_ms indicates the remaining un-processing message bits. nfiecc+0028h nfiecc encoder irq enable register nfiecc_encirqe n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_i rqen type r/w reset 0 timing immd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 359 of 1535 this register is for software programmer to enable nfiecc irq signals ( ignore in nfi mode ) enc_irqen encoder irq mask: triggered when encoder operation is completed. 0 disable 1 enable nfiecc+002ch nfiecc encoder irq status register nfiecc_encirqs ta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc_i rqst a type rc reset 0 timing immd this register is for software programmer tracking nfiecc irq status. ( ignore in nfi mode ) enc_irqsta indicates interrupt status for encoder processing. 0 no interrupt is generated. 1 an interrupt is pending and waiting for service. active when encoder processing is done. nfiecc+0100h nfiecc decoder co ntrol register nfiecc_deccon bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_ en type r/w reset 0 timing immd this register is for decoder control. dec_en indicates the enable in nfi mode and start to work in ahb mode. in ahb mode, the decode- status fer and error number registers and error location registers will be reset to 0 when dec_en is deasserted. 0 means disable the decode block. 1 means enable the decode block. in ahb mode, the decoder starts to fetch data when the register changes from 0 to 1 . in nfi mode, the register enables the decode block, and then the decoder module waits start signal and data from nfi. nfiecc+0104h nfiecc decoder configure register nfiecc_deccnf g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_e mpty_ en dec_cs type r/w r/w reset 0 0 timing immd immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 360 of 1535 name dec_con dec_n fi_mo de dec_tnum type r/w r/w r/w reset 3 0 0 timing immd immd immd this register is for nfiecc configuration. dec_tnum indicates the correct capability in one block size. 0 means the decoder is capable of correct 4 bits in one block size. 1 means the decoder is capable of correct 6 bits in one block size. 2 means the decoder is capable of correct 8 bits in one block size. 3 means the nfiecc is capable of correct 10 bits in one block size. 4 means the nfiecc is capable of correct 12 bits in one block size. dec_nfi_mode indicates the data source from access ahb bus or from nfi. 0 means input data from access ahb bus. 1 means input data from nfi module. dec_con indicates the bypass configuration in decoding processor. 0 is reserved 1 means only active syndrome calculator for error detecting purpose. ecc reports done and fer status after syndrome calculator is done. 2 means error-correction module is bypassed for being aware of error location purpose. ecc reports done , fer , el and errnum status after chien search is done. 3 means the ecc processor decoded data and auto-correction error data. the data address is signaled by dec_diaddr register in ahb mode and nfi_diaddr in nfi mode. ecc reports done , fer , el and errnum status after error-correction is done. dec_cs indicates the total bit size of coded block including protected data and parity bits . the acceptable coded block size is 1~8191bits. if the coded block size is equal to zero, the decoder does nothing. the detail figure shows in figure 2. dec_empty_en indicates the decoder automatically detects the empty source data and by pass the auto-correction block (data are all equal to 1). (ignore in ahb_mode) 0 means disenable the detection of empty source data. 1 means enable the detection of empty source data. nfiecc+0108h nfiecc decoder di memory address register nfiecc_decdiad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_diaddr type r/w reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_diaddr type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 361 of 1535 timing immd the register indicates the data start address of input data to the decoder ahb mode. dec_diaddr indicates the memory address of input data to the decoder block in ahb mode. (4-byte align) . nfiecc+010ch nfiecc decoder idle status register nfiecc_decidle bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_i dle type r reset 0 timing immd this register indicates the decoder idle status. dec_idle indicates the decode block is in idle state and ready for new coded block. 0 means the decode block is under working. 1 means the decode block is in idle state and available for new coded block. nfiecc+0110h nfiecc deco der found error status register nfiecc_decfer bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fer7 fer6 fer5 fer4 fer3 fer2 fer1 fer0 type r r r r r r r r reset 0 0 0 0 0 0 0 0 timing tsyn tsyn tsyn tsyn tsyn tsyn tsyn tsyn this register is for nfiecc decoder status. fer x indicates the error found or not in the coded block. the fer numbered by nfi sector number in nfi mode, otherwise, in ahb mode, always use the fer0. the signal reset when dec_en is deasserted in both nfi and ahb mode. 0 means there is no error detected in the coded block. 1 means there is(are) error(s) de tected in the coded block. nfiecc+0114h nfiecc decode error number register nfiecc_decenu m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name errnum7 errnum6 errnum5 errnum4 type r r r r reset 0 0 0 0 timing tel tel tel tel bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name errnum3 errnum2 errnum1 errnum0 type r r r r reset 0 0 0 0 timing tel tel tel tel the register indicates the error number of the coded block. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 362 of 1535 errnum x indicates the error numbers of coded block in one start signal. 4?hf means the error is uncorrectable. but ecc only can partially detect uncorrectable error. nfiecc+0118h nfiecc decoder error status register nfiecc_decdon e bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name done7 done 6 done 5 done 4 done 3 done 2 done 1 done 0 type r r r r r r r r reset 0 0 0 0 0 0 0 0 timing tdone tdone tdon e tdone tdon e tdone tdone tdon e this register is for nfiecc decoder done status. done x indicates the decoding procedure is done. 0 means the decode block is under working. 1 means the decode block is finished. for different dec_con and empty_en in nfiecc_deccnfg register, decoder done has different meaning. detail of the definitions show in the table 7. dec_con nfi_mode empty_en memo tdone=tsyn 1 - - syndrome stage detects there is error or not in main data and reports fer. 1 or 2 or 3 - - syndrome detects there is no error in main data, then done will be asserted. 1 or 2 or 3 1 1 when nfi input an empty sector, ecc will automatically stop. tdone=tel 2 - - error location stage is finished and error location and error number is updated. 3 - - when error number found in chien search is over correct capability, ecc will automatically stop. tdone=tcorr 3 - - ecc found error in coded block and finished all correction process. table 7 the ecc done signal asserts timing. nfiecc+011c nfiecc decoder error location0 register nfiecc_decel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el1 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el0 type r reset 0 timing immd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 363 of 1535 the register indicates the error location of the decoding result. dec_el0 indicates the error location 0 of the decoding result. the el remains until the dec_en is deasserted to 0 in both ahb and nfi mode. when the error number is less than 12, error location registers will be filled from dec_el0, and the redundant register fields remain 0. dec_el1 indicates the error location 1 of the decoding result. nfiecc+0120h nfiecc decoder error location1 register nfiecc_decel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el3 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el2 type r reset 0 timing immd the register indicates the error location of the decoding result. dec_el2 indicates the error location 2 of the decoding result. dec_el3 indicates the error location 3 of the decoding result. nfiecc+0124h nfiecc decoder error location2 register nfiecc_decel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el5 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el4 type r reset 0 timing immd the register indicates the error location of the decoding result. dec_el4 indicates the error location 4 of the decoding result. dec_el5 indicates the error location 5 of the decoding result. nfiecc+0128h nfiecc decoder error location3 register nfiecc_decel3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el7 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el6 type r reset 0 timing immd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 364 of 1535 the register indicates the error location of the decoding result. dec_el6 indicates the error location 6 of the decoding result. dec_el7 indicates the error location 7 of the decoding result. nfiecc+012ch nfiecc decoder error location4 register nfiecc_decel4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el9 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el8 type r reset 0 timing immd the register indicates the error location of the decoding result. dec_el8 indicates the error location 8 of the decoding result. dec_el9 indicates the error location 9 of the decoding result. nfiecc+0130h nfiecc decoder error location5 register nfiecc_decel5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_el11 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_el10 type r reset 0 timing immd the register indicates the error location of the decoding result. dec_el10 indicates the error location 8 of the decoding result. dec_el11 indicates the error location 9 of the decoding result. nfiecc+00134h nfiecc decode r irq enable register nfiecc_decirqe n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_i rqen type r/w reset 0 timing immd this register is for software programmer to enable nfiecc irq signals (ignore in nfi mode) dec_irqen decoder irq mask: triggered when decoder operation is completed. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 365 of 1535 0 disable 1 enable nfiecc+0138h nfiecc decoder irq status register nfiecc_decirqs ta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_i rqst a type rc reset 0 timing immd this register is for software programmer tracking nfiecc irq status. (ignore in nfi mode) dec_irqsta indicates interrupt status for decoder processing. 0 no interrupt is generated. 1 an interrupt is pending and waiting for serv ice. active when decoder processing is done. nfiecc+013ch nfiecc fdm register address nfiecc_fdmadd r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fdm_addr type r/w reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fdm_addr type r/w reset 0 timing immd the register indicates the address of fdm data in nfi module. fdm_addr indicates the apb register address of fdm data in nfi module. in nfi mode, nfi_fdm_mode*, and dec_con = 2, ecc will correct ( dec_cs?parity ) location errors. ecc assumes main data is 512 bytes and correct the error location in the first 512 bytes using nfi_str_addr and correct the remained errors using fdm_addr to find fdm data, which is in the nfi module, and will not correct parity data errors. in nfi mode, nfi_fdm_mode is disable , and dec_con = 2, ecc will correct all errors using nfi_str_addr. but, if there is any fdm data is not protected by ecc, ecc would not realize those data and might cause data being polluted. z * : nfi_fmd_mode in nfi module is equal to auto_fmt_en. nfiecc+0140h nfiecc decoder fsm nfiecc_decfsm bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name autoc_fsm chien_fsm type r r free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 366 of 1535 reset 0 0 timing immd immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bma_fsm syn_fsm type r r reset 0 0 timing immd immd the register indicates the finite state machine status of decoder. syn_fsm indicates the status of syndrome stage. 6?d0 idle 6?d1 waitin 6?d2 busy 6?d4 done bma_fsm indicates the status of bma stage. 5?d0 idle 5?d1 busy 5?d2 done chien_fsm indicates the status of chien search stage. 5?d0 idle 5?d1 busy 5?d2 done autoc_fsm indicates the status of auto-correction stage. 5?d0 idle 5?d1 read 5?d2 check 5?d4 write 5?d8 done nfiecc+0144h nfiecc syndrome status register nfiecc_syns ta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name syn_snum dibw nfi_sec_num type 0 r r reset r 0 0 timing immd immd immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name nfi_s tr_se t syn_count_cs type r r reset 0 0 timing immd immd this register is for nfiecc syndrom status. syn_count_cs indicates the remaining un-processing coded block bits. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 367 of 1535 nfi_str_set indicates the nfi_str signal from nfi. nfi_sec_num indicates the sector number from nfi. dibw indicates input bandwidth. syn_snum indicates the sector number recorded by syndrome. nfiecc+0148h nfiecc nfi input da ta register nfiecc_decnfidi bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name nfi_di type 0 reset r timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name nfi_di type 0 reset r timing immd this register is for checking nfi input data. nfi_di indicates the latest 4 byte input data from nfi. nfiecc+014ch nfiecc syndrom register nfiecc_syn0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dec_syn3 type r reset 0 timing immd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_syn1 type r reset 0 timing immd the register indicates the error location of the decoding result. dec_syn1 informs the syndrome 1 from syndrome calculator. dec_syn3 informs the syndrome 3 from syndrome calculator. 2.25.3 timing control flow and programming sequence this section lists the program sequences for ecc operations. caution: for MT6516, nfiecc module is in the ap site of mcusys, thus the address (enc_diaddr and dec_diaddr) should be assigned based on ap site mcu address. 2.25.3.1 encoding in nfi mode caution: before nfi address phase enable and configure ecc. configure memo *nfiecc_enccnfg = 0x10400010; //configure encoder parameter in nfi mode. *nfiecc_enccon = 0x1 ; //enable encoder. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 368 of 1535 while (nfi_str==0x1) ; //nfi_str is happened in nfi address phase. nfi_str is from nfi. 0 = *nfiecc_encidle ; //it indicates the start is triggered and encoder is in busy state. while (*nfiecc_encidle==0x1) ; //wait all message data from nfi. after all data has input idle will be asserted. parity = {*nfiecc_par0,*nfiecc_par1, *nfiecc_par2, *nfiecc_par3, *nfiecc_par4} //if parity is necessary, read out parity from apb register after idle=1. 2.25.3.2 encoding in ahb mode configure memo while (*nfiecc_encidle==1) ; //polling idle signal until encoder is available. *nfiecc_enccnfg = 0x10400010; //configure encoder parameter in nfi mode. *nfiecc_encirqen = 0x1; //if irq is required when en coder is done. *nfiecc_encdiaddr= 0x10000000; //configure data start address. *nfiecc_enccon = 0x1 ; //encoder starts fetching data from encdiaddr. 0 = *nfiecc_encidle ; //it indicates the start is triggered and encoder is in busy state. while (*nfiecc_encidle==0x1) ; //after all data has fetched and encoded, idle will be asserted. parity = {*nfiecc_par0,*nfiecc_par1, *nfiecc_par2, *nfiecc_par3, *nfiecc_par4} // read out parity from apb register after idle=1 and must append parity bits behind the original data for decoding. 2.25.3.3 decodi ng in nfi mode caution: before nfi address phase enable and configure ecc. caution: when nfi auto_fmt_en=0 , ecc will correct all errors (include parity bits) found in chien search. be careful of those fdm data that was not protected by ecc. those data would not be realized by ecc module and might be polluted by ecc module. caution: ecc correct limitation is error_limit = error_correct_capability. if the error number(data error number + parity error number) is bigger than the error_limit, ecc might decode error. configure memo *nfiecc_deccnfg = 0x90743010; //configure decoder parameter in nfi mode. *nfiecc_fdmaddr = 0x800320a0; //configure fdm0 apb address in nfi mode into fdmaddr. (nfi_base_addr+fdm0_offset_addr) *nfiecc_deccon = 0x1 ; //enable decoder. for i = 1:8 // 8 is equal to nfi read sector number. while (nfi_str==0x1) ; //nfi_str is happened in nfi address phase. nfi_str is from nfi. 0 = *nfiecc_decidle ; //it indicates the start is triggered and decoder is in busy state. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 369 of 1535 while (*nfiecc_decidle==0x1) ; //wait all message data from nfi. after all data has input idle will be asserted and fer will be reported. end for while (*nfiecc_decdone==0xff) //decoder and correction processor is done. err_num = *nfiecc_decenum //read error number for i = 0 : (err_num-1) //read error location errorlocation[i] = *nfiecc_el0+2i; end for *nfiecc_deccon = 0x0 //disable decoder. 2.25.3.4 decoding in ahb mode configure memo while (*nfiecc_decidle==1) ; //polling id le signal until decoder is available. *nfiecc_deccnfg = 0x90743010; //configure decoder parameter in nfi mode. *nfiecc_decirqen = 0x1; //if irq is required when en coder is done. *nfiecc_decdiaddr= 0x10000000; //configure data start address. *nfiecc_deccon = 0x1 ; //encoder starts to fetch data from decdiaddr. 0 = *nfiecc_decidle ; //it indicates the start is triggered and decoder is in busy state. while (*nfiecc_decdone==0x1) //decoder and correction processor is done. err_num = *nfiecc_decenum //read error number for i = 0 : (err_num-1) //read error location errorlocation[i] = *nfiecc_el0+2i; end for *nfiecc_deccon = 0x0 //disable decoder. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 370 of 1535 figure 2 the recommendation flow of using decoder. 2.25.4 control and timing 2.25.4.1 interface with nfi the next waveform shows the data transfer protocol between ecc and nfi. the nfi_str is only triggered at beginning of a message block, and the input data is always companying with a nfi_divalid signal. ecc outputs nfi_di_rdy signal to indicate that the next data is ready for receiving. 52m_clk 104m_clk nfi_str nfi_divalid nfi_di di0 di1 nfi_di_rdy fifo di0 di1 fifo_valid_set fifo_valid_clr fifo_valid fsm idle waitin busy wai t figure 3 timing diagram of data input from nfi besides data input from nfi, in encoding processing, ecc also needs to output parity data to nfi. when the total message blocks have been input, the nfi_par_rdy will pull high to indicate parity data is ready and ignore remaining input data. figure 4 shows the timing diagram of output parity bits. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 371 of 1535 52m_clk 104m_clk nfi_divalid nfi_di di517 nfi_di_rdy fsm waitin parout nfi_par_rdy nfi_parity par0 par1 nfi_par_req busy figure 4 timing diagram of parity output from ecc 2.25.4.2 interface with ahb the sector describes the data transfer protocol between ecc and ahb arbiter. idle register indicates the module is ready or not to accept a new message block, thus ahb devices who want to use the encoder have to wait the register goes to high. when the enc_en or dec_en is asserted (from low to high), the module starts to capture the data from diaddr. after all the data has been captured, ecc automatically goes back to idle state and pull up the idle signal. the pari ty bits will be stored in pa0~pa4. 52m_clk 104m_clk enc_en / dec_en ahb_str ahb_req ahb_raddr diaddr diaddr+4 ahb_ack ahb_rdata fsm idle waitin busy waitin figure 5 timing diagram of data input from ahb 2.25.4.3 encoding architecture and fsm the 2t consecutive powers of beta generates the generator polynomial which is defined as table below t weight generator polynomial in hex 4 22 14523043ab86ab 6 44 7f3cc930e4f0dcb9b17d 8 49 115f914e07b0c138741c5c4fb23 10 65 65a4ef0d287c9a24ede0ab0157e0b37c9 12 68 1e4873256115a56784a6940a4c6e6d7e1205e051 table 8 generator polynomial in different correct capabilities. the encoding architecture is shown below: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 372 of 1535 figure 6 encoder architecture. the next figure shows the finite state machine of encoder. encoder jumps from idle state to waitin state, after nfi_str signal is asserted. in waitin state, when enc_di_valid is asserted, encoder jumps to processing state which is busy state. the encoder goes to parout state when all bits of message block are received. figure 7 fsm of encoder in nfi mod 2.25.4.4 decoding architecture and fsm the decoding module can be easily separated to four main blocks, syndrome calculation block, bma block, chien search block and auto error-correction block. the protocol between the blocks is used req and ack and shows in next figure. after syndromes have been calculated, the el_req sent to bma state and bma state asserts el_ack if bma is in idle state. the same way is in ac_req and ac_ack. figure 8 fsm of decoder the bma architecture is shown in next figure. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 373 of 1535 } ~ 0 { 2 t j s j i ? + j j d ) ( ) 1 ( x i ? ) ( x p i d figure 9 bma block architecture. 2.26 reset generation unit (aprgu) figure 35 shows the reset scheme used in MT6516. MT6516 provides three kinds of resets: hardware reset, watchdog reset, and software reset. MT6516 provides 8 resets which can be manual reset by individual rgu_usrstx control registers. mux r12 figure 35 reset scheme used in MT6516 2.26.1 general description 2.26.1.1 hardware reset this reset is input through the sysrst# pin, which is driven low during power-on. the hardware reset has a global effect on the chip: all digital and analog circuits are initialized, except the real time clock module. the initial states of the MT6516 sub-blocks are as follows: ? all analog circuits are turned off. ? all plls are turned off and bypassed. the 13 mhz system clock is the default time base. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 374 of 1535 2.26.1.2 watchdog reset a watchdog reset is generated when the watchdog timer expires: the mcu software failed to re-program the timer counter in time. this situation is typically induced by abnormal software execution, which can be aborted by a hardwired watchdog reset. hardware blocks that are affected by the watchdog reset are: ? mcu subsystem, ? dsp subsystem, and ? external components (trigged by software). 2.26.1.3 software resets software resets are local reset signals that initialize specific hardware components. for example, if hardware failures are detected, the mcu or dsp software may write to software reset trigger registers to reset those specific hardware modules to their initial states. the following modules have software resets. ? dsp core ? dsp coprocessors 2.26.2 register definitions rgu +0000h watchdog timer control register wdt_mode bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] wdtin _dis auto- resta rt irq exten extpo l enab le type wo r/w r/w r/w r/w r/w r/w reset 1* 0 0 0 0 reset_ en enable enables the watchdog timer. the reset value depends on the icore: reset_en = icore. 0 disables the watchdog timer. 1 enables the watchdog timer. extpol defines the polarity of the external watchdog pin. 0 active low. 1 active high. exten specifies whether or not to generate an external watchdog reset signal. 0 the watchdog does not generate an external watchdog reset signal. 1 if the watchdog counter reaches zero, an external watchdog signal is generated. irq issues an interrupt instead of a watchdog timer reset. for debug purposes, rgu issues an interrupt to the mcu instead of resetting the system. 0 disable. 1 enable. auto-restart restarts the watchdog timer counter with the value of wdt_length while task id is written into software debug unit. 0 disable. the counter restarts by writing key into the wdt_restart register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 375 of 1535 1 enable. the counter restarts by writing key into the wdt_restart register or by writing task id into the soft ware debug unit. wdtin_dis if the other domain?s watchdog affects the current domain?s watchdog. *wdtin_dis is only reset by external reset pin. 0 this domain will be reset when other domain?s watchdog is timeout. 1 this domain doesn?t care about the other domain?s watchdog. key write access is allowed if key=0x22. rgu +0004h watchdog time-out interval register wdt_length bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name timeout[10:0] key[4:0] type r/w wo reset 111_1111_1111b key write access is allowed if key=08h. timeout the counter is restarted with {timeout [10:0], 1_1111_1111b}. thus the watchdog timer time- out period is a multiple of 512*t 32k =15.6ms. rgu +0008h watchdog timer restart register wdt_restart bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[15:0] type wo reset key restart the counter if key=1971h. rgu +000ch watchdog timer status register wdt_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wdt sw_w dt type ro ro reset 0 0 wdt indicates the cause of the watchdog reset. 0 reset not due to watchdog timer. 1 reset because the watchdog timer time-out period expired. sw_wdt indicates if the watchdog was triggered by software. 0 reset not due to software-triggered watchdog timer. 1 reset due to software-t riggered watchdog timer. note : a system reset does not affect this register. this bit is cleared when the wdt_mode register is written. rgu +0010h cpu peripheral software reset register sw_periph_r stn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 376 of 1535 reset rgu +0014h dsp software reset register sw_dsp_rstn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type reset rgu +0018h watchdog timer reset signal duration register wdt_rstinte rval bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name length[ 11:0] type r/w reset fffh length this register indicates the reset duration when watchdog timer times out. however, if the wdt_mode register irq bit is set to 1, an interrupt is issued instead of a reset. rgu+001ch watchdog timer softw are reset register wdt_swrst bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[15:0] type wo reset software-triggered watchdog timer reset. if the register content matches the key, a watchdog reset is issued. however, if the wdt_mode register irq bit is set to 1, an interrupt is issued instead of a reset. key 1209h rgu+0020h rgu user-defined reset 0 rgu_usrst0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst0[7:0] type wo r/w reset 0 rgu+0024h rgu user-defined reset 1 rgu_usrst1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst1[7:0] type wo r/w reset 0 rgu+0028h rgu user-defined reset 2 rgu_usrst2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst2[7:0] type wo r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 377 of 1535 rgu+002ch rgu user-defined reset 3 rgu_usrst3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst3[7:0] type wo r/w reset 0 rgu+0030h rgu user-defined reset 4 rgu_usrst4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst4[7:0] type wo r/w reset 0 rgu+0034h rgu user-defined reset 5 rgu_usrst5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst5[7:0] type wo r/w reset 0 rgu+0038h rgu user-defined reset 6 rgu_usrst6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst6[7:0] type wo r/w reset 0 rgu+003ch rgu user-defined reset 7 rgu_usrst7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst7[7:0] type wo r/w reset 0 key write access is allowed if key=0xbb. user-defined resets can trigger individual resets derived by mcu. when the usrstx[7:0] is non-zero, the corresponding reset will be pull low. (all resets generated by rgu are active low). usrstx[6:0] is for a period of reset. it will decrease 1 per system clock when usrstx[6:0] is not equal to 0. it is suitable for a predefined period reset. usrstx[7] is for a manual reset. it is only changed by mcu and suitable for a manual reset fully controlled by mcu. generally speaking, usrstx[6:0] and usrstx[7 ] will not be non-zero at the same time. example1: 0 th cycle: usrstx = 0x0. resetx=1. mcu writes usrstx = 0x3. 1 st cycle: usrstx = 0x3. resetx=0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 378 of 1535 2 nd cycle: usrstx = 0x2. resetx=0. 3 rd cycle: usrstx = 0x1. resetx=0. 4 th cycle: usrstx = 0x0. resetx=1. example2: 0 th cycle: usrstx = 0x0. resetx=1. mcu writes usrstx = 0x80. 1 st cycle: usrstx = 0x80. resetx=0. 2 nd cycle: usrstx = 0x80. resetx=0. ~ n th cycle: usrstx = 0x80. resetx=0. mcu writes usrstx = 0x0. n+1 th cycle: usrstx = 0x0. resetx=1. 2.27 sim interface the MT6516 contains two dedicated smart card interfaces to allow the mcu to access the two sim cards. each interface can operate via 5 terminals. as shown is the figure 1, simvcc, simsel, simrst, simclk and simdata are for one sim interface, while sim2vcc, sim2sel, sim2rst, sim2clk and sim2data are for the other one. 1st sim card vcc1 data1 clk1 rst1 level shift simvcc simsel simrst simclk simdata 1st sim i/f apb bridge simirq 13mhz 2nd sim card vcc2 data2 clk2 rst2 sim2vcc sim2sel sim2rst sim2clk sim2data 2nd sim i/f irq ctrl sim2irq 13mhz figure 36 sim interface block diagram free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 379 of 1535 the functions of the two sim interfaces are identical; ther efore, only first sim interface will be described in this document. the simvcc is used to control the external voltage supply to the sim card and simsel determines the regulated smart card supply voltage. simrst is used as the sim card reset signal. besides, simdata and simclk are used for data exchange purpose. basically, the sim interface acts as a half duplex asynchronous communication port and its data format is composed of ten consecutive bits: a start bit in state low, eight information bits, and a tenth bit used for parity checking. the data format can be divided into two modes as follows: direct convention mode (odd=sdir=sinv=0) sb d0 d1 d2 d3 d4 d5 d6 d7 pb sb : start bit (in state low) dx : data byte (lsb is first and logic level one is in state high) pb : even parity check bit inverse convention mode (odd=sdir=sinv=1) sb n7 n6 n5 n4 n3 n2 n1 n0 pb sb : start bit (in state low) nx : data byte (msb is first and logic level one is in state low) pb : odd parity check bit if the receiver gets a wrong parity bit, it will respon d by pulling the simdata low to inform the transmitter and the transmitter will retransmit the character. when the receiver is a sim card, the error response starts 0.5 bits after the pb and it may last for 1~2 bit periods. when the receiver is the sim interface, the error response starts 0.5 bits after the pb and lasts for 1.5 bit period. when the sim interface is the transmitter, it will take totally 14 bits guard period whether the error response appears. if the receiver shows the error response, the sim interface will retransmit the previous character again else it will transmit the next character. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 380 of 1535 figure 37 sim interface timing diagram 2.27.1 register definitions for mcu to control two sim card interface, all registers are duplicated to two copies but with different base address. in the following, n = ? ? is for 1 st sim card interface, while n=2 is for 2 nd sim card interface. for example, address sim+0000h is mapped to sim_sim_cont register, while address sim2+0000h is mapped to sim2_sim_cont register. simn+0000h sim module control register simn_sim_cont bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrst csto p simon type w r/w r/w reset 0 0 0 simon sim card power-up/power-down control 0 an 1-to-0 change will start the card deactivation sequence 1 a 0-to-1 change will start the card activation sequence cstop enable clock stop mode. together with cpol in sim_conf register, it determines the polarity of the simclk in this mode. 0 enable the simclk output. 1 disable the simclk output wrst sim card warm reset control simn+0004h sim module configuration register simn_sim_conf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 381 of 1535 name hfen t0en t1en tout simse l odd sdir sinv cpol txac k rxac k type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 rxack sim card reception error handshake control 0 disable character receipt handshaking 1 enable character receipt handshaking txack sim card transmission error handshake control 0 disable character transmission handshaking 1 enable character transmission handshaking cpol simclk polarity control in clock stop mode 0 make simclk stop in low level 1 make simclk stop in high level sinv data invert mode 0 not invert the transmitted and received data, data logic one is in high state 1 invert the transmitted and received data, data logic one is in low state sdir data transfer direction 0 lsb is transmitted and received first 1 msb is transmitted and received first odd select odd or even parity 0 even parity 1 odd parity simsel sim card supply voltage select 0 simsel pin is set to low level, 1.8v 1 simsel pin is set to high level, 3v tout sim work waiting time counter control 0 disable time-out counter 1 enable time-out counter t1en t=1 protocol controller control 0 disable t=1 protocol controller 1 enable t=1 protocol controller t0en t=0 protocol controller control 0 disable t=0 protocol controller 1 enable t=0 protocol controller hfen hardware flow control 0 disable hardware flow control 1 enable hardware flow control simn +0008h sim baud rate register simn_sim_brr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name etu[8:0] simclk[1:0] type r/w r/w reset 372d 01 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 382 of 1535 simclk set simclk frequency 00 13/2 mhz 01 13/4 mhz 10 13/8 mhz 11 13/12 mhz etu determines the duration of elementary time unit in unit of simclk simn +0010h sim interrupt enable register simn_sim_irqen bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edce rr t1end rxer r t0end simof f atrer r txer r tout ovru n rxtid e txtid e type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 for all these bits 0 interrupt is disabled 1 interrupt is enabled simn +0014h sim module status register simn_sim_sts bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edce rr t1end rxer r t0end simof f atrer r txer r tout ovru n rxtid e txtid e type r/c r/c r/c r/c r/c r/c r/c r/c r/c r r reset ? ? ? ? ? ? ? ? ? ? ? txtide the interrupt occurs when number of transmitted data in the fifo is less than transmitted tide. rxtide the interrupt occurs when number of received data in the fifo is less than received tide. ovrun transmit/receive fifo overflow interrupt occurred tout between characters timeout interrupt occurred txerr character transmission error interrupt occurred atrerr atr start time-out interrupt occurred simoff card deactivation complete interrupt occurred t0end data transfer handled by t=0 contro ller completed interrupt occurred rxerr character reception error interrupt occurred t1end data transfer handled by t=1 controller completed interrupt occurred edcerr t=1 controller crc error occurred simn +0020h sim retry limit register simn_sim_retry bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txretry rxretry type r/w r/w reset 3h 3h rxretry specify the maximum numbers of receive retries that are allowed when parity error has occurred. txretry specify the maximum numbers of transmit retries that are allowed when parity error has occurred. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 383 of 1535 simn +0024h sim fifo tide mark register simn_sim_tide bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txtide[3:0] rxtide[3:0] type r/w r/w reset 0h 0h rxtide trigger point of rxtide interrupt txtide trigger point of txtide interrupt simn +0030h data register used as tx/rx data register simn_sim_data bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[7:0] type r/w reset ? data eight data digits. these correspond to the character being read or written simn +0034h sim fifo count register simn_sim_count bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count[4:0] type r/w reset 0h count the number of characters in the sim fifo when read, and flushes when written. simn +0040h sim activation time register simn_sim_atime bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name atime[15:0] type r/w reset afc7h atime the register defines the duration, in sim clock cycles, of the time taken for each of the three stages of the card activation process, from simon transits to high to turn on vcc, from turn on vcc to pull data high and then from pull data high to turn on clk. simn +0044h sim deactivation ti me register simn_sim_dtime bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dtime[11:0] type r/w reset 3e7h dtime the register defines the duration, in 13mhz clock cycles, of the time taken for each of the three stages of the card deactivation sequence, from pull rst low to turn of clk, from turn off clk to pull data low, from pull data low to turn off to turn off vcc. simn +0048h character to character wa iting time register simn_sim_wtime bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wtime[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 384 of 1535 reset 983h wtime maximum interval between the leading edge of two consecutive characters in 4 etu unit simn +004ch block to block guar d time register simn_sim_gtime bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gtime type r/w reset 10d gtime minimum interval between the leading edge of two consecutive characters sent in opposite directions in etu unit simn +0050h block to error signal time register simn_sim_etime bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name etime type r/w reset 15d etime the register defines the interval, in 1/16 etu unit, between the end of transmitted parity bit and time to check parity error signal sent from sim card. simn +0060h sim command header register: ins simn_sim_ins bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name insd simins[7:0] type r/w r/w reset 0h 0h simins this field should be identical to the ins instruction code. when w riting to this register, the t=0 controller will be activated and data transfer will be initiated. insd [description for this register field] 0 t=0 controller receives data from the sim card 1 t=0 controller sends data to the sim card simn +0064h sim command header register: p3 simn_sim_p3 (icc_len) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name simp3[8:0] type r/w reset 0h simp3 this field should be identical to the p3 instruction code. it should be written prior to the sim_ins register. while the data transfer is going on, this field shows the no. of the remaining data to be sent or to be received simn +0068h sim procedure byte register: sw1 simn_sim_sw1 (icc_len) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name simsw1[7:0] type r free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 385 of 1535 reset 0h simsw1 this field holds the last received procedure byte for debug purpose. when the t0end interrupt occurred, it keeps the sw1 procedure byte. simn +006ch sim procedure byte register: sw2 simn_sim_sw2 (icc_edc) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name simsw2[7:0] type r reset 0h simsw2 this field holds the sw2 procedure byte 2.27.2 sim card insertion and removal the detection of physical connection to the sim card and card removal is done by the external interrupt controller or by gpio. 2.27.3 card activation and deactivation the card activation and deactivation sequence both are controlled by h/w. the mcu initiates the activation sequence by writing a ?1? to bit 0 of the sim_con register, and then the interface performs the following activation sequence: z assert simrst low z set simvcc at high level and simdata in reception mode z enable simclk clock z de-assert simrst high (required if it be longs to active low reset sim card) the final step in a typical card session is contact deactivation in order that the card is not electrically damaged. the deactivation sequence is initiated by writing a ?0? to bit 0 of the sim_cont register, and then the interface performs the following deactivation sequence: z assert simrst low z set scimclk at low level z set simdata at low level z set simvcc at low level 2.27.4 answer to reset sequence after card activation, a reset operation results in an answe r from the card consisting of the initial character ts, followed by at most 32 characters. the initial character ts provides a bit synchronization sequence and defines the conventions to interpret data bytes in all subsequent characters. on reception of the first character, ts, mcu should read this character, establish the respective required convention and reprogram the related registers. these processes should be completed prior to the completion of reception of the next character. and then, the remainder of the atr sequence is received, read via the sim_data in the selected convention and interpreted by the s/w. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 386 of 1535 the timing requirement and procedures for atr sequence are handled by h/w and shall meet the requirement of iso 7816-3 as shown in figure 38 . figure 38 answer to reset sequence time value comment t1 > 400 simclk simclk start to atr appear t2 < 200 simclk simclk start to simdata in reception mode t3 > 40000 simclk simclk start to simrst high t4 ? simvcc high to simclk start t5 ? simrst low to simclk stop t6 ? simclk stop to simdata low t7 ? simdata low to simvcc low table 46 answer to reset sequence time-out condition 2.27.5 sim data transfer two transfer modes are provided, either in software controlled byte by byte fashion or in a block fashion using t=0 controller and dma controller. in both modes, the time-out counter could be enabled to monitor the elapsed time between two consecutive bytes. 1.1.1.1. byte transfer mode this mode is used during atr and pps procedure. in this mode, the sim interface only ensures error free character transmission and reception. receiving character upon detection of the start-bit sent by sim card, the interface transforms into reception mode and the following bits are shifted into an internal register. if no parity error is detected or character-receive handshaking is disabled, the received-character is written into the sim fifo and the sim_count register is increased by one. otherwise, the simdata line is held low at 0.5 etu after detecting the parity error for 1.5 etus, and the character is re-received. if a character fails to be received correctly for the rxretry times, the receive-handshaking is aborted and the last-received character is written into the sim fifo, the sim_count is increased by one and the rxerr interrupt is generated free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 387 of 1535 when the number of characters held in the receive fifo exceeds the level defined in the sim_tide register, a rxtide interrupt is generated. the number of characters held in the sim fifo can be determined by reading the sim_count register and writing to this register will flush the sim fifo. sending character characters that are to be sent to the card are first written into the sim fifo and then automatically transmitted to the card at timed intervals. if character-transmit handshaking is enabled, the simdata line is sampled at 1 etu after the parity bit. if the card indicates that it did not receive the character correctly, the character is retransmitted a maximum of txretry times before a txerr interrupt is generated and the transmission is aborted. otherwise, the succeeding byte in the sim fifo is transmitted. if a character fails to be transmitted and a txerr interrupt is generated, the interface needs to be reset by flushing the sim fifo before any subsequent transmit or receive operation. when the number of characters held in the sim fifo falls below the level defined in the sim_tide register, a txtide interrupt is generated. the number of characters held in the sim fifo can be determined by reading the sim_count register and writing to this register will flush the sim fifo. 1.1.1.2. block transfer mode basically, the sim interface is designed to work in conjunction with the t=0 protocol controller and the dma controller during non-atr and non-pps phase, though it is still possible for software to service the data transfer manually like in byte transfer mode if necessary and thus the t=0 protocol should be controlled by software. the t=0 controller is accessed via four registers representing the instruction header bytes ins and p3, and the procedure bytes sw1 and sw2. these registers are: sim_ins, sim_p3 sim_sw1, sim_sw2 during characters transfer, sim_p3 holds the number of characters to be sent or to be received and sim_sw1 holds the last received procedure byte including null, ack, nack and sw1 for debug purpose. data receive instruction data receive instructions receive data from the sim card. it is instantiated as the following procedure. 1. enable the t=0 protocol controller by setti ng the t0en bit to 1 in sim_conf register 2. program the sim_tide register to 0x0000 (txtide = 0, rxtide = 0) 3. program the sim_irqen to 0x019c (enable rxe rr, txerr, t0end, tout and ovrun interrupts) 4. write cla, ins, p1, p2 and p3 into sim fifo 5. program the dma controller : dma n _msbsrc and dma n _lsbsrc : address of sim_data register dma n _msbdst and dma n _lsbdst : memory address reserved to store the received characters dma n _count : identical to p3 or 256 (if p3 == 0) dma n _con : 0x0078 6. write p3 into sim_p3 register and then ins into sim_ins register (data transfer is initiated now) 7. enable the time-out counter by setting the tout bit to 1 in sim_conf register 8. start the dma controller by writing 0x8000 into the dma n _start register to upon completion of the data receive instruction, t0 end interrupt will be genera ted and then the time-out counter should be disabled by setting the tout bit back to 0 in sim_conf register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 388 of 1535 if error occurs during data transfer (rxerr, txerr, ovrun or tout interrupt is generated), the sim card should be deactivated first and then activated prior subsequent operations. data send instruction data send instructions send data to the sim card. it is instantiated as the following procedure. 1. enable the t=0 protocol controller by sett ing the t0en bit to 1 in sim_conf register 2. program the sim_tide register to 0x0100 (txtide = 1, rxtide = 0) 3. program the sim_irqen to 0x019c (enable rxe rr, txerr, t0end, tout and ovrun interrupts) 4. write cla, ins, p1, p2 and p3 into sim fifo 5. program the dma controller : dma n _msbsrc and dma n _lsbsrc : memory address reserved to store the transmitted characters dma n _msbdst and dma n _lsbdst : address of sim_data register dma n _count : identical to p3 dma n _con : 0x0074 6. write p3 into sim_p3 register and then (0x0100 | ins) into sim_ins register (data transfer is initiated now) 7. enable the time-out counter by setting the tout bit to 1 in sim_conf register 8. start the dma controller by writing 0x8000 into the dma n _start register upon completion of the data send instruction, t0end interrupt will be generated and then the time-out counter should be disabled by setting the tout bit back to 0 in sim_conf register. if error occurs during data transfer (rxerr, txerr, ovrun or tout interrupt is generated), the sim card should be deactivated first and then activated prior subsequent operations. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 389 of 1535 2.28 slow clocking unit for ap side clock_off vcxo_off gmmcu_ck gmdsp_ck clock_off vcxo_off gamcu_ck gaarm_ck gadsp_ck gusb_ck gtv_ck pwm1/2_ck msdc_fec_ck gadsp_ck gemi_lead_ck srclkena gemi_1x_ck figure 39 the block diagram of the slow clocking unit the slow clocking unit is provided to maintain the synchronization to a 32khz crystal oscillator while the 13mhz reference clock is switched off. as shown in figure 39, this unit is composed of pause unit, and clock management unit. the pause unit is used to initiate and terminate the pause mode procedure and it also works as a coarse time-base during the pause period. the clock management unit is used to control the system clock while switching between the normal mode and the pause mode. srclkena is used to turn on/off the clock squarer, dsp pll and off-chip tcvcxo. clock_off signal is used for gating the main mcu and dsp clock, and vcxo_off is used as the acknowledgement signal of the clock_off request. 2.28.1 register definitions apslp +0218h slow clocking unit control register ap_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pause_star t type w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 390 of 1535 reset 0 pause_start initiate the pause mode procedure at the next timer wrap position. in order for safe arm9 and bus power-down, cp15 instruction must be executed before triggering pause_start apslp +021ch slow clocking unit status register ap_sta bit 15 14 13 12 11 10 9 8 name pause_abo rt type r.c bit 7 6 5 4 3 2 1 0 name settle_cpl pause_cpl pause_int pause_rqst type r.c r.c r.c r.c pause_rqst pause mode procedure is requested pause_int asynchronous wake up from pause mode pause_cpl pause period is completed settle_cpl settling period is completed pause_abort pause mode is aborted because of the reception of interrupt prior to entering pause mode apslp +022ch slow clocking unit configuration register ap_cnf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2a p_cci f lowb at tp gpt msdc rtc eint kp sm spar e type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 1 1 sm enable interrupt generation upon completion of pause mode procedure kp enable asynchronous wake-up from pause mode by key press eint enable asynchronous wake-up from pause mode by external interrupt rtc enable asynchronous wake-up from pause mode by real time clock interrupt msdc enable asynchronous wake-up from pause mode by memory card insertion interrupt gpt enable asynchronous wake-up from pause mode by general-purpose timer interrupt tp enable asynchronous wake-up from pause mode by touch panel interrupt lowbat enable asynchronous wake-up from pause mode by low-battery measurement from auxadc md2ap_ccif enable asynchronous wake-up from pause mode by ccif interface coming from md side apslp +0228h turn on pause-complete function ap_wake_pll _setting bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name witho ut_pa use_c pl free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 391 of 1535 type r/w reset 0 without_pause_cpl turn on pause-complete function for ap sleep-controller 1 turn off pause-complete, the ap sleep-controller keeps sleeping until one of the permitted interrupt sources of ap_cnf asserts 0 turn on pause-complete, the ap sleep-controller automatically wake-up according to ap_pause_m and ap_pause_l, at most the ap sleep-controller can sleep by 16ms. after the counter expired, the controller wake-up and enters the settling stage, defined by ap_clk_settle. address type width reset value name description +0200h r/w [2:0] ? ap_pause_m msb of pause duration, in unit of 32khz +0204h r/w [15:0] ? ap_pause_l 16 lsb of pause duration, in unit of 32khz +0208h r/w [13:0] ? ap_clk_settle off-chip vcxo settling duration, in unit of 32khz +020ch r [2:0] ? ap_final_pause_m msb of final pause count +0210h r [15:0] ? ap_final_pause_l 16 lsb of final pause count +0218h w [1:0] 0x0000 ap_con sm control register +021ch r [8:4,1:0] 0x0000 ap_sta sm status register +022ch r/w [7:0] 0x0003 ap_cnf sm configuration register +0230h r [7:0] 0x0000 rtccount_m msb of rtc count +0234h r [15:0] 0x0000 rtccount_l 16 lsb of rtc count +0238h r/w [15:0] 0x8020 wake_apll_settin g only bit 14 is valid. used to indicate whether the controller wakes up by itself 2.29 uart 2.29.1 general description the baseband chipset houses three uarts. the uarts provide full duplex serial communication channels between baseband chipset and external devices. the uart has m16c450 and m16550a modes of operation, which are compatible with a range of standard software drivers. the extensions have been designed to be broadly software compatible with 16550a variants, but certain areas offer no consensus. in common with the m16550a, the uart supports word lengths from five to eight bits , an optional parity bit and one or two stop bits, and is fully programmable by an 8-bit cpu interface. a 16-bit programmable baud rate generator and an 8-bit scratch register are included, together with separate transmit and receive fifos. eight modem control lines and a diagnostic loop-back mode are provided. the uart also includes two dma handshake lines, used to indicate when the fifos are ready to transfer data to the cpu. interrupts can be generated from any of the 10 sources. note: the uart has been designed so that all internal operations are synchronized by the clk signal. this synchronization results in minor timing differences between the uart and the industry standard 16550a free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 392 of 1535 device, which means that the core is not clock for clock identical to the original device. after a hardware reset, the uart is in m16c450 mode. its fifos can be enabled and the uart can then enter m16550a mode. the uart adds further functionality beyond m16550a mode. each of the extended functions can be selected individually under software control. the uart provides more powerful enhancements than the industry-standard 16550: z hardware flow control. this feature is very useful when the isr latency is ha rd to predict and control in the embedded applications. the mcu is relieved of having to fetch the received data within a fixed amount of time. z output of an ir-compatible electrical pulse with a width 3/16 of that of a regular bit period. note: in order to enable any of the enhancements, the enhanced mode bit, efr[4], must be set. if efr[4] is not set, ier[7:5], fcr[5:4], iir[5:4] and mcr[7:6] cannot be written. the enhanced mode bit ensures that the uart is backward compatible with software that has been written for 16c450 and 16550a devices. figure 40 shows the block diagram of the uart device. apb bus i/f baud rate generator tx fifo tx machine rx fifo modem control rx machine modem outputs modem inputs apb bus clock divisor uart_tx_data uart_rx_data baud figure 40 block diagram of uart 2.29.2 register definitions n = 1, 2, 3; for uart1, uart2 and uart3 respectively. uartn+0000h rx buffer register uartn_rbr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rbr[7:0] type ro rbr rx buffer register. read-only register. the received data can be read by accessing this register. modified when lcr[7] = 0. uartn+0000h tx holding register uartn_thr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thr[7:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 393 of 1535 type wo thr tx holding register. write-only register. the data to be transmitted is written to this register, and then sent to the pc via serial communication. modified when lcr[7] = 0. uartn+0004h interrupt enable register uartn_ier bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ctsi rtsi xoffi x edssi elsi etbei erbfi type r/w reset 0 ier by storing a ?1? to a specific bit position, the interrupt associated with that bit is enabled. otherwise, the interrupt is disabled. ier[3:0] are modified when lcr[7] = 0. ier[7:4] are modified when lcr[7] = 0 & efr[4] = 1. ctsi masks an interrupt that is generated when a rising edge is detected on the cts modem control line. note : this interrupt is only enabled when hardware flow control is enabled. 0 unmask an interrupt that is generated when a rising edge is detected on the cts modem control line. 1 mask an interrupt that is generated when a rising edge is detected on the cts modem control line. rtsi masks an interrupt that is generated when a rising edge is detected on the rts modem control line. note : this interrupt is only enabled when hardware flow control is enabled. 0 unmask an interrupt that is generated when a rising edge is detected on the rts modem control line. 1 mask an interrupt that is generated when a rising edge is detected on the rts modem control line. xoffi masks an interrupt that is generated when an xoff character is received. note : this interrupt is only enabled when software flow control is enabled. 0 unmask an interrupt that is generat ed when an xoff character is received. 1 mask an interrupt that is generated when an xoff character is received. edssi when set ("1"), an interrupt is generated if ddcd, teri, ddsr or dcts (msr[4:1]) becomes set. 0 no interrupt is generated if ddcd, teri, ddsr or dcts (msr[4:1]) becomes set. 1 an interrupt is generated if ddcd, teri, ddsr or dcts (msr[4:1]) becomes set. elsi when set ("1"), an interrupt is generated if bi, fe, pe or oe (lsr[4:1]) becomes set. 0 no interrupt is generated if bi, fe, pe or oe (lsr[4:1]) becomes set. 1 an interrupt is generated if bi, fe, pe or oe (lsr[4:1]) becomes set. etbei when set ("1"), an interrupt is generated if the tx holding register is empty or the contents of the tx fifo have been reduced to its trigger level. 0 no interrupt is generated if the tx holding register is empty or the contents of the tx fifo have been reduced to its trigger level. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 394 of 1535 1 an interrupt is generated if the tx holding register is empty or the contents of the tx fifo have been reduced to its trigger level erbfi when set ("1"), an interrupt is generated if the rx buffer contains data. 0 no interrupt is generated if the rx buffer contains data. 1 an interrupt is generated if the rx buffer contains data. uartn+0008h interrupt identifi cation register uartn_iir bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifoe id4 id3 id2 id1 id0 nint type ro reset 0 0 0 0 0 0 0 1 iir identify if there are pending interrupts; id4 and id3 are presented only when efr[4] = 1. the following table gives the iir[5:0] codes as sociated with the possible interrupts: iir[5:0] priority level interrupt source 000001 - no interrupt pending 000110 1 line status interrupt bi, fe, pe or oe set in lsr 000100 2 rx data received rx data received or rx trigger level reached. 001100 2 rx data timeout timeout on character in rx fifo. 000010 3 tx holding register empty tx holding register empty or tx fifo trigger level reached. 000000 4 modem status change ddcd, teri, ddsr or dcts set in msr 010000 5 software flow control xoff character received 100000 6 hardware flow control cts or rts rising edge table 47 the iir[5:0] codes associated with the possible interrupts line status interrupt: a rx line status interrupt (iir[5:0`] == 000110b) is generated if elsi (ier[2]) is set and any of bi, fe, pe or oe (lsr[4:1]) becomes set. the interrupt is cleared by reading the line status register. rx data received interrupt: a rx received interrupt (ier[5:0] == 000100b) is generated if efrbi (ier[0]) is set and either rx data is placed in the rx buffer register or the rx trigger level is reached. the interrupt is cleared by reading the rx buffer register or the rx fifo (if enabled). rx data timeout interrupt: when virtual fifo mode is disabled, rx data timeout interrupt is generated if all of the following apply: 1. fifo contains at least one character; 2. the most recent character was received longer than four character periods ago (including all start, parity and stop bits); 3. the most recent cpu read of the fifo was longer than four character periods ago. the timeout timer is restarted on receipt of a new byte from the rx shift register, or on a cpu read from the rx fifo. the rx data timeout interrupt is enabled by setting efrbi (ier[0]) to 1, and is cleared by reading rx fifo. when virtual fifo mode is enabled, rx data timeout interrupt is generated if all of the following apply: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 395 of 1535 1. fifo is empty; 2. the most recent character was received longer than four character periods ago (including all start, parity and stop bits); 3. the most recent cpu read of the fifo was longer than four character periods ago. the timeout timer is restarted on receipt of a new byte from the rx shift register. rx holding register empty interrupt: a tx holding register empty interrupt (iir[5:0] = 000010b) is generated if etrbi (ier[1]) is set and either the tx holding register or, if fifos are enabled, the tx fifo becomes empty. the interrupt is cleared by writing to the tx holding register or tx fifo if fifo enabled. modem status change interrupt: a modem status change interrupt (iir[5:0] = 000000b) is generated if edssi (ier[3]) is set and either ddcd, teri, ddsr or dcts (msr[3:0]) becomes set. the interrupt is cleared by reading the modem status register. software flow control interrupt: a software flow control interrupt (iir[5:0] = 010000b) is generated if software flow control is enabled and xoffi (ier[5]) becomes set, indicating that an xoff character has been received. the interrupt is cleared by reading the interrupt identification register. hardware flow control interrupt: a hardware flow control interrupt (ier[5:0] = 100000b) is generated if hardware flow control is enabled and either rtsi (ier[6]) or ctsi (ier[7]) becomes set indicating that a rising edge has been detected on either the rts/cts modem control line. the interrupt is cleared by reading the interrupt identification register. uartn+0008h fifo control register uartn_fcr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rftl1 rftl0 tftl1 tftl0 dma1 clrt clrr fifoe type wo fcr fcr is used to control the trigger levels of the fifos, or flush the fifos. fcr[7:6] is modified when lcr != bfh fcr[5:4] is modified when lcr != bfh & efr[4] = 1 fcr[4:0] is modified when lcr != bfh fcr[7:6] rx fifo trigger threshold 0 1 1 6 2 12 3 rxtrig fcr[5:4] tx fifo trigger threshold 0 1 1 4 2 8 3 14 (fifosize - 2) dma1 this bit determines the dma mode, which the txrdy and rxrdy pins support. txrdy and rxrdy act to support single-byte transfers between the uart and memory (dma mode 0) or multiple byte transfers (dma mode1). note that this bit has no effect unless the fifoe bit is set as well free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 396 of 1535 0 the device operates in dma mode 0. 1 the device operates in dma mode 1. txrdy ? mode0: goes active (low) when the tx fifo or the tx holding register is empty. becomes inactive when a byte is written to the transmit channel. txrdy ? mode1: goes active (low) when there are no characters in the tx fifo. becomes inactive when the tx fifo is full. rxrdy ? mode0: becomes active (low) when at least one character is in the rx fifo or the rx buffer register is full. becomes inactive when there are no more characters in the rx fifo or rx buffer register. rxrdy ? mode1: becomes active (low) when the rx fifo trigger level is reached or an rx fifo character timeout occurs. goes inactive when the rx fifo is empty. clrt clear transmit fifo. this bit is self-clearing. 0 leave tx fifo intact. 1 clear all the bytes in the tx fifo. clrr clear receive fifo. this bit is self-clearing. 0 leave rx fifo intact. 1 clear all the bytes in the rx fifo. fifoe fifo enabled. this bit must be set to 1 for any of the other bits in the registers to have any effect. 0 disable both the rx and tx fifos. 1 enable both the rx and tx fifos. uartn+000ch line control register uartn_lcr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dlab sb sp eps pen stb wls1 wls0 type r/w reset 0 0 0 0 0 0 0 0 lcr line control register. determines charac teristics of serial communication signals. modified when lcr[7] = 0. dlab divisor latch access bit. 0 the rx and tx registers are read/written at address 0 and the ier register is read/written at address 4. 1 the divisor latch ls is read/written at address 0 and the divisor latch ms is read/written at address 4. sb set break 0 no effect 1 sout signal is forced into the ?0? state. sp stick parity 0 no effect. 1 the parity bit is forced into a defined state, depending on the states of eps and pen: if eps=1 & pen=1, the parity bit is set and checked = 0. if eps=0 & pen=1, the parity bit is set and checked = 1. eps even parity select free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 397 of 1535 0 when eps=0, an odd number of ones is sent and checked. 1 when eps=1, an even number of ones is sent and checked. pen parity enable 0 the parity is neither transmitted nor checked. 1 the parity is transmitted and checked. stb number of stop bits 0 one stop bit is always added. 1 two stop bits are added after each character is sent; unless the character length is 5 when 1 stop bit is added. wls1, 0 word length select. 0 5 bits 1 6 bits 2 7 bits 3 8 bits uartn+0010h modem contro l register uartn_mcr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xoff statu s ir enabl e x loop out2 out1 rts dtr type r/w reset 0 0 0 0 0 0 0 0 mcr modem control register. control interface signals of the uart. mcr[4:0] are modified when lcr[7] = 0, mcr[7:6] are modified when lcr[7] = 0 & efr[4] = 1. xoff status this is a read-only bit. 0 when an xon character is received. 1 when an xoff character is received. loop loop-back control bit. 0 no loop-back is enabled. 1 loop-back mode is enabled. out2 controls the state of the output nout2, even in loop mode. 0 nout2=1. 1 nout2=0. out1 controls the state of the output nout1, even in loop mode. 0 nout1=1. 1 nout1=0. rts controls the state of the output nrts, even in loop mode. 0 nrts=1. 1 nrts=0. dtr control the state of the output ndtr, even in loop mode. 0 ndtr=1. 1 ndtr=0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 398 of 1535 uartn+0014h line status register uartn_lsr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifoe rr temt thre bi fe pe oe dr type r/w reset 0 1 1 0 0 0 0 0 lsr line status register. modified when lcr[7] = 0. fifoerr rx fifo error indicator. 0 no pe, fe, bi set in the rx fifo. 1 set to 1 when there is at least one pe, fe or bi in the rx fifo. temt tx holding register (or tx fifo) and the tx shift register are empty. 0 empty conditions below are not met. 1 if fifos are enabled, the bit is set whenever the tx fifo and the tx shift register are empty. if fifos are disabled, the bit is set whenever tx holding register and tx shift register are empty. thre indicates if there is room for tx holding regist er or tx fifo is reduced to its trigger level. 0 reset whenever the contents of the tx fifo are more than its trigger level (fifos are enabled), or whenever tx holding register is not empty(fifos are disabled). 1 set whenever the contents of the tx fifo are reduced to its trigger level (fifos are enabled), or whenever tx holding register is empty and ready to accept new data (fifos are disabled). bi break interrupt. 0 reset by the cpu reading this register 1 if the fifos are disabled, this bit is set whenever the sin is held in the 0 state for more than one transmission time (start bit + data bits + parity + stop bits). if the fifos are enabled, this error is associated with a corresponding character in the fifo and is flagged when this byte is at the top of the fi fo. when a break occurs, only one zero character is loaded into the fifo: the next character transfer is enabled when sin goes into the marking state and receives the next valid start bit. fe framing error. 0 reset by the cpu reading this register 1 if the fifos are disabled, this bit is set if the rece ived data did not have a valid stop bit. if the fifos are enabled, the state of this bit is revealed when the byte it refers to is the next to be read. pe parity error 0 reset by the cpu reading this register 1 if the fifos are disabled, this bit is set if the received data did not have a valid parity bit. if the fifos are enabled, the state of this bit is revealed when the referred byte is the next to be read. oe overrun error. 0 reset by the cpu reading this register. 1 if the fifos are disabled, this bit is set if the rx buffer was not read by the cpu before new data from the rx shift register overwrote the previous contents. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 399 of 1535 if the fifos are enabled, an overrun error occurs when the rx fifo is full and the rx shift register becomes full. oe is set as soon as this happens. the character in the shift register is then overwritten, but not transferred to the fifo. dr data ready. 0 cleared by the cpu reading the rx buffer or by reading all the fifo bytes. 1 set by the rx buffer becoming full or by a byte being transferred into the fifo. uartn+0018h modem status register uartn_msr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dcd ri dsr cts ddcd teri ddsr dcts type r/w r/w r/w r/w r/w r/w r/w r/w reset input input input input 0 0 0 0 note: after a reset, d4-d7 are inputs. a modem status interrupt can be cleared by writing ?0? or set by writing ?1? to this register. d0-d3 can be written to. modified when lcr[7] = 0. msr modem status register dcd data carry detect. when loop = "0", this value is the complement of the ndcd input signal. when loop = "1", this value is equa l to the out2 bit in the modem control register. ri ring indicator. when loop = "0", this value is the complement of the nri input signal. when loop = "1", this value is equa l to the out1 bit in the modem control register. dsr data set ready when loop = "0", this value is the complement of the ndsr input signal. when loop = "1", this value is eq ual to the dtr bit in the modem control register. cts clear to send. when loop = "0", this value is the complement of the ncts input signal. when loop = "1", this value is eq ual to the rts bit in the modem control register. ddcd delta data carry detect. 0 the state of dcd has not changed since the modem status register was last read 1 set if the state of dcd has changed since the modem status register was last read. teri trailing edge ring indicator 0 the nri input does not change since this register was last read. 1 set if the nri input changes from ?0? to ?1? since this register was last read. ddsr delta data set ready 0 cleared if the state of dsr has not changed since this register was last read. 1 set if the state of dsr has changed since this register was last read. dcts delta clear to send 0 cleared if the state of cts has not changed since this register was last read. 1 set if the state of cts has changed since this register was last read. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 400 of 1535 uartn+001ch scratch register uartn_scr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name scr[7:0] type r/w a general purpose read/write register. after reset, its value is un-defined. modified when lcr[7] = 0. uartn+0000h divisor latch (ls) uartn_dll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dll[7:0] type r/w reset 1 uartn+0004h divisor latch (ms) uartn_dlm bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dlm[7:0] type r/w reset 0 note: dll & dlm can only be updated if dlab is set (?1?).. note too that division by 1 generates a baud signal that is constantly high. modified when lcr[7] = 1. the table below shows the divisor needed to generate a given baud rate from clk inputs of 6.5, 13, 26 mhz and 52 mhz. the effective clock enable generated is 16 x the required baud rate. baud 6.5mhz 13mhz 26mhz 52mhz 110 3693 7386 14773 29545 300 1354 2708 5417 10833 1200 338 677 1354 2708 2400 169 338 677 1354 4800 85 169 339 677 9600 42 85 169 339 19200 21 42 85 169 38400 11 21 42 85 57600 7 14 28 56 115200 * 6 14 28 table 48 divisor needed to generate a given baud rate uartn+0008h enhanced feat ure register uartn_efr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto cts auto rts d5 enab le -e sw flow cont[3:0] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 401 of 1535 *note: only when lcr=bf?h auto cts enables hardware transmission flow control 0 disabled. 1 enabled. auto rts enables hardware reception flow control 0 disabled. 1 enabled. enable-e enable enhancement features. 0 disabled. 1 enabled. cont[3:0] software flow control bits. 00xx no tx flow control 10xx transmit xon1/xoff1 as flow control bytes 01xx transmit xon2/xoff2 as flow control bytes 11xx transmit xon1 & xon2 and xoff1 & xoff2 as flow control words xx00 no rx flow control xx10 receive xon1/xoff1 as flow control bytes xx01 receive xon2/xoff2 as flow control bytes xx11 receive xon1 & xon2 and xoff1 & xoff2 as flow control words uartn+0010h xon1 uartn_xon1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xon1[7:0] type r/w reset 0 uartn+0014h xon2 uartn_xon2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xon2[7:0] type r/w reset 0 uartn+0018h xoff1 uartn_xoff1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xoff1[7:0] type r/w reset 0 uartn+001ch xoff2 uartn_xoff2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xoff2[7:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 402 of 1535 *note: xon1, xon2, xoff1, xoff2 are valid only when lcr=bfh. uartn+0020h autobaud_en uartn_autobau d_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto _en type r/w reset 0 autobaud_en auto-baud enable signal 0 auto-baud function disable 1 auto-baud function enable uartn+0024h high speed uart uart n_highspeed bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name speed [1:0] type r/w reset 0 speed uart sample counter base 0 based on 16*baud_pulse, baud_rate = system clock frequency/16/{dlh, dll} 1 based on 8*baud_pulse, baud_rate = system clock frequency/8/{dlh, dll} 2 based on 4*baud_pulse, baud_rate = system clock frequency/4/{dlh, dll} 3 based on sampe_count * baud_pulse, baud_rate = system clock frequency / sampe_count the table below shows the divisor needed to generate a given baud rate from clk inputs of 6.5m hz based on different highspeed value. baud highspeed = highspeed = 1 highspeed = 2 110 3693 7386 14773 300 1354 2708 7386 1200 338 677 2708 2400 169 338 677 4800 85 169 338 9600 42 85 169 19200 21 42 85 38400 11 21 42 57600 7 14 21 115200 * 7 14 230400 * * 7 460800 * * * 921600 * * * free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 403 of 1535 table 49 divisor needed to generate a given baud rate from 6.5mhz based on different highspeed value the table below shows the divisor needed to generate a given baud rate from clk inputs of 13 mhz based on different highspeed value. baud highspeed = highspeed = 1 highspeed = 2 110 7386 14773 29545 300 2708 7386 14773 1200 677 2708 7386 2400 338 677 2708 4800 169 338 677 9600 85 169 338 19200 42 85 169 38400 21 42 85 57600 14 21 42 115200 7 14 21 230400 * 7 14 460800 * * 7 921600 * * * table 50 divisor needed to generate a given baud rate from 13mhz based on different highspeed value the table below shows the divisor needed to generate a given baud rate from clk inputs of 26 mhz based on different highspeed value. baud highspeed = highspeed = highspeed = 110 14773 29545 59091 300 5417 14773 29545 1200 1354 5417 14773 2400 677 1354 5417 4800 339 677 1354 9600 169 339 667 19200 85 169 339 38400 42 85 169 57600 28 42 85 115200 14 28 42 230400 7 14 28 460800 * 7 14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 404 of 1535 921600 * * 7 table 51 divisor needed to generate a given baud rate from 26 mhz based on different highspeed value the table below shows the divisor needed to generate a given baud rate from clk inputs of 52mhz based on different highspeed value. baud highspeed = highspeed = highspeed = 110 29545 59091 118182 300 10833 29545 59091 1200 2708 10833 29545 2400 1354 2708 10833 4800 677 1354 2708 9600 339 677 1354 19200 169 339 677 38400 85 169 339 57600 56 85 169 115200 28 56 85 230400 14 28 56 460800 7 14 28 921600 * 7 14 table 52 divisor needed to generate a given baud rate from 52 mhz based on different highspeed value uartn+0028h sample_count uartn_sample_coun t bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name samplecount [7:0] type r/w reset 0 when highspeed=3, the sample_count is the threshold value for uart sample counter (sample_num). count from 0 to sample_count. uartn+002ch sample_point uartn_sample_point bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name samplepoint [7:0] type r/w reset ffh when highspeed=3, uart gets the input data when sample_count=sample_num. e.g. system clock = 13mhz, 921600 = 13000000 / 14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 405 of 1535 sample_count = 14 and sample point = 6 (sample the central point to decrease the inaccuracy) the sample_point is usually (sample_count-1)/2 and remove the decimal. uartn+0030h autobaud_reg uartn_autobaud_re g bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baud_stat[3:0] baudrate[3:0] type ro ro reset 0 0 baud_rate autobaud baud rate 0 115200 1 57600 2 38400 3 19200 4 9600 5 4800 6 2400 7 1200 8 300 9 110 baudstat autobaud format 0 autobaud is detecting 1 at_7n1 2 at_7o1 3 at_7e1 4 at_8n1 5 at_8o1 6 at_8e1 7 at_7n1 8 at_7e1 9 at_7o1 10 at_8n1 11 at_8e1 12 at_8o1 13 autobaud detection fails uartn+0034h rate fix address uartn_ratefix_ad bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name restr ict freq_ sel auto baud _rate _fix rxte_ fix type r/w r/w r/w r/w reset 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 406 of 1535 rate_fix when you set "rate_fix"(34h[0]), you can transmit and receive data only if 1) the f13m_en is enable and the freq_sel (34h[2]) is set to 1, or 2) the f26m_en is enable and the freq_sel (34h[2]) is set to 0. autobaud_rate_fix when you set "autobaud_rate_fix"(34h[1]), you can tx/rx the autobaud packet only if 1) the f13m_en is enable and the freq_sel (34h[2]) is set to 1, or 2) the f26m_en is enable and the freq_sel (34h[2]) is set to 0. freq_sel 0 select f26m_en for rate_fix and autobaud_rate_fix 1 select f13m_en for rate_fix and autobaud_rate_fix restrict the "restrict" (34h[3]) is used to set a more condition for the autobaud fsm starting point uartn+0038h autobaudsample uartn_autobaudsa mple bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name autobaudsample type r/w r/w r/w r/w r/w r/w r/w reset dh since the system clock may change, autobaud sample duration should change as system clock changes. when system clock = 13mhz, autobaudsample = 6; when system clock = 26mhz, autobaudsample = 13. uartn+003ch guard time added register uartn_guard bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_ en guard_cnt[3:0] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 guard_cnt guard interval count value. guard interval = (1/(system clock / div_step / div )) * guard_cnt. guard_en guard interval add enable signal. 0 no guard interval added. 1 add guard interval after stop bit. uartn+0040h escape character re gister uartn_escape_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name escape_dat[7:0] type wo reset ffh escape_dat escape character added before software flow control data and escape character, i.e. if tx data is xon (31h), with esc_en =1, uart transmits data as esc + ceh (~xon). uartn+0044h escape enable re gister uartn_escape_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 407 of 1535 name esc_e n type r/w reset 0 esc_en add escape character in transmitter and remove escape character in receiver by uart. 0 do not deal with the escape character. 1 add escape character in transmitter and remove escape character in receiver. uartn+0048h sleep enable register uartn_sleep_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sellp _en type r/w reset 0 sleep_en for sleep mode issue 0 do not deal with sleep mode indicate signal 1 to activate hardware flow control or software co ntrol according to softwa re initial setting when chip enters sleep mode. releasing hardware flow when chip wakes up; but for software control, uart sends xon when awaken and when fifo does not reach threshold level. uartn+004ch virtual fifo enable register uartn_vfifo_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vfifo _en type r/w reset 0 vfifo_en virtual fifo mechanism enable signal. 0 disable vfifo mode. 1 enable vfifo mode. when virtual mode is enabled, the flow control is based on the dma threshold, and generates a timeout interrupt for dma. uartn+0050h rx trigger address uartn_rxtri_ ad bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxtrig[3:0] type r/w reset 0 rxtrig when {rtm,rtl}=2?b11, the rx fifo threshold will be rxtrig. uartn+0054h fractional divider lsb address uartn_fracdiv_l bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fracdiv_l type r/w reset 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 408 of 1535 fracdiv_l add sampling count (+1) from state data7 to data0, in order to contribute fractional divisor. uartn+0058h fractional divider msb address uartn_fracdiv_m bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fracdiv_m type r/w reset 0 0 fracdiv_m add sampling count when in state stop to parity, in order to contribute fractional divisor. fracdiv_l / fracdiv_l add one sampling period to each symbol, in order to increase the baud rate accuracy. 2.30 usb 2.0 high-speed dual-role controller 2.30.1 general description the usb2.0 controller can support 8 tx and 8 rx endpoints(excluding endpoint 0). these endpoints can be individually configured in software to handle either bulk transfers, interrupt transfers or isochronous transfers. there are 8 dma channels and the embedded ram size is 8kbytes. the embedded ram can be dynamically configured to each endpoint. when acting as the host for point-to-point communications, the controller maintains a frame counter and automatically schedules sof, isochronous, interrupt and bulk transfers. here is provided features. ? operates either as the host/peripheral in point-to-point communications with another usb function or as a function controller for a usb peripheral ? complies with the usb 2.0 standard for high-speed (480mbps) functions and with the on-the-go supplement to the usb 2.0 specification ? certified for high-speed otg ? supports point-to-point communications with one high-, full-, or low-speed device ? supports session request protocol (srp) and host negotiation protocol (hnp) ? supports suspend and resume signaling ? supports high-bandwidth isochronous & interrupt transfers ? utmi+ level 2 transceiver interface ? synchronous ram interface for fifos ? support for dma access to fifos ? software connect/disconnect option ? supports multi-layer operations on the ahb bus ? performs all transaction scheduling in hardware free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 409 of 1535 the usb2.0 controller block diagram is as illustrated. figure 41 [figure caption] 2.30.2 register definitions register address register name synonym usb + 0000h function address register faddr usb + 0001h power management register power usb + 0002h tx interrupt status register intrtx usb + 0004h rx interrupt status register intrrx usb + 0006h tx interrupt enable register intrtxe usb + 0008h rx interrupt enable register intrrxe usb + 000ah common usb interrupts register intrusb usb + 000bh common usb interrupts enable register intrusbe usb + 000ch frame number register frame usb + 000eh endpoint selecting index register index usb + 000fh test mode enable register testmode usb + 0010h ~ it maps to csr ep0 ~ ep5 depends on index indexed csr endpoint control utm synchronization packet encode packet decode crc gen/check rx buffer tx buffer ram controller dma controller cpu interface ahb slave ahb master utmi ram endpoint control utm synchronization packet encode packet decode crc gen/check packet encode packet decode crc gen/check rx buffer tx buffer ram controller rx buffer tx buffer ram controller dma controller cpu interface ahb slave ahb master utmi ram free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 410 of 1535 usb + 001fh usb + 0020h usb endpoint 0 fifo register fifo0 usb + 0024h usb endpoint 1 fifo register fifo1 usb + 0028h usb endpoint 2 fifo register fifo2 usb + 002ch usb endpoint 3 fifo register fifo3 usb + 0030h usb endpoint 4 fifo register fifo4 usb + 0034h usb endpoint 5 fifo register fifo5 usb + 0038h usb endpoint 6 fifo register fifo6 usb + 003ch usb endpoint 7 fifo register fifo7 usb + 0040h usb endpoint 8 fifo register fifo8 usb + 0060h otg device control register devctl usb + 0061h power up counter register pwrupcnt usb + 0062h tx fifo size register txfifosz usb + 0063h rx fifo size register rxfifosz usb + 0064h tx fifo address register txfifoadd usb + 0066h rx fifo address register rxfifoadd usb + 006ch hardware version register hwvers usb + 0070h software reset register swrst usb + 0078h info. about number of tx and rx register epinfo usb + 0079h info. about the width of ram and the number of dma channel register raminfo usb + 007ah info. about delay to be applied register linkinfo usb + 007bh vbus pulsing charge register vplen usb + 007ch time buffer available on hs transactions register hs_eof1 usb + 007dh time buffer available on fs transactions register fs_eof1 usb + 007eh time buffer available on ls transactions register ls_eof1 usb + 007fh reset information register rstinfo usb + 0102h ep0 control status register csr0 usb + 0108h ep0 received bytes register count0 usb + 010bh nak limit register naklimt0 usb + 010fh core configuration register configdata usb + 01n0h txmap register txmap(n) usb + 01n2h tx csr register txcsr(n) usb + 01n4h rxmap register rxmap(n) usb + 01n6h rx csr register rxcsr(n) usb + 01n8h rx count register rxcount(n) usb + 01nah txtype register txtype(n) usb + 01nbh txinterval register txinterval(n) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 411 of 1535 usb + 01nch rxtype register rxtype(n) usb + 01ndh rxinterval register rxinterval(n) usb + 01nfh configured fifo size register fifosize(n) n stands for endpoint number. for example, endpoint 1?s n = 1. usb + 0200h dma interrupt status register dma_intr usb + 0204h dma channel 1 control register dma_cntl1 usb + 0208h dma channel 1 address register dma_addr1 usb + 020ch dma channel 1 byte count register dma_count1 usb + 0210h dma channel 1 limiter register dma_limiter1 usb + 0214h dma channel 2 control register dma_cntl2 usb + 0218h dma channel 2 address register dma_addr2 usb + 021ch dma channel 2 byte count register dma_count2 usb + 0224h dma channel 3 control register dma_cntl3 usb + 0228h dma channel 3 address register dma_addr3 usb + 022ch dma channel 3 byte count register dma_count3 usb + 0234h dma channel 4 control register dma_cntl4 usb + 0238h dma channel 4 address register dma_addr4 usb + 023ch dma channel 4 byte count register dma_count4 usb + 023ch dma channel 5 control register dma_cntl5 usb + 0240h dma channel 5 address register dma_addr5 usb + 0244h dma channel 5 byte count register dma_count5 usb + 0248h dma channel 6 control register dma_cntl6 usb + 024ch dma channel 6 address register dma_addr6 usb + 0250h dma channel 6 byte count register dma_count6 usb + 0254h dma channel 7 control register dma_cntl7 usb + 0258h dma channel 7 address register dma_addr7 usb + 025ch dma channel 7 byte count register dma_count7 usb + 0260h dma channel 8 control register dma_cntl8 usb + 0264h dma channel 8 address register dma_addr8 usb + 0268h dma channel 8 byte count register dma_count8 usb + 0284h dma channel 1 pingpong control register dma_pp_cntl1 usb + 0288h dma channel 1 pingpong address register dma_pp_addr1 usb + 028ch dma channel 1 pingpong count register dma_pp_cnt1 usb + 0294h dma channel 2 pingpong control register dma_pp_cntl2 usb + 0298h dma channel 2 pingpong address register dma_pp_addr2 usb + 029ch dma channel 2 pingpong count register dma_pp_cnt2 usb + 02a4h dma channel 3 pingpong control register dma_pp_cntl3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 412 of 1535 usb + 02a8h dma channel 3 pingpong address register dma_pp_addr3 usb + 02ach dma channel 3 pingpong count register dma_pp_cnt3 usb + 02b4h dma channel 4 pingpong control register dma_pp_cntl4 usb + 02b8h dma channel 4 pingpong address register dma_pp_addr4 usb + 02bch dma channel 4 pingpong count register dma_pp_cnt4 usb + 02c0h dma channel 5 pingpong control register dma_pp_cntl5 usb + 02c4h dma channel 5 pingpong address register dma_pp_addr5 usb + 02c8h dma channel 5 pingpong count register dma_pp_cnt5 usb + 02cch dma channel 6 pingpong control register dma_pp_cntl6 usb + 02d0h dma channel 6 pingpong address register dma_pp_addr6 usb + 02d4h dma channel 6 pingpong count register dma_pp_cnt6 usb + 02d8h dma channel 7 pingpong control register dma_pp_cntl7 usb + 02dch dma channel 7 pingpong address register dma_pp_addr7 usb + 02e0h dma channel 7 pingpong count register dma_pp_cnt7 usb + 02e4h dma channel 8 pingpong control register dma_pp_cntl 8 usb + 02e8h dma channel 8 pingpong address register dma_pp_addr 8 usb + 02ech dma channel 8 pingpong count register dma_pp_cnt8 usb + 0300h ep1 rxpktcount register ep1rxpktcount usb + 0302h ep2 rxpktcount register ep2rxpktcount usb + 0304h ep3 rxpktcount register ep3rxpktcount usb + 0308h ep4 rxpktcount register ep4rxpktcount usb + 030ah ep5 rxpktcount register ep5rxpktcount usb + 030c h ep6 rxpktcount register ep6rxpktcount usb + 030eh ep7 rxpktcount register ep7rxpktcount usb + 0310h ep8 rxpktcount register ep8rxpktcount usb + 0400h dma channel 1 real count register dma_realcnt1 usb + 0404h dma channel 1 pingpong real count register dma_pp_realcnt1 usb + 0408h dma channel 1 timer register dma_timer1 usb + 0410h dma channel 2 real count register dma_realcnt2 usb + 0414h dma channel 2 pingpong real count register dma_pp_realcnt2 usb + 0418h dma channel 2 timer register dma_timer2 usb + 0420h dma channel 3 real count register dma_realcnt3 usb + 0424h dma channel 3 pingpong real count register dma_pp_realcnt3 usb + 0428h dma channel 3 timer register dma_timer3 usb + 0430h dma channel 4 real count register dma_realcnt4 usb + 0434h dma channel 4 pingpong real count register dma_pp_realcnt4 usb + 0438h dma channel 4 timer register dma_timer4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 413 of 1535 usb + 0440h dma channel 5 real count register dma_realcnt5 usb + 0444h dma channel 5 pingpong real count register dma_pp_realcnt5 usb + 0448h dma channel 5 timer register dma_timer5 usb + 0450h dma channel 6 real count register dma_realcnt6 usb + 0454h dma channel 6 pingpong real count register dma_pp_realcnt6 usb + 0458h dma channel 6 timer register dma_timer6 usb + 0460h dma channel 7 real count register dma_realcnt7 usb + 0464h dma channel 7 pingpong real count register dma_pp_realcnt7 usb + 0468h dma channel 7 timer register dma_timer7 usb + 0470h dma channel 8 real count register dma_realcnt8 usb + 0474h dma channel 8 pingpong real count register dma_pp_realcnt8 usb + 0478h dma channel 8 timer register dma_timer8 usb + 0600h phy control register 1 phycr1 usb + 0604h phy control register 2 phycr2 usb + 0608h phy control register 3 phycr3 usb + 060ch phy control register 4 phycr4 usb + 0610h phy control register 5 phycr5 usb + 0614h phy utmi interface register 1 phyir1 usb + 0618h phy utmi interface register 2 phyir2 usb + 061ch phy utmi interface register 3 phyir3 table 53 [table caption] usb cotrol register usb+0000h function address register faddr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name function address type r/w reset 0 function address faddr is an 8-bit register that should be written with the 7-bit address of the peripheral part of the transaction. when the usb2.0 controller is being used in peripheral mode (devctl.bit2=0), this register should be written with the address received through a set_address command, which will then be used for decoding the function address in subsequent token packets. when the usb2.0 controller is being used in host mode (devctl.bit2=1), this register should be set to the value sent in a set_address command during device enumeration as the address for the peripheral device. peripheral mode usb+0001h power management register power bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 414 of 1535 name isoup date softc onn hsen ab hsmo de reset resu me suspe ndmo de enab le_su spen dm type r/w r/w r/w r r r/w r r/w reset 0 0 1 0 0 0 0 0 host mode usb+0001h power management register power bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hsen ab hsmo de resu me suspe nd mode enab lesu spen dm type r/w r r/w set r/w reset 1 0 0 0 0 enable_suspendm set by the cpu to enable the suspendm output suspendmode in host mode, this bit is set by the cpu to enter suspend mode. in peripheral mode, this bit is set on entryo into suspend mode. it is cleared when the cpu reads the interrupt register, or sets the resume bit above. resume set by the cpu to generate resume signaling when the function is in suspend mode. the cpu should clear this bit after 10 ms (a maximum of 15 ms) to end resume signaling. in host mode, this bit is also automatically set when resume signaling from the target is detected while the usb2.0 controller is suspended. reset this bit is set when reset signaling is present on the bus. note: this bit is read/write from the cpu in host mode but read-only in peripheral mode. hsmode when set, this read-only bit indicates high-speed mode successfully negotiated during usb reset. in peripheral mode, becomes valid when usb reset completes (as indicated by usb reset interrupt). in host mode, becomes valid when reset bit is cleared. remains valid for the duration of the session. note: allowance is made for tiny-j signaling in determining the transfer speed to select. hsenab when set by the cpu, the usb2.0 controller will negotiate for high-speed mode when the device is reset by the hub. if not se t, the device will only operate in full-speed mode. softconn if soft connect/disconnect feature is enabled, then the usb d+/d- lines is enabled when this bit is set by the cpu and tri-stated when this bit is cleared by the cpu. note: only valid in peripheral mode. isoupdate when set by the cpu, the usb2.0 controller will wait for an sof token from the time txpktrdy is set before sending the packet. if an in to ken is received before an sof token, then a zero length data packet will be sent.note: only valid in peripheral mode. also, this bit only affects endpoints performing isochronous transfers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 415 of 1535 usb+0002h tx interrupt status register intrtx bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep5_t x ep4_t x ep3_t x ep2_t x ep1_t x ep0 type r r r r r r reset 0 0 0 0 0 0 ep0 endpoint0 interrupt event ep1_tx tx endpoint 1 interrupt event ep2_tx tx endpoint 2 interrupt event ep3_tx tx endpoint 3 interrupt event ep4_tx tx endpoint 4 interrupt event ep5_tx tx endpoint 4 interrupt event usb+0004h rx interrupt status register intrrx bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep3_r x ep2_r x ep1_r x type r/w r/w r/w reset 0 0 0 intrrx[15:0] rx interrupt status register is ?write 0 clear? ep1_rx rx endpoint 1 interrupt event ep2_rx rx endpoint 2 interrupt event ep3_rx rx endpoint 3 interrupt event usb+0006h tx interrupt enable register intrtxe bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep5_t xe ep4_t xe ep3_t xe ep2_t xe ep1_t xe ep0_e type r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 ep0_e 0 endpoint0 interrupt event disable 1 endpoint0 interrupt event enable ep1_txe 0 endpoint1 interrupt event disable 1 endpoint1 interrupt event enable ep2_txe 0 endpoint2 interrupt event disable 1 endpoint2 interrupt event enable ep3_txe 0 endpoint3 interrupt event disable 1 endpoint3 interrupt event enable ep4_txe free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 416 of 1535 0 endpoint4 interrupt event disable 1 endpoint4 interrupt event enable ep5_txe 0 endpoint5 interrupt event disable 1 endpoint5 interrupt event enable usb+0008h rx interrupt enable register intrrxe bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep3_r xe ep2_r xe ep1_r xe type r/w r/w r/w reset 1 1 1 ep1_rxe 0 rx endpoint1 interrupt event disable 1 rx endpoint1 interrupt event enable ep2_rxe 0 rx endpoint1 interrupt event disable 1 rx endpoint1 interrupt event enable ep3_rxe 0 rx endpoint1 interrupt event disable 1 rx endpoint1 interrupt event enable usb+000ah common usb interr upt register intrusb bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vbus erro r sessr eq disco n conn sof reset /babl e resu me susp end type r r r r r r r r reset 0 0 0 0 0 0 0 0 suspend set when suspend signaling is detected on the bus. only valid in peripheral mode. resume set when resume signaling is detected on the bus while the usb2.0 controller is in suspend mode. reset set in peripheral mode when reset signaling is detected on the bus. babble set in host mode when babble is detected. note: only active after first sof has been sent. sof set when a new frame starts. conn set when a device connection is detected. only valid in host mode. valid at all transaction speeds. discon set in host mode when a device disconnect is detected. set in peripheral mode when a session ends. valid at all transaction speeds. sessreq set when session request signaling has been detected. only valid when usb2.0 controller is ?a? device. vbuserror set when vbus drops below the vbus valid threshold during a session. only valid when usb2.0 controller is ?a? device. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 417 of 1535 usb+000bh common usb interrupt enable register intrusbe bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vbus erro r_e sessr eq_e disco n_e conn _e sof_e reset /babl e_e rese um_e susp end_e type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 suspend_e suspend interrupt enable. resume_e resume interrupt enable reset/babble_e reset/babble interrupt enable sof_e sof interrupt enable conn_e conn interrupt enable discon_e discon interrupt enable sessreq_e sessreq interrupt enable vbuserror_e vbuserror interrupt enable usb+000ch frame number register frame bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name frame number type r reset 0 frame_number frame is a 11-bit read-only register that holds the last received frame number. usb+000eh endpoint selection index register index bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name selected endpoint type r/w reset 0 selected endpoint each tx endpoint and each rx endpoint have their own set of control/status registers located between usb+100h ? usb+1ffh. in addition one set of tx control/status and one set of rx control/status registers appear at usb+010h ? usb+01fh. index is a 4-bit register that determines which endpoint control/status registers are accessed. before accessing an endpoint?s control/status registers at usb+010h ? usb+01fh, the endpoint number should be written to the index register to ensure that the correct control/status registers appear in the memory map. usb+000fh test mode enable register testmode bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name forc e_hos t fifo_ acce ss forc e_fs forc e_hs test_ pack et test_ k test_ j test_ se0_n ak type r/w set r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 418 of 1535 reset 0 0 0 0 0 0 0 0 test_se0_nak (high-speed mode) the cpu sets this bit to enter the test_se0_nak test mode. in this mode, the usb2.0 controller remains in high-speed mode but responds to any valid in token with a nak. test_j (high-speed mode) the cpu sets this bit to enter the test_j test mode. in this mode, the usb2.0 controller transmits a continuous j on the bus. test_k (high-speed mode) the cpu sets this bit to enter the test_k test mode. in this mode, the usb2.0 controller transmits a continuous k on the bus. test_packet (high-speed mode) the cpu sets this bit to enter the test_packet test mode. in this mode, the usb2.0 controller repetitively transmits on the bus a 53-byte test packet, the form of which is defined in the universal serial bus specification revision 2.0, section 7.1.20. note: the test packet has a fixed format and must be loaded into the endpoint 0 fifo before the test mode is entered. force_hs the cpu sets this bit either in conjunction with bit 7 above or to force the usb2.0 controller into high-speed mode when it receives a usb reset. force_fs the cpu sets this bit either in conjunction with bit 7 above or to force the usb2.0 controller into fullspeed mode when it receives a usb reset. fifo_access the cpu sets this bit to transfer the packet in the endpoint 0 tx fifo to the endpoint 0 rx fifo. it is cleared automatically. force_host the cpu sets this bit to instruct the core to enter host mode when the session bit is set, regardless of whether it is connected to any peripheral. the state of the cid input, hostdisconnect and linestate signals are ignored. the core will then remain in host mode until the session bit is cleared, even if a device is disconnected, and if the force_host bit remains set, w ill re-enter host mode the ne xt time the session bit is set.while in this mode, the status of the hostdiscon signal from the phy may be read from bit 7 of the actlr0.devctl register. the operating speed is determined from the force_hs and force_fs bits as follows: force_hs force_fs operating speed 0 0 low speed 0 1 full speed 1 0 high speed 1 1 undefined peripheral mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 419 of 1535 usb+0100h ep0 control status register csr0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flush fifo servi ceset uped n servi cedr xpktr dy send stall setup end data end send stall txpkt rdy rxpk trdy type set set set set r set r/cle ar r/set r reset 0 0 0 0 0 0 0 0 0 rxpktrdy this bit is set when a data packet has been received. an interrupt is generated when this bit is set. the cpu clears this bit by setting the servicedrxpktrdy bit. txpktrdy the cpu sets this bit after loading a data packet into the fifo. it is cleared automatically when a data packet has been transmitted. an interrupt is also generated at this point (if enabled). sentstall this bit is set when a stall handshake is transmitted. the cpu should clear this bit. dataend the cpu sets this bit: when setting txpktrdy for the last data packet. when clearing rxpktrdy after unloading the last data packet. when setting txpktrdy for a zero length data packet.it is cleared automatically. setupend this bit will be set when a control transaction ends before the dataend bit has been set. an interrupt will be generated and the fifo flushed at this time. the bit is cleared by the cpu writing a 1 to the servicedsetupend bit. sendstall the cpu writes a 1 to this bit to terminate the current transaction. the stall handshake will be transmitted and then this bit will be cleared automatically. note: the fifo should be flushed before sendstall is set. servicerxpktrdy the cpu writes a 1 to this bit to clear the rxpktrdy bit. it is cleared automatically. servicesetupend the cpu writes a 1 to this bit to clear the setupend bit. it is cleared automatically. flushfifo the cpu writes a 1 to this bit to flush the next packet to be transmitted/read from the endpoint 0 fifo. it is cleared automatically. the fifo pointer is reset and the txpktrdy/rxpktrdy bit (below) is cleared. note: flushfifo should only be used when txpktrdy/rxpktrdy is set. at other times, it may cause data to be corrupted. host mode usb+0102h ep0 control status register csr0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dispin g flush fifo nakti meou t statu spkt reqp kt erro r setup pkt rxsta ll txpkt rdy rxpk trdy type r/w set r/cle ar r/w r/w r/cle ar r/cle ar r/cle ar r/set r/cle ar free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 420 of 1535 reset 0 0 0 0 0 0 0 0 0 0 rxpktrdy this bit is set when a data packet has been received. an interrupt is generated (if enabled) when this bit is set. the cpu should clear this bit when the packet has been read from the fifo. txpktrdy the cpu sets this bit after loading a data packet into the fifo. it is cleared automatically when a data packet has been transmitted. an interrupt is also generated at this point (if enabled). rxstall this bit is set when a stall handshake is received. the cpu should clear this bit. setuppkt the cpu sets this bit, at the same time as the txpktrdy bit is set, to send a setup token instead of an out token for the transaction. note: setting this bit also clears the datatoggle. error this bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. the cpu should clear this bit. an interrupt is generated when this bit is set. reqpkt the cpu sets this bit to request an in transaction. it is cleared when rxpktrdy is set. statuspkt the cpu sets this bit at the same time as the txpktrdy or reqpkt bit is set, to perform a status stage transaction. setting this bit ensures that the data toggle is set to 1 so that a data1 packet is used for the status stage transaction. naktimeout this bit will be set when endpoint 0 is halted fo llowing the receipt of nak responses for longer than the time set by the naklimit0 register. the cpu should clear this bit to allow the endpoint to continue. flushfifo the cpu writes a 1 to this bit to flush the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txpktrdy/rxpktrdy bit (below) is cleared. note: flushfifo should only be used when txpktrdy/rxpktrdy is set. at other times, it may cause data to be corrupted. disping the cpu writes a 1 to this bit to instruct the core not to issue ping tokens in data and status phases of a high-speed control transfer (for use with devices that do not respond to ping) usb+0108h ep0 received bytes register count0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep0 rx count type r reset 0 ep0 rx count0 count0 is a 7-bit read-only register that indicates the number of received data bytes in the endpoint 0 fifo. the value returned changes as the contents of the fifo change and is only valid while rxpktrdy (idxepr0.csr0.bit0) is set. host mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 421 of 1535 usb+010bh nak limit register naklimt0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name naklimit0 type r/w reset 0 naklimit0 naklimit0 is a 5-bit register that sets the number of frames/microframes (high-speed transfers) after which endpoint 0 should timeout on receiving a stream of nak responses. (equivalent settings for other endpoints can be made through their txinterval and rxinterval registers.). the number of frames/microframes selected is 2 (m-1) (where m is the value set in the register, va lid values 2 ? 16). if the host receives nak responses from the target for more frames than the number represented by the limit set in this register, the endpoint will be halted. note: a value of 0 or 1 disables the nak timeout function. usb+010fh core configurat ion register configdata bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mprx e mptx e bigen dian hbrx e hbtxe dynfi fosizi ng softc one utmid atawi dth type r r r r r r r r reset 0 0 0 0 0 0 0 0 utmidatawidth indicates selected utmi+ data width. 0 8 bits 1 16 bits softcone when set to ?1? indicates soft connect/disconnect option selected. dynfifosizeing when set to ?1? indicates dynamic fifo sizing option selected. hbtxe when set to ?1? indicates high-bandwidth tx iso endpoint support selected. hbrxe when set to ?1? indicates high-bandwidth rx iso endpoint support selected bigendian when set to ?1? indicates big endian ordering is selected. mptxe when set to ?1?, automatic splitti ng of bulk packets is selected. mprxe when set to ?1?, automatic amalgamation of bulk packets is selected. usb+0110h txmap register txmap bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m-1 maximum payload transaction type r/w r/w reset 0 0 txmaxp m-1 maxmum payload size for indexed tx endpoint m-1 packet multiplier m txmaxp maximum paylod transaction register free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 422 of 1535 the txmaxp register defines the maximum amount of data that can be transferred through the selected tx endpoint in asingle operation. there is a txmaxp register for each tx endpoint (except endpoint 0).bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. the value set can be up to 1024 bytes but is subject to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in fullspeed and high speed operations. where the option of high-bandwidth isochronous/interrupt endpoints or of packet splitting on bulk endpoints has been taken when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded. in the case of bulk endpoints with the packet splitting option enabled, the multiplier m can be up to 32 and defines the maximum number of ?usb? packets (i.e. packets for transmission over the usb) of the specified payload into which a single data packet placed in the fifo should be split, prior to transfer. (if the packet splitting option is not enabled, bit15?13 is not implemented and bit12?11(if included) is ignored.) note: the data packet is required to be an exact multiple of the payload specified by bits 10:0, which is itself required to be either 8, 16, 32, 64 or (in the case of high speed transfers) 512 bytes. for isochronous/interrupt endpoints operating in high-speed mode and with the high-bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit 12 set, respectively) and it specifies the maximum number of such transactions that can take place in a single microframe. if either bit 11 or bit 12 is non-zero, the usb2.0 controller will automatically split any data packet written to the fifo into up to 2 or 3 ?usb? packets, each containing the specified payload (or less). the maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be transmitted in each microframe. (for isochronous/interrupt transfers in full-speed mod, bits 11 and 12 are ignored.) the value written to bits 10:0 (multiplied by m in the case of high-bandwidth isochronous/interrupt transfers) must match the value given in the wmaxpacketsize field of the standard endpoint descriptor for the associated endpoint (see usb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 423 of 1535 specification revision 2.0, chapter 9). a mismatch could cause unexpected results.the total amount of data represented by the value written to this register (specified payload m) must not exceed the fifo size for the tx endpoint, and should not exceed half the fifo size if double-buffering is required.if this register is changed after packets have been sent from the endpoint, the tx endpoint fifo should be completely flushed (using the flushfifo bit in txcsr) after writing the new value to this register. peripheral mode usb+0112h tx csr register txcsr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto set iso mode dmar eqen frcd atat og dmar eqmo de auto seten spkt incom ptx clrd atat og sents tall send stall flush fifo unde rrun fifon otem pty txpkt rdy type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txpktrdy the cpu sets this bit after loading a data packet into the fifo. it is cleared automatically when a data packet has been transmitted. an interrupt is also generated at this point (if enabled). txpktrdy is also automatically cleared (but no interrupt is generated) prior to loading a second packet into a double-buffered fifo. fifonotempty the usb sets this bit when there is at least 1 packet in the txfifo. underrun the usb sets this bit if an in token is received when the txpktrdy bit not set. the cpu should clear this bit (write 0 clear). flushfifo the cpu writes a 1 to this bit to flush the latest packet from the endpoint txfifo. the fifo pointer is reset, the txpktrdy bit is cleared and an interrupt is generated. may be set simultaneously with txpktrdy to abort the packet that is currently being loaded into the fifo. note: flushfifo should only be used when txpktrdy is set. at other times, it may cause data to be corrupted. also no te that, if the fifo is double-buffe red, flushfifo may need to be set twice to ompletely clear the fifo. sendstall the cpu writes a 1 to this bit to issue a stall handshake to an in token. the cpu clears this bit to terminate the stall condition. note: this bit has no effect where the endpoint is being used for isochronous transfer. sentstall this bit is set when a stall handshake is transmitted. the fifo is flushed and the txpktrdy bit is cleared. the cpu should clear this bit. clrdatatog the cpu writes a 1 to this bit to reset the endpoint data toggle to 0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 424 of 1535 incomptx when the endpoint is being used for high-bandwidth isochronous/interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient in tokens have been received to send all the parts. note: in anything other than a high -bandwidth transfer, this bit will always return 0. autoseten_spkt if the cpu sets this bit, txpktrdy will be automatically set when the short packet is loaded into the txfifo completely. but, this function only works in tx endpoint 1 and 2. besides, tx endpoint 1 has to use dma channel 1 to move data and tx endpoint 2 has to use dma channel 2 to move data. dmareqmode the cpu sets this bit to select dma request mode 1 and clears it to select dma request mode 0.note: this bit must not be cleared either before or in the same cycle as the dmareqen bit is cleared. frcdatatog the cpu sets this bit to force the endpoint dat a toggle to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this can be used by interrupt tx endpoints that are used to communicate rate feedback for isochronous endpoints. dmareqen the cpu sets this bit to enable the dma request for the tx endpoint. mode the cpu sets this bit to enable the endpoint direction as tx, and clears the bit to enable it as rx. note: this bit only has any effect where the same endpoint fifo is used for both tx and rx transactions. iso the cpu sets this bit to enable the tx endpoint for isochronous transfers, and clears it to enable the tx endpoint for bulk or interrupt transfers. note: this bit only has any effect in peripheral mode. in host mode, it always returns zero. autoset if the cpu sets this bit, txpktrdy will be automa tically set when data of the maximum packet size (value in txmaxp) is loaded into the txfifo. if a packet of le ss than the maximum packet size is loaded, then txpktrdy will have to be set manually if autoseten_spkt is not enabled. host mode usb+0112h tx csr register txcsr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto set mode dmar eqen frcd atat og dmar eqmo de nakti meou t/inco mptx clrd atao g rxsta ll flush fifo erro r fifon otem ty txpkt rdy type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 txpktrdy the cpu sets this bit after loading a data packet into the fifo. it is cleared automatically when a data packet free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 425 of 1535 has been transmitted. an interrupt is also generated at this point (if enabled). txpktrdy is also automatically cleared prior to loading a second packet into a double-buffered fifo. fifonotempty the usb sets this bit when there is at least 1 packet in the tx fifo. error the usb sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. when the bit is set, an interrupt is generated, txpktrdy is cleared and the fifo is completely flushed. the cpu should clear this bit. valid only when the endpoint is operating in bulk or interrupt mode. flushfifo the cpu writes a 1 to this bit to flush the latest packet from the endpoint tx fifo. the fifo pointer isreset, the txpktrdy bit (below) is cleared and an interrupt is generated. may be set simultaneously with txpktrdy to abort the packet that is currently being loaded into the fifo. note: flushfifo should only be used when txpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. rxstall this bit is set when a stall handshake is received. when this bit is set, any dma request that is in progress is stopped, the fifo is completely flushed and the txpktrdy bit is cleared (see below). the cpu should clear this bit. clrdatatog the cpu writes a 1 to this bit to reset the endpoint data toggle to 0. naktimeout bulk endpoints only: this bit will be set when the tx endpoint is halted following the receipt of nak responses for longer than the time set as the nak limit by the txinterval register. the cpu should clear this bit to allow the endpoint to continue. incomptx high-bandwidth interrupt endpoints only: this bit will be set if no response is received from the device to which the packet is being sent. dmareqmode the cpu sets this bit to select dma request mode 1 and clears it to select dma request mode 0.note: this bit must not be cleared either before or in the same cycle as the above dmareqenab bit is cleared. frcdatatog the cpu sets this bit to force the endpoint dat a toggle to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this can be used by interrupt tx endpoints that are used to communicate rate feedback for isochronous endpoints. dmareqenab the cpu sets this bit to enable the dma request for the tx endpoint. mode the cpu sets this bit to enable the endpoint direction as tx, and clears it to enable the endpoint direction as rx. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 426 of 1535 note: this bit only has any effect where the same endpoint fifo is used for both tx and rx transactions. autoset if the cpu sets this bit, txpktrdy will be automa tically set when a packet of the maximum packet size (txmaxp) is loaded into the tx fifo. if a packet of less than the maximum packet size is loaded, then txpktrdy will have to be set manually. note: should not be set for either high-bandwidth isochronous endpoints or high- bandwidth interrupt endpoints. usb+0114h rxmap register rxmap bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m-1 maximum payload transaction type r/w r/w reset 0 0 m-1 maxmum payload size for indexed rx endpoint , m-1 packet multiplier m maximum payload transaction register the rxmaxp register defines the maximum amount of data that can be transferred through the selected rx endpoint in a single operation. there is a rxmaxp register for each rx endpoint (except endpoint 0).bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. the value set can be up to 1024 bytes but is subject to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed and high-speed operations. where the option of high-bandwidth isochronous/interrupt endpoints or of combining bulk packets has been taken when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded. for bulk endpoints with the packet combining option enabled, the multiplier m can be up to 32 and defines the number of usb packets of the specified payload which are to be combined into a single data packet within the fifo. (if the packet splitting option is not enabled, bit15?bit13 is not implemented and bit12?bit11 (if included) is ignored.) for isochronous/interrupt endpoints operating in high-speed mode and with the high-bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit 12 set, respectively) and it specifies the maximum number of such transactions that can take place in a single microframe. if either bit 11 or bit 12 is non-zero, the usb2.0 controller will automatically combine the separate usb packets received in any microframe into a single packet within the rx fifo. the free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 427 of 1535 maximum payload for each transaction is 1024 bytes, so this allows up to 3072 bytes to be received in each microframe. (for isochronous/interrupt transfers in full-speed mode or if high-bandwidth is not enabled, bits 11 and 12 are ignored.) the value written to bits 10:0 (multiplied by m in the case of high-bandwidth isochronous/interrupt transfers) must match the value given in the wmaxpacketsize field of the standard endpoint descriptor for the associated endpoint (see usb specification revision 2.0, chapter 9). a mismatch could cause unexpected results. the total amount of data represented by the value written to this register (specified payload m) must not exceed the fifo size for the out endpoint, and should not exceed half the fifo size if double-buffering is required. peripheral mode usb+0116h rx csr register rxcsr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto clea r iso dmar eqen disny et/pid err dmar eqmo de auto clre nspkt incom prxin tren incom prx clrdt atog sents tall send stall flush fifo data err over run fifof ull rxpk trdy type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rxpktrdy this bit is set when a data packet has been received (to rxfifo). the cpu should clear this bit when the packet has been unloaded from the rxfifo. an interrupt is generated when the bit is set. fifofull this bit is set when no more packets can be loaded into the rxfifo. overrun this bit is set if an out packet cannot be loaded into the rxfifo. the cpu should clear this bit (write 0 clear). note: this bit is only valid when the endpoint is operating in iso mode. in bulk mode, it always returns zero. the new incoming packet won?t be written to rxfifo. an interrupt is generated when the bit is set and overrunintren is set. dataerror this bit is set when rxpktrdy is set if the data packet has a crc or bit-stuff error. the cpu should write 0 to clear this bit. note: this bit is only valid when the endpoint is operating in iso mode. in bulk mode, it always returns zero. an interrupt is generated when the bit is set and dataerrintren is set. flushfifo the cpu writes a 1 to this bit to flush the next packet to be read from the endpoint rxfifo. the rxfifo pointer is reset and the rxpktrdy bit is cleared. note: flushfifo should only be used when rxpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the rxfifo is double buffered, flushfifo may need to be set twice to completely clear the rxfifo. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 428 of 1535 sendstall the cpu writes a 1 to this bit to issue a stall handshake. the cpu clears this bit to terminate the stall condition. note: this bit has no effect where the endpoint is being used for iso transfers. sentstall this bit is set when a stall handshake is transmitted. the cpu should clear this bit. an interrupt is generated when the bit is set. clrdatatog the cpu writes a 1 to this bit to reset the endpoint data toggle to 0. incomprx this bit is set in a high-bandwidth isochronous/interrupt transfer if the packet in the rxfifo is incomplete because parts of the data were not received. it is cleared when rxpktrdy is cleared or write 0 to clear. note: in anything other than a high-bandwidth transfer, this bit will always return 0. an interrupt is generated when the bit is set and incomprxintren is set. incomprxintren incomprx and piderr interrupt enable. autoclren_spkt the cpu write a 1 to this bit to enable sh ort packets? rxpktrdy to be automatically cleared. whe this bit is turned on, autoclear must also be turned on. if iso and autoclren_spkt are both set, when short packets are unloaded, rxpktrdy will be cleared automatically. but, these short packets must have no incomprx, piderr, dataerr or overrun status. dmareqmode the cpu sets this bit to select dma request mode 1 and clears it to select dma request mode 0. dma request mode 1: rx endpoint interrupt is generated only when dma request mode 1 and received a short packet. rxdmareq is generated when receiving a max-packet-size packet.dma request mode 0: no rx endpoint interrupt. rxdmareq is generated when rxpktrdy is set. disnyet(bulk/interrupt transactions) the cpu sets this bit to disable the sending of nyet handshakes. when set, all successfully received rx packets are ack?d including at the point at which the rxfifo becomes full. note: this bit only has any effect in high-speed mode, in which mode it should be set for all interrupt endpoint. piderr(iso transactions) this bit is set when there is a pid error in the received packet. it is cleared when rxpktrdy is cleared or write 0 to clear. an interrupt is generated when the bit is set and incomprxintren is set. dmareqen the cpu sets this bit to enable the dma request for the rx endpoint. iso the cpu sets this bit to enable the rx endpoint for isochronous transfers, and clears it to enable the rx endpoint for bulk/interrupt transfers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 429 of 1535 autoclear if the cpu sets this bit then the rxpktrdy bit will be automatically cleared when a packet of rxmaxp bytes has been unloaded from the rxfifo. when packets of less than the maximum packet size are unloaded, rxpktrdy will have to be cleared manually if autoclren_spkt is not enabled. host mode usb+0116h rx csr register rxcsr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto clea r auto req dmar eqen ab pider ror dmar eqmo de incom prx clrd atat og rxsta ll reqp kt flush fifo data err/n aktim er erro r fifof ull rxpk trdy type r/w r/w r/w r r/w r/cle ar r/w r/cle ar r/w set r/cle ar r/cle ar r r/cle ar reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rxpktrdy this bit is set when a data packet has been received. the cpu should clear this bit when the packet has been unloaded from the rx fifo. an interrupt is generated when the bit is set. fifofull this bit is set when no more packets can be loaded into the rx fifo. error the usb sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. the cpu should clear this bit. an interrupt is generated when the bit is set. note: this bit is only valid when the rx endpoint is operating in bulk or interrupt mode. in iso mode, it always returns zero. naktimeout in bulk mode, this bit will be set when the rx endpoint is halted following the receipt of nak responses for longer than the time set as the nak limit by the rxinterval register. dataerror when operating in iso mode, this bit is set when rxpktrdy is set if the data packet has a crc or bit-stuff error and cleared when rxpktrdy is cleared. flushfifo the cpu writes a 1 to this bit to flush the next packet to be read from the endpoint rx fifo. the fifo pointer is reset and the rxpktrdy bit (below) is cleared. note: flushfifo should only be used when rxpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. reqpkt the cpu writes a 1 to this bit to request an in transaction. it is cleared when rxpktrdy is set. rxstall when a stall handshake is received, this bit is set and an interrupt is generated. the cpu should clear this bit. clrdatatog the cpu writes a 1 to this bit to reset the endpoint data toggle to 0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 430 of 1535 incomprx this bit will be set in a high-bandwidth isochronous/interrupt transfer if the packet received is incomplete. it will be cleared when rxpktrdy is cleared. note: if usb protocols are followed correctly, this bit should never be set. the bit becoming set indicates a failure of the associated peripheral device to behave correctly. (in anything other than a high-bandwidth transfer, this bit will always return 0.) dmareqmode the cpu sets this bit to select dma request mode 1 and clears it to select dma request mode 0.note: this bit should not be cleared in the same cycle as rxpktrdy is cleared piderror iso transactions only: the core sets this bit to indicate a pid error in the received packet. bulk/interrupt transactions: the se tting of this bit is ignored. dmareqena b the cpu sets this bit to enable the dma request for the rx endpoint. autoreq if the cpu sets this bit, the reqpkt bit will be au tomatically set when the rxpktrdy bit is cleared. note: this bit is automatically cleared when a short packet is received. autoclr f the cpu sets this bit then the rxpktrdy bit will be automatically cleared when a packet of rxmaxp bytes has been unloaded from the rx fifo. when packets of less than the maximum packet size are unloaded, rxpktrdy will have to be cleared manually. note: should not be set for highbandwidth isochronous endpoints. usb+0118h rx count register rxcount bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxcount type r reset 0 rxcoun t it is a 14-bit read-only register that holds the number of received data bytes in the packet in the rxfifo. note: the value returned changes as the fifo is unloaded and is only valid while rxpktrdy(rxcsr.d0) is set. host mode usb+011ah txtype register txtype bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx protocol tx target ep number type r/w r/w reset 0 0 tx target ep number (host mode only) the cpu should set this value to the endpoint number contained in the tx endpoint descriptor returned to the usb2.0 controller during device enumeration. tx protocol (host mode only) the cpu should set this to select the required protocol for the tx endpoint: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 431 of 1535 00 illegal 01 isochronous 10 bulk 11 interrupt usb+011bh txinterval register txinterval bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx polling interval/nak limit m type r/w reset 0 txinterval register txinterval is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently-selected tx endpoint. fo r bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of nak responses. there is a txinterval register for each configured tx endpoint (except endpoint 0). tx polling interval / nak limit (m), (host mode only) in each case the value that is set defines a number of frames/microframes (high speed transfers), as follows: transfer type speed valid values ( m ) interpretation low speed or full speed 1 ? 255 polling interval is m frames. interrupt high speed 1 ? 16 polling interval is 2 ( m-1 ) microframes isochronous full speed or high speed 1 ? 16 polling interval is 2 ( m-1 ) frames/microframes bulk full speed or high speed 2 ? 16 nak limit is 2 ( m-1 ) frames/microframes. note: a value of 0 or 1 disables the nak timeout function. usb+011ch rxtype register rxtype bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx protocol rx target ep number type r/w r/w reset 0 0 rx target ep number (host mode only) the cpu should set this value to the endpoint number contained in the tx endpoint descriptor returned to the usb2.0 controller during device enumeration. rx protocol (host mode only) the cpu should set this to select the required protocol for the tx endpoint: 00 illegal 01 isochronous 10 bulk 11 interrupt free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 432 of 1535 usb+011dh rxinterval register rxinterval bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx polling interval/nak limit m type r/w reset 0 rxinterval register rxinterval is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently-selected rx endpoint. fo r bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of nak responses. there is a rxinterval register for each configured rx endpoint (except endpoint 0). rx polling interval / nak limit (m), (host mode only) in each case the value that is set defines a number of frames/microframes (high speed transfers), as follows: transfer type speed valid values ( m ) interpretation low speed or full speed 1 ? 255 polling interval is m frames. interrupt high speed 1 ? 16 polling interval is 2 ( m-1 ) microframes isochronous full speed or high speed 1 ? 16 polling interval is 2 ( m-1 ) frames/microframes bulk full speed or high speed 2 ? 16 nak limit is 2 ( m-1 ) frames/microframes. note: a value of 0 or 1 disables the nak timeout function. peripheral mode usb+011fh configured fifo size register fifosize bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxfifosize txfifosize type r r reset 0 0 txfifosize indicate the txfifo size of 2n bytes, (ex: value 10 means 210 = 1024 bytes.) rxfifosize indicate the rxfifo size of 2n bytes, (ex: value 10 means 210 = 1024 bytes.) usb+0120h ~ usb+012fh stands for endpoint 2 registers and their behaviors are the same as endpoint 1. usb+0130h ~ usb+013fh stands for endpoint 3 registers and their behaviors are the same as endpoint 1. usb+0140h ~ usb+014fh stands for endpoint 4 registers and their behaviors are the same as endpoint 1. usb+0020h usb endpoint 0 fifo register fifo0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 433 of 1535 usb+0024h usb endpoint 1 fifo register fifo1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+0028h usb endpoint 2 fifo register fifo2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+002ch usb endpoint 3 fifo register fifo3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+0030h usb endpoint 4 fifo register fifo4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+0034h usb endpoint 5 fifo register fifo5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 434 of 1535 reset 0 usb+0038h usb endpoint 6 fifo register fifo6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+003ch usb endpoint 7 fifo register fifo7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 usb+0040h usb endpoint 8 fifo register fifo8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo data[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo data[15:0] type r/w reset 0 fifodata 32-bits fifo data access window the endpoint fifo registers provides 6 addresses for cpu access to the fifos for each endpoint. writing to these addresses loads data into the txfifo for the correspond ing endpoint. reading from these addresses unloads data from the rxfifo for the corresponding endpoint. note: (i) transfers to and from fifos may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the data accessed is contiguous. however, all the transfers associated with one packet must be of the ame width so that the data is consistently byte-, word- or double-word-aligned. the last transfer may however contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 435 of 1535 (ii) depending on the size of the fifo and the expected maximum packet size, the fifos support either single-packet or double-packet buffering. however, burst writing of multiple packets is not supported as flags need to be set after each packet is written. (iii) following a stall response or a tx strike out error on endpoint 0 ? 4, the associated fifo is completely flushed usb+0060h otg device control register devctl bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_dev ice fsdev lsdev host mode host req sessi on type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 session when operating as an ?a? device, this bit is set or cleared by the cpu to start or end a session. when operating as a ?b? device, this bit is set/cleared by the usb2.0 controller when a session starts/ends. it is also set by the cpu to initiate the session request protocol. when the usb2.0 controller is in suspend mode, the bit may be cleared by the cpu to perform a software disconnect. note: clearing this bit when the core is not suspended will result in undefined behavior. hostreq when set, the usb2.0 controller will initiate the host negotiation when suspend mode is entered. it is cleared when host negotiation is completed. (?b? device only) hostmode this read-only bit is set when the usb2.0 controller is acting as a host. lsdev this read-only bit is set when a low-speed device has been detected being connected to the port. only valid in host mode. fsdev this read-only bit is set when a full-speed or high-speed device has been detected being connected to the port. (high-speed devices are distinguished from full-speed by checking for high-speed chirps when the device is reset.) only valid in host mode. b_device this read-only bit indicates whether the usb2.0 controller is operating as the ?a? device or the ?b? device. 0 ?a? device 1 ?b? device only valid while a session is in prog ress. note: if the core is in force_host mode, this bit will indicate the state of the hostdiscon input signal from the phy. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 436 of 1535 usb+0061h power up counter register pwrupcnt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwrupcnt type r/w reset 4?hf pwrupcnt[3:0] power up counter limit. power up counter is used to count the k state duration during suspend and when it is timeout, the resume interrupt will be issued. the register should be configured according to ahb clock speed. usb+0062h tx fifo size register txfifosz bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txdpb txsz type r/w r/w reset 0 0 txdpb defines whether double-packet buffering supported for txfifo. when ?1?, double-packet buffering is supported. when ?0?, only single-packet buffering is supported. txsz maximum packet size to be allowed for (before any splitting within the fifo of bulk/high-bandwidth packets prior to transmission). if txdpb = 0, the fifo will also be this size; if txdpb = 1, the fifo will be twice this size txsz[3:0] packet size (bytes) 0 0 0 0 8 0 0 0 1 16 0 0 1 0 32 0 0 1 1 64 0 1 0 0 128 0 1 0 1 256 0 1 1 0 512 0 1 1 1 1024 1 0 0 0 2048 (single-packet buffering only) 1 0 0 1 4096 (single-packet buffering only) 1 1 1 1 3072 (single-packet buffering only) usb+0063h rx fifo size register rxfifosz bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxdp b rxsz type r/w r/w reset 0 0 rxdpb defines whether double-packet buffering supported for txfifo. when ?1?, double-packet buffering is supported. when ?0?, only single-packet buffering is supported. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 437 of 1535 rxsz maximum packet size to be allowed for (before any splitting within the fifo of bulk/high-bandwidth packets prior to transmission). if txdpb = 0, the fifo will also be this size; if txdpb = 1, the fifo will be twice this size rxsz[3:0] packet size (bytes) 0 0 0 0 8 0 0 0 1 16 0 0 1 0 32 0 0 1 1 64 0 1 0 0 128 0 1 0 1 256 0 1 1 0 512 0 1 1 1 1024 1 0 0 0 2048 (single-packet buffering only) 1 0 0 1 4096 (single-packet buffering only) 1 1 1 1 3072 (single-packet buffering only) usb+0064h tx fifo address register txfifoadd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name txfifoadd type r/w reset 0 txfifoadd txfifoadd is a 13-bit register which controls the start address of the selected rx endpoint fifo. txfifoadd[12:0] start address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? 1 f f f fff8 usb+0066h rx fifo address register rxfifoadd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data errin tre over runit ren rxfifoadd type r/w r/w r/w reset 0 0 0 rxfifoadd rxfifoadd is a 13-bit register which controls the start address of the selected rx endpoint fifo. rxfifoadd[12:0] start address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 438 of 1535 0 0 0 0 0 ? ? 1 f f f fff8 overrunintren overrun interrupt enable. the overrun status bit is in rxcsr[2] and it should be write 0 to clear. dataerrintren dataerr interrupt enable. the dataerr status bit is in rxcsr[3] and it should be write 0 to clear. usb+006ch version register hwvers bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rc xx yyy type r r r reset 0 0 0 rc set to ?1? if rtl used from a release candidate rather than from a full release of the core. xx major version number (range 0 ? 31). yyy minor version number (range 0 ? 999). hwvers register is a 16-bit read-only register that returns information about the version of the rtl from which the core hardware was generated, in particular the rtl version number (vxx.yyy). usb+0070h software reset register swrst bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name opstate redu cedly undo srpfi x frcv busv alid swrs t disus bres et type ro r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 disusbreset the cpu sets this bit to disable usbreset function. and, then the cpu can reset the hardware byswrst. usbreset will be asserted when doing high speed detect ion handshake. (this bit will only be reset when hardware reset.) swrst the cpu sets this bit to reset the endpoint and ram interface hardware. frc_vbusvalid the cpu sets this bit to force vbusval = 1, vbussess = 1 and vbuslo = 0. undo_srpfix the cpu sets this bit to recover to the original circuit of usb2.0 ip about srp. reducedly the cpu can set this bit to reduce inter-pkt delay. opstate this register indicates the us b controller state information. usb+0078h info. about number of tx and rx register epinfo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxendpoints txendpoints type r r reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 439 of 1535 txendpoints the number of tx endpoints implemented in the design. rxendpoints the number of rx endpoints implemented in the design. this 8-bit read-only register allows read-back of the number of tx and rx endpoints included in the design. usb+0079h info. about the width of ram and the number of dma channel register raminfo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dmachans rambits type r r reset 0 0 rambits the width of the ram address bus ? 1. dma channels the number of dma channels implemented in the design. this 8-bit read-only register provides information about the width of the ram and the number of dma channels. usb+007ah info. about delay to be applied register linkinfo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wtcon wtid type r/w r/w reset 4?h5 4?hc wtid sets the delay to be applied from idpullup being asserted to iddig being considered valid in units of 4.369ms. (the default setting corresponds to 52.43ms.) wtcon sets the wait to be applied to allow for the user?s connect/disconnect filter in units of 533.3ns. (the default setting corresponds to 2.667s.) this 8-bit register allows some delays to be specified. usb+007bh vbus pulsing charge register vplen bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vplen type r/w reset 8?h3c vplen sets the duration of the vbus pulsing charge in units of 136.5 us. (the default setting corresponds to 8.19ms) this 8-bit register sets the duration of the vbus pulsing charge. usb+007ch time buffer available on hs transaction register hs_eof1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hs_eof1 type r/w reset 8?h80 hs_eof1 sets for high-speed transactions the time before eof to stop beginning new transactions, in units of 133.3ns. (the default setting corresponds to 17.07s.) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 440 of 1535 usb+007dh time buffer available on fs transaction register fs_eof1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fs_eof1 type r/w reset 8?h77 fs_eof1 sets for full-speed transactions t he time before eof to stop beginning new transactions, in units of 533.3ns. (the default setting corresponds to 63.46s.) usb+007eh time buffer available on ls transaction register ls_eof1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ls_eof1 type r/w reset 8?h72 ls_eof1 sets for low-speed transactions the time before eof to stop beginning new transactions, in units of 1.067s. (the default setting corresponds to 121.6s.). usb+007fh reset information register rstinfo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wtfsse0 wtchrp type r/w r/w reset 0 0 wtchrp sets the delay to be applied from detecting reset to sending chirp k (for device only). the duration = 272.8 x wtchrp + 0.1 usec. (this register will only be reset when hardware reset.) wtfsse0 the field signifies the se0 signal duration before issue the reset signal(for device only). the duration = 272.8 x wtfsse0 + 2.5 usec. (this register will only be reset when hardware reset.) usb+0300h ep1 rxpktcount register ep1rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep1rxpktcount type r/w reset 0 ep1rqpktcount (host mode only) sets the number of packets of rx endpoint 1 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+0302h ep2 rxpktcount register ep2rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 441 of 1535 name ep2rxpktcount type r/w reset 0 ep2rqpktcount (host mode only) sets the number of packets of rx endpoint 2 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+0304h ep3 rxpktcount register ep3rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep3rxpktcount type r/w reset 0 ep3rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+0308h ep4 rxpktcount register ep4rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep4rxpktcount type r/w reset 0 ep4rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+030ah ep5 rxpktcount register ep5rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep5rxpktcount type r/w reset 0 ep5rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 442 of 1535 usb+030ch ep6 rxpktcount register ep6rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep6rxpktcount type r/w reset 0 ep3rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+030eh ep7 rxpktcount register ep7rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep3rxpktcount type r/w reset 0 ep7rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. usb+0310h ep8 rxpktcount register ep8rxpktcou nt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ep8rxpktcount type r/w reset 0 ep8rqpktcount (host mode only) sets the number of packets of rx endpoint 3 size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set. rqpktcount (host mode only) for each rx endpoint 1 ? 8, the usb2.0 controller provides a 16-bit rqpktcount register. this read/write register is used in host mode to specify the number of packets that are to be transferred in a block transfer of one or more bulk packets of length maxp to rx endpoint n. the core uses the value recorded in this register to etermine free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 443 of 1535 the number of requests to issue where the autoreq option (included in the rxcsr register) has been set.note: multiple packets combined into a single bulk packet within the fifo count as one packet. usb+0200h dma interrupt st atus register dma_intr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ppb_f inish8 ppa_f inish8 ppb_f inish7 ppa_f inish7 ppb_f inish6 ppa_f inish6 ppb_f inish5 ppa_f inish5 ppb_f inish4 ppa_f inish4 ppb_f inish3 ppa_f inish3 ppb_f inish2 ppa_f inish2 ppb_f inish1 ppa_f inish1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_limiter dma_intr type r r/w reset 0 0 dma_intr indicates pending dma interrupts, one bit per dma channel implemented. bit 0 is used for dma channel 1, bit 1 is used for dma channel 2 etc. write 0 clear. ppa_finish1 indicates dma channel 1 pingponga finish status. write 0 clear. ppb_finish1 indicates dma channel 1 pingpongb finish status. write 0 clear. ppa_finish2 indicates dma channel 2 pingponga finish status. write 0 clear. ppb_finish2 indicates dma channel 2 pingpongb finish status. write 0 clear. ppa_finish3 indicates dma channel 3 pingponga finish status. write 0 clear. ppb_finish3 indicates dma channel 3 pingpongb finish status. write 0 clear. ppa_finish4 indicates dma channel 4 pingponga finish status. write 0 clear. ppb_finish4 indicates dma channel 4 pingpongb finish status. write 0 clear. ppa_finish5 indicates dma channel 5 pingponga finish status. write 0 clear. ppb_finish5 indicates dma channel 5 pingpongb finish status. write 0 clear. ppa_finish6 indicates dma channel 6 pingponga finish status. write 0 clear. ppb_finish6 indicates dma channel 6 pingpongb finish status. write 0 clear. ppa_finish7 indicates dma channel 7 pingponga finish status. write 0 clear. ppb_finish7 indicates dma channel 7 pingpongb finish status. write 0 clear. ppa_finish8 indicates dma channel 8 pingponga finish status. write 0 clear. ppb_finish8 indicates dma channel 8 pingpongb finish status. write 0 clear. dma_limiter please refer to usb+210 register .the dma_limiter can be read in this address,too. usb+0204h dma channel 1 co ntrol register dma_cntl1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name endm amod e2 pp_rs t pp_en burst mode buse rr endpnt inten dmam ode dmadi r dmae n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 dma_en enable dma. the bit will be cleared when the dma transfer is completed. dma_dir direction. 0 : dma write(rx endpoint), 1 : dma read(tx endpoint). dma_mode dma mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 444 of 1535 int_en interrupt enable. endpnt[3 :0] endpoint number. bus_err bus error. burst_mode burst mode. 00 burst mode 0 : bursts of unspecified length. 01 burst mode 1 : incr4 or unspecified length 10 burst mode 2 : incr8, incr4 or unspecified length. 11 burst mode 3 : incr16, incr8, incr4 or unspecified length pp_en pingpong buffer enable. pp_rst the cpu writes 1 to this bit to reset pingpong buffer sequence. the bit stands for current pingpong buffer sequence when read. endmamode2 enable dma mode 2 function. dma mode 2: the short packets will be moved by dma even the short packets are not the last transfer of this dma count. the dma mode 2 function can?t be turned on when autoreq = 1 dma_cntl2, dma_cntl3, dma_cntl4, dma_cntl5 and dma_cntl6 have the same modification. usb+0208h dma channel 1 address register dma_addr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma_addr1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_addr1[15:0] type r/w reset 0 dma_addr1 32bits dma start address, updated (increase) by usb2.0 controller automatically while multiple packet dma (dma mode = 1) is used dma_addr2, dma_addr3, dma_addr4, dma_addr5 and dma_addr6 have the same modification. usb+020ch dma channe l1 byte count register dma_count1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma count1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_count1[15:0] type r/w reset 0 dma_count1 32bits dma transfer count with byte unit, updated (decrease) by usb2.0 controller automatically while each packet is transferred. dma_count 2, dma_count3, dma_count4, dma_count5 and dma_count6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 445 of 1535 have the same modification. usb+0214h ~ usb+021ch stands for dma channel 2 registers and their behaviors are the same as dma channel 1. usb+0224h ~ usb+022ch stands for dma channel 3 registers and their behaviors are the same as dma channel 1. usb+0234h ~ usb+023ch stands for dma channel 4 registers and their behaviors are the same as dma channel 1. usb+0210h dma channel limiter register dma_limiter bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_limiter type r/w reset 0 dma_limiter this register is to suppress the bus utilization of the dma channel. the value is from 0 to 255. 0 means no limitation, and 255 means totally banned. the value between 0 and 255 means certain dma can have permission to use ahb every (4 x n) ahb clock cycles.note that it is not recommended to limit the bus utilization of the dma channels because this increases the latency of response to the masters, and the transfer rate decreases as well. before using it, programmer must make sure that the bus masters have some protective mechanism to avoid entering the wrong states. usb+0284h dma channel pingp ong control register dma_pp_cntl 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dmae n type r/w reset 0 dma_en enable dma(pingpong buffer dma). the bit will be cleared when the dma transfer is completed. usb+0288h dma channel 1 pi ngpong address register dma_pp_addr 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma_pp_addr1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 446 of 1535 name dma_pp_addr1[15:0] type r/w reset 0 dma_pp_addr1[31:0] dma(pingpong buffer dma) channel 1 ahb memory address. usb+028ch dma channel 1 pingpong count register dma_pp_cnt1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma_pp_cnt1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_pp_cnt1[15:0] type r/w reset 0 dma_pp_cnt1[31:0 ] dma(pingpong buffer dma) channel 1 byte count. usb+0294h ~ usb+029ch stands for dma channel 2 pingpong registers and their behaviors are the same as dma channel 1. usb+02a4h ~ usb+02ach stands for dma channel 3 pingpong registers and their behaviors are the same as dma channel 1. usb+02b4h ~ usb+02bch stands for dma channel 4 pingpong registers and their behaviors are the same as dma channel 1. usb+02c0h ~ usb+02c8h stands for dma channel 5 pingpong registers and their behaviors are the same as dma channel 1. usb+02cch ~ usb+02d4h stands for dma channel 6 pingpong registers and their behaviors are the same as dma channel 1. usb+02d8h ~ usb+02e0h stands for dma channel 7 pingpong registers and their behaviors are the same as dma channel 1. usb+02e4h ~ usb+02ech stands for dma channel 8 pingpong registers and their behaviors are the same as dma channel 1. usb+0400h dma channel re al count register dma_realcnt 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma realcnt[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 447 of 1535 name dma realcnt[15:0] type r reset 0 dma_realcnt[31:0] indicate current transferred bytes of dma channel 1. usb+0404h dma channel 1 pingp ong real count register dma_pp_real cnt1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma pp realcnt[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma pp realcnt[15:0] type r reset 0 dma_pp_realcnt[31:0] indicate current transferred bytes of dma channel 1 pingpong. usb+0408h dma channel 1 timer register dma_timer1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name timeo utsta tus entim er reg timeout type r/w r/w r/w reset 0 0 0 entimer enable timer. when the timer is enabled and there is no this dma transaction during the reg_timeout duration, then dma interrupt will be issued. the timer will be reset whenever entimer = 0 or (dma_en = 0 and dam_en_pp = 0). reg_timeout to config timeout duration. timeout duration = 1280 * reg_timeout + 2.5 us. timeout_status indicates the dma channel has timeout situation. write 0 clear. usb+0410h ~ usb+0418h stands for dma channel 2 registers and their behaviors are the same as dma channel 1. usb+0420h ~ usb+0428h stands for dma channel 3 registers and their behaviors are the same as dma channel 1. usb+0430h ~ usb+0438h stands for dma channel 4 registers and their behaviors are the same as dma channel 1. usb+0440h ~ usb+0448h stands for dma channel 5 registers and their behaviors are the same as dma channel 1. usb+0450h ~ usb+0458h stands for dma channel 6 registers and their behaviors are the same as dma channel 1. usb+0460h ~ usb+0468h stands for dma channel 7 registers and their behaviors are the same as dma channel 1. usb+0470h ~ usb+0478h stands for dma channel 8 registers and their behaviors are the same as dma channel 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 448 of 1535 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 449 of 1535 figure 42 [figure caption] usb+0600h phy control register 1 phycr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hs_tx _ien_ mode hs_tx _spse l hs_sq_init_ en_dg[1:0] hs_sq _end g hs_sq _en_m ode hs_sq s hs_ rcv_ en_m ode hs_ rcvb[3:0] pll_ vcog[1:0] pll_ vcob[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 0 2?b01 1 1 0 1 4?b0100 2?b01 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pll_ccp[3:0] pll_c lf en_ls _cmp sat pll_e n neg_t ri_en _b usb20 _tx_t st bidi_m ode cdr_tst[1:0] gate _en_b type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 4?b0110 0 0 0 0 0 0 0 0 gated_en_b high level clock gating enable 0 enable 1 disable cdr_tst cdr function option d cdr_tst[1]: phase accumulation option d 0 accumulation disable 1 accumulation enable cdr_tst[0]: reference phase number option d 0: 4 phases d 1: 6 phases bidi_mode utmi data bus bi -directional mode 0 enable 1 disable usb20_tx_tst tx macro test option, debug usage d 0 enable 1 disable neg_tri_en_b utmi output signal aligned to negative edge for hold time issue 0 negative edge triggered output 1 positive edge triggered output pll_en usb2.0 phy pll enable d 0 enable 1 disable en_ls_cmpsat ls tx mode dm rpu compensation enable when in client mode d 0 disable 1 enable pll_clf pll loop filter control d 0 disable 1 enable pll_cpp pll cp bias current selection d charge pump current = 3.125ua * n d 0001 : 3.125ua * 1 d 0010 : 3.125ua * free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 450 of 1535 2?1111 : 3.125ua * 15 pll_ccp should be set to 0x03 for better performance. pll_vcob pll vco bias current selection d 00 0ua 01 25ua * 1.5 10 25ua * 2.5 11 25ua * 3.5 pll_vcog[0] pll vco gain selection d 0 normal kvco gain. 1 decrease kvco gain pll_vcog[1] this bit is used to gated internal clock source. hs_rcvb hs rcv bias selection, hs rcv 1st stage bias current d xxx0 600u xxx1 675u hs_rcv_en_mode hs rcv enable mode selection d 0 hs rcv enable by hs rcv 1 hs rcv always enabled while usb operating in hs mode hs_sqs hs sq hystress mode reserved hs_sq_en_mode hs sq enable mode selection d 0 sq enable by hs rcv 1 sq always enabled while usb operating hs_sq_en_dg hs sq de-glitch time after hs rcv enabled d 0 sq output de-glitch 4t 480m clk 1 sq output de-glitch 5t 480m clk hs_sq_init_en_dg hs sq first time initia lizing de-glitch:gated by 00 1t ref clk 01 1.5t ref clk 10 2t ref clk 11 2.5t ref clk hs_tx_sp_sel hs tx load sampling point selection d 0 sampling the hs tx data at rising edge 1 sampling the hs tx data at falling edge hs_tx_i_en_mode hs tx i enable mode selection d 0 hs tx current always enabled while hs term enabled 1 hs_tx current enabled when hs tx module enabled usb+0604h phy control register 2 phycr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 451 of 1535 name forc e_drv _vbus forc e_dm_ pulld own froc e_dp_ pulld own hs_termc[4:0] fix_s onyb ug froc e_dat a_in froc e_txv alid hs_te rm_s el hs_discth[1: 0] hs_discb[1:0 ] type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 5?b01000 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hs_sqtl[2:0] hs_sqth[2:0] hs_sqd[3:0] hs_sqb[3:0] type r/w r/w r/w r/w reset 3?b011 3?b100 4?b0010 4?b0010 hs_sqb hs sq bias selection d hs_sqb[0]: hs sq 1st stage bias current d xxx0 600ua xxx1 675ua hs_sqd hs sq de-glitch control xx00 16u (min current, max de-glitch) xx01 32u xx10 61u xx11 122u (max current de-glitch) hs_sqth hs sq threshold high selection 000 165mv 001 155mv 010 145mv 011 135mv 100 125mv 110 105mv 111 95mv hs_sqtl hs sq threshold low selection d reserved hs_discb hs_discp[0] : see hs_discn[1:0] d hs_discp[1]: disconnect 1st stage bias current d 0 420ua 1 490ua hs_discth hs disc threshold selection 000 615mv 001 605mv 010 595mv 011 585mv 100 575mv 101 565mv 110 555mv 111 545mv hs_term_sel hs term module selection (see hs_termc) d 0: analog termination d 1: digital termination force_tavalid it is used to force phy input signal txvalid to a specific value. 1: enable. 0: disable. force_tavalidh it is used to force phy input signal txvalidh to a specific value. 1: enable. 0: disable. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 452 of 1535 force_datain it is used to force phy input signal datain to a specific value. 1: enable. 0: disable. fix_sonybug when this bit is set , then txfifo write poin ter will be reset when flushfifo. when this bit is not set, then txfifo write pointe r won?t be reset when flushfifo. hs_termc hs term impedence control code (see hs_term_sel) d in analog termination mode hs_term_sel: 0 internal reference voltage: x0000 480mv x0001 470mv x0010 460mv x0011 450mv x0100 440mv x0101 430mv x0110 420mv x0111 410mv x1000 400mv x1001 390mv x1010 380mv x1011 370mv the final output swing is about (the termnation voltage + 400mv)/2. in digital termination mode hs_term_sel: 1 00000 for max swing ? 11111 for min swing force_dp_pulldown it is used to force phy input signal dp_pulldown to a specific value. 0 disable 1 enable force_dm_pulldown it is used to force phy input signal dm_pulldown to a specific value. 0 disable 1 enable. force_drv_vbus it is used to force phy input signal drvvbus to a specific value. 0 disable 1 enable usb+0608h phy control register 3 phycr3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aioi_sel[2:0] ghx_sel[3:0] clkm ode[0] xtal_bias[2:0] test_ctrl[3:0] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pll_dr[5:0] fen_h s_tx_i fen_f s_ls_ rcv fen_f s_ls_ tx iref_ mode _sel fen_h s_rcv iadj[2:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 453 of 1535 type r/w r/w r/w r/w r/w r/w r/w reset 6?b001010 0 0 0 0 0 3?b100 iadj hs tx bias current selection 000 840mv(rext + 300) 001 830mv(rext + 300) 010 820mv(rext + 300) 011 810mv(rext + 300) 100 800mv(rext + 300) 101 790mv(rext + 300) 110 780mv(rext + 300) 111 770mv(rext + 300) rext = 5.1k (typ.) fen_hs_rcv forced hs rcv and squelch enable for test purpose 0 disable 1 enable iref_mode_sel hs sq reference current mode selection d 0: hs sq current always enabled while usb operating d 1: hs sq current enabled while hs rx module enabled fen_fs_ls_tx forced fs/ls output enable for test purpose 0 disable 1 enable fen_fs_ls_rcv forced fs/ls rcv enable for test purpose d 0 disable 1 enable fen_hs_tx_i forced hs tx current source enable for test purpose d 0 disable 1 enable pll_dr pll div ratio 480/reference clk=pll_dr ex: 30mhz xtal case, pll_dr = 480/30 = 16 = 0x10 test_ctrl test mode control test_ctrl[3]:0: normal utmi operation 1: 240mhz clock ouput, with while test_ctrl[0]=1 and fen_hs_tx_i=11 test_ctrl[3]: 0 normal utmi operation 1 240mhz clock output ,with while test_ctrl[0]=1 and fen_hs_tx_i=11 test_ctrl[2]: 0 no tx early 1 tx_early test_ctrl[1]: 0 turn off 100k ohm register pull up dm signal 1 turn on 100k ohm register pull up dm signal test_ctrl[0]: 0 normal utmi operation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 454 of 1535 1 tx controlled by fen_hs_tx_i/fen_fs_ls_tx xtal_bias xtal bias selection reserved clkmode external/internal input clk source selection x00 internal clk source usb_inta1_ck x01 internal clk source usb_inta2_ck x10 internal clk source usb_intd_ck ghx_sel ghx digital output selection xx00 none xx01 hs disc output for usb 2.0 rxdc test(set dout1_sel) xx10 hs sq output for usb 2.0 rxdc test(set dout1_sel) xx11 hs rx output for usb 2.0 rxdc test(set dout1_sel) aio1_sel analog io1 selection for test (io via xtali pin) 0xxx disable aio1 100 external bgr input 101 monitor internal bgr voltage 110 monitor internal pll loop filter voltage 111 monitor internal hs termination control voltage aio ouput only valid for xtali_gpio_en=1 & xtali_gpio_oe=0 usb+060ch phy control register 4 phycr4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clkm ode[1] hs_di scth[ 2] tx_fl ush_e n xtali _gpio _oe xtalo _gpio _es xtalo _gpio _en xtali _gpio _i xtali _gpio _oe xtali _gpio _es xtali _gpio _en xtali _gpio _i type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bgr_div[1:0] bgr_ selph bgr_ chip_ en bgr_i src_e n bgr_ clk_e n bgr_ bgr_ en dout2_sel[2:0] dout1_sel[2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 2?b01 0 1 0 0 0 3?b100 3?b100 dout1_sel digital output 1 selection for test (output via vrt pin) 000 normal function 001 bgr ph1 010 bgr ph1s 011 bgr pheq 100 usb 2.0 rx dc test (see ghx_sel) 101 usb 1.1 rxm 110 usb 1.1 rxp 111 usb 1.1 rxd dout1 ouput only valid for xtali_gpio_en=1 & xtali_gpio_oe=1 dout2_sel digital output 2 selection for test (output via vrt pin) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 455 of 1535 000 normal function x01 bgr ph2 x10 bgr ph2s_ x11 bgr pho_ dout2 ouput only valid for xtalo_gpio_en=1 & xtalo_gpio_oe=1 bgr_bgr_en force bgr enable 0: disable 1: enablebgrclken bgr_clk_en force bgr chop clock enable 0: disable 1: enable bgr_isrc_en force bgr current source generator enable 0: disable 1: enable bgr_chp_en bgr chop enable 0: disable 1: enable bgr_div bgr chop clk rate 00 836k 11 836k/2 10 836k/4 11 836k/8 xtali_gpio_i it?s used to control gpio output data when xtali pin gpio function is enabled. xtali_gpio_en enable xtali pin gpio function. xtali_gpio_es it?s used to control gpio output driving strength when xtali pin gpio function is enabled. xtali_gpio_oe it?s used to enable gpio output function when xtali pin gpio function is enabled. xtalo_gpio_i it?s used to control gpio output data when xtalo pin gpio function is enabled. xtalo_gpio_en enable xtalo pin gpio function. xtalo_gpio_es it?s used to control gpio output driving strength when xtalo pin gpio function is enabled. xtalo_gpio_oe it?s used to enable gpio output function when xtali pin gpio function is enabled. tx_flush_en when this bit is set , then txfifo write pointer will be reset when flushfifo. when this bit is not set, then txfifo write pointer won?t be reset when flushfifo. usb+0610h phy control register 5 phycr5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dm_p ull_d own dp_pu ll_do wn xcvr_selec t[1:0] susep ndm term_ selec t op_mode[1:0 ] froc e_idp ullup utmim uxsel usb_mode[1: 0] froc e_xve r_sel ect froc e_sus pend m froc e_ter m_sel ect forc e_op_ mode type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name probe_sel[7:0] vbus_ cmp_ en clk_div_cnt[2:0] cdr_filt[3:0] type r/w r/w r/w r/w reset 0 1 0 4?b0010 cdr_filt cdr low pass filter selection, debug usage clk_divc_cnt the divide ratio of div_ck probe_sel debug signal selection force_opmode it is used to force phy input signal opmode to a specific value. 1: enable. 0: disable. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 456 of 1535 force_term_select it is used to force phy input signal term_select to a specific value. 1: enable. 0: disable. force_suspendm it is used to force phy input signal suspendm to a specific value. 1: enable. 0: disable. force_xcvr_select it is used to force phy input signal xcvr_select to a specific value. 1: enable. 0: disable. usb_mode test mode selectio n ( for testing) 00 normal operation 01 loop-back mode1 enable, the pseudo random number will be generated inside usb2.0 phy macro and transmit onto usb bus. the data will be received by receiver and then be compared. the compared result is muxed on line_state[1] and should be always be 1. 10 loop-back mode2 enable, the packet is longer. utmi_muxsel it is used to force all phy utmi input signals to specific values 0 disable 1 enable . force_idpullup it is used to force phy input signal idpullup to a specific value. 0 disable 1 enable opmode it is used to control phy input signal opmode when force_opmode = 1 or utmi_muxsel = 1. termsel it is used to control phy input signal termsel when force_termsel = 1 or utmi_muxsel = 1. suspendm it is used to control phy input signal suspendm when force_suspendm = 1 or utmi_muxsel = 1. xcvrsel it is used to control phy input signal xcvrsel when force_xcvrsel = 1 or utmi_muxsel = 1. dppulldown it is used to control phy input signal dppulldown when force_dppulldown = 1 or utmi_muxsel = 1. dmpulldown it is used to control phy input signal dmpulldown when force_dmpulldown = 1 or utmi_muxsel = 1. usb+0614h phy utmi interface register 1 phyir1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name linestate[1: 0] host disc_ on txrea dy rxer ror rxac tive rxval idh rxval id xdata_out[15:8] type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xdata_out[7:0] xdata_in[3:0] tx_va lidh tx_va lid drvv bus idpul lup type r r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 idpullup it is used to control phy input signal idpullup when force_idpullup = 1 or utmi_muxsel = 1. drvvbus it is used to control phy input signal drvvbus when force_drvvbus = 1 or utmi_muxsel = 1. tx_valid it is used to control phy input signal tx_valid when force_txvalid = 1 or utmi_muxsel = 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 457 of 1535 tx_validh it is used to control phy input signal tx_validh when force_txvalidh = 1 or utmi_muxsel = 1. xdata_in it is used to control phy input signal xdata_in when force_datain = 1 or utmi_muxsel = 1. xdata_out it is used to control phy input signal idpullup when force_idpullup = 1 or utmi_muxsel = 1. rxvalid it indicates the phy output signal rxvalid status. rxvalidh it indicates the phy output signal rxvalidh status. rxactive it indicates the phy output signal rxactive status. rxerror it indicates the phy output signal rxerror status. txready it indicates the phy output signal txready status. hostdiscon it indicates the phy output signal hostdiscon status. line_state it indicates the phy output signal line_state status. usb+0618h phy utmi interface register 2 phyir2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name forc e_aux _en forc e_otg _pro be forc e_usb _clko n forc e_bva lid forc e_iddi g forc e_vbu svali d forc e_ses send forc e_ava lid usb_reserved[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name usb_reserved[7:0] iddig vbus valid sesse nd avali d type r/w r r r r reset 0 0 0 0 0 force_avalid it is used to force phy input signal avalid to a specific value. 1: enable. 0: disable. force_sessend it is used to force phy input signal sessend to a specific value. 1: enable. 0: disable. force_vbusvalid it is used to force phy input signal vbusvalid to a specific value. 1: enable. 0: disable. force_iddig it is used to force phy input signal idig to a specific value. 1: enable. 0: disable. force_bvalid it is used to force phy input signal bvalid to a specific value. 1: enable. 0: disable. force_usb_clkon it is used to force phy input signal usb_clkoff to a specific value. 1: enable. 0: disable. force_otg_probe it is used to force phy input signal otg_probe to a specific value. 1: enable. 0: disable. force_aux_en it is used to force phy input signal aux_en to a specific value. 1: enable. 0: disable. avalid it indicates the otg avalid comparator result. 0 avalid< 0.8v 1 avalid > 2v sessend it indicates the otg sessend comparator result. 0 sessend< 0.2v 1 sessend > 0.8v free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 458 of 1535 vbusvalid it indicates the otg vbus comparator result. 0 vbus< 4.4v 1 vbus > 4.75v iddig it indicates the id pin comparator result when idpullup = 1. 0 a-plug is plugged in. 1 b-plug is plugged in usb+061ch phy utmi interface register 3 phyir3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aux_e n otg_p robe usb_c lkon bvali d_w iddig_ w vbus valid _w sesse nd_w avali d_w type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 avalid_w it is used to control phy input signal avalid when force_avalid = 1 or utmi_muxsel = 1 sessend_w it is used to control phy input signal sessend when force_sessend = 1 or utmi_muxsel = 1. vbusvalid_w it is used to control phy input signal vbusvalid when force_vbusvalid = 1 or utmi_muxsel = 1. iddig_w it is used to control phy input signal iddig when force_iddig = 1 or utmi_muxsel = 1. bvalid_w it is used to control phy input signal bvalid when force_bvalid = 1 or utmi_muxsel = 1. usb_clkon usb phy input 48mhz clock source signal enable 0: disable 1: enable otg_probe otg debug signal enable 0: disable 1: enable aux_en uart usb share pad function enable 0: disable 1: enable 2.30.3 power on/off usb phy and controller sequence 1 power on sequence after plug-in. 1.1 turn on vusb(phy 3.3v power) ? the control register is in pmic document. 1.2 turn on usb ahb clock(52mhz) ? the control register is in config document. 1.3 turn on internal 48mhz pll ? the control register is in clock document. 1.4 wait 50 usec. (phy 3.3v power stable time) 1.5 it should set force_aux_en= 0 and force_usb_clkon = 1 to enable 48mhz pll and switch to usb function. ? reg[usb+061bh] = 0x20. 1.6 turn on bandgap ? reg[usb+060dh] bit0 = 1. (bgr_bgr_en). 1.7 wait 10 usec. 1.8 release force suspendm. ? reg[usb+0612h] bit2 = 0. (force_suspendm) 1.9 wait 20 usec. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 459 of 1535 1.10 pll_en = 1. ? reg[usb+0600h] bit7 = 1. 2 power off sequence after plug-out. 2.1 force suspendm = 0. ? reg[usb+0613h] bit3 = 0.(suspendm) and reg[usb+0612h] bit2 = 1.(force_suspendm) 2.2 wait 6 * 33.33ns 2.3 pll_en = 0. ? reg[usb+0600h] bit7 = 0 2.4 turn off bandgap ? reg[usb+060dh] bit0 = 0. (bgr_bgr_en). 2.5 turn off vusb(phy 3.3v power) ? the control register is in pmic document 3 initialzation sequence 3.1 pll_ccp[3:0]=0x3; (for better jitter performance). 3.2 test_ctrl[2] = 1; (for better jitter performance. turn on tx earrlier). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 460 of 1535 3 modem micro-controller unit subsystem figure 43 illustrates the block diagram of the modem micro-controller unit subsystem in MT6516. the subsystem utilizes a main 32-bit arm7ej-s risc proces sor, which plays the role of the main bus master controlling the whole subsystem. all proc essor transactions go to core cach e first. the core cache controller accesses tcm (96kb memory dedicated to arm7ejs core), cache memory, or bus according to the processor?s request address. if the requested content is found in tcm or in cache, no bus transaction is required. if the core cache hit rate is high enough, bus traffic can be effectively reduced and processor core performance maximized. in addition to the benefits of reuse of memory contents, core cache also has a mpu (memory protection unit), which allows cacheable and protection settings of predefined regions. the contents of core cache are only accessible to mcu. the bus comprises of two-level system buses: advanced high-performance bus (ahb) and advanced peripheral bus (apb). all bus transactions originate from bus masters, while slaves can only respond to requests from bus masters. before data transfer can be established, the bus master must ask for bus ownership, accomplished by request-grant handshaking protocol between masters and arbiters. two levels of bus hierarchy are designed to provide optimum usage for different performance requirements. specifically, ahb bus, the main system bus, is tailored toward high-speed requirements and provides 32-bit data path with multiplex scheme for bus interconnections. the apb bus, on the other hand, is designed to reduce interface complexity for lower data transfer rate, and so it is isolated from high bandwidth ahb bus by apb bridge. apb bus supports 16-bit addressing and 32-bit data path. apb bus is also optimized for minimal power consumption by turning off the clock when there is no apb bus activity. during operation, if the target slave is located on ahb bus, the transaction is conducted directly on ahb bus. however, if the target slave is a peripheral and is attached to the apb bus, then the transaction is conducted between ahb and apb bus through the use of apb bridge. the MT6516 modem mcu subsystem supports only memory addressing method. therefore all components are mapped onto the mcu 32-bit address space. a memory management unit is employed to allow for a central decode scheme. the mmu generates appropriate selection signals for each memory-addressed module on the ahb bus. in order to off-load the processor core, a dma controller is designated to act as a master and share the bus resources on ahb bus to perform fast data movement between modules. this controller provides five dma channels. the interrupt controller provides a software interface to manipulate interrupt events; it can handle up to 32 interrupt sources asserted at the same time. in general, the controller generates 2 levels of interrupt requests, fiq and irq, to the processor. for factory programming purposes, a boot rom module is also integrated. this module uses internal memory controller to connect to ahb bus. MT6516 is fabricated using 65nm process. in deep-submicron process, leakage power dominates entire power consumption. therefore, several power saving techniques are applied, such as mtcmos (multi- threshold cmos). if the system is not working, power can be switched off to save standby leakage power. modem mcu subsystem is a non-power-down subsystem, and other subsystem will be powered off if not using. several submodules in other subsystem which cannot be powered down are moved into modem mcu subsystem, like shreg1, shreg2, tdma, afc, sleep_ctrl, etc, which locate in modem 2g subsystem originally. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 461 of 1535 mcu-dsp interface arm7ej-s system rom dma controller apb bridge peripheral peripheral interrupt controller internal memory controller arbiter ahb bus apb bus usb core cache to emi figure 43 block diagram of the modem micro-controller unit subsystem in MT6516 3.1 processor core 3.1.1 general description the modem micro-controller unit subsystem in MT6516 uses the 32-bit arm7ej-s risc processor that is based on the von neumann architecture with a single 32-bit data bus that carries both instructions and data. the memory interface of arm7ej-s is totally compliant with the amba based bus system, which allows direct connection to the ahb bus. in mt 6516, arm7ej-s processor supports two operational frequencies : 104 & 52mhz, whereas in tk6516 arm7 only operates in 104mhz. 3.2 memory management 3.2.1 general description the processor core of MT6516 supports only a memory addressing method for instruction fetch and data access. the core manages a 32-bit address space that has addressing capability of up to 4 gb. system rom, registers, mcu peripherals and external components are all mapped onto such 32-bit address space, as depicted in figure 2-2 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 462 of 1535 bank bank0 bank1 bank2 bank3 bank4 bank5 bank6 bank7 bank8 bank9 bank10 bank11 bank12 bank13 bank14 bank15 base address description 0000_0000h 1000_0000h 2000_0000h 3000_0000h 4000_0000h 4800_0000h 5000_0000h 6000_0000h 6100_0000h 7000_0000h 8000_0000h 9000_0000h a000_0000h a100_0000h a200_0000h a300_0000h b000_0000h c000_0000h d000_0000h e000_0000h f000_0000h emi bank 0 / boot code emi bank 1 reserved reserved reserved reserved reserved reserved reserved emi bank 2 emi bank 3 system rom tcm usb virtual fifo apb peripheral share ram if 1 share ram if 2 idma 1 idma 2 reserved figure 44 the memory layout of MT6516 the address space is organized into blocks of 256 mb each. the block number is uniquely selected by address line a31-a28 of the internal system bus. 3.2.1.1 external access to allow external access, the MT6516 outputs 27 bits (a26-a0) of address lines along with 4 selection signals that correspond to associated memory blocks. that is, MT6516 can support up to 4 mcu addressable external components. the data width of internal system bus is fixed at 32-bit wide, while the data width of the external components can be 8-, 16- or 32- bit. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 463 of 1535 since devices are usually available with varied operating grades, adaptive configurations for different applications are needed. MT6516 provides software programmable registers to configure their wait-states to adapt to different operating conditions. 3.2.1.2 memory re-mapping mechanism to permit more flexible system configuration, a memory re-mapping mechanism is provided. the mechanism allows software program to swap bank0 (ecs0#) and bank1 (ecs1#) dynamically. whenever the bit value of rm0 in register emi_gena is changed, these two banks are swapped accordingly. furthermore, it allows system to boot from system rom as detailed in 2.2.1.3 boot sequence. 3.2.1.3 boot sequence since the arm7ej-s core always starts to fetch instructions from the lowest memory address at 00000000h after system has been reset, the system is designed to have a dynamic mapping architecture capable of associating boot code, external flash or external sram with the memory block 0000_0000h ? 0fff_ffffh. both modem side arm7ej-s and ap side arm926ej-s start to fetch instruction at 0x00000000h and execute the same program by default. if two cores would like to execute separate codes respectively, register emi_gene bit 0-15 should be configured to specify the offset address value for modem side mcusys. by default, the boot code is mapped onto 0000_0000h ? 0fff_ffffh after a system reset. in this special boot mode, external memory controller does not access external memory; instead, the emi controller send predefined boot code back to the arm7ej-s core, which instructs the processor to execute the program in system rom. this configuration can be changed by programming bit value of rm1 in register emi_gena directly. MT6516 system provides one boot up scheme: z start up system of running codes from boot code for factory programming or nand flash boot. 3.2.1.3.1 boot code the boot code is placed together with memory re-mapping mechanism in external memory controller, and comprises of just two words of instructions as shown be low. a jump instruction leads the processor to run the code starting at address 4800_0000h where the system rom is placed. address binary code assembly 00000000h e51ff004h ldr pc, 0x4 00000004h 48000000h (data) 3.2.1.3.2 factory programming the configuration for factory programming is shown in figure 2-3 . usually the factory programming host connects with MT6516 via the uart interface. the download speed can be up to 921k bps while mcu is running at 26mhz. after the system has reset, the boot code guides the processor to run the factory programming software placed in system rom. then, MT6516 starts and polls the uart1 port until valid information is detected. the first information received on the uart1 is used to configure the chip for factory programming. the flash downloader program is then transferred into system ram or external sram. further information is detailed in the mt 6516 software programming specification. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 464 of 1535 MT6516 factory programming host flash uart external memory interface figure 45 system configuration required for factory programming 3.2.1.3.3 nand flash booting if MT6516 cannot receive data from uart1 for a certain amount of time, the program in system rom checks if any valid boot loader exists in nand flash. if found, the boot loader code is copied from nand flash to ram (external) and executed to start the real application software. if no valid boot loader can be found in nand flash, MT6516 starts executing code in emi bank0 memory. the whole boot sequence is shown in the following figure. boot from system rom check uart input receive from uart copy loader from nand to ram valid loader on nand y n y n factory programming boot from loader in ram boot from emi bank 0 boot from system rom check uart input receive from uart copy loader from nand to ram valid loader on nand y n y n factory programming boot from loader in ram boot from emi bank 0 figure 46 boot sequence free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 465 of 1535 3.2.1.4 little endian mode the MT6516 system always treats 32-bit words of memory in little endian format. in little endian mode, the lowest numbered byte in a word is stored in the least significant position, and the highest numbered byte in the most significant position. byte 0 of the memory system is therefore connected to data lines 7 through 0. 3.3 bus system 3.3.1 general description two levels of bus hierarchy are employed in the modem micro-controller unit subsystem of MT6516. as depicted in figure 43 , ahb bus and apb bus serve as system backbone and peripheral buses, while an apb bridge connects these two buses. both ahb and apb buses operate at the same or half the clock rate of processor core. the apb bridge is the only bus master residing on the apb bus. all apb slaves are mapped onto memory block mb8 in the mcu 32-bit addressing space. a central address decoder is implemented inside the bridge to generate select signals for individual peripherals. in addition, since the base address of each apb slave is associated with select signals, the address bus on apb contains only the value of offset address. the maximum address space that can be allocated to a single apb slave is 64 kb, i.e. 16-bit address lines. the width of the data bus is mainly constrained to 32 bits. in the case where an apb slave needs large amount of transfers, the device driver can also request dma channels to conduct a burst of data transfer. the base address and data width of each peripheral are listed in table 54 . table 54 register base addresses for mcu peripherals address description data width software base id 8001_0000h configuration registers (clock, power down and reset) 32 confgsys_confg_base 8002_0000h general purpose inputs/outputs 16 mdgpio_base 8003_0000h reset generation unit 16 mdrgu_base 8100_0000h external memory interface 32 emi_base 8101_0000h interrupt controller 32 mdcirq_base 8102_0000h dma controller 32 mddma_base 8103_0000h uart 1 16 uart1_base 8104_0000h uart 2 16 uart2_base 8105_0000h uart 3 16 uart3_base 8106_0000h general purpose timer 16 mdgpt_base 810a_0000h sim 16 sim_base 8112_0000h nand flash interface 32 nfi_base 8116_0000h ccif 32 ccif_base 8119_0000h mcu-dsp shared register 1 16 share1_base 811b_0000h log accelerator 32 la_base free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 466 of 1535 811c_0000h mdmcusys configuration register 32 mdmcusys_confg_base 811d_0000h uart 4 16 uart4_base 811e_0000h mcu-dsp shared register 2 16 share2_base 811f_0000h tdma timer 32 tdma_base 8120_0000h automatic frequency control unit 13 afc_base 8121_0000h sim2 16 sim2_base 8122_0000h nfiecc 32 nfiecc_base 8200_0000h md2gsys configuration register 32 md2gsys_confg_base 8201_0000h baseband serial interface 32 bsi_base 8202_0000h baseband parallel interface 16 bpi_base 8204_0000h automatic power control unit 32 apc_base 8206_0000h divider/modulus coprocessor 32 divider_base 8207_0000h frame check sequence 16 fcs_base 8208_0000h gprs cipher unit 32 gcu_base 8209_0000h csd format conversion coprocessor 32 csd_acc_base 820a_0000h mcu-dsp shared register 1 16 shared1_base 820b_0000h irdbg1 16 irdbg1_base 820c_0000h mcu-dsp shared register 2 16 shared2_base 820d_0000h irdbg2 16 irdbg2_base 820e_0000h dsp patch unit 16 patch_base 820f_0000h video front end 32 vfe_base 8210_0000h baseband front end 16 bfe_base 8301_0000h analog interface controller 16 mixed_base 3.4 interrupt controller 3.4.1 general description figure 47 outlines the major functionality of the mcu interrup t controller. the interrupt controller processes all interrupt sources coming from external lines and internal mcu peripherals. since arm7ej-s core supports two levels of interrupt latency, this controller generates two request signals: fiq for fast, low latency interrupt request and irq for more gener al interrupts with lower priority. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 467 of 1535 z a z figure 48 block diagram of the interrupt controller one and only one of the interrupt sources can be assigned to fiq controller and have the highest priority in requesting timing critical service. all the others share the same irq signal by connecting them to irq controller. the irq controller manages up 32 interrupt lines of irq0 to irq31 with fixed priority in descending order. the interrupt controller provides a simple software interf ace by mean of registers to manipulate the interrupt request shared system. irq selection registers and fiq selection register determine the source priority and connecting relation among sources and interrupt lines. irq source status register allows software program to identify the source of interrupt that generates the interrupt request. irq mask register provides software to mask out undesired sources some time. end of interrupt register permits software program to indicate to the controller that a certain interrupt service routine has been finished. binary coded version of irq source status register is also made available for software program to helpfully identify the interrupt source. note that while taking advantage of this feature, it should also take the binary coded version of end of interrupt register coincidently. the essential interrupt table of arm7ej-s core is shown as table 55 . address description 00000000h system reset 00000018h irq 0000001ch fiq table 56 interrupt table of arm7ej-s 3.4.1.1 interrupt source masking interrupt controller provides the function of interrupt source masking by the way of programming mask register. any of them can be masked individually. interrupt input multiplex fiq controlle r irq controller registers fiq irq irq0 irq1 irq2 irqn irq31 softirq a pb bus gpi tdm a gpt uart sim usb dma dsp2mcu free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 468 of 1535 however, because of the bus latency, th e masking takes effect no earlier than 3 clock cycles later. in this time, the to-be-masked interrupts could come in and generate an irq pulse to mcu, and then disappear immediately. this irq forces mcu going to interrupt service routine and polling status register (irq_sta(irq_stah+irq_stal) or irq_sta2), but the register shows there is no interrupt. this might cause mcu malfunction. there are two ways for programmer to protect their software. 1. return from isr (interrupt service routine) immediately while the status register shows no interrupt. 2. set i bit of mcu before doing interrupt masking, and then clear it after interrupt masking done. both avoid the problem, but the first item recommended to have in the isr. 3.4.1.2 external interrupt this interrupt controller also integrates an external interrupt controller that can support up to 21 interrupt requests coming from external sources, the eint0~20, and 3 wakeup interrupt requests, i.e. eint21~23, coming from peripherals used to inform system to resume the system clock. eint0~eint4 interrupt source can be configured as from external pin or internal peripherals. the external interrupts can be used for different kind of applications, mainly for event detections: detection of hand free connection, detection of hood opening, detection of battery charger connection. since the external event may be unstable in a certain period, a de-bounce mechanism is introduced to ensure the functionality. the circuitry is ma inly used to verify that the input signal remains stable for a programmable number of periods of the clock. when this condition is satisfied, for the appearance or the disappearance of the input, the output of the de-bounce logic changes to the desired state. note that, because it uses the 32 khz slow clock for performing the de-bounce process, the parameter of de-bounce period and de-bounce enable takes effect no sooner than one 32 khz clock cycle (~31.25us) after the software program sets them. when the sources of external interrupt controller are used to resume the system clock in sleep mode, the de- bounce mechanism must be enabled. however, the polarities of eints are clocked with the system clock. any changes to them take effect immediately. z z figure 49 block diagram of external interrupt controller free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 469 of 1535 3.4.1.3 external interrupt input pins ei n t edge / level hw debounc e source pin suppleme nt ei n t0 edge / level yes if (gpio59 m==1) then eint0= usb dp pin else eint0= gpio59 ei n t1 edge / level yes if (gpio60 m==1) then eint1= uart1_rxd else eint1= gpio60 ei n t2 edge / level yes if (gpio61 m==1) then eint2= urxd2 else eint2= gpio61 ei n t3 edge / level yes if (gpio62 m==1) then eint3 = urxd3 else eint3= gpio62 ei n t4 edge / level yes if(gpio63_m==1) then eint4=gpio63 else eint4=1 ei n t5 edge / level yes if(gpio64_m==1) then eint5=gpio64 else eint5=1 ei n t6 edge / level yes if(gpio65_m==1) then eint6=gpio65 else eint6=1 ei n t7 edge / level yes if(gpio66_m==1) then eint7=gpio66 else eint7=1 ei n t8 edge / level yes if(gpio21_m==1) then eint8=gpio21 else eint8=1 ei n t9 edge / level yes if(gpio22_m==3) then eint9=gpio22 else eint9=1 ei n t1 0 edge / level yes if(gpio87_m==3) then eint10=gpio87 else eint10=1 ei n t1 1 edge / level yes if(gpio88_m==3) then eint11 =gpio88 else eint11=1 ei n t1 2 edge / level yes if(gpio89_m==3) then eint12=gpio89 else eint12=1 ei n t1 edge / level yes if(gpio90_m==3) then eint13=gpio90 else eint13=1 1. gpios should be in the input mode and are effected by gpio data input inversion registers. 2. gpioxx_m is the gpio mode control registers, please refer to gpio segment. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 470 of 1535 3 ei n t1 4 edge / level yes if(gpio91_m==3) then eint14=gpio91 else eint14=1 ei n t1 5 edge / level yes if(gpio1_m==3) then eint15=gpio1 else eint15=1 ei n t1 6 edge / level yes if(gpio54_m==2) then eint16=gpio54 else eint16=1 ei n t1 7 edge / level yes if(gpio55_m==3) then eint17=gpio55 else eint17=1 ei n t1 8 edge / level yes if(gpio56_m==2) then eint18=gpio56 else eint18=1 ei n t1 9 edge / level yes if(gpio57_m==2) then eint19=gpio57 else eint19=1 ei n t2 0 edge / level yes if(gpio58_m==2) then eint20=gpio58 else eint20=1 ei n t2 1 edge / level yes usb20 iddig ei n t2 2 edge / level yes usb20 vbusvalid ei n t2 3 edge / level yes cpu interface irq_b register address register name synonym mdcirq + 0000h irq selection 0 register mdirq_sel0 mdcirq + 0004h irq selection 1 register mdirq_sel1 mdcirq + 0008h irq selection 2 register mdirq_sel2 mdcirq + 000ch irq selection 3 register mdirq_sel3 mdcirq + 0010h irq selection 4 register mdirq_sel4 mdcirq + 0014h irq selection 5 register mdirq_sel5 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 471 of 1535 mdcirq + 0018h fiq selection register mdfiq_sel mdcirq + 001ch irq mask register mdirq_mask mdcirq + 0020h irq mask disable register mdirq_mask_dis mdcirq + 0024h irq mask enable register mdirq_mask_en mdcirq + 0028h irq status register mdirq_sta mdcirq + 002ch irq end of interrupt register mdirq_eoi mdcirq + 0030h irq sensitive register mdirq_sens mdcirq + 0034h irq software interrupt register mdirq_soft mdcirq + 0038h fiq control register mdfiq_con mdcirq + 003ch fiq end of interrupt register mdfiq_eoi mdcirq + 0040h binary coded value of irq_status mdirq_sta2 mdcirq + 0044h binary coded value of irq_eoi mdirq_eoi2 mdcirq + 0100h eint status register mdeint_sta mdcirq + 0104h eint mask register mdeint_mask mdcirq + 0108h eint mask disable register mdeint_mask_dis mdcirq + 010ch eint mask enable register mdeint_mask_en mdcirq + 0110h eint interrupt acknowledge register mdeint_intack mdcirq + 0114h eint sensitive register mdeint_sens mdcirq + 0120h eint0 de-bounce control register mdeint0_con mdcirq + 0130h eint1 de-bounce control register mdeint1_con mdcirq + 0140h eint2 de-bounce control register mdeint2_con mdcirq + 0150h eint3 de-bounce control register mdeint3_con mdcirq + 0160h eint4 de-bounce control register mdeint4_con mdcirq + 0170h eint5 de-bounce control register mdeint5_con mdcirq + 0180h eint6 de-bounce control register mdeint6_con mdcirq + 0190h eint7 de-bounce control register mdeint7_con mdcirq + 01a0h eint8 de-bounce control register mdeint8_con mdcirq + 01b0h eint9 de-bounce control register mdeint9_con mdcirq + 01c0h eint10 de-bounce control register mdeint10_con mdcirq + 01d0h eint11 de-bounce control register mdeint11_con mdcirq + 01e0h eint12 de-bounce control register mdeint12_con mdcirq + 01f0h eint13 de-bounce control register mdeint13_con mdcirq + 0200h eint14 de-bounce control register mdeint14_con mdcirq + 0210h eint15 de-bounce control register mdeint15_con mdcirq + 0220h eint16 de-bounce control register mdeint16_con mdcirq + 0230h eint17 de-bounce control register mdeint17_con mdcirq + 0240h eint18 de-bounce control register mdeint18_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 472 of 1535 mdcirq + 0250h eint19 de-bounce control register mdeint19_con mdcirq + 0260h eint20 de-bounce control register mdeint20_con mdcirq + 0270h eint21 de-bounce control register mdeint21_con mdcirq + 0280h eint22 de-bounce control register mdeint22_con mdcirq + 0290h eint23 de-bounce control register mdeint23_con table 57 interrupt controller register map 3.4.2 register definitions mdcirq+0000 h irq selection 0 register mdirq_sel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq5 irq4 irq3 type r/w r/w r/w reset 5 4 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq2 irq1 irq0 type r/w r/w r/w reset 2 1 0 mdcirq+0004 h irq selection 1 register mdirq_sel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irqb irqa irq9 type r/w r/w r/w reset b a 9 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq8 irq7 irq6 type r/w r/w r/w reset 8 7 6 mdcirq+0008 h irq selection 2 register mdirq_sel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq11 irq10 irqf type r/w r/w r/w reset 11 10 f bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqe irqd irqc type r/w r/w r/w reset e d c mdcirq+000 ch irq selection 3 register mdirq_sel3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 473 of 1535 name irq17 irq16 irq15 type r/w r/w r/w reset 17 16 15 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq14 irq13 irq12 type r/w r/w r/w reset 14 13 12 mdcirq+0010 h irq selection 4 register mdirq_sel4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1d irq1c irq1b type r/w r/w r/w reset 1d 1c 1b bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq1a irq19 irq18 type r/w r/w r/w reset 1a 19 18 mdcirq+0014 h irq selection 5 register mdirq_sel5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq1f irq1e type r/w r/w reset 1f 1e mdcirq+0018 h fiq selection register mdfiq_sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fiq type r/w reset 0 the irq/fiq selection registers provide system designers with a flexible routing scheme to make various mappings of priority among interrupt sources possible. the registers allow the interrupt sources to be mapped onto interrupt requests of either fiq or irq. while only one interrupt source can be assigned to fiq, the other ones share irqs by mapping them onto irq0 to irq1f connected to irq controller. the priority sequence of irq0~irq1f is fixed, i.e. irq0 > irq1 > irq2 > ? > irq1e > irq1f. during the software configuration process, the interrupt source code of desired interrupt source should be written into source free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 474 of 1535 field of the corresponding irq_sel0-irq_sel4/fiq_sel. 5-bit interrupt source codes for all interrupt sources are fixed and defined. interrupt source sta2 (hex) sta gpi_fiq 0 00000001 tdma_ctirq1 1 00000002 tdma_ctirq2 2 00000004 dsp12cpu 3 00000008 dsp22cpu 4 00000010 sim1 5 00000020 tdma 6 00000040 uart1 7 00000080 uart2 8 00000100 uart3 9 00000200 gptimer a 00000400 eint b 00000800 usb c 00001000 gpi_mirq d 00002000 wdt e 00004000 usb1 f 00008000 irdbg1 10 00010000 irdbg2 11 00020000 nfi 12 00040000 ccif 13 00080000 dma 14 00100000 emi 15 00200000 uart4 16 00400000 la 17 00800000 sim2 18 01000000 nfi_ecc 19 02000000 table 58 interrupt source code for interrupt sources z fiq, irq0-1f the 5-bit content of this field corresponds to an interrupt source code shown above. mdcirq+001 ch irq mask register mdirq_mask bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 475 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register contains a mask bit for each interrupt line in irq controller. the register allows each interrupt source irq0 to irq1f to be disabled or masked separately under software control. after a system reset, all bit values are set to 1 to indicate that interrupt requests are prohibited. z irq0-1f mask control for the associated interrupt source in the irq controller z 0 interrupt is enabled z 1 interrupt is disabled mdcirq+0020 h irq mask clear register mdirq_mask_ clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c this register is used to clear bits in irq mask register. when writing to this register, the data bits that are high cause the corresponding bits in irq mask register to be cleared. data bits that are low have no effect on the corresponding bits in irq mask register. z irq0-1f clear corresponding bits in irq mask register. z 0 no effect z 1 disable the corresponding mask bit mdcirq+0024 h irq mask set register mdirq_mask_ set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s this register is used to set bits in the irq mask register . when writing to this regi ster, the data bits that are high cause the corresponding bits in irq mask register to be set. data bits that are low have no effect on the corresponding bits in irq mask register. z irq0-1f set corresponding bits in irq mask register. z 0 no effect z 1 enable corresponding mask bit free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 476 of 1535 mdcirq+0028 h irq source status register mdirq_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 ir q3 irq2 irq1 irq0 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register allows software to poll which interrupt line has generated an irq interrupt request. a bit set to 1 indicates a corresponding active interrupt line. only one flag is active at a time. the irq_sta is type of read-clear; write access has no effect on the content. z irq0-1f interrupt indicator for the associated interrupt source. z 0 the associated interrupt source is non-active. z 1 the associated interrupt source is asserted. mdcirq+002 ch irq end of interrupt register mdirq_eoi bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register provides a mean for software to relinquish and to refresh the interrupt controller. writing a 1 to a specific bit position results in an end of interrupt command issued internally to the corresponding interrupt line. z irq0-1f end of interrupt command for the associated interrupt line. z 0 no service is currently in progress or pending z 1 interrupt request is in-service mdcirq+0030 h irq sensitive register mdirq_sens bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 477 of 1535 all interrupt lines of irq controller, irq0~irq1f can be programmed as either edge or level sensitive. by default, all the interrupt lines are edge sensitive and should be active low. once a interrupt line is programmed as edge sensitive, an interrupt request is t riggered only at the falling e dge of interrupt line, and the next interrupt is not accepted until the eoi command is given. however, level sensitive interrupts trigger is according to the signal level of the interrupt line. once the interrupt line become from high to low, an interrupt request is triggered, and anot her interrupt request is triggered if the signal level remain low after an eoi command. note that in edge sensitive mode, even if the signal level remains low after eoi command, another interrupt request is not triggered. that is because edge sensitive interrupt is only triggered at the falling edge. z irq0-1f sensitivity type of the associated interrupt source z 0 edge sensitivity with active low z 1 level sensitivity with active low mdcirq+0034 h irq software interrupt register mdirq_soft bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq1f irq1e irq1d irq1c irq1b irq1a irq19 irq18 irq17 irq16 irq15 irq14 irq13 irq12 irq11 irq10 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irqf irqe irqd irqc irqb irqa irq9 ir q8 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 setting ?1? to the specific bit position generates a software interrupt for corresponding interrupt line before mask. this register is used for debug purpose. z irq0-irq1f software interrupt mdcirq+0038 h fiq control register mdfiq_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sens mask type r/w r/w reset 0 1 this register provides a means for software program to control the fiq controller. z mask mask control for the fiq interrupt source z 0 interrupt is enabled z 1 interrupt is disabled z sens sensitivity type of the fiq interrupt source z 0 edge sensitivity with active low free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 478 of 1535 z 1 level sensitivity with active low mdcirq+003 ch fiq end of interrupt register mdfiq_eoi bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eoi type wo reset 0 this register provides a means for software to relinquish and to refresh the fiq controller. writing a ?1? to the specific bit position results in an end of interrupt command issued internally to the corresponding interrupt line. z eoi end of interrupt command mdcirq+0040 h binary coded value of irq_status mdirq_sta2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name noirq sta type rc rc reset 0 0 this register is a binary coded version of irq_sta. it is used by the software program to poll which interrupt line has generated the irq interrupt request in a much easier way. any read to it has the same result as reading irq_sta. the irq_sta2 is also read-only and read-clear; write access has no effect on the content. note that irq_sta2 should be coupled with irq_eoi2 while using it. z sta binary coded value of irq_sta z noirq indicating if there is an irq or not. if there is no irq, this bit is high, and the value of sta is 0_0000b. mdcirq+0044 h binary coded value of irq_eoi mdirq_eoi2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eoi type wo reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 479 of 1535 this register is a binary coded version of irq_eoi. it provides an easier way for software program to relinquish and to refresh the interrupt controller. writing a specific code results in an end of interrupt command issued internally to the corresponding interrupt line. note that irq_eoi2 should be coupled with irq_sta2 while using it. z eoi binary coded value of irq_eoi mdcirq+0100 h eint interrupt status register mdeint_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register keeps up with current status of which eint source generated the interrupt request. the status will be changed to zero if the corresponding eint source mask bit is set. z eint0-eint23 interrupt status z 0 no interrupt request is generated z 1 interrupt request is pending mdcirq+0104 h eint interrupt mask register mdeint_mask bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register controls whether or not eint source is allowed to generate an interrupt request. setting a ?1? to the specific bit position prohibits the external interrupt line from becoming active. z eint0-eint23 interrupt mask z 0 interrupt request is enabled. z 1 interrupt request is disabled. mdcirq+0108 h eint interrupt mask clear register mdeint_mask _clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 480 of 1535 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type w1c w1c w1c w1c w1c w1c w1c w1c bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c this register is used to clear individual mask bits. only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are cleared (set to 0). otherwise the interrupt mask bit retains its original value. z eint0-eint23 disable mask for the associated external interrupt source z 0 no effect. z 1 disable the corresponding mask bit. mdcirq+010 ch eint interrupt mask set register mdeint_mask _set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type w1s w1s w1s w1s w1s w1s w1s w1s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s w1s this register is used to set individual mask bits. only the bits set to 1 are in effect, and interrupt masks for which the mask bit is set are set to 1. otherwise the interrupt mask bit retains its original value. z eint0-eint23 disable mask for the associated external interrupt source. z 0 no effect. z 1 enable corresponding mask bit. mdcirq+0110 h eint interrupt acknowledge register mdeint_intac k bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 writing ?1? to the specific bit position is to acknowledge the interrupt request that correspondingly to the external interrupt line source. write this register to clear edge sensitive eint triggered status. write this register to clear eint edge status first, if the eint source is changed from level sensitive to edge sensitive. z eint0-eint23 interrupt acknowledgement z 0 no effect. z 1 interrupt request is acknowledged. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 481 of 1535 mdcirq+0114 h eint sensitive register mdeint_sens bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eint23 eint22 eint21 eint20 eint19 eint18 eint17 eint1 6 type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eint15 eint14 eint13 eint12 eint11 eint10 eint9 eint8 eint7 eint6 eint5 eint4 eint3 eint2 eint1 eint0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 sensitivity type of external interrupt source. z eint0-eint23 sensitive type of the associated external interrupt source z 0 edge sensitivity. z 1 level sensitivity. mdcirq+0120 h+n*10h eintn de-bounce control register mdeintn_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en pol cnt type r/w r/w r/w reset 0 0 0 these registers control the de-bounce logic for external interrupt sources in order to minimize the possibility of false activations. when the external interrupt sources is used to resume the system clock from the sleep mode, the de-bounce control circuit must be enabled. note that n is from 0 to 23 z cnt de-bounce duration in terms of numbers of 32khz clock cycles z pol activation type of the eint source z 0 negative polarity z 1 positive polarity z en de-bounce control circuit z 0 disable z 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 482 of 1535 3.5 direct memory access 3.5.1 general description a generic dma controller is placed on layer 2 ahb bus to support fast data transfers and to off-load the processor. with this controller, specific devices on ahb or apb buses can benefit greatly from quick completion of data movement from or to memory modules such as external sram, excluding tcm. tcm is invisible for dma engine. such generic dma controller can also be used to connect any two devices other than memory module as long as they can be addressed in memory space. figure 50 variety data paths of dma transfers up to six channels of simultaneous data transfers are supported. they are channel 1, 4, 5, and 11 to 14. each channel has a similar set of registers to be configured to different scheme as desired. if more than six devices are requesting the dma resources at the same time, software based arbitration should be employed. once the service candidate is decided, the responsible device driver should configure the generic dma controller properly in order to conduct dma transfers. both interrupt and polling based sc hemes in handling the completion event are supported. the block diagram of such generic dma co ntroller is illustrated in figure 51 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 483 of 1535 figure 51 block diagram of direct memory access module 3.5.1.1 full-size , half-size & half-size dma channels there are three types of dma channels in the dma controller. the first one is called a full-size dma channel, the second one is called a half-size dma channel, and the last is virtual fifo dma. channels 1 is full-size dma channel; channels 4 and 5 are half-size ones; and channels 11 and 14 are virtual fifo dma channels. the difference between the first two types of dma channels is that both source and destination address are programmable in full-size dma channels, but only the address of one side can be programmed in half-size dma channel. in half-size channels, only either the source or destination address can be programmed, while the addresses of the other side is preset. which preset address is used depends on the setting of mas in dma channel control register. refer to the register definition section for more detail. 3.5.1.2 ring buffer & double buffer memory data movement dma channels 1, 4, 5 support ring-buffer and double-buffer memory data movement. this can be achieved by programming dma_wppt and dma_wpto, as well as setting wpen in dma_con register to enable. figure 52 illustrates how this function works. once the transfer counter reaches the value of wppt, the next address will jump to the wpto address after completing the wppt data transfer. note that only one side can be configured as ring-buffer or double-buffer memory, and this is controlled by wpsd in dma_con register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 484 of 1535 figure 52 ring buffer and double buffer memory data movement 3.5.1.3 unaligned word access the address of word access on ahb bus must be aligned to word boundary, or the 2 lsb is truncated to 00b. if programmers do not notice this, it may cause an incorrect data fetch. in the case where data is to be moved from unaligned addresses to aligned addresses, the word is usually first split into four bytes and then moved byte by byte. this results in four read and four write transfers on the bus. to improve bus efficiency, unaligned-word access is provided in dma4, 5. while this function is enabled, dmas move data from unaligned address to aligned address by executing four continuous byte-read access and one word-write access, reducing the number of transfers on the bus by three. figure 53 unaligned word accesses free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 485 of 1535 3.5.1.4 virtual fifo dma virtual fifo dma is used to ease uart control. the difference between the virtual fifo dmas and the ordinary dmas is that virtual fifo dma contains additional fifo controller. the read and write pointers are kept in the virtual fifo dma. during a read from the fifo, the read pointer points to the address of the next data. during a write to the fifo, the write pointer moves to the next address. if the fifo is empty, a fifo read is not allowed. similarly, data is not written into the fifo if the fifo is full. due to uart flow control requirements, an alert length is programmed. once the fifo space is less than this value, an alert signal is issued to enable uart flow control. the type of flow control performed depends on the setting in uart. each virtual fifo dma can be programmed as rx or tx fifo. this depends on the setting of dir in dma_con register. if dir is ?0?(read), it means tx fifo. on the other hand, if dir is ?1?(write), the virtual fifo dma is specified as a rx fifo. virtual fifo dma provides an interrupt to mcu. this interrupt informs mc u that there is data in the fifo, and the amount of data is over or under the value defined in dma_count register. with this, mcu does not need to poll dma to know when data must be removed from or put into the fifo. note that virtual fifo dmas cannot be used as generic dmas, i.e. dma1, 4, 5. figure 54 virtual fifo dma dma number address of virtual fifo access port associated uart dma11 6100_0000h uart1 rx dma12 6100_0100h uart2 rx dma13 6200_0200h uart1 tx dma14 6300_0300h uart2 tx table 59 virtual fifo access port dma number type ring buffer double buffer burst mode unaligned word access dma1 full size dma4 half size free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 486 of 1535 dma5 half size dma11 virtual fifo dma12 virtual fifo dma13 virtual fifo dma14 virtual fifo able 60 function list of dma channels register address register name synonym mddma + 0000h dma global status register mddma_glbsta mddma + 0028h dma global bandwidth limiter register mddma_glblimiter mddma + 0100h dma channel 1 source address register mddma1_src mddma + 0104h dma channel 1 destination address register mddma1_dst mddma + 0108h dma channel 1 wrap point address register mddma1_wppt mddma + 010ch dma channel 1 wrap to address register mddma1_wpto mddma + 0110h dma channel 1 transfer count register mddma1_count mddma + 0114h dma channel 1 control register mddma1_con mddma + 0118h dma channel 1 start register mddma1_start mddma + 011ch dma channel 1 interrupt status register mddma1_intsta mddma + 0120h dma channel 1 interrupt acknowledge register mddma1_ackint mddma + 0124h dma channel 1 remaining length of current transfer mddma1_rlct mddma + 0128h dma channel 1 bandwidth limiter register mddma1_limiter mddma + 0408h dma channel 4 wrap point address register mddma4_wppt mddma + 040ch dma channel 4 wrap to address register mddma4_wpto mddma + 0410h dma channel 4 transfer count register mddma4_count mddma + 0414h dma channel 4 control register mddma4_con mddma + 0418h dma channel 4 start register mddma4_start mddma + 041ch dma channel 4 interrupt status register mddma4_intsta mddma + 0420h dma channel 4 interrupt acknowledge register mddma4_ackint mddma + 0424h dma channel 4 remaining length of current transfer mddma4_rlct mddma + 0428h dma channel 4 bandwidth limiter register mddma4_limiter mddma + 042ch dma channel 4 programmable address register mddma4_pgmaddr mddma + 0508h dma channel 5 wrap point address register mddma5_wppt mddma + 050ch dma channel 5 wrap to address register mddma5_wpto free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 487 of 1535 mddma + 0510h dma channel 5 transfer count register mddma5_count mddma + 0514h dma channel 5 control register mddma5_con mddma + 0518h dma channel 5 start register mddma5_start mddma + 051ch dma channel 5 interrupt status register mddma5_intsta mddma + 0520h dma channel 5 interrupt acknowledge register mddma5_ackint mddma + 0524h dma channel 5 remaining length of current transfer mddma5_rlct mddma + 0528h dma channel 5 bandwidth limiter register mddma5_limiter mddma + 052ch dma channel 5 programmable address register mddma5_pgmaddr mddma + 0b10h dma channel 11 transfer count register mddma11_count mddma + 0b14h dma channel 11 control register mddma11_con mddma + 0b18h dma channel 11 start register mddma11_start mddma + 0b1ch dma channel 11 interrupt status register mddma11_intsta mddma + 0b20h dma channel 11 interrupt acknowledge register mddma11_ackint mddma + 0b28h dma channel 11 bandwidth limiter register mddma11_limiter mddma + 0b2ch dma channel 11 programmable address register mddma11_pgmaddr mddma + 0b30h dma channel 11 write pointer mddma11_wrptr mddma + 0b34h dma channel 11 read pointer mddma11_rdptr mddma + 0b38h dma channel 11 fifo count mddma11_ffcnt mddma + 0b3ch dma channel 11 fifo status mddma11_ffsta mddma + 0b40h dma channel 11 alert length mddma11_altlen mddma + 0b44h dma channel 11 fifo size mddma11_ffsize mddma + 0c10h dma channel 12 transfer count register mddma12_count mddma + 0c14h dma channel 12 control register mddma12_con mddma + 0c18h dma channel 12 start register mddma12_start mddma + 0c1ch dma channel 12 interrupt status register mddma12_intsta mddma + 0c20h dma channel 12 interrupt acknowledge register mddma12_ackint mddma + 0c28h dma channel 12 bandwidth limiter register mddma12_limiter mddma + 0c2ch dma channel 12 programmable address register mddma12_pgmaddr mddma + 0c30h dma channel 12 write pointer mddma12_wrptr mddma + 0c34h dma channel 12 read pointer mddma12_rdptr mddma + 0c38h dma channel 12 fifo count mddma12_ffcnt mddma + 0c3ch dma channel 12 fifo status mddma12_ffsta free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 488 of 1535 mddma + 0c40h dma channel 12 alert length mddma12_altlen mddma + 0c44h dma channel 12 fifo size mddma12_ffsize mddma + 0d14h dma channel 13 control register mddma13_con mddma + 0d18h dma channel 13 start register mddma13_start mddma + 0d1ch dma channel 13 interrupt status register mddma13_intsta mddma + 0d20h dma channel 13 interrupt acknowledge register mddma13_ackint mddma + 0d28h dma channel 13 bandwidth limiter register mddma13_limiter mddma + 0d2ch dma channel 13 programmable address register mddma13_pgmaddr mddma + 0d30h dma channel 13 write pointer mddma13_wrptr mddma + 0d34h dma channel 13 read pointer mddma13_rdptr mddma + 0d38h dma channel 13 fifo count mddma13_ffcnt mddma + 0d3ch dma channel 13 fifo status mddma13_ffsta mddma + 0d40h dma channel 13 alert length mddma13_altlen mddma + 0d44h dma channel 13 fifo size mddma13_ffsize mddma + 0e14h dma channel 14 control register mddma14_con mddma + 0e18h dma channel 14 start register mddma14_start mddma + 0e1ch dma channel 14 interrupt status register mddma14_intsta mddma + 0e20h dma channel 14 interrupt acknowledge register mddma14_ackint mddma + 0e28h dma channel 14 bandwidth limiter register mddma14_limiter mddma + 0e2ch dma channel 14 programmable address register mddma14_pgmaddr mddma + 0e30h dma channel 14 write pointer mddma14_wrptr mddma + 0e34h dma channel 14 read pointer mddma14_rdptr mddma + 0e38h dma channel 14 fifo count mddma14_ffcnt mddma + 0e3ch dma channel 14 fifo status mddma14_ffsta mddma + 0e40h dma channel 14 alert length mddma14_altlen mddma + 0e44h dma channel 14 fifo size mddma14_ffsize table 61 dma controller register map 3.5.2 register definitions register programming tips: z start registers shall be cleared, when associated channels are being programmed. z pgmaddr, i.e. programmable address, only exists in half-size dma channel s. if dir in control register is high, pgmaddr represents destination address. conversely, if dir in control register is low, pgmaddr represents source address. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 489 of 1535 z functions of ring-buffer and double-buffer memory data movement can be activated on either source side or destination side by programming dma_wppt & and dma_wpto, as well as setting wpen in dma_con register high. wpsd in dma_con register determines the activated side. mddma+0000 h dma global status register mddma_glbs ta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name it14 run14 it13 run13 it12 run12 it11 run11 type ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name it5 run5 it4 run4 it1 run1 type ro ro ro ro ro ro reset 0 0 0 0 0 0 this register helps software program keep track of the global status of dma channels. run n dma channel n status z 0 channel n is stopped or has completed the transfer already. z 1 channel n is currently running. it n interrupt status for channel n z 0 no interrupt is generated. 2 an interrupt is pending and waiting for service. mddma+0028 h dma global bandwidth limiter register mddma_glbli miter bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name glblimiter type wo reset 0 z please refer to the expression in dman_limiter for detailed note. the value of dma_glblimiter is set to all dma channels, 1, 4, 5, 11, 12. mddma+0n00 h dma channel n source addr ess register mddman_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src[15:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 490 of 1535 the above registers contain the base or current source address that the dma channel is currently operating on. writing to this register specifies the base address of transfer source for a dma channel. before programming these registers, the software program should make sure that str in dman_start is set to 0; that is, the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. reading this register returns the address value from which the dma is reading. note that n is 1 and src can?t be tcm address. tcm is not accessible by dma.. src src [31:0] specifies the base or current address of transfer source for a dma channel, i.e. channel 1. z write base address of transfer source z read address from which dma is reading mddma+0n04 h dma channel n destination address register mddman_dst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst[15:0] type r/w reset 0 the above registers contain the base or current destination address that the dma channel is currently operating on.. writing to this register specifies the base address of the transfer destination for a dma channel. before programming these registers, the software should make sure that str in dman_start is set to ?0?; that is, the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. reading this register returns the address value to which the dma is writing. note that n is 1 and dst can?t be tcm address. tcm is not accessible by dma. dst dst [31:0] specifies the base or current address of transfer destination for a dma channel, i.e. channel 1. z write base address of transfer destination. z read address to which dma is writing. mddma+0n08 h dma channel n wrap point count register mddman_wpp t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wppt[15:0] type r/w reset 0 the above registers are to specify the transfer count required to perform before the jump point. this can be used to support ring buffer or double buffer style memory accesses. to enable this function, two control bits, free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 491 of 1535 wpen and wpsd, in dma control register must be programmed. see the following register description for more details. if the transfercounter in the dma engine matches this value, an address jump occurs, and the next address is the address specified in dman_wpto. before programming these registers, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. to enable this function, wpen in dma_con is set. note that the total size of data specify in the wrap point count in a dma channel is determined by len together with the size in dman_con, i.e. wppt x size. note that n is 1, 4, 5. wppt wppt [15:0] specifies the amount of the transfer count from start to jumping point for a dma channel, i.e. channel 1, 4, 5. z write wrap point transfer count. z read value set by the programmer. mddma+0n0c h dma channel n wrap to address register mddman_wpt o bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wpto[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wpto[15:0] type r/w reset 0 the above registers specify the address of the jump destination of a given dma transfer to support ring buffer or double buffer style memory accesses. to enable this function, set the two control bits, wpen and wpsd, in the dma control register. see the following register description for more details. before programming these registers, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. to enable this function, wpen in dma_con should be set. note that n is 1, 4, 5 wpto wpto [31:0] specifies the address of the jump point for a dma channel, i.e. channel 1, 4, 5. z write address of the jump destination. z read value set by the programmer. mddma+0n10 h dma channel n transfer count register mddman_cou nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name len type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 492 of 1535 reset 0 this register specifies the amount of total transfer count that the dma channel is required to perform. upon completion, the dma channel generates an interrupt request to the processor while iten in dman_con is set as ?1?. note that the total size of data being transferred by a dma channel is determined by len together with the size in dman_con, i.e. len x size. for virtual fifo dma, this register is used to configure the rx threshold and tx threshold. interrupt is triggered while fifo count >= rx threshold in rx path or fifo count =< tx threshold in tx path. note that iten bit in dma_con register shall be set, or no interrupt is issued. note that n is 1, 4, 5, 11, 12, 13, 14. len the amount of total transfer count mddma+0n14 h dma channel n control register mddman_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mas dir wpen wpsd type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iten burst b2w drq dinc sinc size type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 this register contains all the available control schemes for a dma channel that is ready for software programmer to configure. note that all these fields cannot be changed while dma transfer is in progress or an unexpected situation may occur. note that n is 1, 4, 5, 11, 12,13,14. size data size within the confine of a bus cycle per transfer. these bits confines the data transfer size between source and destination to the specified value for individual bus cycle. the size is in terms of byte and has maximum value of 4 bytes. it is mainly decided by the data width of a dma master. z 00 byte transfer/1 byte z 01 half-word transfer/2 bytes z 10 word transfer/4 bytes z 11 reserved sinc incremental source address. source addresses increase every transfer. if the setting of size is byte, source addresses increase by 1 every single transfer. if half-word, increase by 2; and if word, increase by 4. z 0 disable z 1 enable dinc incremental destination address. destination addresses increase every transfer. if the setting of size is byte, destination addresses increase by 1 every single transfer. if half-word, increase by 2; and if word, increase by 4. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 493 of 1535 z 0 disable z 1 enable dreq throttle and handshake control for dma transfer z 0 no throttle control during dma transfer or transfers occurred only between memories 2 hardware handshake management z the dma master is able to throttle down the transfer rate by way of request-grant handshake. b2w word to byte or byte to word transfer for the applications of transferring non-word-aligned-address data to word-aligned-address data. note that burst is set to 4-beat burst while enabling this function, and the size is set to byte. no effect on channel 1, 11, 12,13,14. z 0 disable z 1 enable burst transfer type. burst-type transfers have better bus efficiency. mass data movement is recommended to use this kind of transfer. however, note that burst-type transfer does not stop until all of the beats in a burst are completed or transfer length is reached. fifo threshold of peripherals must be configured carefully while being used to move data from/to the peripherals. what transfer type can be used is restricted by the size. if size is 00b, i.e. byte transfer, all of the four transfer types can be used. if size is 01b, i.e. half-word transfer, 16-beat incrementing burst cannot be used. if size is 10b, i.e. word transfer, only single and 4-beat incrementing burst can be used. no effect on channel 17-24 z 000 single z 001 reserved z 010 4-beat incrementing burst z 011 reserved z 100 8-beat incrementing burst z 101 reserved z 110 16-beat incrementing burst z 111 reserved iten dma transfer completi on interrupt enable. z 0 disable z 1 enable wpsd the side using address-wrapping function. only one side of a dma channel can activate address- wrapping function at a time. no effect on channel 17-24 z 0 address-wrapping on source . z 1 address-wrapping on destination. wpen address-wrapping for ring buffer and double buffer. the next address of dma jumps to wrap to address when the current address matches wrap point count. no effect on channel 17-24 z 0 disable z 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 494 of 1535 dir directions of dma transfer for half-size and virtual fifo dma channels, i.e. channels 4, 5, 11, 12,13,14. the direction is from the perspective of the dma masters. write means read from master and then write to the address specified in dma_pgmaddr, and vice versa. no effect on channel 1. z 0 read z 1 write mas master selection. specifies which master occupies this dma channel. once assigned to certain master, the corresponding dreq and dack are connected. for half-size and virtual fifo dma channels, i.e. channels 4, 5, 11, 12,13,14, a predefined address is assigned as well. z 00000 sim1 z 00001 uart1 tx z 00010 uart1 rx z 00011 uart2 tx z 00100 uart2 rx z 00101 nfi tx z 00110 nfi rx z 00111 idma 1 1000 idma 2 z 1001 reserved z 1010 reserved z 1011 reserved z 1100 reserved z 1101 sim2 z others reserved mddma+0n18 h dma channel n start register mddman_star t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of a dma channel. when str is changed from 0 to 1, the dma channel starts to work. note that prior to setting str to ?1?, all the configurations should be done by giving proper value to the registers. note also that once the str is set to ?1?, the hardware does not clear it automatically no matter if the dma channel accomplishes the dma transfer or not. in other words, the value of str stays ?1? regardless of the completion of dma transfer. therefore, the software program should be sure to clear str to ?0? for starting another transfer for the same dma channel. if this bit is cleared to ?0? during dma transfer is active, software should polling mddma_glbsta run n after this bit is cleared to ensure current dma transfer is terminated by dma engine. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 495 of 1535 note that n is 1, 4, 5, 11, 12. mddma+0n1c h dma channel n interrupt status register mddman_ints ta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name int type ro reset 0 this register shows the interrupt status of a dma channel. it has the same value as dma_glbsta. note that n is 1, 4, 5, 11, 12, 13,14. int interrupt status for dma channel z 0 no interrupt request is generated. z 1 one interrupt request is pend ing and waiting for service. mddma+0n20 h dma channel n interrupt acknowledge register mddman_acki nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ack type wo reset 0 this register is used to acknowledge the current interrupt request associated with the completion event of a dma channel by software program. note that this is a write-only register, and any read to it returns a value of ?0?. note that n is 1, 4, 5, 11, 12 ,13,14. ack interrupt acknowledge for the dma channel z 0 no effect z 1 interrupt request is acknowledged and should be relinquished. mddma+0n24 h dma channel n remaining length of current transfer mddman_rlct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rlct free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 496 of 1535 type ro reset 0 z this register is to reflect the left transfer coun t of the transfer. note that this value is transfer count not the transfer data size. note that n is 1, 4, 5. mddma+0n28 h dma bandwidth limiter register mddman_limit er bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limiter type r/w reset 0 z this register is to suppress the bus utilizatio n of the dma channel. the value is from 0 to 255. 0 means no limitation, and 255 means totally banned. the value between 0 and 255 means certain dma can have permission to use ahb every (4 x n) ahb clock cycles. z note that it is not recommended to limit the bus utilization of the dma channels because this increases the latency of response to the masters, and the transfer rate decreases as well. before using it, programmer must make sure that the bus masters have some protective mechanism to avoid entering the wrong states. note that n is 1, 4, 5, 11, 12. limiter from 0 to 255. 0 means no limitation, 255 means totally banned, and others mean bus access permission every (4 x n) ahb clock. mddma+0n2c h dma channel n programmable address register mddman_pgm addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pgmaddr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pgmaddr[15:0] type r/w reset 0 the above registers specify the address for a half-size dma channel. this address represents a source address if dir in dma_con is set to 0, and represents a destination address if dir in dma_con is set to 1. before being able to program these register, the software should make sure that str in dman_start is set to ?0?, that is the dma channel is stopped and disabled completely. otherwise, the dma channel may run out of order. note that n is 4, 5, 11, 12, 13,14 and pgmaddr can?t be tcm address. tcm is not accessible by dma. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 497 of 1535 pgmaddr pgmaddr [31:0] specifies the addresses for a half-size or a virtual fifo dma channel, i.e. channel 4, 5, 11, 12 13 14. z write base address of transfer source or destination according to dir bit. z read current address of the transfer. mddma+0n30 h dma channel n virtual fifo write pointer register mddman_wrp tr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wrptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrptr[15:0] type ro note that n is 11, 12. wrptr virtual fifo write pointer. mddma+0n34 h dma channel n virtual fifo read pointer register mddman_rdp tr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rdptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rdptr[15:0] type ro note that n is 11, 12. rdptr virtual fifo read pointer. mddma+0n38 h dma channel n virtual fifo data count register mddman_ffcn t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ffcnt type ro note that n is 11, 12. ffcnt to display the number of data stored in fifo. 0 means fifo empty, and fifo is full if ffcnt is equal to ffsize. mddma+0n3c h dma channel n virtual fifo status register mddman_ffst a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 498 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alt empt y full type ro ro ro reset 0 1 0 note that n is 11, 12. full to indicate fifo is full. z 0 not full 2 full empty to indicate fifo is empty. z 0 not empty 2 empty alt to indicate fifo count is larger than altlen. dma issues an alert signal to uart to enable uart flow control. z 0 not reach alert region. 2 reach alert region. mddma+0n40 h dma channel n virtual fifo alert length register mddman_altl en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name altlen type r/w reset 0 note that n is 11, 12. altlen specifies the alert length of virtual fifo dma. once the remaining fifo space is less than altlen, an alert signal is issued to uart to enable flow control. normally, altlen shall be larger than 16 for uart application. mddma+0n44 h dma channel n virtual fifo size register mddman_ffsi ze bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ffsize type r/w reset 0 note that n is 11, 12.13,14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 499 of 1535 ffsize specifies the fifo size of virtual fifo dma. 3.6 general purpose inputs/outputs MT6516 offers 4 general-purpose i/o pins for modem side usage. by setting the control registers, mcu software can control the direction, the output value, and read the input values on these pins. these gpios and are multiplexed with other functionalities to reduce the pin count. figure 55 gpio block diagram gpios at reset upon a hardware reset (sysrst#), gpios are all configured as inputs and the following alternative usages of the gpio pins are enabled. these gpios are used to latch the inputs upon reset to memorize the desired configuration to ensure that the system restarts or boots up in the right mode. 3.6.1 register definitions 80020000h gpio direction control register 1 md_gpio_dir1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w reset 0 0 0 0 gpio n gpio direction control 0 gpios are configured as input 2 gpios are configured as output 80020100h gpio pull-up/pull-down enable register 1 md_gpio_pull en1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w reset 1 1 1 1 gpio n gpio pull-up/pull-down control free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 500 of 1535 80020200h gpio pull-up/pull-down selection register 1 md_gpio_pulls el1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w reset 0 0 0 0 note pd pd pd pd gpio n gpio pull-up/pull-down selection control 0 gpios pull-down 1 gpios pull-up 80020300h gpio data inversion control register 1 md_gpio_dinv 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name inv3 inv2 inv1 inv0 type r/w r/w r/w r/w reset 0 0 0 0 invn gpio inversion control 0 gpios data inversion disable 1 gpios data inversion enable 80020400h gpio data output register 1 md_gpio_dou t1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 gpio2 gpio1 gpio0 type r/w r/w r/w r/w reset 0 0 0 0 gpion gpio data output control 0 gpios data output 0 1 gpios data output 1 80020500h gpio data input register 1 md_gpio_din1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3 gpio2 gpio1 gpio0 type ro ro ro ro reset x x x x gpion gpios data input 80020600h gpio mode control register 1 md_gpio_mod e1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio3_m gpio2_m gpio1_m gpio0_m free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 501 of 1535 type r/w r/w r/w r/w reset 00 00 00 00 gpio0_m gpio mode selection 00 configured as gpio function 01 o: bpi_bus6 10 reserved 11 reserved gpio1_m gpio mode selection 00 configured as gpio function 01 o: bpi_bus7 10 reserved 11 reserved gpio2_m gpio mode selection 00 configured as gpio function 01 o: bpi_bus8 10 reserved 11 reserved gpio3_m gpio mode selection 00 configured as gpio function 01 o: bpi_bus9 10 reserved 11 reserved 3.7 general purpose timer (md) 3.7.1 general description three general-purpose timers are provided. the timers are 16 bits long and run independently of each other, although they share the same clock source. two timers can operate in one of two modes: one-shot mode and auto-repeat mode; the other is a free running timer. in one-shot mode, when the timer counts down and reaches zero, it is halted. in au to-repeat mode, when the timer reaches ze ro, it simply resets to countdown initial value and repeats th e countdown to zero; this loop repeats until the disable signal is set to 1. regardless of the timer?s mode, if the countd own initial value (i.e. mdgpt1_dat for mdgpt1 or mdgpt_dat2 for mdgpt2) is written when the timer is running, the new initial value does not take effect until the next time the timer is restarted. in auto-repeat mode, the new countdown start value is used on the next countdown iteration. therefore, before enabling the general purpose timer, the desired values for mdgpt_dat and the mdgpt_prescaler registers must first be set. 3.7.2 register definitions mdgpt+0000 h gpt1 control register mdgpt1_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 502 of 1535 name en mode type r/w r/w reset 0 0 mode this register controls gpt1 to count repeatedly (in a loop) or just one-shot. 0 one-shot mode is selected. 2 auto-repeat mode is selected. en this register controls gpt1 to start counting or to stop. 0 gpt1 is disabled. 1 gpt1 is enabled. mdgpt+0004 h gpt1 time-out interval register mdgpt1_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt [15:0] type r/w reset ffffh cnt [15:0] initial counting value. gpt1 counts down from gpt1_dat. when gpt1 counts down to zero, a gpt1 interrupt is generated. mdgpt+0008 h gpt2 control register mdgpt2_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en mode type r/w r/w reset 0 0 mode this register controls gpt2 to count repeatedly (in a loop) or just one-shot. 0 one-shot mode is selected 1 auto-repeat mode is selected en this register controls gpt2 to start counting or to stop. 0 gpt2 is disabled. 1 gpt2 is enabled. mdgpt+000c h gpt2 time-out interval register mdgpt2_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt [15:0] type r/w reset ffffh cnt [15:0] initial counting value. gpt2 counts down from gpt2_dat. when gpt2 counts down to zero, a gpt2 interrupt is generated. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 503 of 1535 mdgpt+0010 h gpt status register mdgpt_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpt2 gpt1 type rc rc reset 0 0 this register illustrates the gptimer timeout status. each flag is set when the corresponding timer countdown completes, and can be cleared when the cpu reads the status register. mdgpt+0014 h gpt1 prescaler register mdgpt1_presc aler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b prescaler this register controls the counting clock for gptimer1. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 102 1024 hz 103 512 hz 110 256 hz 112 128 hz mdgpt+0018 h gpt2 prescaler register mdgpt2_presc aler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b prescaler this register controls the counting clock for gptimer2. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 100 1024 hz 101 512 hz 110 256 hz 112 128 hz free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 504 of 1535 mdgpt+001c h gpt3 control register mdgpt3_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en type r/w reset 0 en this register controls gpt3 to start counting or to stop. 0 gpt3 is disabled. 1 gpt3 is enabled. mdgpt+0020 h gpt3 time-out interval register mdgpt3_dat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cnt[15:0] type ro reset 0 cnt [15:0] if en=1, gpt3 is a free running timer . software reads this register for the countdown start value for gpt3. mdgpt+0024 h gpt3 prescaler register mdgpt3_presc aler bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prescaler [2:0] type r/w reset 100b prescaler this register controls the counting clock for gptimer3. 000 16384 hz 001 8192 hz 010 4096 hz 011 2048 hz 100 1024 hz 101 512 hz 110 256 hz 111 128 hz 3.8 l1 cache controller 3.8.1 general description MT6516 core processor has been implemented with a subsystem in which consists of core cache and tcm (tightly coupled memory). this subsystem is placed in between mcu core and ahb bus interface, as shown in figure 12 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 505 of 1535 arm7ej core cache controller & mpu ahb bus interface tcm cache way 0 cache way 1 cache way 2 cache way 3 ahb figure 56 [figure caption] tcm is a high-speed (zero wait state) dedicated memory accessed exclusively only by mcu. because of the latency penalty when mcu accesses memory or peripherals through on-chip bus, by moving timing critical code and data into tcm, the performance of mcu can be increased and the response to particular events can be guaranteed. another method to increase mcu performance is the implementation of cache. in this case, core cache is a small block of memory, in which contents a copy of small portion of cacheable data in the external memory. if mcu reads a cacheable data, the data will be copied into core cache. once mcu requests the same data again, it can be obtained directly from core cache (called cache hit) instead of fetching it again from external memory. consider the fact that accessing cache is much faster than accessing external memory through bus system, a faster instruction fetching can be obtained, and that leads to a higher ipc (instruction per cycle) which is a major factor in the evaluation of core performance. since a large external memory maps to a small cache, cache can hold only a small portion of external memory. if mcu accesses a data not found in the cache (called cache miss), one cache line must be dropped (flushed), the required data and its neighboring data are transferred from external memory to cache (cal led cache line fill). before ca che line fill, an important step to maintain data consistency between cache and external memory needs to be performed. this important step is so called cache write back, and its introd uction will be carried out in th e later section. in this design, a cache line consists of eight words (8x32 bits) and it will be introduced late r. on the other hand, the best way to utilize tcm is to maintain the critical instruction or data in tcm. this is due to the advantage of tcm that has been described above. after power-on reset, the boot loader copies tcm contents from external storage (such as flash) to internal tcm. if necessary, mcu can replace tcm contents with other data in the external storage during the runtime to implement a mechanism such like ?overlay?. tcm is also an ideal place to put stack data. the sizes of tcm and cache can be set to one of the following 4 configurations: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 506 of 1535 figure 57 [figure caption] z 96kb tcm, 16kb cache (4 way) z 104kb tcm, 8kb cache (2 way) z 108kb tcm, 4kb cache (1 way) z 112kb tcm, 0kb cache (no cache) these different configurations provide flexibility for soft ware to adjust and reach optimum system performance. the address mapping of these memories is like the following: 96kb 4kb tcm cache cache cache cache tcm tcm tcm cache cache tcm tcm tcm cache 4kb 4kb 4kb 96kb 4kb 4kb 4kb 4kb 96kb 4kb 4kb 4kb 4kb 96kb 4kb 4kb 4kb 4kb tcm tcm tcm tcm tcm tcm 4-way h 2-way h 1-way h no cache free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 507 of 1535 figure 58 [figure caption] organization of cache the cache system has the following features: z write back (in the unit of 4 words) z configurable 1/2/4 way set associative (4kb/8kb/16kb) z each way has 128 cache lines with 8-word line size (128*8*4=4kb) z 22-bit tag memory (only 21 of them are used), 1 valid bit for each cache line. z 2-bit dirty memory (each dirty bit records th e dirtiness of half cache line ? 4 words) each way of cache comprises of two memories: tag memory and data memory. tag memory stores each line?s valid bit and tag (upper 20 bits of address). data memory stores line data. when mcu accesses memory, the address is compared to the contents of tag memory. first, the line index (address bit [11:5]) is used to locate a line in tag memory. when a particular line is found in the tag memory, the upper 20 bits (address bit [31:12]), called tag, of the desired memory address are compared with the content of found tag line. if an match is found in both line address and tag address plus valid bit is 1, it is said a cache hit, and data from that particular cache way is returned to mc u. this process is illustrated in the following figure: cache cache tcm tcm tcm cache tcm tcm tcm tcm tcm tcm tcm tcm tcm tcm cache cache cache cache 96 k 4k 4k 4k increasingly adjacent address. no memory holes. cache cache tcm tcm tcm cache tcm tcm tcm tcm tcm tcm tcm tcm tcm tcm cache cache cache cache k 4k increasingly adjacent free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 508 of 1535 figure 59 [figure caption] if most memory accesses are cache hit, mcu is able to get data immediately without wait states and the overall system performance will be higher. there ar e several factors that may affect cache hit rate: z cache size and the organization the larger the cache size is, the higher the hit rate will be. but the hit rate starts to saturate when cache size is larger than a threshold size. normally the size of 16kb and above and two or four way can achieve a good hit rate. z program behavior if the system has several numbers of tasks and switches frequently between tasks, it may cause cache contents to be flushed out frequently. this is due to the fact that each time a new task runs cache will hold its data for a period of time for the opportunity of likely-be-used-again; however, the stored data might get flushed out before being used again if the following task requires the data that occupies the same cache entries. interrupts can cause program flow to change dynamically and a d d r e s s 20 7 v ta g i n d e x 0 1 2 125 126 127 da t a v ta g d a t a v ta g d a t a v ta g d a t a 3 2 1 9 4 -t o -1 mu l t ip le x o r hi t d at a 4 5 11 1 2 3 1 0 d d d d free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 509 of 1535 reduces the benefit of cache. the interrupt handler code itself and the data it processes may cause cache to flush out data used by current task. thus, after returning from interrupt handler to current task, the flushed data may need to be filled into cache again if it is required by the program routine. this causes performance degradation. to assist software engineer tuning system performance, the cache controller in MT6516 records cache hit count and number of cacheable memory accesses. cache hit rate can be obtained from dividing these two numbers. the cache system also comprises a module called mpu (memory protecti on unit). mpu can prevent illegal memory access and specify which memory regions are cacheable or non-cacheable. two fields in cache_con register control the enable of mpu functions. mpu has its own registers to define memory region and associated regions. these settings only take effect after the enable bit in cache_con is set to 1. for more details on the settings, please refer to mpu section of this design specification. 3.8.2 cache write back there are two different types of cache design to maintain the data consistency. one is cache write through and the other is cache write back. the second one can improve the performance especially when processors can generate writes as fast as or faster than the writes can be handled by the external memory; however, the implementation of write back is much harder than it of write through. when a cache line is dirty, four or eight words will be written back to external memory at once, a nd this will certainly occupy significant bus bandwidth. therefore, decreases the overall efficiency. to solve this problem, a write buffer is necessary in the write back implementation. once the writes get written into write buffer, processor can continue execution. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 510 of 1535 3.8.2.1 write back implementation when a cache hit happens on the write request, only the cache content gets modified and dirty bit gets set (in contrast to write through, write through modifies both the contents of cache and external memory). now the content of the cache location where just got modified is inconsistent with that is in the external memory. when cache misses on the read request, line fill will be performed and a randomly selected cache line will be replaced, but before that, the dirty bits of that selected cache line have to be checked for the necessity of write back. if dirty bits are not set, line fill can proceed right away, and the selected cache line can be simplify flushed and replaced by a newly fetched line from external memory in which consists the requesting data. on the other hand, if one or both of the dirty bits are set, write back has to be performed before line fill. in that case, half or the whole cache line gets written into write buffer. to summarize above, the following figure is employed: 8sjuf3frvftu 8sjufjoup dbdifpomz boetfuuif ejsuzcju 8sjufjoup fyufsobm nfnpsz $ b d i f ) j u $ b d i f . j t t 3fbe3frvftu 3fbe'spn $bdif $ifdl%jsuz #jut -jof'jmm $bdif8sjuf #bdl $ b d i f ) j u $ b d i f . jt t % j s u z $ m f b o 8sjufcbdlepof boexsjufcvggfsdpoufout 0/-:uifmbtutfupg xsjufcbdlxpset figure 60 [figure caption] 3.8.2.2 write buffer write buffer consists of address buffer, data buffer, buffer for htrans, buffer for hsize, buffer for hlock , and buffer for hburst. the write buffer is first-in-first-out (fifo) design, and depth of write buffer is eight free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 511 of 1535 words. since the outputs from code cache meet amba format, address buffer and data buffer are independent and the outputs of write buffer also meet amba format and are designed for pipelining. 3.8.3 cache operations upon power on, cache memory contains random values and these numbers are useless by mcu. mcu needs to flush out the cach e content in each cache line before it gets utilized. cache controller provides a register which, when written, could do operations on cache memory to fulfill the necessary prerequisite mentioned above. these are called cache operations, and the operations involve: z invalidate one cache line the user must give a memory address. if it is found within cache, that particular cache line contents the given address is invalidated. the invalidation is done by writing a zero to the valid bit at the corresponding tag line. alternatively, the user can invalidate a cache line by specifying a set/way that maps to that cache line. z invalidate all cache lines the user needs not to specify an address. the cache controller clears valid bit in all tag lines when this operation is requested. z flush one cache line the user must give a memory address. if it is found within cache and the dirty bit or bits are set, that particular cache line contents the given address is flushed into write buffer. alternatively, the user can invalidate a cache line by specifying a set/way that maps to that cache line. z flush all cache lines the user needs not to specify an address. the cache controller flushes all the cache lines with dirty bit or bits are set. 3.8.4 cache controller register definition cache base address is assumed to be 0x5fff0000 (subject to change). cache+00h cache general control register cache_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cachesize cnte n1 cnte n0 mpen mcen type rw rw rw r/w r/w reset 00 0 0 0 0 this register determines the size of cache; cache hit counter and the enable of mpu. cachesize cache size select 00 no cache (112kb tcm) 01 4kb, 1-way cache (108kb tcm) 10 8kb, 2-way cache (104kb tcm) 11 16kb, 4-way cache (96kb tcm) cnten1 enable cache hit counter 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 512 of 1535 if enabled, cache controller will increment a 48-bit co unter by one when a cache hit is detected. this number can provide a reference in performance evaluation for tuning the application programs. this counter increments only when the data is obtained from mpu cacheable region 4~7. 0 disable 1 enable cnten0 enable cache hit counter 0 if enabled, cache controller will increment a 48-bit co unter by one when a cache hit is detected. this number can provide a reference in performance evaluation for tuning the application programs. this counter increments only when the data is obtained from mpu cacheable region 0~3. 0 disable 1 enable mpen enable mpu comparison of read/write permission setting if disabled, mcu can access any memory without restriction. if enabled, mpu will compare the address of mcu to mpu protection setting. if the mcu accessed address falls into restricted region, mpu will stop this memory access and send an ?abort? signal to mcu. for details, please refer to mpu portion of the specification. 0 disable 1 enable mcen enable mpu comparison of cacheable/non-cacheable setting if disabled, mcu memory accesses are all non-cacheable, i.e., they will go through ahb bus (except for tcm access). if enabled, the setting in mpu will take effect. if mcu accesses a cacheable memory region, the cache controller will return the dat a in cache if it?s found in cache and will get the data through ahb bus only if a cache miss occurs. please refer to mpu part of the specification for more details. 0 disable 1 enable cache+04h cache operation cache_op bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name taddr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name taddr[15:5] op[3:0] en type r/w w w1 reset 0 0 0 this register defines the address and/or which kinds of cache operations to be taken. when mcu writes this register, the pipeline of mcu will be stopped for the cache controller to complete the operation. bit 0 of the register must be written 1 to enable the command. taddr[31:5] target address this field contains the address of invalidation operation. if op[3:0]=0010, taddr[31:5] is the address[31:5] of a memory whose line will be invalidated if it exists in the cache. if op[3:0]=0100, taddr[13:5] indicates the set, while taddr[19:16] indicates which way to clear: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 513 of 1535 0001 way #0 0010 way #1 0100 way #2 1000 way #3 op[3:0] operation this field determines which cache operations will be performed. 0001 invalidate all cache lines 0010 invalidate one cache line using address 0100 invalidate one cache line using set/way 1001 flush all cache lines 1010 flush one cache line using address 1100 flush one cache line using set/way en enable command this enable bit must be written 1 to enable the command. 1 enable 0 not enable cache+08h cache hit count 0 lower part cache_hcnt0 l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name chit_cnt0[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chit_cnt0[15:0] type r/w reset 0 cache+0ch cache hit count 0 upper part cache_hcnt0 u bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserved type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chit_cnt0[47:32] type r/w reset 0 when cnten0 bit in cache_con register is set to 1 (enabled), this register starts to record cache hit count until it is disabled. if the value increases to over maximum value (0xffffffffffff), it w ill be rolled over to 0 and continue counting. the 48 bit counter can provide a recording time of 31 days even if mcu runs at 104mhz and every cycle is a cache hit. note that before enabling the counter, it is recommended to write the initial value of zero to the counter. chit_cnt0[47:0] cache hit count 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 514 of 1535 write writing any value to cache_hcnt0l or ca che_hcnt0u clears chit_cnt0 to all zeros read current counter value cache+10h cacheable access count 0 lower part cache_ccnt0 l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cacc_cnt0[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cacc_cnt0[15:0] type r/w reset 0 cache+14h cacheable access count 0 upper part cache_ccnt0 u bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserved type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cacc_cnt0[47:32] type r/w reset 0 when cnten0 bit in cache_con register is set to 1 (enabled), this register is incremented at each cacheable memory access (no matter it?s a cache miss or a cache hit). if the value increases to over maximum value (0xffffffffffff), it w ill be rolled over to 0 and continue co unting. for 104mhz mcu speed, if all memory accesses are cacheable and cache hit, this counte r will overflow after (2^48) * 9.6ns = 31 days. this is the shortest time for the counter to overflow. in a more realistic case, the system will have cache misses, non-cacheable accesses, idle mode that makes the counter overflow at later time. cacc_cnt0[47:0] cache access count 0 write writing any value to cache_ccnt0l or cache_ccnt0u clears cacc_cnt0 to all zeros read current counter value the best way to use cache_hcnt0 and cache_ccnt0 is to set zero as initial value in both registers, enable both counters (set cnten0 to 1), run a portion of program to be benchmarked, stop the counters and get their values. therefore during this period % 100 _ _ = ccnt cache hcnt cache rate hit cache . the cache hit rate value may help tune the performance of application program. note that chit_cnt0 and cacc_cnt0 only increment if the cacheable attribute is defined in mpu cacheable region 0~3. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 515 of 1535 cache+18h cache hit count 1 lower part cache_hcnt1 l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name chit_cnt1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chit_cnt1[15:0] type r/w reset 0 cache+1ch cache hit count 1 upper part cache_hcnt1 u bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserved type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chit_cnt1[47:32] type r/w reset 0 when cnten1 bit in cache_con register is set to 1 (enabled), this register starts to record cache hit count until it is disabled. if the value increases to over maximum value (0xffffffffffff), it w ill be rolled over to 0 and continue counting. the 48 bit counter can provide a recording time of 31 days even if mcu runs at 104mhz and every cycle is a cache hit. note that before enabling the counter, it is recommended to write the initial value of zero to the counter. chit_cnt1[47:0] cache hit count write writing any value to cache_hcnt1l or cach e_hcnt1u clears chit_cnt1 to all zeros read current counter value cache+20h cacheable access count 1 lower part cache_ccnt1 l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cacc_cnt1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cacc_cnt1[15:0] type r/w reset 0 cache+24h cacheable access count 1 upper part cache_ccnt1 u bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 516 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cacc_cnt1[47:32] type r/w reset 0 when cnten1 bit in cache_con register is set to 1 (enabled), this register is incremented at each cacheable memory access (no matter it?s a cache miss or a cache hit). if the value increases to over maximum value (0xffffffffffff), it w ill be rolled over to 0 and continue co unting. for 104mhz mcu speed, if all memory accesses are cacheable and cache hit, this counte r will overflow after (2^48) * 9.6ns = 31 days. this is the shortest time for the counter to overflow. in a more realistic case, the system will have cache misses, non-cacheable accesses, idle mode that makes the counter overflow at later time. cacc_cnt1[47:0] cache access count 1 write writing any value to cache_ccnt1l or ca che_ccnt1u clears cacc_cnt1 to all zeros read current counter value the best way to use cache_hcnt1 and cache_ccnt1 is to set zero as initial value in both registers, enable both counters (set cnten1 to 1), run a portion of program to be benchmarked, stop the counters and get their values. therefore during this period % 100 _ _ = ccnt cache hcnt cache rate hit cache . the cache hit rate value may help tune the performance of application program. note that chit_cnt1 and cacc_cnt1 only increment if the cacheable attribute is defined in mpu cacheable region 4~7. 3.9 mpu 3.9.1 general description the purpose of mpu is to provide a protection mechanism and cacheable indication of memory. the planned features of mpu include: z 16-entry protection settings. determine if mcu can read/write a memory region. if the setting doesn?t allow mcu?s particular access to a memory address, mpu will stop the memory access and issue ?abort? signal to mcu, making it entering into ?abort? mode. the exception handler must then process the situation. z 16-entry cacheable settings. determine a memory region is cacheable or not. if cacheable, mcu will keep a small copy in its cache after read accesses. if mcu requires the same data later, it can get it from the high-speed local copy, instead of from low-speed external memory. normally the protection and cacheable attributes are combined together for the same address range, as in the example of arm946e. for greater flexibility, the mpu in MT6516 provides independent protection and cacheable settings. that is to say, the memory regions defined for memory protection and for cacheable are different and independent of each other. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 517 of 1535 the 4gb memory space is divided to 16 memory blocks with 256mb size each, i.e., mb0~mb15. emi takes mb0~mb3, sysram takes mb4, tcm uses mb5, apb peripherals mb8. the characteristics of these memory blocks are listed below: z read/write protection setting mb6 and above are always readable/writeable. mb0~mb4 and mb5 are determined by mpu. z cacheable setting mb4 and above are always non-cacheable. mb0~mb3 are determined by mpu. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 518 of 1535 3.9.2 protection settings figure 61 [figure caption] figure 61 shows the protection setting in each memory block. five regions are defined in the figure. note that each region can be continuous or non-continuous to each other, and those address ranges not covered by any region are set to be readable/writeable automatically. one restriction exists: different regions must not overlap. the user can define maximum 16 regions in mb0~mb4 and mb10. each region has its own setting defined in a 32-bit register: a pb peripherals mb3 ~ mb0 mb4 mb5 region 0 region 1 region 2 region 3 region 0 base address region 1 base address region 2 base address region 3 base address non-readable/writeable readable/non - writeable non-readable/non -writeable readable/writeable mb8 mb6 a hb peripherals tcm sysram emi free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 519 of 1535 base address 31 0 size en 10 1 5 prot 7 6 00 z region base address (22 bits) z region size (5 bits) z region protection attribute (2 bits) z enable bit (1 bit) mpu will abort mcu if it accesses mb11~mb15 regions. 3.9.2.1 region base address region base address defines the starting point of the memory region. the user needs only to specify several upper address bits. the number of valid address bits depends on the region size. the user must align the base address to a region-size boundary. for example, if a region size is 8kb, its base address must be a multiple of 8kb. 3.9.2.2 region size the bit representation of region size and its relationship with base address are listed as follows. region size bit encoding base address 1kb 00000 bit [31:10] of region start address 2kb 00001 bit [31:11] of region start address 4kb 00010 bit [31:12] of region start address 8kb 00011 bit [31:13] of region start address 16kb 00100 bit [31:14] of region start address 32kb 00101 bit [31:15] of region start address 64kb 00110 bit [31:16] of region start address 128kb 00111 bit [31:17] of region start address 256kb 01000 bit [31:18] of region start address 512kb 01001 bit [31:19] of region start address 1mb 01010 bit [31:20] of region start address 2mb 01011 bit [31:21] of region start address 4mb 01100 bit [31:22] of region start address table 62 region size and bit encoding 3.9.2.3 region prot ection attribute this attribute has two bits. the msb determines read access permission, and the lsb for write access permission. bit encoding permission 00 non-readable / non-writeable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 520 of 1535 10 readable / non-writeable 01 non-readable / writeable 11 readable / writeable table 63 region protection attribute bit encoding note that bit encoding ?11? allows full read/write permission, which is the case when no region is specified. so it is recommended to only spec ify regions with protection attribute ?00?, ?10? or ?01?. 3.9.3 cacheable settings figure 62 [figure caption] cacheable setting and non-cacheable setting are similar to cache protection settings please refer to figure 7 . note that each region can be continuous or non-continuous to each other. for those address ranges that not being covered by any region in the mpu cacheable settings are set to be uncacheable automatically. one restriction exists: different regions must not overlap. cacheable emi sysram tcm peripheral mb3 ~ mb0 mb4 mb5 mb9 ~ mb6 region 0 region 1 region 2 region 0 base address region 1 base address region 2 base address uncacheable mb 10 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 521 of 1535 the user can define maximum 16 regions in mb0~mb3. each region has its own setting defined in a 32-bit register: base address 31 0 size en 10 1 5 c 6 000 z region base address (22 bits) z region size (5 bits) z region cacheable attribute (1 bit) z enable bit (1 bit) the region base address and region size bit encoding are the same as those of protection setting. the user must also align the base address to a region-size boundary. the cacheable attribute has the following meaning. bit encoding attribute 0 uncacheable 1 cacheable table 64 region cacheable attribute bit encoding 3.9.4 mpu register definition mpu base address is assumed 0x5fff1000 (subject to change). mpu+0000h protection setting for region 0 mpu_prot0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 0. baseaddr base address of this region attr protection attribute 00 non-readable / non-writeable 01 non-readable / writeable 10 readable / non-writeable 11 readable / writeable size size of this region 00000 1kb 00001 2kb 00010 4kb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 522 of 1535 00011 8kb 00100 16kb 00101 32kb 00110 64kb 00111 128kb 01000 256kb 01001 512kb 01010 1mb 01011 2mb 01100 4mb en enable this region 0 disable 1 enable mpu+0004h protection setting for region 1 mpu_prot1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 1. mpu+0008h protection setting for region 2 mpu_prot2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 2. mpu+000ch protection setting for region 3 mpu_prot3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 523 of 1535 this register sets protection attributes for region 3. mpu+0010h protection setting for region 4 mpu_prot4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 4. mpu+0014h protection setting for region 5 mpu_prot5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 5. mpu+0018h protection setting for region 6 mpu_prot6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 6. mpu+001ch protection setting for region 7 mpu_prot7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 7. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 524 of 1535 mpu+0020h protection setting for region 8 mpu_prot8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 8. mpu+0024h protection setting for region 9 mpu_prot9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 9. mpu+0028h protection setting for region 10 mpu_prot10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 10. mpu+002ch protection setting for region 11 mpu_prot11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 11. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 525 of 1535 mpu+0030h protection setting for region 12 mpu_prot12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 12. mpu+0034h protection setting for region 13 mpu_prot13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 13. mpu+0038h protection setting for region 14 mpu_prot14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 14. mpu+003ch protection setting for region 15 mpu_prot15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] attr[1:0] size[4:0] e n type r w r w r w r w reset 11 00000 0 this register sets protection attributes for region 15. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 526 of 1535 mpu+0040h cacheable setting for region 0 mpu_cache0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 0. baseaddr base address of this region c cacheable attribute 0 uncacheable 1 cacheable size size of this region 00000 1kb 00001 2kb 00010 4kb 00011 8kb 00100 16kb 00101 32kb 00110 64kb 00111 128kb 01000 256kb 01001 512kb 01010 1mb 01011 2mb 01100 4mb en enable this region 0 disable 1 enable mpu+0044h cacheable setting for region 1 mpu_cache1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 527 of 1535 mpu+0048h cacheable setting for region 2 mpu_cache2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 2. mpu+004ch cacheable setting for region 3 mpu_cache3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 3. mpu+0050h cacheable setting for region 4 mpu_cache4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 4. mpu+0054h cacheable setting for region 5 mpu_cache5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 5. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 528 of 1535 mpu+0058h cacheable setting for region 6 mpu_cache6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 6. mpu+005ch cacheable setting for region 7 mpu_cache7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 7. mpu+0060h cacheable setting for region 8 mpu_cache8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 8. mpu+0064h cacheable setting for region 9 mpu_cache9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 9. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 529 of 1535 mpu+0068h cacheable setting for region 10 mpu_cache10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 10. mpu+006ch cacheable setting for region 11 mpu_cache11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 11. mpu+0070h cacheable setting for region 12 mpu_cache12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 12. mpu+0074h cacheable setting for region 13 mpu_cache13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 13. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 530 of 1535 mpu+0078h cacheable setting for region 14 mpu_cache14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 14. mpu+007ch cacheable setting for region 15 mpu_cache15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name baseaddr[31:16] type r w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name baseaddr[15:10] c size[4:0] e n type r w r w r w r w reset 0 00000 0 this register sets cacheable attributes for region 15. 3.10 log accelerator 3.10.1 general description in order to download more information from the network and to reduce the software loading, software only writes all information (the layer 1 and protocol servic e) at the specified external memory and triggers the hardware to transmit it though uart to the pc client. before transmitting data though uart, software needs to specify some settings. at first, the address of the layer 1 and ps data is needed. the amount of data is so huge that the data usually is located at the external memory. software needs to specify the starting address and the size of the ring buffer. however, if the address is located at the internal ram (at the same layer of the ahb bus), it is acceptable. for MT6516, there is no the internal ram at the same layer with the log_acc. therefore, the log_acc can not access the internal ram. besides the location of the original data, software needs to specify the target address. there are two ways to transmit data to uart. i. the log_acc module writes all encoded data to the specified memory and then issues an interrupt to mcu after the whole block is transmitted. then, software uses dma to move the data to uart or usb. ii. the log_acc module writes the uart port directly. in the first approach, software needs to set the specify memory for storing all encoded data. while arm receives the irq signal from log_acc, software can start to use dma to move the data to uart or usb. this approach has a limit: if the encoded data is not word-aligned, sw should separate encoded data into two free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 531 of 1535 parts: one part is sent by ?dma size=word? way, and the remaining not-word-aligned data is sent by ?dma size=byte?. if sw uses ?dma size=byte? to send all data, the bus performance will be degraded and the transmission rate is too slow. in the second approach, the log_acc will write uart port directly by ahb single mode. software needs to enable this function in the register the set the target address to uart port. sw should set the appreciate threshold value in ?uartn_fcr?, otherwise the log_acc will write too much data to uart fifo. although the log_acc can detect the status of the uart, the log_acc may not be the first master to access the uart while the uart fifo is safe to send. if it happens (too much data), sw can try to use the dma approach because this approach will hold the transmissi on until the fifo is not full. if sw can grantee the on e uart dedicated to the log_acc module, then there is no such problem. log_acc process flow: 3 3 3 3 3 5jnf 3 3 - 3 3 3 14 3 - 3 3 14 3 - 14 - red blocks belongs to the layer 1, and blue blocks belongs to the protocol stack. the layer 1 data has higher priority so that the layer 1 can send first if both layer 1 and ps data are ready. if there is no layer 1 data needed to send, then the log_acc starts to send ps data. however, if the layer 1 data is ready at the transmission of the ps data, the next transmission block will be the layer 1 data. after all layer 1data is sent, the next ps block continues to be sent. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 532 of 1535 in this hw version, hw supports to send data via two uarts at the same time. while sw enables the dual master mode, the arbiter will become transparent and ps core will use the independent tx device and ahb access device. this mode setting must be set before the transmission. ahb access1 & tx1 module are activated at the dual master mode. 3.10.2 register definition register address register function acronym 0x811b0000 log accelerator control setting log_con 0x811b0004 layer 1 base address log_lyr1_base 0x811b0008 layer 1 ring buffer size log_lyr1_size 0x811b000c ps base address log_ps_base 0x811b0010 ps ring buffer size log_ps_size 0x811b0014 target 0 address (for lyr1 or share mode) log_target0_addr 0x811b0018 target 0 size (for lyr1 or share mode) log_target0_size 0x811b001c target 0 buffer data amount (for lyr1 or share mode) log_ txbuf_cnt0 0x811b0020 target 0 log status (for lyr1 or share mode) log_status0 0x811b0024 uart_sel for target 0 (for lyr1 and share mode) log_uart_sel0 0x811b0028 layer 1 pointer log_lyr1_pt free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 533 of 1535 0x811b002c ps pointer log_ps_pt 0x811b0044 log irq status log_irq_sta 0x811b0050 tx_state log_debug1 0x811b0054 write pointer in tx module log_debug2 0x811b0058 buffer pointer in tx module log_debug3 0x811b005c tx buffer count in tx module log_debug4 0x811b0060 checksum in tx module log_debug5 0x811b0064 encoded data to memory or uart log_debug6 0x811b0068 escaping index & encoded data in internal buffer log_debug7 table 65 log_acc registers 0x811b0000 log accelerator co ntrol setting log_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rst_b log_ dbg tx1_u art tx0_u art tx1_m ode tx0_m ode ahb sp_m ode dual_ mast er ps_lo g_tri g lyr1_ log_t rig type r/w r/w r/w r/w r/w r/w r/w r/w w w reset 1 0 0 0 0 0 0 0 0 0 lyr1_log_trig trigger the hardware to check the ready byte of the monitored block. once the hardware detects this trigger, then this bit will be desserted. 0 disable 1 trigger the hardware ps_log_trig trigger the hardware to check the ready byte of the monitored block. if the ready byte is no ok or the transmission is done, this bit will be disserted. 0 disable 1 trigger the hardware tx0_mode approach 1 or 2 for tx0 module 0 approach 1 (dma -> uart or usb) 1 approach 2 (uart directly), irq will no t be issued while tx block is ready. tx1_mode approach 1 or 2 for tx1 module (only valid at dual master mode) 0 approach 1 (dma -> uart or usb) 1 approach 2 (uart directly), irq will no t be issued while tx block is ready. tx0_uart the specified uart will be dedicated to tx0 module, which is specified by log_uart_sel0 register. caution: 1. do not change the setting at the transmission of log_acc. 2. tx0_mode should be set to 1. 0 uart can be shared to other modules 1 uart will be dedicated to log_acc module only. tx1_uart the specified uart will be dedicated to tx0 module, which is specified by log_uart_sel0 register. caution: 1. do not change the setting at the transmission of log_acc. 2. tx1_mode should be set to 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 534 of 1535 0 uart can be shared to other modules 1 uart will be dedicated to log_acc module only. ahb sp_mode turn on ahb burst mode at the approach 2. (caution: under this special mode, the performance of the ahb increases, but this will violate the ahb protocol) dual_master enable two ahb masters to access bus to support two uart devices transmission at the same time 0 disable 1 enable log_dbg select the output of debug information 0 layer 1 1 protocol stack rst_b force the hardware to reset 0x811b0004 layer 1 base address log_lyr1_ba se bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr the address of the original data ( 4 word-aligned ) 0x811b0008 layer 1 ring buffer size log_lyr1_siz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name size type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name size type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 size the ring buffer size for the original data ( 4 word-aligned ) 0x811b000c ps base address log_ps_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 535 of 1535 addr the address of the original data ( 4 word-aligned ) 0x811b0010 ps ring buffer size log_ps_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name size type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name size type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 size the ring buffer size for the original data ( 4 word-aligned ) 0x811b0014 target 0 address (for lyr1 or share mode) log_target0_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr the address of the encoded data ( 4 word-aligned , except for uart port) if your target is uart, please write the address of rx buffer register in the uart. 0x811b0018 target 0 size (for lyr1 or share mode) log_target0_si ze bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name size type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name size type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr the address of the encoded data ( 4 word-aligned ) 0x811b001c target 0 buffer data amount (for lyr1 or share mode) log_ txbuf_cnt0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 536 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 size the amount of the encoded data in the target buffer (unit: byte) 0x811b0020 target 0 log status (for ly r1 or share mode) log_status0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rdy- to-rd type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rdy-to-rd indicate whether the target buffer is full. if the target is full or there is no block needed to process, the interrupt will be issued. after sw uses dma move the data in the target buffer to the uart, sw should write 1?b0 to clear this register . the log_acc will wait until this bit is 1?b0. 0x811b0024 uart_sel for target 0 (for lyr1 and share mode) log_uart_se l0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name uart2 uart1 uart0 type r/w r/w r/w reset 0 0 0 uartx which uart is selected (only valid when tx_mode = 1). this setting is for indicating which uart?s full alarm should be monitored. 0x811b0028 layer 1 pointer log_lyr1_pt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr the pointer of the processing block (the real hardware address = base_addr + pointer) 0x811b002c ps pointer log_ps_pt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addr the pointer of the processing block (the real hardware address = base_addr + pointer) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 537 of 1535 0x811b0044 log irq status log_irq_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq1 irq0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 irqx indicate which tx0/tx1 fire a interrupt. after reading this register, the register will be cleared. 0 no interrupt 1 interrupt 0x811b0050 log_acc debug information (state machine) log_debug1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name core_state type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tx_state type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b0054 log_acc debug information (pointer) log_debug2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wt_pt3 wt_pt2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wt_pt1 wt_pt0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b0058 log_acc debug information (pointer) log_debug3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf_p t bt_pt3 bt_pt2 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bt_pt1 bt_pt0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b005c log_acc debug information (counter) log_debug4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tx_cnt type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name total_read_data_count type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b0060 log_acc debug information (check_sum) log_debug5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 538 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ps_check_sum lyr1_check_sum type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b0064 log_acc debug information (encoded output data) log_debug6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x811b0068 log_acc debug information (buffer data, encoded index) log_debug7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name index buf_data type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name index buf_data type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w use log_con bit 21~16 to select which buf_data should be read back. use bit 22 to select msb or lsb buf_data to read back. 3.11 md config register 3.11.1 apb bridge register map register address register name synonym 8001_0000h hardware version register hw_ver 8001_0004h software version register sw_ver 8001_0008h hardware code register hw_code 8001_0010h software misc. low register sw_misc_l 8001_0014h software misc. high register sw_misc_h 8001_0020h hardware misc. register hw_misc 8001_0204h sleep control register sleep_con 8001_0208h mcu clock control register mcuclk_con 8001_0300h md2gsys output isolation register iso_en 8001_0304h md2gsys power down register pwr_off 8001_0308h md2gsys memory power down register mem_pdn 8001_030ch md2gsys input isolation register in_iso_en 8001_0404h apb bus control register apb_con 8001_0408h security boot register security_reg free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 539 of 1535 8001_0500h external write buffer control register extb_size 8001_0504h vcxo_off register vcxo_off 3.11.2 register definitions 8001_0000h hardware version register hw_version bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extp majrev minrev type ro ro ro ro reset 7 a 0 0 this register is used by software to determine the hardware version of the chip. the register contains a new value whenever each metal fix or major step is performed. all values are incremented by a step of 1. minrev minor revision of the chip majrev major revision of the chip extp this field shows the existence of hardware code register that presents the hardware id while the value is other than zero. 8001_0004h software version register sw_version bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extp majrev minrev type ro ro ro ro reset 7 a 0 0 this register is used by software to determine the so ftware version used with this chip. all values are incremented by a step of 1. minrev minor revision of the software majrev major revision of the software extp this field shows the existence of hardware code register that presents the hardware id when the value is other than zero. 8001_0008h hardware code register hw_code bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name code3 code2 code1 code0 type ro ro ro ro reset 6 5 1 6 this register presents the hardware id. code1 & code0 can be programmed by efuse_dout[61:54]. 8001_0010h software misc low register sw_misc_l bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sw_misc_l type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spare registers for software control. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 540 of 1535 8001_0014h software misc high register sw_misc_h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sw_misc_h type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spare registers for software control. 8001_0020h hardware misc register hw_misc bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irdma_limit_cnt irdma _limit _en tdma _idn type r/w r/w r/w reset 0 0 0 spare registers for platform control. tdma_idn tdma debug unit on/off control 0 disable 1 enable. irdma_limit_en enable the limiter for irdma 0 disable 1 enable. irdma_limit_cnt set the maximum count for limiter, irdma only issues the request when counting to the end of irdma_limit_cnt. 8001_0204h sleep control register sleep_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ap_ac t_b dsp2 dsp1 ahb mdmc u type r/w r/w r/w wo wo reset ~ico re 1 1 0 0 mdmcu stop the mcu clock to force mcu processor to enter sleep mode. mcu clock will be resumed as long as there is an interrupt request or system is reset. 0 mcu clock is running 1 mcu clock is stopped ahb stop the ahb bus clock to force the entire bus to enter sleep mode. ahb clock will be resumed as long as there is an interrupt request or system is reset. 0 ahb bus clock is running 2 ahb bus clock is stopped dsp1 stop the dsp1 clock. 0 dsp bus clock is running 1 dsp bus clock is stopped dsp2 stop the dsp2 clock. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 541 of 1535 0 dsp bus clock is running 1 dsp bus clock is stopped ap_act_b active ap mcu. after md mcu finish the initialization of the memory and system setting for ap mcu. md mcu can set the bit as ?1? to activate ap mcu. 0 enable ap mcu. (md mcu clock stops) 1 disable ap mcu. 8001_0208h mcu clock control register mcuclk_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arm7_ fsel mcu_fsel type r/w r/w reset 0 7 mcu_fsel mcu clock frequency selection. this control register is used to control the output clock frequency of mcu dynamic clock manager. the clock frequency is from 13mhz to 104mhz. the waveforms of the output clock are shown below. this register setting applies to the free-running clock, e.g. irq controller clock, in idle an d slow idle mode. in normal mode this field is not working. 104mhz 52mhz 26mhz 13mhz figure 63 output of dynamic clock manager high speed bus (and arm7) low speed bus 0 13mhz 13mhz 1 26mhz 26mhz 2 reserved reserved 3 52mhz 52mhz 4 reserved reserved 5 reserved reserved 6 reserved reserved 7 104mhz 52mhz others reserved arm7_fsel arm7 working clock frequency selection. this control register is used to control the arm7 working clock frequency. 0 arm7 clock runs at 52mhz 1 arm7 clock runs at 104mhz 8001_0300h md2gsys output isolation register iso_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _iso_ en type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 542 of 1535 reset 0 md2gsys output isolation control 8001_0304h md2gsys power down control register pwr_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _sw_p dn md2g _pdn type r/w r/w reset 1 0 md2gsys power down control register md2g_pdn md2gsys power down, this bit is valid in software control mode. 0 disable 1 enable md2g_sw_pdn md2gsys hw/sw power down select 0 hardware control 1 software control 8001_0308h md2gsys memory power down register mem_pdn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vfe_m em_p dn md2g _mem _pdn type r/w r/w reset 0 0 md2gsys memory power down control register md2g_mem_pdn md2gsys memory power down 0 disable 1 enable vfe_mem_pdn vfe memory power down 0 disable 1 enable 8001_030ch md2gsys input isolation register in_iso_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _in_is o_en type r/w reset 0 md2gsys input isolation control register 8001_0404h apb bus control register apb_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 543 of 1535 name apbw 6 apbw 5 apbw 4 apbw 3 apbw 2 apbw 1 apbw 0 apbr6 apbr5 apbr4 apbr3 apbr2 apbr1 apbr 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used to control the timing of read cycle and write cycle on apb bus. apbr0-apbr6 read access time on apb bus 0 1-cycle access 1 2-cycle access apbw0-apbw6 write access time on apb bus 0 1-cycle access 1 2-cycle access 8001_0408h security boot register security_boot bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name security_boot type ro reset 0 8001_0500h mcu external write buffer size register wb_size bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wb_si ze type r/w reset 0 this register is used to configure the external write buffer size of mcu. wb_size 0 32-word data buffer and 8 address buffer 1 16-word data buffer and 4 address buffer 8001_0504h vcxo_off register vcxo_off bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vcxo _off type ro reset vcxo_ off this register is used to monitor vcxo_off signal 3.12 mdmcusys config register in addition to the pause mode capability while in the standby state, the software program can also put each peripheral independently into power down mode while in the active state by gating off their clock. the typical logic implementation is depicted in figure 13 . for all configuration bits, 1 signifies that the function is in power down mode, and 0 means the function is in the active mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 544 of 1535 clock power down testmode figure 64 power down control at block level register address register name synonym 811c_0000h clock gating control status register 0 mdmcusys_pdn_con0 811c_0020h clock gating set register 0 mdmcusys_pdn_set0 811c_0040h clock gating clear register 0 mdmcusys_pdn_clr0 811c_0400h memory delsel control register 0 (used by hardware) mdmcusys_delsel0 table 66 apb bridge register map 3.12.1 register definitions 811c_0000h clock gating control status register 0 mdmcusys_p dn_con0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name la type ro reset 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sim2 sim afc tdma mddm a type ro ro ro ro ro reset 1 1 1 1 1 mdmcu sub-system power down control status register (read only). value 1 represents power down. mddma status of the modem dma controller power down tdma status of the tdma power down afc status of the afc power down. this control is not being updated until both tdma_evtval and qbit_en are asserted. sim status of the sim controller power down sim2 status of the sim2 controller power down. sim2 is actually power down when both ap and md sim2 power down bit are set. la status of the log accelerator power down 811c_0020h clock gating set register 0 mdmcusys_p dn_set0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 545 of 1535 name la type wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sim2 sim afc tdma mddm a type wo wo wo wo wo mdmcu sub-system power down set register, value 1 represents power down. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?h0f0f, writing pdn_ set0 = 16?f0f0 will result in pdn_con0 = 16?hffff. 811c_0040h clock gating clear register 0 mdmcusys_p dn_clr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name la type wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sim2 sim afc tdma mddm a type wo wo wo wo wo mdmcu sub-system power down clear register, value 1 represents power up. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_con registers. for example, if pdn_con0 = 16?hffff, writing pdn_clr0 = 16?f0f0 will result in pdn_con0 = 16?h0f0f. 811c_0400h memory delsel control register 0 mdmcusys_d elsel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mdsysrom tcm l1cache l1tag type r/w r/w r/w r/w reset 0101 11 11 10 when writing bit 9, the effective value will be inversed. th at is, effect will be logic 1 when writing 0, and effect will be 0 when writing 1. 3.13 reset generation unit (mdrgu) figure 35 shows the reset scheme used in MT6516. MT6516 provides three kinds of resets: hardware reset, watchdog reset, and software reset. MT6516 provides 8 resets which can be manual reset by individual rgu_usrstx control registers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 546 of 1535 usrst0 usrst1 usrst2 usrst3 usrst4 usrst5 usrst6 usrst7 watchdog timer peri. soft reset dsp soft reset sysrst# watchdog# r1 r2 r4 dsp subsystem dsp coprocessor r124 r12 mdmcusys md2gsys mdrgu figure 65 reset scheme used in MT6516 3.13.1 general description 3.13.1.1 hardware reset this reset is input through the sysrst# pin, which is driven low during power-on. the hardware reset has a global effect on the chip: all digital and analog circuits are initialized, except the real time clock module. the initial states of the MT6516 sub-blocks are as follows:. ? all analog circuits are turned off. ? all plls are turned off and bypassed. the 13 mhz system clock is the default time base. 3.13.1.2 watchdog reset a watchdog reset is generated when the watchdog timer expires: the mcu software failed to re-program the timer counter in time. this situation is typically induced by abnormal software execution, which can be aborted by a hardwired watchdog reset. hardware blocks that are affected by the watchdog reset are: ? mcu subsystem, ? dsp subsystem, and ? external components (trigged by software). 3.13.1.3 software resets software resets are local reset signals that initialize specific hardware components. for example, if hardware failures are detected, the mcu or dsp software may write to software reset trigger registers to reset those specific hardware modules to their initial states. the following modules have software resets. ? dsp core free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 547 of 1535 ? dsp coprocessors 3.13.2 register definitions rgu +0000h watchdog timer control register wdt_mode bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] wdtin _dis auto- resta rt irq exten extpo l enab le type wo r/w r/w r/w r/w r/w r/w reset 1* 0 0 0 0 reset_ en enable enables the watchdog timer. the reset value depends on the icore: reset_en = ~icore. 0 disables the watchdog timer. 1 enables the watchdog timer. extpol defines the polarity of the external watchdog pin. 0 active low. 2 active high. exten specifies whether or not to generate an external watchdog reset signal. 0 the watchdog does not generate an external watchdog reset signal. 1 if the watchdog counter reaches zero, an external watchdog signal is generated. irq issues an interrupt instead of a watchdog timer reset. for debug purposes, rgu issues an interrupt to the mcu instead of resetting the system. 0 disable. 1 enable. auto-restart restarts the watchdog timer counter with the value of wdt_length while task id is written into software debug unit. 0 disable. the counter restarts by writing key into the wdt_restart register. 2 enable. the counter restarts by writing key into the wdt_restart register or by writing task id into the software debug unit. wdtin_dis if the other domain?s watchdog affects the current domain?s watchdog. *wdtin_dis is only reset by external reset pin. 0 this domain will be reset when other domain?s watchdog is timeout. 1 this domain doesn?t care about the other domain?s watchdog. key write access is allowed if key=0x22. rgu +0004h watchdog time-out interval register wdt_length bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name timeout[10:0] key[4:0] type r/w wo reset 111_1111_1111b key write access is allowed if key=08h. timeout the counter is restarted with {timeout [10:0], 1_1111_1111b}. thus the watchdog timer time- out period is a multiple of 512*t 32k =15.6ms. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 548 of 1535 rgu +0008h watchdog timer restart register wdt_restart bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[15:0] type wo reset key restart the counter if key=1971h. rgu +000ch watchdog timer status register wdt_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wdt sw_w dt type ro ro reset 0 0 wdt indicates the cause of the watchdog reset. 0 reset not due to watchdog timer. 2 reset because the watchdog timer time-out period expired. sw_wdt indicates if the watchdog was triggered by software. 0 reset not due to software-triggered watchdog timer. 1 reset due to software-triggered watchdog timer. note : a system reset does not affect this register. this bit is cleared when the wdt_mode register is written. rgu +0010h cpu peripheral software reset register sw_periph_r stn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved type reset rgu +0014h dsp software reset register sw_dsp_rstn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rst key type r/w reset 0 key write access is allowed if key=0x48. rst controls the dsp system reset control. 0 no reset. 1 invoke a reset. rgu +0018h watchdog timer re set signal duration register wdt_rstinte rval bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name length[ 11:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 549 of 1535 type r/w reset fffh length this register indicates the reset duration when watchdog timer times out. however, if the wdt_mode register irq bit is set to 1, an interrupt is issued instead of a reset. rgu+001ch watchdog timer softwa re reset register wdt_swrst bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[15:0] type wo reset software-triggered watchdog timer reset. if the register content matches the key, a watchdog reset is issued. however, if the wdt_mode register irq bit is set to 1, an interrupt is issued instead of a reset. key 1209h rgu+0020h rgu user-defined reset 0 rgu_usrst0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst0[7:0] type wo r/w reset 0 rgu+0024h rgu user-defined reset 1 rgu_usrst1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst1[7:0] type wo r/w reset 0 rgu+0028h rgu user-defined reset 2 rgu_usrst2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst2[7:0] type wo r/w reset 0 rgu+002ch rgu user-defined reset 3 rgu_usrst3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst3[7:0] type wo r/w reset 0 rgu+0030h rgu user-defined reset 4 rgu_usrst4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst4[7:0] type wo r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 550 of 1535 rgu+0034h rgu user-defined reset 5 rgu_usrst5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst5[7:0] type wo r/w reset 0 rgu+0038h rgu user-defined reset 6 rgu_usrst6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst6[7:0] type wo r/w reset 0 rgu+003ch rgu user-defined reset 7 rgu_usrst7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key[7:0] usrst7[7:0] type wo r/w reset 0 key write access is allowed if key=0xbb. user-defined resets can trigger individual resets derived by mcu. when the usrstx[7:0] is non-zero, the corresponding reset will be pull low. (all resets generated by rgu are active low) usrstx[6:0] is for a period of reset. it will decrease 1 per system clock when usrstx[6:0] is not equal to 0. it is suitable for a predefined period reset. usrstx[7] is for a manual reset. it is only changed by mcu and suitable for a manual reset fully controlled by mcu. generally speaking, usrstx[6:0] and usrstx[7] will not be non-zero at the same time. example1: 0 th cycle: usrstx = 0x0. resetx=1. mcu writes usrstx = 0x3. 1 st cycle: usrstx = 0x3. resetx=0. 2 nd cycle: usrstx = 0x2. resetx=0. 3 rd cycle: usrstx = 0x1. resetx=0. 4 th cycle: usrstx = 0x0. resetx=1. example2: 0 th cycle: usrstx = 0x0. resetx=1. mcu writes usrstx = 0x80. 1 st cycle: usrstx = 0x80. resetx=0. 2 nd cycle: usrstx = 0x80. resetx=0. ~ free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 551 of 1535 n th cycle: usrstx = 0x80. resetx=0. mcu writes usrstx = 0x0. n+1 th cycle: usrstx = 0x0. resetx=1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 552 of 1535 4 2.75g modem subsystem 4.1 automatic frequency control (afc) unit 4.1.1 general description the automatic frequency control (afc) unit provides the direct control of the oscillator for frequency offset and doppler shift compensation. the block diagram is of the afc unit depicted in figure 66. the module utilizes a 13-bit d/a converter to achieve high-resolution control. two modes of operation provide flexibility when controlling the oscillator; they are described as follows. active buffer power control apb bus tdma_afc ( from tdma timer ) write buffer afc_bu s control register tdma_evtval ( from tdma timer ) dac oscillator pdn_afc ( from global control ) vc afc unit immediate write output buffer pdn_dac f_mode i_mode afc figure 66 the block diagram of the afc controller in timer-triggered mode , the tdma timer controls the afc enabling events. each tdma frame can pulse at most four events. double buffer architecture is supported. afc values can be written to the write buffers. when the signal tdma_evtval is received, the values in the write buffers are latched into the active buffers. however, afc values can also be written to the active buffers directly. each event is associated with an active buffer sharing the same index. when a tdma event is triggered by tdma_afc, the value in the corresponding active buffer takes effect. figure 67 shows a timing diagram of afc events with respect to tx/rx/mx windows. in this mode, the d/a converter can stay powered on or be powered on for a programmable duration (256 quarter-bits, by default). the latter option is for power saving. rx mx mx tx afc_str0 afc_str3 afc_str2 afc_str1 figure 67 timing diagram for the afc controller in immediate mode , the mcu can directly control the afc value without event-triggering. the value written by the mcu takes effect immediately. in this mode, the d/a converter must be powered on continuously. when transitioning from immediate mode into timer-triggered mode (by setting flag i_mode in the register afc_con to be 0), the d/a converter is kept powered on for a programmable duration (256 quarter-bits by default) if a tdma_afc is not been pulsed. the duration is prolonged upon receiving events. external devices turn on afc dac: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 553 of 1535 because the external devices (ex. wifi & bluetooth) need 26mhz clock, afc dac is needed to power-up when baseband chip is under the sleep mode. the external devices can use srclkenai to turn on afc dac and vafc value will be as same as one that sw programs before the baseband chip enters the sleep mode. analog afc vafc $psf wifi srclkenao srclkenai digital afc 1%/ "'$@#64<> figure 68 architecture of external devices turning on afc dac while the mobile or wifi needs 26mhz, vafc is needed to turn on. one difference of on state is that vafc is adjustable (on mode) at the mobile one turning on, but otherwise vafc keeps at the same voltage (hold mode). in figure 4, while wifi is asserted (srclkenai=1), vafc will be turned on at the voltage which is set by the baseband chip before entering the sleep mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 554 of 1535 figure 69 waveform of afc dac on/off 4.1.2 register definitions register address register function acronym 0x81200000 afc control afc_con 0x81200004 afc control value 0 afc_dat0 0x81200008 afc control value 1 afc_dat1 0x8120000c afc control value 2 afc_dat2 0x81200010 afc control value 3 afc_dat3 0x81200014 afc power up period afc_puper table 67 afc registers 0x81200000 afc control register afc_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aly_o n rdac t f_mo de feten v i_mod e type r/w r/w r/w r/w r/w reset 0 0 0 0 0 four control modes are defined and can be controlled through the afc control register. f_mode enables the force power up mode. fetenv enables the direct write operation to the active buffer. i_mode enables the immediate mode. rdact enables the direct read operation from the active buffer. hold_on enables the afc dac hold mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 555 of 1535 i_mode the flag enables the immediate mode. to enable the immediate mode also enable the force power up mode. 0 the immediate mode is not enabled. 1 the immediate mode is enabled. fetenv the flag enables the direct write operation to the active buffer. note the control flag is only applicable to the for data buffer including afc_dat0 , afc_dat1 , afc_dat2 , and afc_dat3 . 0 apb write to the write buffer. 1 apb write to the active buffer. f_mode the flag enables the force power up mode. 0 the force power up mode is not enabled. 1 the force power up mode is enabled. rdact the flag enables the direct read operation from the active buffer. note the control flag is only applicable to the four data buffer including afc_dat0 , afc_dat1 , afc_dat2 , and afc_dat3 . 0 apb read from the write buffer. 1 apb read from the active buffer. aly_on force afc dac power on regardless of pdn_conx setting in software power down control 0 normal power down procedure of pdn_conx 1 force afc dac to keep power up state while srclkenai = 1?b1, afc dac will be turned on at the normal mode. srclkenai is a gpio_mux pin. make sure that the gpio mode is configured at the correct mode before bb enters the sleep mode. 0x81200004 afc data register 0 afc_dat0 bit 15 14 13 12 11 10 9 8 7 6 15 4 3 2 1 0 name afcd type r/w the register stores the afc value for the event 0 triggered by the tdma timer in timer-triggered mode. when the rdact or fetenv bit (of the afc_con register) is set, the data transfer operates on the active buffer. when neither flag is set, the data transfer operates on the write buffer. afcd the afc sample for the d/a converter. four registers ( afc_dat0 , afc_dat1 , afc_dat2 , afc_dat3 ) of the same type correspond to the event triggered by the tdma timer. the four registers are summarized in table 1 . register address register function acronym 0x81200004 afc control value 0 afc_dat0 0x81200008 afc control value 1 afc_dat1 0x8120000c afc control value 2 afc_dat2 0x81200010 afc control value 3 afc_dat3 table 1 afc data registers immediate mode can only use afc_dat0. in this mode, only the control value in the afc_dat0 write buffer is used to control the d/a converter. unlike timer-triggered mode, the control value in afc_dat0 write buffer can bypass the active buffer stage and be directly coupled to the output buffer in immediate mode. to use free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 556 of 1535 immediate mode, program the afc_dat0 in advance and then enable immediate mode by setting the i_mode flag in the afc_con register. the registers afc_data0 , afc_dat1 , afc_dat2 , and afc_dat3 have no initial values, thus the register must be programmed before any afc event takes place. the afc value for the d/a converter, i.e., the output buffer value, is initially 0 after power up before any event occurs. 0x81200014 afc power up period afc_puper bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pu_per type r/w reset ff this register stores the afc power up period, which is 13 bits wide. the value ranges from 0 to 8191. if the i_mode or f_mode flag is set, this register has no effect since the d/a converter is powered up continuously. if neither flag is set, the register controls the power up duration of the d/a converter. during that period, the signal pdn_dac in figure 66 is set to 1(power up). pu_per stores the afc power up period. after hardware power up, the field is initialized to 255. 4.1.3 application note in gsm, dcs and pcs mobile system, gsm05.10 specify the ms carrier frequency should be accurate to within 0.1 ppm, or accurate to within 0.1 ppm compared to signals received from the bts. in order to compensate the frequency error, which caused by bts frequency error or doppler shift effect, exists between ms and bts, afc (automatic frequency control) resides in ms should take the responsibility to adjust ms reference clock, 13mhz or 26mhz voltage controlled crystal oscillator (vcxo), in order to track up the frequency base of the signal from bts. because afc controls vcxo, vcxo characteristics will affect how to program afc data. typically, temperature compensated vcxo (tcvcxo) is used popularly in ms phone design, the following diagram illustrates the typical characteristic curve of tcvcxo in gsm900 and used on radio daughter board of mt62xx evb. therefore, by mt62xx evb design, the tuning range 0~8191 of mt62xx 13bit dac is mapping to the frequency error ?8535~ 10208 hz gotten from mt62xx report, and the slope is quite linear within 15% deviation in the full range of tcvcxo used for mt62xx dvb. by calculation, the slope is 2.367 hz/step, which the important parameter used in afc operation. actually, the slope is only valid for gsm900 application, layer 1 will convert it for dcs1800 or pcs1900, automatically. 4.2 automatic power control (apc) unit 4.2.1 general description the automatic power control (apc) unit controls the power amplifier (pa) module. through apc unit, the proper transmit power level of the handset can be set to ensure that burst power ramping requirements are met. in one tdma frame, up to 7 tdma events can be enabled to support multi-slot transmission. in practice, 5 banks of ramp profiles are used in one frame to make up 4 consecutive transmission slots. the shape and magnitude of the ramp profiles are configurable to fit ramp-up (ramp up from zero), intermediate ramp (ramp between transmission windows), and ramp-down (ramp down to zero) profiles. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 557 of 1535 each bank of the ramp profile consists of 16 8-bit unsigned values, which are adjustable for different conditions. the entries from one bank of the ramp profile are partitioned into two parts, with 8 values in each half. in normal operation, the entries in the left half are multiplied by a 10-bit left scaling factor, and the entries in the right half are multiplied by a 10-bit right scaling factor. the values are then truncated to form 16 10-bit intermediate values. finally the intermediate ramp profile are linearly interpolated into 32 10-bit values and sequentially used to update the d/a converter. the block diagram of the apc unit is shown in figure 70 . the apb bus interface is 32 bits wide. four write accesses are required to program each bank of ramp profile. the detailed register allocations are listed in table 68. z ramp profile, scaling factor, & offset multiplier & interpolator apb i/f apb bus (32bits data bus) apc_bus (10 bits) dac_pu dac power and clock control output buffer tdma_apcen ( from tdma timer ) tdma_apcstr (0~6) ( from tdma timer) qbit_en apc unit pdn_apc ( from global control) figure 70 block diagram of apc unit. 4.2.2 register definitions 0x82040000 apc 1st ramp profile #0 apc_pfa0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ent3 ent2 type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ent1 ent0 type r/w r/w the register stores the first four entries of the first power ramp profile. the first entry resides in the least significant byte [7:0], the second entry in the second byte [15:8], the third entry in the third byte [23:16], and the fourth in the most significant byte [31:24]. since this register provides no hardware reset, the programmer must configure it before any apc event takes place. ent3 the field signifies the 4 th entry of the 1 st ramp profile. ent2 the field signifies the 3 rd entry of the 1 st ramp profile. ent1 the field signifies the 2 nd entry of the 1 st ramp profile. ent0 the field signifies the 1 st entry of the 1 st ramp profile. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 558 of 1535 the overall ramp profile register definition is listed in table 68. register address register function acronym 0x82040000 apc 1 st ramp profile #0 apc_pfa0 0x82040004 apc 1 st ramp profile #1 apc_pfa1 0x82040008 apc 1 st ramp profile #2 apc_pfa2 0x8204000c apc 1 st ramp profile #3 apc_pfa3 0x82040020 apc 2 nd ramp profile #0 apc_pfb0 0x82040024 apc 2 nd ramp profile #1 apc_pfb1 0x82040028 apc 2 nd ramp profile #2 apc_pfb2 0x8204002c apc 2 nd ramp profile #3 apc_pfb3 0x82040040 apc 3 rd ramp profile #0 apc_pfc0 0x82040044 apc 3 rd ramp profile #1 apc_pfc1 0x82040048 apc 3 rd ramp profile #2 apc_pfc2 0x8204004c apc 3 rd ramp profile #3 apc_pfc3 0x82040060 apc 4 th ramp profile #0 apc_pfd0 0x82040064 apc 4 th ramp profile #1 apc_pfd1 0x82040068 apc 4 th ramp profile #2 apc_pfd2 0x8204006c apc 4 th ramp profile #3 apc_pfd3 0x82040080 apc 5 th ramp profile #0 apc_pfe0 0x82040084 apc 5 th ramp profile #1 apc_pfe1 0x82040088 apc 5 th ramp profile #2 apc_pfe2 0x8204008c apc 5 th ramp profile #3 apc_pfe3 0x820400a0 apc 6 th ramp profile #0 apc_pff0 0x820400a4 apc 6 th ramp profile #1 apc_pff1 0x820400a8 apc 6 th ramp profile #2 apc_pff2 0x820400ac apc 6 th ramp profile #3 apc_pff3 0x820400c0 apc 7 th ramp profile #0 apc_pfg0 0x820400c4 apc 7 th ramp profile #1 apc_pfg1 0x820400c8 apc 7 th ramp profile #2 apc_pfg2 0x820400cc apc 7 th ramp profile #3 apc_pfg3 table 68 apc ramp profile registers 0x82040010 apc 1st ramp profile left scaling factor apc_scal0l bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sf type r/w reset 1_0000_0000 the register stores the left scaling factor of the 1 st ramp profile. this factor multiplies the first 8 entries of the 1 st ramp profile to provide the scaled profile, which is then interpolated to control the d/a converter. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 559 of 1535 after a hardware reset, the initial value of the register is 256. in this case, no scaling is done (each entry of the ramp profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication. the overall scaling factor register definition is listed in table 69 . sf scaling factor. after a hardware reset, the value is 256. 0x82040014 apc 1st ramp profile right scaling factor apc_scal0r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sf type r/w reset 1_0000_0000 the register stores the right scaling factor of the 1 st ramp profile. this factor multiplies the last 8 entries of the 1 st ramp profile to provide the scaled profile, which is then interpolated to control the d/a converter. after a hardware reset, the initial value of the register is 256. in this case, no scaling is done (each entry of the ramp profile is multiplied by 1), because the 8 least significant bits are truncated after multiplication. the overall scaling factor register definition is listed in table 69 . sf scaling factor. after a hardware reset, the value is 256. 0x82040018 apc 1st ramp profile offset value apc_offset0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset type r/w reset 0 there are 7 offset values for the corresponding ramp profile. the 1 st offset value also serves as the pedestal value. the value is used to power up the apc d/a converter before the rf signals start to transmit. the d/a converter is then biased on the value, to provide the initial control voltage for the external control loop. the exact value depends on the characteristics of the external components. the timing to output the pedestal value is configurable through the tdma_bulcon2 register of the timing generator; its valid range is 0~127 quarter-bits of time after the baseband d/a converter is powered up. offset offset value for the corresponding ramp profile. after a hardware reset, the default value is 0. the overall offset register definition is listed in table 69. register address register function acronym 0x82040010 apc 1 st ramp profile left scaling factor apc_scal0l 0x82040014 apc 1 st ramp profile right scaling factor apc_scal0r 0x82040018 apc 1 st ramp profile offset value apc_offset0 0x82040030 apc 2 nd ramp profile left scaling factor apc_scal1l 0x82040034 apc 2 nd ramp profile right scaling factor apc_scal1r 0x82040038 apc 2 nd ramp profile offset value apc_offset1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 560 of 1535 0x82040050 apc 3 rd ramp profile left scaling factor apc_scal2l 0x82040054 apc 3 rd ramp profile right scaling factor apc_scal2r 0x82040058 apc 3 rd ramp profile offset value apc_offset2 0x82040070 apc 4 th ramp profile left scaling factor apc_scal3l 0x82040074 apc 4 th ramp profile right scaling factor apc_scal3r 0x82040078 apc 4 th ramp profile offset value apc_offset3 0x82040090 apc 5 th ramp profile left scaling factor apc_scal4l 0x82040094 apc 5 th ramp profile right scaling factor apc_scal4r 0x82040098 apc 5 th ramp profile offset value apc_offset4 0x820400b0 apc 6 th ramp profile left scaling factor apc_scal5l 0x820400b4 apc 6 th ramp profile right scaling factor apc_scal5r 0x820400b8 apc 6 th ramp profile offset value apc_offset5 0x820400d0 apc 7 th ramp profile left scaling factor apc_scal6l 0x820400d4 apc 7 th ramp profile right scaling factor apc_scal6r 0x820400d8 apc 7 th ramp profile offset value apc_offset6 table 69 apc scaling factor and offset value registers 0x820400e0h apc control register apc_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gsm fpu type r/w r/w reset 1 0 gsm defines the operation mode of the apc module. in gsm mode, each frame has only one slot, thus only one scaling factor and one offset value must be configured. if the gsm bit is set, the programmer needs only to configure apc_scal0l and apc_offset0 . if the bit is not set, the apc module is operating in gprs mode. 0 the apc module is operating in gprs mode. 1 the apc module is operating in gsm mode. default value. fpu forces the apc d/a converter to power up. test only. 0 the apc d/a converter is not forced to power up. the converter is only powered on when the transmission window is opened. default value. 1 the apc d/a converter is forced to power up. 4.2.3 ramp profile programming the first value of the first normalized ramp profile must be written in the least significant byte of the apc_pfa0 register. the second value must be written in the second least significant byte of the apc_pfa0 , and so on. each ramp profile can be programmed to form an arbitrary shape. the start of ramping is triggered by one of the tdma_apcstr signals. the timing relationship between tdma_apcstr and tdma slots is depicted in figure 71 for 4 consecutive time slots case. the power free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 561 of 1535 ramping profile must comply with the timing mask defined in gsm spec 05.05. the timing offset values for 7 ramp profiles are stored in the tdma timer register from tdma_apc0 to tdma_apc6 . rx mx tx rx tdma_apcstr0 tdma_apcstr1 tx tx tx tdma_apcstr2 tdma_apcstr3 tdma_apcstr4 figure 71 timing diagram of tdma_apcstr. because the apc unit provides more than 5 ramp profiles, up to 4 consecutive transmission slots can accommodated. the 2 additional ramp profiles are useful particularly when the timing between the last 2 transmission time slots and ctirq is uncertain; software can begin writing the ramp profiles for the succeeding frame during the current frame, alleviating the risk of not writing the succeeding frame?s profile data in time. in gprs mode, to fit the intermediate ramp profile between different power levels, a simple scaling scheme is used to synthesize the ramp profile. the equation is as follows: 8 15 if 1, 0 8 if 0, 0,1,...,15 , dn s off da ,...,15 1 , 2 dn dn s off da 2 dn dn s off da 1 2 1 2 0 , 15 0 0 ? ? ? > = = ? + = = + ? + = + ? + = + ? k k l k k k l k k k l k pre where da = the data to present to the d/a converter, dn = the normalized data which is stored in the register apc_pf n , s 0 = the left scaling factor stored in register apc_scal nl , s 1 = the right scaling factor stored in register apc_scal nr , and off = the offset value stored in the register apc_offset n . the subscript n denotes the index of the ramp profile. the ramp calculation before interpolation is as depicted in figure 72 . during each ramp process, each word of the normalized profile is first multiplied by 10-bit scaling factors and added to an offset value to form a bank of 18-bit words. the first 8 words (in the left half part as in figure 72 ) are multiplied by the left scaling factor s 0 and the last 8 words (in the right half part as in figure 72 ) are multiplied by the right scaling factor s 1 . the lowest 8 bits of each word are then truncated to get a 10-bit result. the scaling factor is 0x100, which represents no scaling on reset. a value smaller than 0x100 scales the ramp profile down, and a value larger than 100 scales the ramp profile up. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 562 of 1535 z dn 0 * s 0 + off dn 4 * s 0 + off dn 8 * s 1 + off dn 12 * s 1 + off dn 15 * s 1 + off 16 qb dn 4 * s 0 dn 8 * s 1 off figure 72 the timing diagram of the apc ramp. the 16 10-bit words are linearly interpolated into 32 10-bit words. a 10-bit d/a converter is then used to convert these 32 ramp values at a rate of 1.0833 mhz, that is, at quarter-bit rate. the timing diagram is shown in figure 73 and the final value is retained on the output until the next event occurs. z tx tx tx burst tx burst tdma_apcstr0 ramp profile ramp profile ramp profile tdma_apcstr2 tdma_apcstr1 ~29.5us ~29.5us apc_data tdma_apcstr1 1 3 2 29 30 31 tdma_apcen tdma_apcstrx ~29.5us offset figure 73 timing diagram of the apc ramping. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 563 of 1535 the apc unit is only powered up when the apc window is open. the apc window is controlled by configuring the tdma registers tdma_bulcon 1 and tdma_bulcon2 . please refer to the tdma timer unit for more detailed information. the first offset value stored in the register apc_offset0 also serves as the pedestal value, which is used to provide the initial power level for the pa. since the profile is not double-buffered, the timing to write the ramping profile is critical. the programmer must be restricted from writing to the data buffer during the ramping process, otherwise the ramp profile may be incorrect and lead to a malfunction. 4.3 baseband front end baseband front end is a modem interface between tx/rx mixed-signal modules and digital signal processor (dsp). we can divide this block into two parts (see figure 74 ). the first is the uplink (transmitting) path, which converts bit-stream from dsp into digital in-phase (i) and quadrature (q) signals for tx mixed-signal module. the second part is the downlink (receiving) path, which receives digital in-phase (i) and quadrature (q) signals from rx mixed-signal module, performs fir filtering and then sends results to dsp. figure 74 illustrates interconnection around baseband front end. in the figure the shadowed blocks compose baseband front end. to enhance the capability of data processing of mobile phone and base station, the enhanced data for gsm evolution (edge), which used 8psk modulation rather than gmsk modulation in gsm system may provide the triple data transmission rate of 384 kbps for system to supply the solution of voice, data, internet linkage, and other kinds of mutual linkage, while 3bits per symbols in 8psk modulation and 1 bit per symbol in gmsk modulation. the uplink path is mainly composed of gmsk modulator or 8psk modulator and uplink parts of baseband serial ports, and the downlink path is mainly composed of rx digital fir filter and downlink parts of baseband serial ports. baseband serial ports is a serial interface used to communicate with dsp. in addition, there is a set of control registers in baseband front end that is intended for control of tx/rx mixed-signal modules, inclusive of several compensation circuit :calibration of i/q dc offset, i/q quadrature phase compensation and i/q gain mismatch of uplink analog-to-digital (d/a) converters as well as i/q gain mismatch for downlink digital-to-analog (a/d) converters in tx/rx mixed-signal modules. the timing of bit streaming through baseband front end is completely under control of tdma timer. usually only either of uplink and downlink paths is active at one moment. however, both of the uplink and downlink paths will be active simultaneously when baseband front end is in loopback mode. when either of tx windows in tdma timer is opened, the uplink path in baseband front end will be activated. accordingly components on the uplink path such as gmsk modulator or 8psk modulator will be powered on, and then tx mixed-signal module is also powered on. the subblock baseband serial ports will sink tx data bits from dsp and then forward them to gmsk modulator or 8psk modulator. the outputs from gmsk modulator or 8psk modulator are sent to tx mixed-signal module in format of i/q signals. finally d/a conversions are performed in tx mixed-signal module and the output analog signal is output to rf module. additionally, 8psk modulation intrinsically extends the bursts window and reports in 8mvd (8psk modulation valid) in bfe_sta status register. similarly, while either of rx windows in tdma timer is opened, the downlink path in baseband front end will be activated. accordingly components on the downlink path such as rx mixed-signal module and rx digital free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 564 of 1535 fir filter are then powered on. first a/d conversions are performed in rx mixed-signal module, and then the results in format of i/q signals are sourced to low pass filtering with different bandwidth (narrow one about fc = 90 khz, wide one about fc = 110khz), interference detection circuit to determine which filter to be used by judging receiving power on current burst, additionally, ?i/q compensation circuit? is an option in data path for modifying receiving i/q pair gain mismatch.. finally the results will be sourced to dsp through baseband serial ports. gmsk/8psk modulator p/s rx digital fir filter 10 bits i-signal 10 bits q-signal comb filter 16bits i-signal 16 bits q-signal bbtx bbrx 2 bits i-signal 2 bits q-signal uplink path downlink path 4 bits i/q-signal 1x bit stream rx itd iir filter 16bits i-signal 16 bits q-signal figure 74 block diagram of baseband front end 4.3.1 baseband serial ports 4.3.1.1 general description baseband front end communicates with dsp through the sub block of baseband serial ports. baseband serial ports interfaces with dsp in serial manner. this implies that dsp must be configured carefully in order to have baseband serial ports cooperate with dsp core correctly. if downlink path is programmed in bypass-filter mode ( not bypass-filter loopback mode), behavior of baseband serial ports will be completely be different from that in normal function mode. the special mode is for testing purpose. please see the subsequent section of downlink path for more details. tx and rx windows are under control of tdma timer. please refer to functional specification of tdma timer for the details on how to open/close a tx/rx window. opening/closing of tx/rx windows have two major effects on baseband front end: power on/off of corresponding components and data souring/sinking. it is worth noticing that baseband serial ports is only intended for sinking tx data from dsp or sourcing data to dsp. it does not involve power on/off of tx/rx mixed-signal modules. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 565 of 1535 as far as downlink path is concerned, if a rx window is opened by tdma timer baseband front end will have rx mixed-signal module proceed to make a/d conversion, two parallel rx digital filter proceed to perform filtering and baseband serial ports be activated to source data from rx digital filter to master dsp. however, the interval between the moment that rx mixed-signal module is powered on and the moment that data proceed to be dumped by baseband serial ports can be well controlled in tdma timer. let us denote rx enable window as the interval that rx mixed-signal module is powered on and denote rx dump window as the interval that data is dumped by baseband serial ports. if the first samples from rx digital filter desire to be discarded, the corresponding rx enable window must cover the corresponding rx dump window. note that rx dump windows always win over rx enable windows. it means that a rx dump window will always raise a rx enable window. rx enable windows can be raised by tdma timer or by programming rx power- down bit in global control registers to be ?0?. this is useful in debugging environment. similarly, a tx dump window refers to the interval that baseband serial ports sinks data from dsp on uplink path and a tx enable window refers to the interval that tx mixed-signal module is powered on. a tx window controlled by tdma timer involves a tx dump window and a tx enable window simultaneously. the interval between the moment that tx mixed-signal module is powered on and the moment that data proceed to be forwarded from dsp to gmsk or 8psk modulator by baseband serial ports can be well controlled in tdma timer. tx dump windows always win over tx enable windows. it means that a tx dump window will always raise a tx enable window. tx enable windows can be raised by tdma timer or by programming tx power- down bit in global control registers to be ?0?. it is useful in debugging environment. accordingly, baseband serial ports are only under the control of tx/rx dump window. note that if tx/rx dump window is not integer multiplies of bit-time it will be extended to be integer multiplies of bit-time. for example, if tx/rx dump window has interval of 156.25 bit-times then it will be extended to 157 bit-times in baseband serial ports. for uplink path, if uplink path is enabled, then the bit bulen (baseband up-link enable) will be ?1?. otherwise the bit bulen will be 0. the mdsel (modulation mode select [3:0]) in tx_conf control register needs to be latched in mdsel shadow register according to the rising edge of tdma event validate signal from tdma controller, which used to indicate the modulation scheme selection between 8psk or gmsk modulator for four transmit burst. generally there will at most 4 sequential bursts, 1 st burst, 2 nd burst, 3 rd bursts, and 4 th bursts, which are not necessary to be all turn on in a burst sequence. the btxen1, btxen2, btxen3, btxen4 will be asserted prior to each bursts, and their rising edge will update the mode selection control bit to select appropriate modulation type for current input data symbols in each bursts. additionally, this mode selection status for each bursts will be stored in bfe_sta status register, including mdsts1 (modulation mode status1) , mdsts2(modulation mode status2), mdsts3(modulation mode status3), mdsts4(modulation mode status4), respectively.(figure 75 uplink modulation mode selection status timing diagram) during these 4 bursts valid period, the bit bulfs (baseband uplink frame sync) in bfe_sta status register will be ?1?. otherwise will be ?0?. meanwhile, uplink path will forward tx bit from dsp to gmsk modulator or 8psk free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 566 of 1535 modulation bultxen4 bultxen3 bultxen2 bultxen1 mdsts1 mdsts2 mdsts3 mdsts4 bulfs 1st burst 2nd burst 3rd burst 4th burst for 4th burst for 3rd burst for 2nd burst for 1st burst mdsel1 tdma event validate c mdsel shadow register mdsel from apb bus figure 75 uplink modulation mode selection status timing diagram for downlink path, if bdlen (baseband downlink enable) is enabled, rx mixed-signal module will also be powered on. similarly, once uplink path is enabled, tx mixed-signal module will also be powered on. furthermore, enabling bdlfs (baseband down-link framesync) baseband serial ports for downlink path refers to dumping results from rx digital fir filter to dsp. 4.3.1.2 register definitions 0x82100000 base-band common control register bfe_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bcien type r/w reset 0 this register is for common control of baseband front end. it consists of ciphering encryption control. bcien the bit is for ciphering encryption control. if the bit is set to ?1?, xor will be performed on some tx bits (payload of normal burst) and ciphering pattern bit from dsp, and then the result is forwarded to gmsk modulator only. meanwhile, baseband front end will generate signals to drive dsp ciphering process and produce corresponding ciphering pattern bits if the bit is set to ?1?. if the bit is set to ?0?, the tx bit from dsp will be forwarded to gmsk modulator directly. baseband front end will not activate dsp ciphering process. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 567 of 1535 0 disable ciphering encryption. 1 enable ciphering encryption. 0x82100004 base-band common status register bfe_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mdst s4 mdst s3 mdst s2 mdst s1 bule n4 bule n3 bule n2 bule n1 bulfs 4 bulfs 3 bulf s2 bulfs 1 bdlfs bdle n type ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register indicates status of baseband front end this register indicates status of baseband front end. under control of tdma timer, baseband front end can be driven in several statuses. if downlink path is enabled, then the bit bdlen will be ?1?. otherwise the bit bdlen will be ?0?. if downlink parts of baseband serial ports is enabled, the bit bdlfs will be ?1?. otherwise the bit bdlfs will be ?0?. if uplink path is enabled, then the bit bulen will be ?1?. otherwise the bit bulen will be 0. if uplink parts of baseband serial ports is enabled, the bit bulfs will be ?1?. otherwise the bit bulfs will be ?0?. once downlink path is enabled, rx mixed-signal module will also be powered on. similarly, once uplink path is enabled, tx mixed-signal module will also be powered on. furthermore, enabling baseband serial ports for downlink path refers to dumping results from rx digital fir filter to dsp. similarly, enabling baseband serial ports for uplink path refers to forwarding tx bit from dsp to gmsk modulator. bdlen stands for ? b aseband d own l ink en able?. bulen stands for ? b aseband u p l ink en able?. bdlfs stands for ? b aseband d own l ink f rame s ync?. bulfs stands for ? b aseband u plink f rame s ync?. bdlen indicate if downlink path is enabled. 0 disabled 1 enabled bdlfs indicate if baseband serial ports for downlink path is enabled. 0 disabled 1 enabled bulfs1 indicate if baseband serial ports for uplink path is enabled in 1 st burst 0 disabled 1 enabled bulfs2 indicate if baseband serial ports for uplink path is enabled in 2 nd burst 0 disabled 1 enabled bulfs3 indicate if baseband serial ports for uplink path is enabled in 3 rd burst 0 disabled 1 enabled bulfs4 indicate if baseband serial ports for uplink path is enabled in 4 th burst 0 disabled 1 enabled bulen1 indicate if uplink path is enabled in 1 st burst. 0 disabled 1 enabled free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 568 of 1535 bulen2 indicate if uplink path is enabled in 2 nd burst. 0 disabled 1 enabled bulen3 indicate if uplink path is enabled in 3 rd burst. 0 disabled 1 enabled bulen4 indicate if uplink path is enabled in 4 th burst. 0 disabled 1 enabled mdsts1 indicate the current modulation mode selection in 1 st burst 0 gmsk modulation 1 8psk modulation mdsts2 indicate the current modulation mode selection in 2 nd burst 0 gmsk modulation 1 8psk modulation mdsts3 indicate the current modulation mode selection in 3 rd burst 0 gmsk modulation 1 8psk modulation mdsts4 indicate the current modulation mode selection in 4 th burst 0 gmsk modulation 1 8psk modulation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 569 of 1535 4.3.2 downlink path (rx path) 4.3.2.1 general description on the downlink path, the sub-block between rx mixed-signal module and baseband serial ports is rx path. it mainly consists of two parallel digital fir filter with programmable tap number, two sets of multiplexing paths for loopback modes, interface for rx mixed-signal module, interference detection circuit, i/q gain mismatch compensation circuit, and interface for baseband serial ports. the block diagram is shown in figure 76 block diagram of rx path. while rx enable windows are open, rx path will issue control signals to have rx mixed-signal module proceed to make a/d conversion. as each conversion is finished, one set of i/q signals will be latched. there exists a digital fir filter for these i/q signals. the result of filtering will be dumped to baseband serial ports whenever rx dump windows are opened. rx_comp.v rxfltr_tap.v 14 bits 14 bits 14 bits 14 bits rx_path.v 18 bits 18 bits programmable tap/coefficient fir (adjacent channel) programmable tap/coefficient fir (co-channel) high pass filter (adjacent channel) band pass filter (co-channel) power measurement rx_bsp.v 16 bits 16 bits 16 bits 1 bits 540 khz 540 khz 540 khz 26 mhz 52 mhz 540 khz 52 mhz 26 mhz 2 bits 2 bits 16 bits loopback path bypass fir loopback path througth fir clock rate data rate figure 76 block diagram of rx path 4.3.2.2 comb filter the comb filter which takes the 2-bit a/d converter as input, and output the 18-bit i/q data words to the baseband receiving path. the system is designed as 48x over-sampling with symbol period 541.7 khz, thus the data inputs are 26mhz 2-bit signal. the input 2-bit signals are formed in (sign, magnitude) manner; that is, total 3 values are permitted as input: (-1, 0, +1). the data path is mainly a decimation filter which contains the integration stages and the decimation stages. for a 3 rd order design with 48x over-sampling, gain of the data path is 48 3 = 110592, which locates between 2 16 and 2 17 . thus the internal word-length must be set to 18-bit to avoid overflow in the integration process. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 570 of 1535 4.3.2.3 compensation circuit - i/q gain mismatch in order to compensate i/q gain mismatch , configure igainsel(i gain selection) in rx_con control register, the i over q ratio can be compensate for 0.3 db/step, totally 11 steps resulted in dynamic range up to +/-1.5db. rx_filter i/q mismatch compensation 14 14 14 q i a/d a/d 16 figure 77 i/q mismatch compensation block diagram the i/q swap functionality can be setting ?1? for swap(i/q swapping) in rx_cfg control register, which is used to swap i/q channel signals from rx mixed-signal module before they are latched into rx digital fir filter. it is intended to provide flexibility for i/q connection with rf modules 4.3.2.4 phase de-rotation circuit phase de-rotation mode will usually turn on during fcb detection for down conversion the wide spread receiving power to 67.7 khz single tone. two separate control for implement this mode on data path through narrowfir filter or widefir filter by setting ?1? to phroen_n (phase rotate enable for narrowfir) or phroen_w(phase rotate enable for widefir) in rx_con control register, respectively. 4.3.2.5 adaptive bandwidth & pr ogrammable digital fir filter for the two parallel digital fir filter, the total tap number is programmable by firtpno(fir tap number) in rx_cfg control register, which will configure the filter with different tap buffer depth. 4.3.2.5.1 programmable tap & programmable coefficient for fir in order to satisfy the signal requirements in both of idle and traffic modes, two sets of coefficients must be provided for the rx digital fir filter. therefore, the rx digital fir filter is implemented as a fir filter with programmable coefficients which can be accessed on the apb bus. the coefficient number can be programmable, range from 1~31. each coefficient is ten-bit wide and coded in 2?s complement. take 21 tap coefficient for example, based on assumption that the fir filter has symmetric coefficients, only 11 coefficients are implemented as programmable registers to save gate count. denoting these digital filter coefficients as rx_ram0_cs0 ~ rx_ram0_cs11 (rx_ram0 coefficient set 0~11), and these tap registers for i/q channel signals as i/qtapr [0:20], then the rx digital fir filtering can be represented as the following equation: , ! p " % ' / ' ) & 5 > l @ , 7 $ 3 5 > l @ % ' / ' ) & 5 > @ , 7 $ 3 5 > @ % ' / ' ) & 5 > l @ ! , 7 $ 3 5 > l @ , 7 $ 3 5 > l @ " r x w l l d w w l p h q p 4 ! p " % ' / ' ) & 5 > l @ 4 7 $ 3 5 > l @ % ' / ' ) & 5 > @ 4 7 $ 3 5 > @ % ' / ' ) & 5 > l @ ! 4 7 $ 3 5 > l @ 4 7 $ 3 r x w l d w w l p h q p | | | 5 > l @ " l % ' / ' ) & 5 > l @ % ' / ' ) & 5 > l @ l | where itapr [0] and qtapr [0] are the latest samples for i- and q-channel respectively and assume ) 0 ( ), 0 ( out out q i are obtained based on the content of tap registers at time moment n . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 571 of 1535 additionally, the data sequence of two parallel fir filter output will dump to master dsp rx buffer in following order : ?i channel output from narrow fir?=> ? i channel output from wide fir??=>?q channel output from narrow fir=>? q channel output from wide fir. 4.3.2.5.2 coefficient set selection the coefficient set used for digital fir can be changed during different burst mode switching. for example, during normal burst while no fb_strobe (frequency burst strobe, comes from tdma controller) assertion, defined as ?state b?, ?coefficient set id? (cs id) selection for both narrow/wide filter can be configured by st_b_wcof_sel(state b wide fir coefficient selection) and ?st_b_ncof_sel? (state b narrow fir coefficient selection) on rx_fir_csid_con control register, respectively. usually during state b, layer 1 software will select ram table confidence from either ram0 or ram1 table in condition i for narrow fir and wide fir, respectively. the cs id for both narrow / wide fir filter be stored at slave dsp rx buffer once tdma trigger rx interrupt to dsp..st_a_ncof_sel? (state a narrow fir coefficient selection) on rx_fir_csid_con control register. during fcb detection, mcu will notice tdma controller by assertion fb_strobe, defined as ?statea?. ?coefficient set id? ( cs id) selection for both narrow/wide filter can be configured by st_a_wcof_sel(state a wide fir coefficient selection) and ?st_a_ncof_sel? (state a narrow fir coefficient selection) on rx_fir_csid_con control register, respectively. usually during state b, layer 1 software will select cs id 2 and csid 3 from either rom0 or rom1 table or ram0 or ram1 table in condition ii for narrow fir and wide fir, respectively. 4.3.2.5.3 interference detection circuit for adaptive bandwidth scheme used to compare the power of co-channel interference and adjacent-channel interference for determine if widefir filter is needed rather than default narrowfir filter. two parallel path of power measurement for evaluating co-channel effect or adjacent channel effect by analyzing power after high pass filter (hpf) or band pass filter (bpf), respectively. if co-channel effect is worse than adjacent channel effect, widefir filter is needed. the power measurement is accumulate i/q root mean square (rms) power over the whole rx burst window, while exact accumulation period within the burst can be adjusted the starting point offset and duration length.. the ?starting point offset? and be configured by ?rxid_pwr_off[7:0]? ( rx interference detection power starting point offset) and duration period by ? rxid_pwr_per[7:0]?(rx interference detection power duration period) in rx_pm_con control register, while default value for starting offset is 11 and duration period is 141. the two accumulated power measurement output for co-channel and adjacent-channel will be received by dsp through dsp i/o port at the end of the duration period within a burst. the power result can be further scale down by control the pwr_shft_no( power right shift number) in rx_con control register. e.g. set to ?1? will divide the power output by two. 4.3.2.6 debug mode 4.3.2.6.1 normal mode bypass filter by setting ?1? for bypfltr(bypass filter) in rx_cfg control register, the adc outputs out of rx mixed- signal module will be directed into baseband serial ports directly without through fir. limited by bandwidth of the serial interface between baseband serial ports and dsp, only adc outputs which are from either i- channel or q-channel adc can be dumped into dsp. both i- and q-channel adc outputs cannot be dumped free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 572 of 1535 simultaneously. which channel will be dumped is controlle d by the register bit swap of the control register rx_cfg when downlink path is programmed in ?bypass rx digital fir filter? mode. see register definition below for more details. the mode is for measurement of performance of a/d converters in rx mixed-signal module. 4.3.2.6.2 tx-rx digital loopback mode (debug mode) in addition to normal function, there are two loopback modes in rx path. one is bypass-filter loopback mode, and the other is through-filter loopback mode. they are intended for verification of dsp firmware and hardware. the bypass-filter loopback mode refers to that rx digital fir filter is not on the loopback path. however, the through-filter loopback mode refers to that rx digital fir filter is on the loopback path, while ? thru-filter loopback mode? can be configured by setting ?2?b10? for blpen(baseband loopback enable) or ?bypass-filter loopback mode? by setting ? 2?b01? for blpen in rx_con control register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 573 of 1535 4.3.2.7 register definitions 4.3.2.7.1 apb register 0x82100010 rx configuration register rx_cfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name firtpno bypfl tr swap type r/w r/w r/w reset 000000 0 0 this register is for configuration of downlink path, inclusive of configuration of rx mixed-signal module and rx path in baseband front end. swap this register bit is for control of whether i/q channel signals need to swap before they are inputted to baseband front end. it provides flexibility flexible of connection of i/q channel signals between rf module and baseband module. the register bit has another purpose when the register bit ?bypfltr? is set to 1. please see description for the register bit ?bypfltr?. 0 i- and q-channel signals are not swapped 1 i- and q-channel signals are swapped bypfltr bypass rx fir filter control. the register bit is used to configure baseband front end in the state called ?bypass rx fir filter state? or not. once the bit is set to ?1?, rx fir filter will be bypassed. that is, adc outputs of rx mixed-signal module that are has 14-bit resolution and at sampling rate of 571 khz can be dumped into dsp by baseband serial ports and rx fir filtering will not be performed on them. 0 not bypass rx fir filter 1 bypass rx fir filter firtpno rx fir filter tap no. select. this control register will control the two parallel digital filter with different tap buffer depth since the fir function in symmetric behavior. the maximum tap number is 31, minimum is 1. odd number only. 00001 1 tap 00011 3 tap 11101 29 tap 11111 31 tap 0x82100014 rx control register rx_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwr_shft_no igainsel ph_r oen_ n ph_r oen_ w blpen type r/w r/w r/w r/w r/w reset 0000 0000 0 0 00 this register is for control of downlink path, inclusive of control of rx mixed-signal module and rx path in baseband front end module. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 574 of 1535 blpen the register field is for loopback configuration selection in baseband front end. 00 configure baseband front end in normal function mode 01 configure baseband front end in bypass-filter loopback mode 10 configure baseband front end in through-filter loopback mode 11 reserved ph_roen_w enable for i/q pair phase de-rotation in wide fir data path, 0 disable phase de-rotation for i/q pair 1 enable phase de-rotation for i/q pair ph_roen_n enable for i/q pair phase de-rotation in narrow fir data path, 0 disable phase de-rotation for i/q pair. 1 enable phase de-rotation for i/q pair igainsel rx i data gain compensation select. 0.3db/step, totally 11 steps and dynamic range up to +/- 1.5db for 0000 compensate 0db for i/q 0001 compensate 0.3db for i/q 0010 compensate 0.6db for i/q 0011 compensate 0.9db for i/q 0100 compensate 1.2db for i/q 0101 compensate 1.5db for i/q 1001 compensate ?0.3db for i/q 1010 compensate -0.6db for i/q 1011 compensate ?0.9db for i/q 1100 compensate ?1.2db for i/q 1101 compensate ?1.5db for i/q default no compensation for i/q pwr_shft_no power measuring result right shift number. the power level measurement result can be right shift from 0 to 15 bits. 0x82100018 rx interference detection power measurement control register rx_pm_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxid_pwr_per rxid_pwr_off type r/w r/w reset 0x8d 0xb rxid_pwr_off rx interference detection power measurement starting offset. setting this register will delay the starting time of interference detection power measurement in symbol time unit. maximum value is 156, while default value is 11 (0xb). rxid_pwr_per rx interference detection power measurement accumulation period. by setting this control register will determine the length of accumulation duration for power measurement. minimum value is 0, maximum value is 156, while default value is 141(0x8d). please notice that rxid_pwr_off + rxid_pwr_per should less than 154 due to hardware implementation limitation. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 575 of 1535 0x8210001c rx fir coefficient set id control register rx_fir_csid_c on bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name st_a_ncof_sel st_b_ncof_sel st_b_wcof_sel type r/w r/w r/w reset 0000 0010 0011 these three set of coefficient set id will be dump to slave dsp rx buffer for indicating the current selection of fir coefficient from either ram or rom table, while csid= 0 represents rom table selection, and csid2~csid15 represent ram table selection. st_b_wcof_sel state b coefficient set selection for wide fir. st_b_ncof_sel state b coefficient set selection for narrow fir. st_a_ncof_sel state a coefficient set selection for narrow fir. 0x82100070 rx ram0coefficient set 0register rx_ram0_cs0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_ram0_cs0 type r/w reset 000000000 this register is 1 st of the 16 coefficient in ram0 table, coefficient set id 2 or 4. the content is coded in 2?s complement. that is, its maximum is 255 and its minimum is ?256, while the total coefficient number in this coefficient set has to be greater than half of tapno(programmable tap no.) and smaller than half of maximum tap no(15). register address register function acronym 0x82100070 rx ram0coefficient set 0 register rx_ram0_cs0 0x82100074 rx ram0coefficient set 1 register rx_ram0_cs1 0x82100078 rx ram0coefficient set 2 register rx_ram0_cs2 0x8210007c rx ram0coefficient set 3 register rx_ram0_cs3 0x82100080 rx ram0coefficient set 4 register rx_ram0_cs4 0x82100084 rx ram0coefficient set 5 register rx_ram0_cs5 0x82100088 rx ram0coefficient set 6 register rx_ram0_cs6 0x8210008c rx ram0coefficient set 7 register rx_ram0_cs7 0x82100090 rx ram0coefficient set 8 register rx_ram0_cs8 0x82100094 rx ram0coefficient set 9 register rx_ram0_cs9 0x82100098 rx ram0coefficient set 10 register rx_ram0_cs10 0x8210009c rx ram0coefficient set 11register rx_ram0_cs11 0x821000a0 rx ram0coefficient set 12register rx_ram0_cs12 0x821000a4 rx ram0coefficient set 13register rx_ram0_cs13 0x821000a8 rx ram0coefficient set 14 register rx_ram0_cs14 0x821000ac rx ram0coefficient set 15 register rx_ram0_cs15 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 576 of 1535 0x82100020 rx ram1 coefficient set 0 register rx_ram1_cs0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_ram1_cs0 type r/w reset 000000000 this register is 1 st of the 16 coefficient in ram1 table, coefficient set id 2 or 4. the content is coded in 2?s complement. that is, its maximum is 255 and its minimum is ?256, while the total coefficient number in this coefficient set has to be greater than half of tapno(programmable tap no.) and smaller than half of maximum tap no(15). register address register function acronym 0x82100020 rx ram1 coefficient set 0 register rx_ram1_cs0 0x82100024 rx ram1 coefficient set 1register rx_ram1_cs1 0x82100028 rx ram1 coefficient set 2 register rx_ram1_cs2 0x8210002c rx ram1 coefficient set 3 register rx_ram1_cs3 0x82100030 rx ram1 coefficient set 4 register rx_ram1_cs4 0x82100034 rx ram1 coefficient set 5 register rx_ram1_cs5 0x82100038 rx ram1 coefficient set 6 register rx_ram1_cs6 0x8210003c rx ram1 coefficient set 7 register rx_ram1_cs7 0x82100040 rx ram1 coefficient set 8 register rx_ram1_cs8 0x82100044 rx ram1 coefficient set 9 register rx_ram1_cs9 0x82100048 rx ram1 coefficient set 10 register rx_ram1_cs10 0x8210004c rx ram1 coefficient set 11 register rx_ram1_cs11 0x82100050 rx ram1 coefficient set 12 register rx_ram1_cs12 0x82100054 rx ram1 coefficient set 13 register rx_ram1_cs13 0x82100058 rx ram1 coefficient set 14 register rx_ram1_cs14 0x8210005c rx ram1 coefficient set 15 register rx_ram1_cs15 0x821000b0 rx interference detection hpf power register rx_hpwr_sts bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_pwr_hpf type r/o reset 0000000000000000 this register is for read the power measurement result of the hpf interference detection filter. rx_pwr_hpf value of the power measurement result for the outband interference detection. 0x821000b4 rx interference detection bpf power register rx_bpwr_sts bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rx_pwr_bpf type r/o reset 0000000000000000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 577 of 1535 this register is for read the power measurement result of the bpf interference detection filter. rx_pwr_bpf value of the power measurement result for the inband interference detection 4.3.2.7.2 dsp i/o register 0x743 rx hpf itd power register of window0 dspio_itd_h_0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name itd_h_data_0 type r/o reset 0000000000000000 this register is for dsp to read the power measurement result of the bpf interference detection filter through dsp i/o. dspio_itd_h_0 value of the power measurement result for the outband interference detection of window 0. register address register function acronym 0x743 rx hpf itd power register of window0 dspio_itd_h_0 0x747 rx hpf itd power register of window1 dspio_itd_h_1 0x74b rx hpf itd power register of window2 dspio_itd_h_2 0x74f rx hpf itd power register of window3 dspio_itd_h_3 0x753 rx hpf itd power register of window4 dspio_itd_h_4 0x757 rx hpf itd power register of window5 dspio_itd_h_5 0x744 rx bpf itd power register of window0 dspio_itd_b_0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name itd_b_data_0 type r/o reset 0000000000000000 this register is for dsp to read the power measurement result of the bpf interference detection filter through dsp i/o. dspio_itd_b_0 value of the power measurement result for the inband interference detection of window 0. register address register function acronym 0x744 rx bpf itd power register of window0 dspio_itd_b_0 0x748 rx bpf itd power register of window1 dspio_itd_b_1 0x74c rx bpf itd power register of window2 dspio_itd_b_2 0x750 rx bpf itd power register of window3 dspio_itd_b_3 0x754 rx bpf itd power register of dspio_itd_b_4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 578 of 1535 window4 0x758 rx bpf itd power register of window5 dspio_itd_b_5 0x759 rx itd power measurement ready flag dspio_rxid_rdy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rxid_rdy_5 rxid_rdy_4 rxid_rdy_3 rxid_rdy_2 rxid_rdy_1 rxid_rdy_0 type r/o r/o r/o r/o r/o r/o reset 0 0 0 0 0 0 this register is for dsp to see whether the rx itd power register is ready or not through dsp i/o. when the dspio_itd_h_0 and dspio_itd_b_0 are ready, bit 0 is set to 1. moreover, while dsp read the data of dspio_itd_h_0 and dspio_itd_b_0, bit 0 is reset to 0. rxid_rdy_0 ready flag for dsp to read the itd power measurement result of window0. rxid_rdy_1 ready flag for dsp to read the itd power measurement result of window1. rxid_rdy_2 ready flag for dsp to read the itd power measurement result of window2. rxid_rdy_3 ready flag for dsp to read the itd power measurement result of window3. rxid_rdy_4 ready flag for dsp to read the itd power measurement result of window4. rxid_rdy_5 ready flag for dsp to read the itd power measurement result of window5. 4.3.3 uplink path (tx path) 4.3.3.1 general description the purpose of the uplink path inside baseband front end is to sink tx symbols, from dsp, then perform gmsk modulation or 8psk modulation on them, then perform offset cancellation on i/q digital signals, and finally control tx mixed-signal module to make d/a conversion on i/q signals out of gmsk modulator or 8psk modulator with offset cancellation. accordingly, the uplink path is composed of uplink parts of baseband serial ports, gsm encryptor, gmsk modulator, 8psk modulator and several compensation circuit including i/q dc offset, i/q quadrature phase compensation, and i/q gain mismatch. the block diagram of uplink path is shownas followed. gmsk modulator gsm encryptor uplink patrts of baseband serial ports dsp offset cancellation 1-bit tx 1-bit tx 1-bit tx gsm tx mixed- signal module i/q 8psk modulator 3-bit tx symbol i/q figure 78 block diagram of uplink path on uplink path, the content of a burst, including tail bits, data bits, and training sequence bits is sent from dsp. dsp outputs will be t translated by either gmsk modulator or 8psk modulator. the modulation mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 579 of 1535 selection is controlled by mdsel1 (modulation mode select1) mdsel2, mdsel3, mdsel4 in tx_cfg control register, and these translated bits after modulation will become i/q digital signals with certain latency. tdma timer having a quarter-bit timing accuracy gives the timing windows for uplink operation. uplink operation is controlled by tx enable window and tx dump window of tdma timer. usually, tx enable window is opened earlier than tx dump window. when tx enable window of tdma timer is opened, uplink path in baseband front end will power-on gsk tx mixed-signal module and thus drive valid outputs to rf module. however, uplink parts of baseband serial ports still do not sink data from dsp through the serial interface between baseband serial ports and dsp until tx dump window of tdma timer is opened. 4.3.3.2 compensation circuit 4.3.3.2.1 quadrature phase for 8psk modulation, in order to improve the evm performance, use phsel[3:0](phase select) in tx_cfg control register to compensate the quadrature phase. 10 steps, 1degree/step, up to +/5 degree dynamic range. 4.3.3.2.2 dc offset cancellation offset cancellation will be performed on these i/q digital signals to compensate offset error of d/a converters (dac) in tx mixed-signal module. finally the generated i/q digital signals will be input to tx mixed-signal module that contains two dac for i/q signal respectively. 4.3.3.3 auxiliary calibration circuit - 540khz sine tone generator by setting ?1? to sgen(sine tone generation) in tx_cfg control register, the bbtx output will become 540khz single sine tone, which is used for factory calibration scheme for mixed signal low pass filter cut- off frequency accuracy. 4.3.3.4 gsm encryptor when uplink parts of baseband serial ports pass a tx symbol to gsm encryptor, gsm encryptor will perform encryption on the tx symbol if set ?1? to bcien(baseband ciphering encryption) in bfe_con register. otherwise, the tx symbol will be directed to gmsk modulator directly. 4.3.3.5 modulation 4.3.3.5.1 gmsk modulation gmsk modulator is used to convert bit stream of gsm bursts into in-phase and quadrature-phase outputs by means of gmsk modulation scheme. it consists of a rom table, timing control logic and some state registers for gmsk modulation scheme. gmsk modulator is activated when tx dump window is opened. there is latency between assertion of tx dump window and the first valid output of gmsk modulator. the reason is because the bit rate of tx symbols is 270.833 khz and the output rate of gmsk modulator is 4.333 mhz, and therefore timing synchronization is necessary between the two rates. additionally, in order to prevent phase discontinuity in between the multiple-burst mode, the gmsk modulator will output continuous 67.7khs sine tone outside the burst once rx dac enable window is still asserted. once rx dac enable window is disserted, gmsk modulator will park at dc level. 4.3.3.5.2 8psk modulation 8psk modulator is used to convert bit stream of edge bursts into basically 8 phase i/q pair output by means of 8psk modulation scheme. it consists of rom table, timing control logic and some state registers for 8psk free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 580 of 1535 modulation scheme. the conversion is based on 5 sequential symbol and performed moving average from the rom table lookup. 8psk modulator is activated when tx dump window is opened. there is one clock delay between assertion of tx dump window and the first valid output of 8psk modulator. the reason is because the bit rate of tx symbols is 270.833 khz and the output rate of 8psk modulator is 4.333 mhz, and therefore timing synchronization is necessary between the two rates. 4.3.3.5.2.1 8psk ramp profile during 8pskmodulation, there will be 3 ramp profile to select to choose the bbtx i/q output during the guard period, where the dac_on is asserted while tx_window is de-asserted. this control register is an option to adjust the transmitter performance on ?modulation transient spectrum? requirement of etsi spec if different companion power amplifier solution is chosen by setting rpsel (ramp profile select) in tx_cfg control register to ?0?will configured 8psk modulator to ramp profile i and i/q output will be about 50 khz sine-tone before the first rising edge of bulfs, after the last falling edge of bulfs, and in between the bursts. for ramp profile ii, bbtx i/q output will be quiescent low dc (null-dc) level during the guard period. for ramp profile iii, initial guard period will be 50 khz sine-tone, while the reset guard period will be null-dc level. ramp profile i bulfs btxen ramp profile ii ramp profile iii figure 79 ramp profile i/ii/iii in 8psk modulation for multi-bursts configuration.. 4.3.3.5.3 i/q swap by setting ?1? to iqswp in tx_cfg control register, phase on i/q plane will rotate in inverse direction. this option is to meet the different requirement form rf chip regarding i/q plane. this control signal is for gmsk modulation only. 4.3.3.5.4 modulation output latency adjustment for multiple bursts, there maybe are consecutive bursts with different modulation mode. (e.g. switch gmsk to 8psk or vice versa). however, there are about 8 to 10 qb output latencies for either gmsk/8pskmodulation output. in order to match the transition timing of power ramp control in the power amplifier outside the baseband chip, we have to precisely control the sw_qbcnt (modulation switching quarter bit count) in free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 581 of 1535 tx_cfg control register. , which will program the mode switching timing in qb count unit during the inter-slot period. normally the inter-slot period is about 33 qb count, and the default value to switch the modulation mode is 24 qb count (8 qb count after the middle point) additionally, by programming gmsk_dtap_sym(gmsk delay tap) in tx_cfg and gmsk_dtap_qb in tx_con control register, the output latency for gmsk modulation output can be adjust to compensate the offset between gmsk/8psk modulator. the gmsk_dtap_sym adjust the output latency in symbol time(3.69us), while gmsk_dta_qb adjust in quarter bit(qb) time ( 0.92us).default value is delay 1 symbol ( 3.69us) of gmsk modulator output. 4.3.3.5.5 modulation mode switching by setting ?1? to inten(interpolation enable) in tx_cfg control register, if two consecutive bursts belongs to 8psk modulation and gmsk modulation, or vice versa, 32 steps interpolation between two modulator outputs for 4quater bit long in guard period. . 4.3.3.5.6 debug mode 4.3.3.5.6.1 modulation bypass mode for dsp debug purpose, set both ?1? for mdbyp(modulator bypass) in tx_cfg control register and bypflr(bypass rx filter) in rx_cfg control register for directly loopback dsp 16-bits data ( 10bits valid data plus sign or zero extension) through dac only. 4.3.3.5.6.2 force gmsk/8psk modulator turn on by setting ?1? to apnden(append enable) bit in tx cfg control register, both gmsk and 8psk modulator will park on constant dc level during the non-burst period, while the i/q pair output phase maybe discontinuous since both modulator will be reset at the beginning of the burst. however, the reset of the modulator will be helpful for the debugging purpose. 4.3.3.6 register definitions 0x82100060 tx configuration register tx_cfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gmsk_dtap_ sym sw_qbcnt all_10_en sgen mdby p inten rpsel apnd en type r/w rw rw r/w r/w r/w r/wr/w r/w reset 00 11000 00 0 0 0 00 0 this register is for configuration of uplink path, inclusive of configuration of tx mixed-signal module and tx path in baseband front end. apnden appending bits enable.(for dsp digital loopback debug mode) the register bit is used to control the ending scheme of gprs mode gmsk modulation only. 0 suitable for gprs /edge mode. if a tx enable window contains several tx dump window, then gmsk modulator will still output in the intervals between two tx dump window and all 1?s will be fed into gmsk modulator. in the other word, mainly used pa to perform the power ramp up/down, while modulator output low amplitude sinewave. note that when the bit is set to ?0?, the free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 582 of 1535 interval between the moment at which tx enable window is activated and the moment at which tx dump window is activated must be multiples of one bit time. 1 suitable for gsm only. after a tx dump window, gmsk modulator will only output for some bit time. rpsel ramp profile select for 8psk modulation. the register bit is used to select either ramp profile i / ramp profile ii for edge mode 8psk modulation only. 0 ramp profile i. generate 50khz sine tone during the guard period among bbtx bursts by repeated input pattern [7 7 7 7] 1 ramp profile ii. generate null dc i/q output during guard period among bbtx bursts 2 reserved 3 ramp profile iii , generate 50 khz sine tone after dac_on asserted and before tx_widnow asserted if 1 st burst is 8psk modulation, while the reset guard period always output null dc i/q output. if the 1 st burst is gmsk modulation, the i/q output will be always null dc as ramp profile ii. inten interpolation enable. during multi-bursts mode, if two consecutive bursts belongs to 8psk modulation and gmsk modulation, or vice versa, set this bit to select either takes 32 steps interpolation between two modulator outputs in guard period. . 0 regular transition mode. 1 interpolation transition mode. mdbyp modulator bypass (for dsp debug mode) select. the register bit is used to select the bypass mode for i/q pair outputs bypassed both the gmsk/8psk modulator 0 regular modulation mode 1 bypass modulator mode (dsp debug mode). sgen sinetone generator enable.(for factory calibration purpose). the register bit is used to select the tx modulator output switch to 540 khz sine tone. 0 bbtx output from regulator modulator output. 1 bbtx output switch to 540 khz sine tone. all_10gen for debug mode of bbtx. generate all 1?s or zero?s input during bbtx valid burst. for gmsk modulation, set 2?b1 or 2?b10 will generate 67.7 khz sine tone, while 8psk modulator will generate 50khz sine tone. default value 2?b00 is normal mode. 0 normal mode, regular modulator input from slave dsp tx buffer. 1 debug mode, all zero?s input pattern generated; gmsk modulator will generate 67.7 khz sine tone. 8psk modulator will generate 50 khz sine tone. 2 debug mode all 1?s input pattern generated; gmsk modulator will generate 67.7 khz sine tone. 8psk modulator will generate 50 khz sine tone. sw_qbcnt control the mode switching timing in the inter-slot period in quarter bit count for modulation mode switching in multiple bursts. normally the inter-slot period is about 33 qb count, and the default value to switch the modulation mode is 24 qb count (8 qb count after the middle point). program range from ?5~31?, while default value is 24. gmsk_dtap_sym control the gmsk modulator output latency in symbol time (3.69us/symbol) in order to match the output latency offset between 8psk /gmsk modulator 0 delay 1 tap for gmsk modulator output 1 no delay for gmsk modulator output free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 583 of 1535 2 delay 2 tap for gmsk modulator output 0x82100064 tx control register tx_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gmsk_dtap_ qb phsel mdse l4 mdse l3 mdse l2 mdse l1 iqsw p type r/w r/w r/w r/w r/w r/w r/w reset 00 0000 0 0 0 0 0 this register is for control of uplink path, inclusive of control of tx mixed-signal module and tx path in baseband front end. iqswp the register bit is for control of i/q swapping. when the bit is set to ?1 ?, phase on i/q plane will rotate in inverse direction. moreover, this register is double buffered by event_validate. 0 i and q are not swapped. 1 i and q are swapped. mdsel1 modulation mode select for 1 st burst. the register bit is used to select either gmsk or 8psk modulation for gsm/gprs mode or edge mode. 0 gmsk modulation for gsm/gprs mode. 1 8psk modulation for edge mode. mdsel2 modulation mode select for 2 nd burst. the register bit is used to select either gmsk or 8psk modulation for gsm/gprs mode or edge mode. 0 gmsk modulation for gsm/gprs mode. 1 8psk modulation for edge mode. mdsel3 modulation mode select for 3 rd burst. the register bit is used to select either gmsk or 8psk modulation for gsm/gprs mode or edge mode. 0 gmsk modulation for gsm/gprs mode. 1 8psk modulation for edge mode. mdsel4 modulation mode select for 4 th burst. the register bit is used to select either gmsk or 8psk modulation for gsm/gprs mode or edge mode. 0 gmsk modulation for gsm/gprs mode. 1 8psk modulation for edge mode. phsel quadrature phase compensation select 0000 : 0 degree compensation. 0001 : 1 degree compensation. 0010 : 2 degree compensation. 0011 : 3 degree compensation. 0100 : 4 degree compensation. 0101 : 5 degree compensation. 1010 : -5 degree compensation. 1011 : -4 degree compensation. 1100 : -3 degree compensation. 1101 : -2 degree compensation. 1110 : -1 degree compensation. 1111 : 0 degree compensation. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 584 of 1535 gmsk_dtap_qb control the gmsk modulator output latency in quarter bit(qb) time (0.92us/qb) in order to match the output latency offset between 8psk /gmsk modulator 0 no delay gmsk modulator output 1 delay 1qb for gmsk modulator output 2 delay 2 qb for gmsk modulator output 3 delay 3qb for gmsk modulator output 0x82100068 tx i/q channel offset compensation register tx_off bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name off_t yp offq[5:0] offi[5:0] type r/w r/w r/w reset 0 000000 000000 the register is for offset cancellation of i-channel dac in tx mixed-signal module. it is for compensation of offset error caused by i/q-channel dac in tx mixed-signal module. it is coded in 2?s complement, that is, with maximum 31 and minimum ?32. offi value of offset cancellation for i-channel dac in tx mixed-signal module (+31mv ? -32mv) offq value of offset cancellation for q-channel dac in tx mixed-signal module (+31mv ? -32mv) off_typ type of the offi and offq register. while off_typ = 1, the offset values are double buffered and can be chaneged burst by burst after event_validate comes. otherwise, the offset values would change immidately after the coming of apb commands, which can't be adjusted burst by burst. 0 no double buffer 1 double buffered 4.4 baseband para llel interface 4.4.1 general description the baseband parallel interface features 10 control pins, which are used for timing-critical external circuits. these pins typically control front-end components which must be turned on or off at specific times during gsm operation, such as transmit-enable, band switching, tr-switch, etc. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 585 of 1535 event register apb i/f active buffer write buffer output buffer tdma_evtval (from tdma timer) tdma_bpistr (0~41) (from tdma timer) bpi_bus0 bpi_bus1 bpi_bus2 bpi_bus3 bpi_bus4 bpi_bus5 bpi_bus6 bpi_bus7 mux mux immediate mode petev bpi_bus8 bpi_bus9 the driving capability is configurable. the driving capability is fixed. figure 80 block diagram of bpi interface the user can program 42 sets of 10-bit registers to set the output value of bpi_bus0 ~ bpi_bus9. the data is stored in the write buffers. the write buffers are then forwarded to the active buffers when the tdma_evtval signal is pulsed, usually once per frame. each of the 42 write buffers corresponds to an active buffer, as well as to a tdma event. each tdma_bpistr event triggers the transfer of data in the corresponding active buffer to the output buffer, thus changing the value of the bpi bus. the user can disable the events by programming the enable registers in the tdma timer. if the tdma_bpistr event is disabled, the corresponding signal tdma_bpistr is not pulsed, and the value on the bpi bus remains unchanged. for applications in which bpi signals serve as the switch, current-driving components are typically added to enhance driving capability. three configurable output pins provide current up to 8 ma, and help reduce the number of external components. the output pins bpi_bus6 , bpi_bus7 , bpi_bus8 , and bpi_bus9 are multiplexed with gpio. please refer to the gpio table for more detailed information. 4.4.2 register definitions register address register function acronym 0x82020000 bpi control register bpi_con 0x820200b0 bpi event enable register 0 bpi_ena0 0x820200b4 bpi event enable register 1 bpi_ena1 0x820200b8 bpi event enable register 2 bpi_ena2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 586 of 1535 table 70 bpi control registers 0x82020000 bpi control register bpi_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pinm2 pinm1 pinm0 petev type wo wo wo r/w reset 0 0 0 0 this register is the control register of the bpi unit. the register controls the direct access mode of the active buffer and the current driving capability for the output pins. the driving capabilities of bpi_bus0 , bpi_bus1 and bpi_bus2 can be 2 ma or 8 ma, determined by the value of pinm0 , pinm1 and pinm2 respectively. these output pins provide a higher driving capability and save on external current-driving components. in addition to the configurable pins, pins bpi_bus3 to bpi_bus9 provide a driving capability of 2 ma (fixed). petev enables direct access to the active buffer. 0 the user writes data to the write buffer. the data is latched in the active buffer after the tdma_evtval signal is pulsed. 1 the user directly writes data to the active buffer without waiting for the tdma_evtval signal. pinm0 controls the driving capability of bpi_bus0 . 0 the output driving capability is 2ma. 1 the output driving capability is 8ma. pinm1 controls the driving capability of bpi_bus1 . 0 the output driving capability is 2ma. 1 the output driving capability is 8ma. pinm2 controls the driving capability of bpi_bus2 . 0 the output driving capability is 2ma. 1 the output driving capability is 8ma. 0x82020004 bpi data register 0 bpi_buf0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name po9 po8 po7 po6 po5 po4 po3 po2 po1 po0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register defines the bpi signals that are associated with the event tdma_bpi0. table 71 lists 42 registers of the same structure, each of which is associated with one specific event signal from the tdma timer. the data registers are all double-buffered. when petev is set to 0, the data register links to the write buffer. when petev is set to 1, the data register links to the active buffer. one register, bpi_bufi , is dedicated for use in immediate mode. writing a value to that register effects an immediate change in the corresponding bpi signal and bus. pox this flag defines the corresponding signals for bpix after the tdma event 0 takes place. the overall data register definition is listed in table 71. register address register function acronym free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 587 of 1535 0x82020004 bpi pin data for event tdma_bpi 0 bpi_buf0 0x82020008 bpi pin data for event tdma_bpi 1 bpi_buf1 0x8202000c bpi pin data for event tdma_bpi 2 bpi_buf2 0x82020010 bpi pin data for event tdma_bpi 3 bpi_buf3 0x82020014 bpi pin data for event tdma_bpi 4 bpi_buf4 0x82020018 bpi pin data for event tdma_bpi 5 bpi_buf5 0x8202001c bpi pin data for event tdma_bpi 6 bpi_buf6 0x82020020 bpi pin data for event tdma_bpi 7 bpi_buf7 0x82020024 bpi pin data for event tdma_bpi 8 bpi_buf8 0x82020028 bpi pin data for event tdma_bpi 9 bpi_buf9 0x8202002c bpi pin data for event tdma_bpi 10 bpi_buf10 0x82020030 bpi pin data for event tdma_bpi 11 bpi_buf11 0x82020034 bpi pin data for event tdma_bpi 12 bpi_buf12 0x82020038 bpi pin data for event tdma_bpi 13 bpi_buf13 0x8202003c bpi pin data for event tdma_bpi 14 bpi_buf14 0x82020040 bpi pin data for event tdma_bpi 15 bpi_buf15 0x82020044 bpi pin data for event tdma_bpi 16 bpi_buf16 0x82020048 bpi pin data for event tdma_bpi 17 bpi_buf17 0x8202004c bpi pin data for event tdma_bpi 18 bpi_buf18 0x82020050 bpi pin data for event tdma_bpi 19 bpi_buf19 0x82020054 bpi pin data for event tdma_bpi 20 bpi_buf20 0x82020058 bpi pin data for event tdma_bpi 21 bpi_buf21 0x8202005c bpi pin data for event tdma_bpi 22 bpi_buf22 0x82020060 bpi pin data for event tdma_bpi 23 bpi_buf23 0x82020064 bpi pin data for event tdma_bpi 24 bpi_buf24 0x82020068 bpi pin data for event tdma_bpi 25 bpi_buf25 0x8202006c bpi pin data for event tdma_bpi 26 bpi_buf26 0x82020070 bpi pin data for event tdma_bpi 27 bpi_buf27 0x82020074 bpi pin data for event tdma_bpi 28 bpi_buf28 0x82020078 bpi pin data for event tdma_bpi 29 bpi_buf29 0x8202007c bpi pin data for event tdma_bpi 30 bpi_buf30 0x82020080 bpi pin data for event tdma_bpi 31 bpi_buf31 0x82020084 bpi pin data for event tdma_bpi 32 bpi_buf32 0x82020088 bpi pin data for event tdma_bpi 33 bpi_buf33 0x8202008c bpi pin data for event tdma_bpi 34 bpi_buf34 0x82020090 bpi pin data for event tdma_bpi 35 bpi_buf35 0x82020094 bpi pin data for event tdma_bpi 36 bpi_buf36 0x82020098 bpi pin data for event tdma_bpi 37 bpi_buf37 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 588 of 1535 0x8202009c bpi pin data for event tdma_bpi 38 bpi_buf38 0x820200a0 bpi pin data for event tdma_bpi 39 bpi_buf39 0x820200a4 bpi pin data for event tdma_bpi 40 bpi_buf40 0x820200a8 bpi pin data for event tdma_bpi 41 bpi_buf41 0x820200ac bpi pin data for immediate mode bpi_bufi table 71 bpi data registers. 0x820200b0 bpi event enable register 0 bpi_ena0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ben15 ben14 ben13 ben12 ben11 ben10 ben9 ben8 ben7 ben6 ben5 ben4 ben3 ben2 ben1 ben0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register enables the events that are signaled by the tdma timer: by clearing a register bit, the corresponding event signal is ignored. after a hardware reset, all the enable bits default to 1 (enabled). upon receiving a tdma_evtval pulse, all register bits are also set to 1 (enabled). benn this flag indicates whether event n signals are heeded or ignored. 0 event n is disabled (ignored). 1 event n is enabled. 0x820200b4 bpi event enable register 1 bpi_ena1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ben31 ben30 ben29 ben28 ben27 ben26 ben25 ben2 4 ben23 ben22 ben21 ben20 ben19 ben18 ben17 ben16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register enables the events that are signaled by the tdma timing generator: by clearing a register bit, the corresponding event signal is ignored. after a hardware reset, all the enable bits default to 1 (enabled). upon receiving the tdma_evtval pulse, all register bits are also set to 1 (enabled). benn this flag indicates whether event n signals are heeded or ignored. 0 event n is disabled (ignored) 1 event n is enabled 0x820200b8 bpi event enable register 2 bpi_ena2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ben41 ben40 ben39 ben38 ben37 b en36 ben35 ben34 ben33 ben32 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 the register is used to enable the events that are signaled by the tdma timing generator. after hardware reset, all the enable bits defaults to be 1 (enabled). upon receiving the tdma_evtval pulse, those bits are also set to 1 (enabled). benn the flag controls the function of event n. 0 the event n is disabled. 1 the event n is enabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 589 of 1535 4.4.3 application note figure 81 rf module connected with bpi mt62xx also provides several gpo-like signals called bpi (baseband parallel interface) bus, which is activated at the specific time, to perform this control purpose. the timing of activating high/low states of signals on bpi bus is programmable, and the state of signals on bpi bus is changed on the specified timing. the timing of changing the states of bpi bus is called bpi event . the state of bpi signals with corresponding bpi event is call bpi data . bpi event can be programmable in the tdma timer, and bpi data can be programmable in this module. in the above figure, bb can control r/tx switch, band select, and power on/off etc. of rf module via bpi pins. 4.5 baseband serial interface the baseband serial interface controls external radio components. a 3-wire serial bus transfers data to rf circuitry for pll frequency change, reception gain setting, and other radio control purposes. in this unit, bsi data registers are double-buffered in the same way as the tdma event registers. the user writes data into the write buffer and the data is transferred from the write buffer to the active buffer when a tdma_evtval signal (from the tdma timer) is pulsed. each data register bsi_d n _dat is associated with one data control register bsi_d n _con , where n denotes the index. each data control register identifies which events (signaled by tdma_bsistr n , generated by the tdma timer) trigger the download process of the word in register bsi_d n _dat . the word and its length (in bits) is downloaded via the serial bus. a special event is triggered when the imod flag is set to 1: it provides immediate download process without software programming the tdma timer. if more than one data word is to be downloaded on the same bsi event, the word with the lowest address among them is downloaded first, followed by the next lowest and so on. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 590 of 1535 the total download time depends on the word length, the number of words to download, and the clock rates. the programmer must space the successive event to provide enough time. if the download process of the previous event is not complete before a new event arrives, the latter is suppressed. the unit has four output pins: bsi_clk is the output clock, bsi_data is the serial data port, and bsi_cs0 and bsi_cs1 are the select pins for 2 external components. bsi_cs1 is multiplexed with another function. please refer to gpio table for more detail. in order to support bi-directional read and write operations of the rf chip, software can directly write values to bsi_clk, bsi_data and bsi_cs by programming the bsi_dout register. data from the rf chip can be read by software via the register bsi_din. if the rf chip interface is a 3-wire interface, then bsi_data is bi- directional. before software can program the 3-wire behavior, the bsi_io_con register must be set. an additional signal path from gpio accommodates rf chips with a 4-wire interface. the block diagram of the bsi unit is as depicted in figure 82. z control write buffer active buffer serial port control setenv imod bsi_cs0 bsi_data bsi_clk bsi_cs1 (gpio) bsi unit tdma_bsistr (0~15) (from tdma timer) tdma_evtval (from tdma timer) apb bus bsi_din_gpio (read from rfic) (gpio) figure 82 block diagram of bsi unit. z bsi_csx (long) bsi_clk (true) bsi_csx (short) bsi_data bsi_clk (invert) lsb msb figure 83 timing characteristic of bsi interface. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 591 of 1535 4.5.1 register definitions register address register function acronym 0x82010000 bsi control register bsi_con 0x82010190 bsi event enable register bsi_ena_0 0x82010194 bsi event enable register ? msb 4 bits bsi_ena_1 0x82010198 bsi io mode control register bsi_io_con 0x8201019c software-programmed data out bsi_dout 0x820101a0 input data from rf chip bsi_din 0x820101a4 bsi data pair number bsi_pair_num table 72 bsi control registers 0x82010000 bsi control register bsi_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name seten v en1_p ol en1_l en en0_p ol en0_l en imod clk_spd clk_p ol type r/w r/w r/w r/w r/w wo r/w r/w reset 0 0 0 0 0 n/a 0 0 this register is the control register for the bsi unit. the register controls the signal type of the 3-wire interface. clk_pol controls the polarity of bsi_clk. refer to figure 83. 0 true clock polarity 1 inverted clock polarity clk_spd defines the clock rate of bsi_clk. the 3-wire interface provides 4 choices of data bit rate. the default is 52/2 mhz. 00 52/2 mhz 01 52/4 mhz 10 52/6 mhz 11 52/8 mhz imod enables immediate mode. if the user writes 1 to the flag, the download is triggered immediately without waiting for the timer events. the words for which the register event id equals 1fh are downloaded following this signal. this flag is write-only. the immediate write is exercised only once: the programmer must write the flag again to invoke another immediate download. setting the flag does not disable the other events from the timer; the programmer can disable all events by setting bsi_ena to all zeros. 0 reserved 1 trigger immediate mode enx_len controls the type of signals bsi_cs0 and bsi_cs1. refer to figure 82. 0 long enable pulse 1 short enable pulse enx_pol controls the polarity of signals bsi_cs0 and bsi_cs1. 0 true enable pulse polarity free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 592 of 1535 1 inverted enable pulse polarity setenv enables the write operation of the active buffer. 0 the user writes to the write buffer. the data is then latched in the active buffer after tdma_evtval is pulsed. 1 the user writes data directly to the active buffer. 0x82010004 control part of data register 0 bsi_d0_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isb len evt_id type r/w r/w r/w this register is the control part of the data register 0. the register determines the required length of the download data word, the event to trigger the download process of the word, and the targeted device. table 74 lists the 44 data registers of this type. the max length of the first 40 data registers is 32 bits, and that of the last 4 data registers is 78 bits. multiple data control registers may contain the same event id. the data words of all registers with the same event id are downloaded when the event occurs. evt_id stores the event id for which the data word awaits to be downloaded. 00000~10011 synchronous download of the word with the selected evt_id event. the relationship between this field and the event is listed as table 77. event id (in binary) ? evt_id event name 00000 tdma_bsistr0 00001 tdma_bsistr1 00010 tdma_bsistr2 00011 tdma_bsistr3 00100 tdma_bsistr4 00101 tdma_bsistr5 00110 tdma_bsistr6 00111 tdma_bsistr7 01000 tdma_bsistr8 01001 tdma_bsistr9 01010 tdma_bsistr10 01011 tdma_bsistr11 01100 tdma_bsistr12 01101 tdma_bsistr13 01110 tdma_bsistr14 01111 tdma_bsistr15 10000 tdma_bsistr16 10001 tdma_bsistr17 10010 tdma_bsistr18 10011 tdma_bsistr19 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 593 of 1535 table 77 the relationship between the value of evt_id field in the bsi control registers and the tdma_bsistr events. 10100~11110 reserved 11111 immediate download len the field stores the length of the data word. the actual length is defined as len + 1 in units of bits . for data registers 0~39 , the value ranges from 0 to 31, corresponding to 1 to 32 bits in length. for data registers 40~43 , the value ranges from 0 to 77, corresponding to 1 to 78 bits in length. isb the flag selects the target device. 0 device 0 is selected. 1 device 1 is selected. 0x82010008 data part of data register 0 bsi_d0_dat bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dat [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dat [15:0] type r/w this register is the data part of the data register 0. the legal length of the data is up to 32 bits. the actual number of bits to be transmitted is specified in len field in the bsi_d0_con register. dat the field signifies the data part of the data register. table 74 lists the address mapping and function of the 44 pairs of data registers. register address register function acronym 0x82010004 control part of data register 0 bsi_d0_con 0x82010008 data part of data register 0 bsi_d0_dat 0x8201000c control part of data register 1 bsi_d1_con 0x82010010 data part of data register 1 bsi_d1_ dat 0x82010014 control part of data register 2 bsi_d2_con 0x82010018 data part of data register 2 bsi_d2_ dat 0x8201001c control part of data register 3 bsi_d3_con 0x82010020 data part of data register 3 bsi_d3_ dat 0x82010024 control part of data register 4 bsi_d4_con 0x82010028 data part of data register 4 bsi_d4_ dat 0x8201002c control part of data register 5 bsi_d5_con 0x82010030 data part of data register 5 bsi_d5_ dat 0x82010034 control part of data register 6 bsi_d6_con 0x82010038 data part of data register 6 bsi_d6_ dat 0x8201003c control part of data register 7 bsi_d7_con 0x82010040 data part of data register 7 bsi_d7_ dat 0x82010044 control part of data register 8 bsi_d8_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 594 of 1535 0x82010048 data part of data register 8 bsi_d8_ dat 0x8201004c control part of data register 9 bsi_d9_con 0x82010050 data part of data register 9 bsi_d9_ dat 0x82010054 control part of data register 10 bsi_d10_con 0x82010058 data part of data register 10 bsi_d10_ data 0x8201005c control part of data register 11 bsi_d11_con 0x82010060 data part of data register 11 bsi_d11_ dat 0x82010064 control part of data register 12 bsi_d12_con 0x82010068 data part of data register 12 bsi_d12_ dat 0x8201006c control part of data register 13 bsi_d13_con 0x82010070 data part of data register 13 bsi_d13_ dat 0x82010074 control part of data register 14 bsi_d14_con 0x82010078 data part of data register 14 bsi_d14_ dat 0x8201007c control part of data register 15 bsi_d15_con 0x82010080 data part of data register 15 bsi_d15_ dat 0x82010084 control part of data register 16 bsi_d16_con 0x82010088 data part of data register 16 bsi_d16_ dat 0x8201008c control part of data register 17 bsi_d17_con 0x82010090 data part of data register 17 bsi_d17_ dat 0x82010094 control part of data register 18 bsi_d18_con 0x82010098 data part of data register 18 bsi_d18_ dat 0x8201009c control part of data register 19 bsi_d19_con 0x820100a0 data part of data register 19 bsi_d19_ dat 0x820100a4 control part of data register 20 bsi_d20_con 0x820100a8 data part of data register 20 bsi_d20_ dat 0x820100ac control part of data register 21 bsi_d21_con 0x820100b0 data part of data register 21 bsi_d21_ dat 0x820100b4 control part of data register 22 bsi_d22_con 0x820100b8 data part of data register 22 bsi_d22_ dat 0x820100bc control part of data register 23 bsi_d23_con 0x820100c0 data part of data register 23 bsi_d23_ dat 0x820100c4 control part of data register 24 bsi_d24_con 0x820100c8 data part of data register 24 bsi_d24_ dat 0x820100cc control part of data register 25 bsi_d25_con 0x820100d0 data part of data register 25 bsi_d25_ dat 0x820100d4 control part of data register 26 bsi_d26_con 0x820100d8 data part of data register 26 bsi_d26_ dat 0x820100dc control part of data register 27 bsi_d27_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 595 of 1535 0x820100e0 data part of data register 27 bsi_d27_ dat 0x820100e4 control part of data register 28 bsi_d28_con 0x820100e8 data part of data register 28 bsi_d28_ dat 0x820100ec control part of data register 29 bsi_d29_con 0x820100f0 data part of data register 29 bsi_d29_ dat 0x820100f4 control part of data register 30 bsi_d30_con 0x820100f8 data part of data register 30 bsi_d30_ dat 0x820100fc control part of data register 31 bsi_d31_con 0x82010100 data part of data register 31 bsi_d31_ dat 0x82010104 control part of data register 32 bsi_d32_con 0x82010108 data part of data register 32 bsi_d32_ dat 0x8201010c control part of data register 33 bsi_d33_con 0x82010110 data part of data register 33 bsi_d33_ dat 0x82010114 control part of data register 34 bsi_d34_con 0x82010118 data part of data register 34 bsi_d34_ dat 0x8201011c control part of data register 35 bsi_d35_con 0x82010120 data part of data register 35 bsi_d35_ dat 0x82010124 control part of data register 36 bsi_d36_con 0x82010128 data part of data register 36 bsi_d36_ dat 0x8201012c control part of data register 37 bsi_d37_con 0x82010130 data part of data register 37 bsi_d37_ dat 0x82010134 control part of data register 38 bsi_d38_con 0x82010138 data part of data register 38 bsi_d38_ dat 0x8201013c control part of data register 39 bsi_d39_con 0x82010140 data part of data register 39 bsi_d39_ dat 0x82010144 control part of data register 40 bsi_d40_con 0x82010148 data part of data register 40 (msb 14 bits) bsi_d40_ dat2 0x8201014c data part of data register 40 bsi_d40_ dat1 0x82010150 data part of data register 40 (lsb 32 bits) bsi_d40_ dat0 0x82010154 control part of data register 41 bsi_d41_con 0x82010158 data part of data register 41 (msb 14 bits) bsi_d41_ dat2 0x8201015c data part of data register 41 bsi_d41_ dat1 0x82010160 data part of data register 41 (lsb 32 bits) bsi_d41_ dat0 0x82010164 control part of data register 42 bsi_d42_con 0x82010168 data part of data register 42 (msb 14 bits) bsi_d42_ dat2 0x8201016c data part of data register 42 bsi_d42_ dat1 0x82010170 data part of data register 42 (lsb 32 bits) bsi_d42_ dat0 0x82010174 control part of data register 43 bsi_d43_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 596 of 1535 0x82010178 data part of data register 43 (msb 14 bits) bsi_d43_ dat2 0x8201017c data part of data register 43 bsi_d43_ dat1 0x82010180 data part of data register 43 (lsb 32 bits) bsi_d43_ dat0 table 74 bsi data registers 0x82010190 bsi event enable register bsi_ena_0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsi15 bsi14 bsi13 bsi12 bsi11 bsi10 bsi9 bsi8 bsi7 bsi6 bsi5 bsi4 bsi3 bsi2 bsi1 bsi0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register enables an event by setting the corresponding bit. after a hardware reset, all bits are initialized to 1. these bits are also set to 1 after tdma_evtval pulse. bsix enables downloading of the words corresponding to the events signaled by tmda_bsi. 0 the event is not enabled. 1 the event is enabled. 0x82010194 bsi event enable register ? msb 4 bits bsi_ena_1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsi19 bsi18 bsi17 bsi16 type r/w r/w r/w r/w reset 1 1 1 1 the register could enable the event by setting the corresponding bit. after hardware reset, all bits are initialized as 1. besides, those bits are set as 1 after tdma_evtval is pulsed. bsix the flag enables the downloading of the words that corresponds to the events signaled by tmda_bsi. 0 the event is not enabled. the event is enabled. 0x82010198 bsi io mode control register bsi_io_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sel_c s1 4_wir e dat_d ir mode type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 mode defines the source of bsi signal. 0 bsi signal is generated by the hardware. 1 bsi signal is generated by the software. in this mode, the bsi clock depends on the value of the field dout.clk . bsi_cs depends on the value of the field dout.cs and bsi_data depends on the value of the field dout.data . dat_dir defines the direction of bsi_data. 0 bsi _data is configured as input. the 3-wire interface is used and bsi_data is bi-directional. 1 bsi_data is configured as output. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 597 of 1535 4_wire defines the bsi_din source. 0 the 3-wire interface is used and bsi_data is bi-directional. bsi_din comes from the same pin as bsi_data. 1 the 4-wire interface is used. another pin (gpio) is used as bsi_din. sel_cs1 defines which of the bsi_csx (bsi_cs0 or bsi_cs1) is written by the software. 0 bsi_cs0 is selected. 1 bsi_cs1 is selected. 0x8201019c software-programmed data out bsi_dout bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data cs clk type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk signifies the bsi_clk signal. cs signifies the bsi_cs signal. data signifies the bsi_data signal. 0x820101a0 input data from rf chip bsi_din bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 din registers the input value of bsi_data from the rf chip. 0x820101a4 bsi data pair number bsi_pair_num bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pair_num type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 0 0 28 pair_num the software can program how many pairs of data register to be used. the default value is 28 pairs. this value must be smaller or equal to 44. the first 40 pairs are 32-bit long, and the last four pairs are 78-bit long. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 598 of 1535 4.5.2 application note figure 84 rf module connected with bsi (3-wire) interface some rf chips can be commanded by receiving serial signals. 3 wires, i.e. device select, serial clock, and serial data, are needed to control the device. in mt62xx baseband chip, this interface named bsi (baseband serial interface) is provided. the timing to activate bsi unit sending 3-wire control signals is called bsi event . the serial data sent with corresponding bsi event is call bsi data . bsi event can be programmable in the tdma module, and bsi data can be programmable at this module. bsi module can support different clock rates and device select types. the output clock rate depends on rf module?s spec & sw?s timing budget. because bsi is serial transmission, it needs some time to send the whole data words. it must be considered in the sw?s timing budget. 4.6 csd accelerator 4.6.1 general description this unit performs the data format conversion of ra0, ra1, and fax in csd service. csd service consists of two major functions: data flow throttling and data format conversion. the data format conversion is a bit-wise operation and takes a number of instructions to complete a conversion. therefore, it is not efficient to do by mcu itself. a coprocessor, csd accelerator, is designed here to reduce the computing power needed to perform this function. csd accelerator only helps in converting data format; the data flow throttling function is still implemented by the mcu. csd accelerator performs three types of data format conversion, ra0, ra1, and fax. for ra0 conversion, only uplink ra0 data format conversion is provided here. this is because there are too many judgments on the downlink path conversion, which will greatly increase area cost. uplink ra0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 599 of 1535 conversion is to insert one start bit and one stop bit before and after a byte, respectively, during 16 bytes. figure 85 illustrates the detailed conversion table. ra0 converter can only process ra0 data state by state. before filling in new data, software must make sure the converted data of certain state is withdrawn, or the converted data will be replaced by the new data. for example, if 32-bit data is written, and the state pointer goes from state 0 to state 1, and word ready of state 0 is asserted; then, before writing the next 32-bit data, the word of state 0 should be withdrawn first, or the data will be lost. ra0 records the number of written bytes, state pointer, and ready state word. the information can help software to perform flow control. see register definition for more detail. %bubcjut 4upqcju 4ubsucju 4ubuf 4ubuf 4ubuf 4ubuf 4ubuf figure 85 data format conversion of ra0 for ra1 conversion, both directions, downlink and uplink, are supported. the data formats vary in different data rate. the detailed conversion table is shown in figure 86 and figure 87 . the yellow part is the payload data, and the blue part is the status bit. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 600 of 1535 % % % % % % 4 % % % % % % 9 % % % % % % 4 % % % % % % 4 & & & & % % % % % % 4 % % % % % % 9 % % % % % % 4 % % % % % % 4 #ju #ju #ju figure 86 data format conversion for 6k/12k ra1 figure 87 data format conversion for 3.6k ra1 for fax, two types of bit-reversal functions are provided. one is bit-wise reversal, and the other is byte-wise reversal, which are illustrated in figure 88 and figure 89 , respectively. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 601 of 1535 c c c c c c c c figure 88 type 1 bit reverse c c c c c c c c c c c c c figure 89 type 2 bit reverse register address register function acronym 0x82090000 csd ra0 control register csd_ra0_con 0x82090004 csd ra0 status register csd_ra0_sta 0x82090008 csd ra0 input data register csd_ra0_di 0x8209000c csd ra0 output data register csd_ra0_do 0x82090100 csd ra1 6k/12k uplink input data register 0 csd_ra1_6k_12k_uldi0 0x82090104 csd ra1 6k/12k uplink input data register 1 csd_ra1_6k_12k_uldi1 0x82090108 csd ra1 6k/12k uplink status data register csd_ra1_6k_12k_ulstus 0x8209010c csd ra1 6k/12k uplink output data register 0 csd_ra1_6k_12k_uldo0 0x82090110 csd ra1 6k/12k uplink output data register 1 csd_ra1_6k_12k_uldo1 0x82090200 csd ra1 6k/12k downlink input data register 0 csd_ra1_6k_12k_dldi0 0x82090204 csd ra1 6k/12k downlink input data register 1 csd_ra1_6k_12k_dldi1 0x82090208 csd ra1 6k/12k downlink output data register 0 csd_ra1_6k_12k_dldo0 0x8209020c csd ra1 6k/12k downlink output data register 1 csd_ra1_6k_12k_dldo1 0x82090210 csd ra1 6k/12k downlink status data register csd_ra1_6k_12k_dlstus 0x82090300 csd ra13.6k uplink input data register 0 csd_ra1_3p6k_uldi0 0x82090304 csd ra13.6k uplink status data register csd_ra1_3p6k_ulstus 0x82090308 csd ra13.6k uplink output data register 0 csd_ra1_3p6k_uldo0 0x8209030c csd ra13.6k uplink output data register 1 csd_ra1_3p6k_uldo1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 602 of 1535 0x82090400 csd ra1 3.6k downlink input data register 0 csd_ra1_3p6k_dldi0 0x82090404 csd ra1 3.6k downlink input data register 1 csd_ra1_3p6k_dldi1 0x82090408 csd ra1 3.6k downlink output data register 0 csd_ra1_3p6k_dldo0 0x8209040c csd ra1 3.6k downlink status data register csd_ra1_3p6k_dlstus 0x82090500 csd fax bit reverse type 1 input data register csd_fax_br1_di 0x82090504 csd fax bit reverse type 1 output data register csd_fax_br1_do 0x82090510 csd fax bit reverse type 2 input data register csd_fax_br2_di 0x82090514 csd fax bit reverse type 2 output data register csd_fax_br2_do table 79 csd accelerater registers 4.6.2 register definitions 0x82090000 csd ra0 control register csd_ra0_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rst bts0 vld_byte type wo wo wo reset 0 0 100 vld_byte specify how many valid bytes in the current input data. it must be specified before filling data in. bts0 back to state 0. force ra0 converter go back to state 0. incomplete word will be padded by stop bit. for instance, back-to-state0 command is issued after 8 byte data are filled in. then these bit after the 8 th byte will be padded with stop bits, and rdywd2 is asserted. after removing state word 2, the state pointer goes back to state 0. note that new data filling should take place after removing state word 2, or the state pointer may be out of order. %bubcjut 4upqcju 4ubsucju 4ubuf 4ubuf 4ubuf figure 90 example of back to state 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 603 of 1535 rst reset ra0 converter. in case, erroneously operation makes data disordered. this bit can restore all state to original state. 0 reserved 1 reset 0x82090004 csd ra0 status register csd_ra0_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bytecnt crtsta rdywd type ro ro rc reset 0 0 0 rdywd0~4 ready word. to indicate which state word is ready for withdrawal. data should be withdrawn before next data fills into csd_ra0_di, if there are any bits asserted. 0 not ready 1 ready crtsta current state. state0 ~ state4. to indicate which state word software is filling in. bytecnt the total number of bytes software is filling in. 0x82090008 csd ra0 input data register csd_ra0_di bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the ra0 convert input data. ready word indicator shall be check before filling in data. if any words are ready, withdraw them first; otherwise the ready data in ra0 converter will be replaced. 0x8209000c csd ra0 output data register csd_ra0_do bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout ra0 converted data. the return data corresponds to the ready word indicator defined in csd_ra0_sta register. the five bit of rdywd map to state0 ~ state 4 accordingly. when csd_ra0_do is read, the asserted state word will be returned. if there are two state words asserted at the same time, the lower one will be returned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 604 of 1535 0x82090100 csd ra1 6k/12k uplink input data register 0 csd_ra1_6k_1 2k_uldi0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the d1 to d32 of ra1 uplink data. 0x82090104 csd ra1 6k/12k uplink input data register 1 csd_ra1_6k_1 2k_uldi1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the d33 to d48 of ra1 uplink data. 0x82090108 csd ra1 6k/12k uplink status data register csd_ra1_6k_1 2k_ulstus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name e7 e6 e5 e4 x sb sa type wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 sa represents s1, s3, s6, and s8 of status bits. sb represents s4 and s9 of status bits. x represents x of status bits. e4 represents e4 of status bits. e5 represents e5 of status bits. e6 represents e6 of status bits. e7 represents e7 of status bits. 0x8209010c csd ra1 6k/12k uplink output data register 0 csd_ra1_6k_1 2k_uldo0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 605 of 1535 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dou type ro reset 0 dout the bit 0 to bit 31 of ra1 6k/12k uplink frame. 0x82090110 csd ra1 6k/12k uplink output data register 1 csd_ra1_6k_1 2k_uldo1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout the bit32 to bit 59 of ra1 6k/12k uplink frame. 0x82090200 csd ra1 6k/12k downlink input data register 0 csd_ra1_6k_1 2k_dldi0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the bit 0 to bit 31 of ra1 6k/12k downlink frame. 0x82090204 csd ra1 6k/12k downlink input data register 1 csd_ra1_6k_1 2k_dldi1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the bit32 to bit 59 of ra1 6k/12k downlink frame. 0x82090208 csd ra1 6k/12k downlink output data register 0 csd_ra1_6k_1 2k_dldo0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 606 of 1535 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout the d1 to d32 of ra1 downlink data. 0x8209020c csd ra1 6k/12k downlink output data register 1 csd_ra1_6k_1 2k_dldo1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout the d33 to d48 of ra1 downlink data. 0x82090210 csd ra1 6k/12k downlink status data register csd_ra1_6k_1 2k_dlstus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name e7 e6 e5 e4 x sb sa type ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 sa the result of majority votes of s1, s3, s6 and s8. sa is ?0? if equal vote. sb the result of majority votes of s4 and s9. sb is ?0? if equal vote. x the result of majority votes of two x bits in downlink frame. x is ?0? if equal vote. e4 represents e4 of status bits. e5 represents e5 of status bits. e6 represents e6 of status bits. e7 represents e7 of status bits. 0x82090300 csd ra1 3.6k uplink input data register 0 csd_ra1_3p6k _uldi0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 607 of 1535 reset 0 din the d1 to d24 of ra1 3.6k uplink data. 0x82090304 csd ra1 3.6k uplink status data register csd_ra1_3p6k _ulstus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name e7 e6 e5 e4 x sb sa type wo wo wo wo wo wo wo reset 0 0 0 0 0 0 0 sa represents s1, s3, s6, and s8 of status bits. sb represents s4 and s9 of status bits. x represents x of status bits. e4 represents e4 of status bits. e5 represents e5 of status bits. e6 represents e6 of status bits. e7 represents e7 of status bits. 0x82090308 csd ra1 3.6k uplink output data register 0 csd_ra1_3p6k _uldo0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout the bit 0 to bit 31 of ra1 3.6k uplink frame 0x8209030c csd ra1 3.6k uplink output data register 1 csd_ra1_3p6k _uldo1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout the bit 32 to bit 35 of ra1 3.6k uplink frame free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 608 of 1535 0x82090400 csd ra1 3.6k downlink input data register 0 csd_ra1_3p6k _dldi0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the bit 0 to bit 31 of ra1 3.6k downlink frame 0x82090404 csd ra1 3.6k downlink input data register 1 csd_ra1_3p6k _dldi1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din the bit 32 to bit 35 of ra1 3.6k downlink frame 0x82090408 csd ra1 3.6k downlink output data register 0 csd_ra1_3p6k _dldo0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 din the d1 to d24 of ra1 3.6k downlink data. 0x8209040c csd ra1 3.6k downlink status data register csd_ra1_3p6k _dlstus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name e7 e6 e5 e4 x sb sa type ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 sa the result of majority votes of s1, s3, s6 and s8. sa is ?0? if equal vote. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 609 of 1535 sb the result of majority votes of s4 and s9. sb is ?0? if equal vote. x the result of majority votes of two x bits in downlink frame. x is ?0? if equal vote. e4 represents e4 of status bits. e5 represents e5 of status bits. e6 represents e6 of status bits. e7 represents e7 of status bits. 0x82090500 csd fax bit reverse type 1 input data register csd_fax_br1_ di bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din 32-bit input data for type 1 bit reverse of fax data. the action of type 1 bit reverse is to reverse this word by word. 0x82090504 csd fax bit reverse type 1 output data register csd_fax_br1_ do bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout 32-bit result data for type 1 bit reverse of fax data. 0x82090510 csd fax bit reverse type 2 input data register csd_fax_br2_ di bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name din type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name din type wo reset 0 din 32-bit input data for type 2 bit reverse of fax data. the action of type 1 bit reverse is to reverse this word by byte. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 610 of 1535 0x82090514 csd fax bit reverse type 2 output data register csd_fax_br2_ do bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dout type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dout type ro reset 0 dout 32-bit result data for type 2 bit reverse of fax data. 4.7 divider to ease the processing load of mcu, a divider is employed here. the divider can operate signed and unsigned 32bit/32bit division, as well as modulus. the processing time of the divider is from 1 clock cycle to 33 clock cycles, which depends upon the magnitude of the value of the dividend. the detailed processing time is listed below in table 6 . from the table we can see that there are two kind of processing time (except for when the dividend is zero) in an item. which kind depends on whether there is the need for restoration at the last step of the division operation. after the divider is started by setting start to ?1? in divider control register, div_rdy will go low, and it will be asserted after the division process is finished. mcu could detect this status bit by polling it to know the correct access timing. in order to simplify polling, only the value of register div_rdy will appear while divider control register is read. hence, mcu does not need to mask other bits to extract the value of div_rdy. in gsm/gprs system, many divisions are executed with some constant divisors. therefore, some often-used constants are stored in the divider to speed up the process. by controlling control bits is_cnst and cnst_idx in divider control register, one can start a division without giving a divisor. this could save the time for writing divisor in and the instruction fetch time, and thus make the process more efficient. signed division unsigned division dividend clock cycles dividend clock cycles 0000_0000h 1 0000_0000h 1 0000_00ffh ? (-0000_0100h), excluding 0x0000_0000 8 or 9 0000_0001h - 0000_00ffh 8 or 9 0000_ffffh ? (-0001_0000h) 16 or 17 0000_0100h - 0000_ ffffh 16 or 17 00ff_ffffh ? (-0100_0000h) 24 or 25 0001_0000h - 00ff_ffffh 24 or 25 7fff_ffffh ? (-8000_0000h) 32 or 33 0100_0000h - ffff_ffffh 32 or 33 table 80 processing time in different value of dividend. 4.7.1 register definitions register address register function acronym 0x82060000 divider control register div_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 611 of 1535 0x82060004 divider dividend register div_dividend 0x82060008 divider divisor register div_divisor 0x8206000c divider quotient register div_quotient 0x82060010 divider remainder register div_remainder table 81 all registers table 0x82060000 divider control register div_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cnst_idx type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name in_cns t sign div_rd y star t type wo wo ro wo reset 0 1 1 0 start to start division. it will return to 0 after division has started. 0 reserved 1 start division div_rdy current status of divider. note that when div_con register is read, only the value of div_rdy will appear. that means program does not need to mask other part of the register to extract the information of div_rdy. 0 division is in progress. 1 division is finished. sign to indicate signed or unsigned division. 0 unsigned division. 1 signed division. is_cnst to indicate if internal constant value should be used as a divisor. if is_cnst is enabled, user does not need to write the value of the divisor, and divider will automatically use the internal constant value instead. what value divider will use depends on the value of cnst_idx. 0 normal division. divisor is written in via apb 1 using internal constant divisor instead. cnst_idx index of constant divisor. 0 divisor = 13 1 divisor = 26 2 divisor = 51 3 divisor = 52 4 divisor = 102 5 divisor = 104 0x82060004 divider dividend register div_dividend bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dividend[31:16] type wo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 612 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dividend[15:0] type wo reset 0 dividend dividend 0x82060008 divider divisor register div_divisor bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name divisor[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name divisor[15:0] type r/w reset 0 divisor divisor 0x8206000c divider quotient register div_quotient bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name quotient[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name quotient[15:0] type ro reset 0 quotient quotient 0x82060010 divider remainder register div_remainde r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name remainder[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name remainder[15:0] type ro reset 0 remainder remainder 4.8 fcs codec 4.8.1 general description fcs (frame check sequence) is used to detect errors in the following information bits: z rlp-frame of csd services in gsm. the frame length is fixed as 240 or 576 bits including the 24-bit fcs field. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 613 of 1535 z llc-frame of gprs service. the frame length is determined by the information field, and length of the fcs field is 24-bit. generation of the frame check sequence is very similar to the crc coding in baseband signal processing. etsi gsm specifications 04.22 and 04.64 both define the coding rule. the coding rules are: 1. the crc shall be ones complement of the modulo-2 sum of: z the remainder of x k x (x 23 +x 22 +x 21 +?+x 2 +x+1) modulo-2 divided by the generator polynomial, where k is the number of bits of the dividend. (i.e. fill the shift registers with all ones initially before feeding data) z the remainder of the modulo-2 division by the generator polynomial of the product of x 24 by the dividend, which are the information bits. 2. the crc-24 generator polynomial is: g(x)=x 24 +x 23 +x 21 +x 20 +x 19 +x 17 +x 16 +x 15 +x 13 +x 8 +x 7 +x 5 +x 4 +x 2 +1 3. the 24-bit crc are appended to the data bits in the msb-first manner. 4. decoding is identical to encoding except that data fed into the syndrome circuit is 24-bit longer than the information bits at encoding. the dividend is also multiplied by x 24 . if no error occurs, the remainder should satisfy r(x)=x 22 +x 21 +x 19 +x 18 +x 16 +x 15 +x 11 +x 8 +x 5 +x 4 (0x6d8930) and the parity output word will be 0x9276cf. in contrast to conventional crc, this special coding scheme makes the encoder fully identical to the decoder and simplifies the hardware design. 4.8.2 register definitions register address register function acronym 0x82070000 fcs input data register fcs_data 0x82070004 input data length indication register fcs_dlen 0x82070008 fcs parity output register 1, msb part fcs_par1 0x8207000c fcs parity output register 2, lsb part fcs_par2 0x82070010 fcs codec status register fcs_stat 0x82070014 fcs codec reset register fcs_rst table 82 fcs registers 0x82070000 fcs input data register fcs_data bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dx the data bits input. first write of this register is the starting point of the encode or decode process. x=0?15. the input format is d15 x n + d14 x n-1 + d13 x n-2 + ? + dk x k + ?, thus d15 is the first bit free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 614 of 1535 being pushed into the shift register. if the last data word is less than 16 bits, the rest bits are neglected. 0x82070004 input data length indication register fcs_dlen bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name len type wo len the mcu specifies the total data length in bits to be encoded or decoded. the data length. a number of multiple-of-8 is required (number_of_bytes x 8). 0x82070008 fcs parity output register 1, msb part fcs_par1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 type rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8207000c fcs parity output register 2, lsb part fcs_par2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p23 p22 p21 p20 p19 p18 p17 p16 type rc rc rc rc rc rc rc rc reset 0 0 0 0 0 0 0 0 px parity bits output. for fcs_par2 , bit 8 to bit15 will be filled by zeros when reading. x=0?23. the output format is p23 d 23 + p22 d 22 + p21 d 21 + ? + pk d k + ?+ p1 d 1 + p0 , thus p23 is the earliest bit being popped out from the shift register and first appended to the information bits. in other words, { fcs_par2[7:0], fcs_par1[15:8], fcs_par1[7:0] } is the order of appending parity to data. 0x82070010 fcs codec status register fcs_stat bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy fer rdy type rc rc rc reset 0 1 0 busy since the codec works in serial manner and the data word is input in parallel manner, busy = 1 indicates that current data word is being processed and write to fcs_data is invalid. busy = 0 allows write of fcs_data during encode or decode process. 0 idle 1 busy fer frame error indication, only for decode mode. fer = 0 means no error occurs and fer = 1 means the parity check has failed. write of fcs_rst.rst or first write of fcs_data will reset this bit to 0. 0 parity check pass 1 parity check fail rdy when rdy = 1, the encode or decode process has been finished. for encode, the parity data in fcs_par1 and fcs_par2 are correctly available. for decode, fcs_stat.fer indication is valid. write of fcs_rst.rst or first write of fcs_data will reset this bit to 0. 0 process is on-going. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 615 of 1535 1 process is finished. 0x82070014 fcs codec reset register fcs_rst bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en_de par bit rst type wo wo wo wo rst rst = 0 resets the crc coprocessor. before setup of fcs codec, the mcu needs to set rst = 0 to flush the shift register content before encode or decode. 0 reset 1 reserved bit bit = 0 means not to invert the bit order in a byte of data words when the codec is running. bit = 1 means the bit order in a byte written in fcs_data should be reversed. 0 not invert the bit order of data words 1 invert the bit order of data par par = 0 means not to invert the bit order in a byte of parity words when the codec is running, include reading of fcs_par1 and fcs_par2 . par = 1 means bit order of parity words should be reversed, in decoding or encoding. 0 not invert the bit order of data words 1 invert the bit order of data en_de en_de = 0 means encode; en_de = 1 means decode 0 encode 1 decode 4.9 gprs cipher unit 4.9.1 general description the unit implements the gprs encryption/decryption scheme that accelerates the computation of encryption and decryption gprs pattern. the block accelerates the computation of the key stream. however the bit-wise encryption/decryption of the data is still done by the mcu. both gea, gea2 and gea3 are supported. register address register function acronym 0x82080000 gprs encryption algorithm control register gcu_con 0x82080004 gprs encryption algorithm status register gcu_sat 0x82080008 gprs secret key kc 0 register gcu_skey0 0x8208000c gprs secret key kc 1 register gcu_skey1 0x82080010 gprs message key register gcu_mkey 0x82080014 gprs ciphered data register gcu_cdata free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 616 of 1535 table 83 gcu registers 4.9.2 register definitions 0x82080000 gprs encryption algorithm control register gcu_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rbo ks sinit dir alg type r/w r/w wo r/w r/w reset 0 10 0 0 0 this register controls the key generation function of the gprs encryption algorithm. alg choose the encryption/decryption algorithm. 00 = gea 01 = gea2 10 = gea3 11 = reserved dir the direction input of the gprs encryption algorithm. sinit start initialization. the mcu writes 1 to start initialization. the bit is always read at 0. ks control the read access. 00 = byte access, 01 = half word (16 bits) access, 10 = word access, 11 reserved. default value is 10. rbo reversal byte order bit. if the bit was set to 1, the byte order of gcu_skey0, gcu_skey1, gcu_mkey in write operation and gcu_skey0, gcu_skey1, gcu_mkey, gcu_ckey in read operation would be the reverse of baseband processor, and if the bit was 0, the behavior would be the same as baseband processor. byte-order of gcu_con and gcu_sat is not affected. the default value is 0 which is different from that in mt6218b. 0x82080004 gprs encryption algorith m status register gcu_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name stat key_c om init type ro ro ro reset 110 0 0 this register shows the status of the gprs encryption unit. init initialization flag. 0 otherwise 1 gcu is currently performing the initialization phase of gea or gea2. key_com key-stream computation. 0 a new key is available or the gcu is in initialization phase of gea , gea2 or gea3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 617 of 1535 1 the gcu is computing new key stream for gea, gea2, or gea3 stat the state of gcu core of gea and gea2. for debug purpose . 0x82080008 gprs secret key kc 0 register gcu_skey0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name kc[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name kc[15:0] type r/w reset 0 0x8208000c gprs secret key kc 1 register gcu_skey1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name kc[63:48] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name kc[47:32] type r/w reset 0 kc this set of registers shall be programmed with the gprs encryption algorithm secret key. 0x82080010 gprs message key register gcu_mkey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mkey[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mkey[15:0] type r/w reset 0 mkey this register shall be programmed with the ?message key? for the gprs encryption algorithm. 0x82080014 gprs ciphered data register gcu_cdata bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cdata[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cdata[15:0] type ro cdata the register contains the key stream. gcu will continue to generate next word of key while current word of key is removed. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 618 of 1535 4.9.3 programming guide to trigger the hardware, all register fields in gcu_skey0, gcu_skey1, and gcu_mkey must be well informed. then program gcu_sta to kick-off hardware operation.. then confirm the key_com register to be high before read-back the cdata. 4.10 md2gsys config register in addition to the pause mode capability while in the standby state, the software program can also put each peripheral independently into power down mode while in the active state by gating off their clock. the typical logic implementation is depicted in figure 13 . for all configuration bits, 1 signifies that the function is in power down mode, and 0 means the function is in the active mode. clock power down testmode figure 91 power down control at block level register address register name synonym 8200_0000h clock gating control register 0 md2gsys_cg_con0 8200_0004h clock gating control register 1 md2gsys_cg_con1 8200_0010h clock gating set register 0 md2gsys_cg_set0 8200_0014h clock gating set register 1 md2gsys_cg_set1 8200_0020h clock gating clear register 0 md2gsys_cg_clr0 8200_0024h clock gating clear register 1 md2gsys_cg_clr1 8200_0040h dsp clock dcm control register dspclk_con 8200_0100h memory delsel control regsiter 0 (used by hardware) md2gsys_delsel0 8200_0104h memory delsel control regsiter 1 (used by hardware) md2gsys_delsel1 8200_0108h memory delsel control regsiter 2 (used by hardware) md2gsys_delsel2 8200_010ch memory delsel control regsiter 3 (used by hardware) md2gsys_delsel3 8200_0110h memory delsel control regsiter 4 (used by hardware) md2gsys_delsel4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 619 of 1535 table 84 apb bridge register map 4.10.1 register definitions 8200_0000h clock gating control status register md2gsys_cg_ con0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irdbg 2 type ro reset 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irdbg 1 div gcc bfe vfe fcs apc bpi bsi irdma gcu type ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 md2g sub-system power down control status register (read only), value 1 represents power down. gcu status of the gcu controller power down. irdma status of the irdma power down. rtc status of the rtc power down. bsi status of the bsi power down. this status is not taken effect until both tdma_evtval and qbit_en are asserted. bpi status of the bpi power down. this status is not taken effect until both tdma_evtval and qbit_en are asserted. apc status of the apc power down. this status is not taken effect until both tdma_evtval and qbit_en are asserted. fcs status of the fcs power down. vfe status of the audio front end of vbi power down. bfe status of the base-band front end power down. gcc status of the gcc power down. div status of the divider power down. irdbg1 status of the irdbg1 power down. irdbg2 status of the irdbg2 power down. 8200_0004h clock gating control status register for radio blocks md2gsys_ cg_ con1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irdbg 2 type ro reset 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irdbg 1 div gcc bfe vfe fcs apc bpi bsi irdma gcu type ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 md2g sub-system radio block power down direct status, value 1 represents power down. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 620 of 1535 bsi status of the bsi power down. this status takes effect immediately. bpi status of the bpi power down. this status takes effect immediately. apc controls the apc power down. this status takes effect immediately. others same as md2gsys_cg_con0. 8200_0010h clock gating set register md2gsys_cg_ set0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irdbg 2 type wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irdbg 1 div gcc bfe vfe fcs apc bpi bsi irdma gcu type wo wo wo wo wo wo wo wo wo wo wo md2g sub-system power down set register, value 1 represents power down. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con0 = 16?h0f0f, writing cg_set0 = 16?f0f0 will result in cg_con0 = 16?hffff. gcu set the gcu controller power down. irdma set the irdma power down. rtc set the rtc power down. bsi set the bsi power down. this set value is not taken effect until both tdma_evtval and qbit_en are asserted. bpi set the bpi power down. this set value is not taken effect until both tdma_evtval and qbit_en are asserted. apc set the apc power down. this set value is not taken effect until both tdma_evtval and qbit_en are asserted. fcs set the fcs power down. vfe set the audio front end of vbi power down. bfe set the base-band front end power down. gcc set the gcc power down. div set the divider power down. irdbg1 set the irdbg1 power down. irdbg2 set the irdbg2 power down. 8200_0014h clock gating set register for radio blocks md2gsys _cg _set1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apc bpi bsi free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 621 of 1535 type wo wo wo md2g sub-system power down direct set register, value 1 represents power down. bsi set the bsi power down. this setting takes effect immediately. bpi set the bpi power down. this setting takes effect immediately. apc set the apc power down. this setting takes effect immediately. 8200_0020h clock gating clear register md2gsys_cg_ clr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irdbg 2 type wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irdbg 1 div gcc bfe vfe fcs apc bpi bsi irdma gcu type wo wo wo wo wo wo wo wo wo wo wo md2g sub-system power down set register, value 1 represents power down. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con0 = 16?hffff, writing cg_clr0 = 16?f0f0 will result in cg_con0 = 16?h0f0f. gcu clear the gcu controller power down. irdma clear the irdma power down. rtc clear the rtc power down. bsi clear the bsi power down. this clear value is not taken effect until both tdma_evtval and qbit_en are asserted. bpi clear the bpi power down. this clear value is not taken effect until both tdma_evtval and qbit_en are asserted. apc clear the apc power down. this clear value is not taken effect until both tdma_evtval and qbit_en are asserted. fcs clear the fcs power down. vfe clear the audio front end of vbi power down. bfe clear the base-band front end power down. gcc clear the gcc power down. div clear the divider power down. irdbg1 clear the irdbg1 power down. irdbg2 clear the irdbg2 power down. 8200_0024h clock gating clear register for radio blocks md2gsys _cg _clr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 622 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apc bpi bsi type wo wo wo md2g sub-system power down direct clear register. bsi clear the bsi power down. this setting takes effect immediately. bpi clear the bpi power down. this setting takes effect immediately. apc clear the apc power down. this setting takes effect immediately. 8200_0040 dsp clock frequency setting dspclk_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsp2_fsel dsp1_fsel type r/w r/w reset 111 111 the register defines the output frequency of dual dsp dcm (dynamic clock management) for dsp1 and dsp2. totally 7 levels are provided, ranging from 13mhz to 104mhz (default). dsp1_fsel dsp1 clock rate is (dsp1_fsel + 1) x 13 mhz dsp2_fsel dsp2 clock rate is (dsp2_fsel + 1) x 13 mhz 8200_0100h memory delsel control register 0 md2gsys_del sel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sc60 sp00 sp10 sp11 type r/w r/w r/w r/w reset 1011 1011 1011 1011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sp40 sp41 sp50 sp51 type r/w r/w r/w r/w reset 1011 1011 1011 1011 8200_0104h memory delsel control register 1 md2gsys_del sel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sc10 sc11 sc20 sc21 type r/w r/w r/w r/w reset 1011 1011 1011 1011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sc30 sc31 sc50 sc51 type r/w r/w r/w r/w reset 1011 1011 1011 1011 8200_0108h memory delsel control register 2 md2gsys_del sel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sd21 sd30 sd31 sp30 sp31 spn3 mcn0 type r/w r/w r/w r/w r/w r/w r/w reset 11 11 11 11 10 10 1011 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 623 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mcn1 mpn0 sc00 sc01 type r/w r/w r/w r/w reset 1011 1011 1011 1011 8200_010ch memory delsel control register 3 md2gsys_del sel3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name shramd2_2 vfe mcn2 md00 md01 md02 md03 md04 type r/w r/w r/w r/w r/w r/w r/w r/w reset 10 10 10 10 10 10 10 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpn1 sc40 sc41 sd01 sd10 sd11 sd12 sd20 type r/w r/w r/w r/w r/w r/w r/w r/w reset 11 11 11 10 10 11 10 11 8200_0110h memory delsel control register 4 md2gsys_del sel4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsi viterbi eqlzr prefilter shramd1 shramd2_1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 10 11 01 01 10 10 4.11 timing generator timing is the most critical issue in gsm/gprs applications. the tdma timer provides a simple interface for the mcu to program all the timing-related events for receive event control, transmit event control and the timing adjustment. detailed descriptions are mentioned in section 4.11.1. 4.11.1 tdma timer the tdma timer unit is composed of three major blocks: quarter bit counter, signal generator and event registers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 624 of 1535 figure 92 the block diagram of tdma timer by default, the quarter-bit counter continuously counts from 0 to the wrap position. in order to apply to cell synchronization and neighboring cell monitoring, the wrap position can be changed by the mcu to shorten or lengthen a tdma frame. the wrap position is held in the tdma_wrap register and the current value of the tdma quarter bit counter may be read by the mcu via the tdma_tqcnt register. the signal generator handles the overall comparing and event-generating processes. when a match has occurred between the quarter bit counter and the event register, a predefined control signal is generated. these control signals may be used for on-chip and off-chip purposes. signals that change state more than once per frame make use of more than one event register. the event registers are programmed to contain the quarter bit position of the event that is to occur. the event registers are double buffered. the mcu writes into the write buffers of the registers, and the event tdma_evtval trigger hw to transfer the data from the write buffers to the active buffers. caution: values in the active buffers are updated at the end of qbit count (tdma_evtval). the tdma_evtval signal itself may be programmed at any quarter bit position. these event registers could be classified into four groups: on-chip control events tdma_evtval this event allows the data values written by the mcu to pass through to the active buffers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 625 of 1535 tdma_wrap tdma quarter bit counter wrap position. this sets the position at which the tdma quarter bit counter resets back to zero. the default value is 4999, changing this value will advance or retard the timing events in the frame following the next tdma_evtval signal. caution: the wrap value of the first frame after the sleep mode will refer to tqwrap_sm value if sw enables turbo sleep mode. tdma_dtirq dsp tdma interrupt requests. dtirq triggers the dsp to read the command from the mcu/dsp shard ram to schedule the activities that will be executed in the current frame. tdma_ctirq1/ctirq2 mcu tdma interrupt requests. ctirqx triggers the arm to schedule the activities that will be executed in the next frame. tdma_auxadc [1:0] this signal triggers the monitoring adc to measure the voltage, current, temperature, device id etc.. tdma_afc [3:0] this signal powers up the automatic frequency control dac for a programmed duration after this event. note: for both mcu and dsp tdma interrupt requests, these signals are all active low during one quarter bit duration and they should be used as edge sensitive events by the respective interrupt controllers. on-chip receive events tdma_bdlon [5:0] these registers are a set of six which contain the quarter bit event that initiates the receive window assertion sequence which powers up and enables the receive adc, and then enables loading of the receive data into the receive buffer. tdma_bdloff [5:0] these registers are a set of six which contain the quarter bit event that initiates the receive window de- assertion sequence which disables loading of the receive data into the receive buffer, and then powers down the receive adc. tdma_rxwin[5:0] dsp tdma interrupt requests. tdma_rxwin is usually used to initiate the related rx processing including two modes. in single-shot mode, tdma_rxwin is generated when the brxfs signal is de-asserted. in repetitive mode, tdma_rxwin will be generated both regularly with a specific interval after brxfs signal is asserted and when the brxfs signal is de-asserted. figure 93 the timing diagram of brxen and brxfs note: tdma_bdlon/off event registers, together with tdma_bdlcon register, generate the corresponding brxen and brxfs window used to power up/down baseband downlink path and control the duration of data transmission to the dsp, respectively. on-chip transmit events tdma_apc [6:0] these registers initiate the loading of the transmit burst shaping values from the transmit burst shaping ram into the transmit power control dac. tdma_bulon [3:0] this register contains the quarter bit event that initiates the transmit window assertion sequence which powers up the modulator dac and then enables reading of bits from the transmit buffer into the gmsk modulator. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 626 of 1535 tdma_buloff [3:0] this register contains the quarter bit event that initiates the transmit window de-assertion sequence which disables the reading of bits from the transmit buffer into the gmsk modulator, and then power down the modulator dac. figure 94 the timing diagram of btxen and btxfs note: tdma_bulon/off event registers, together with tdma_bulcon1, tdma_bulcon2 register, generate the corresponding btxen, btxfs and apcen window used to power up/down the baseband uplink path, control the duration of data transmission from the dsp and power up/down the apc dac, respectively. off-chip control events tdma_bsi [19:0] the quarter bit positions of these 20 bsi events are used to initiate the transfer of serial words to the transceiver and synthesizer for gain control and frequency adjustment. tdma_bpi [41:0] the quarter bit positions of these 30 bpi events are used to generate changes of state on the output pins to control the external radio components. 4.11.1.1 register definitions 0x811f0150 event enable register 0 tdma_evtena 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name afc3 afc2 afc1 afc0 bd l5 bdl4 bdl3 bdl2 bdl1 bdl0 ctirq 2 ctirq 1 dtirq type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 dtirq enable tdma_dtirq ctirq n enable tdma_ctirq n afc n enable tdma_afc n bdl n enable tdma_bdlon n and tdma_bdloff n for all these bits, 0 function is disabled 1 function is enabled 0x811f0154h event enable register 1 tdma_evtena 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gprs bul3 bul2 bul1 bul0 apc6 apc5 apc4 apc3 apc2 apc1 apc0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 627 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 gprs indicate which mode is on-going. 0 tdma_apc0 & tdma_apc1 events are controlled by apc0 & apc1 in the register tdma_evtena1 & tdma_dtxcon. (gsm mode) 1 tdma_apc0 & tdma_apc1 events are controlled by apc0 & apc1 in the register tdma_evtena1 only. (gprs mode) apc n enable tdma_apc n bul n enable tdma_bulon n and tdma_buloff n for all these bits, 0 function is disabled 1 function is enabled 0x811f0158 event enable register 2 tdma_evtena 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsi15 bsi14 bsi13 bsi12 bsi11 bsi10 bsi9 bsi8 bsi7 bsi6 bsi5 bsi4 bsi3 bsi2 bsi1 bsi0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x811f015c event enable register 3 tdma_evtena 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bsi19 bsi18 bsi17 bsi16 type r/w r/w r/w r/w reset 0 0 0 0 bsi n bsi event enable control 0 disable tdma_bsi n 1 enable tdma_bsi n 0x811f0160 event enable register 4 tdma_evtena 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bpi15 bpi14 bpi13 bpi12 bpi11 bpi10 bpi9 bpi8 bpi7 bpi6 bpi5 bpi4 bpi3 bpi2 bpi1 bpi0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x811f0164 event enable register 5 tdma_evtena 5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bpi31 bpi30 bpi29 bpi28 bpi27 bpi26 bpi25 bpi24 bpi23 bpi22 bpi21 bpi20 bpi19 bpi18 bpi17 bpi16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 628 of 1535 bpi n bpi event enable control 0 disable tdma_bpi n 1 enable tdma_bpi n 0x811f0168 event enable register 6 tdma_evtena 6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bpi41 bpi40 bpi39 bpi38 bpi37 bpi36 bpi35 bpi34 bpi33 bpi32 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 bpi n bpi event enable control 0 disable tdma_bpi n 1 enable tdma_bpi n 0x811f016c event enable register 7 tdma_evtena 7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aux1 aux0 type r/w r/w reset 0 0 aux auxiliary adc event enable control 0 disable auxiliary adc event 1 enable auxiliary adc event 0x811f0170 qbit timer offset control register tdma_wrapo fs bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name toi[1:0] type r/w reset 0 toi this register defines the value used to advance the qbit timer in unit of 1/4 quarter bit; the timing advance will be take place as soon as the tdma_evtval is occurred, and it will be cleared automatically. 0x811f0174 qbit timer biasing control register tdma_regbia s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tq_bias[13:0] type r/w reset 0 tq_bias this register defines the qbit offset value which will be added to the registers being programmed. it only takes effects on afc, bdlon/off, bulon/off, apc, auxadc, bsi and bpi event registers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 629 of 1535 0x811f0180 dtx control register tdma_dtxcon bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dtx3 dtx2 dtx1 dtx0 type r/w r/w r/w r/w dtx dtx flag is used to disable the associated transmit signals 0 bulon0~3, buloff0~3, apc_ev0 & apc_ev1 are controlled by tdma_evtena1 register 1 bulon0~3, buloff0~3, apc_ev0 & apc_ev1 are disabled 0x811f0184 receive interrupt control register tdma_rxcon bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mod5 mod4 mod3 mod2 mod1 mod0 rxintcnt[9:0] type r/w r/w r/w r/w r/w r/w r/w rxintcnt tdma_rxwin interrupt generation interval in quarter bit unit mod n mode of receive interrupts 0 single shot mode for the corresponding receive window 1 repetitive mode for the corresponding receive window 0x811f0188 baseband downlink control register tdma_bdlco n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name adc_on adc_off type r/w r/w adc_on brxen to brxfs setup up time in quarter bit unit. adc_off brxen to brxfs hold up time in quarter bit unit. 0x811f018c baseband uplink control register 1 tdma_bulco n1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dac_on dac_off type r/w r/w dac_on btxen to btxfs setup up time in quarter bit unit. dac_off btxen to btxfs hold up time in quarter bit unit. 0x811f0190 baseband uplink control register 2 tdma_bulco n2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apc_hys type r/w apc_hys apcen to btxen hysteresis time in quarter bit unit. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 630 of 1535 0x811f0194 frequency burst indication register tdma_fb_fla g bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbdl5 fbdl4 fbdl3 fbdl2 fbdl1 fbdl0 type r/w r/w r/w r/w r/w r/w fbdln indication of frequency burst for rx window n the register is double-buffered. the value at the write buffers will be auto-cleared at the next event-validate (tdma_evtval) and its value will be at the same time loaded to the active buffer. the exact fb indication comes from the active buffer and the corresponding mode in register tdma_rxcon (bit15~bit10). it will be asserted after tdma_evtval signals if the corresponding fbdlx & tdma_rxcon[x+10] are set to 1. the fb indication de-assertion only depends tdma_fb_clri and the falling edge of the corresponding rx window. 0x811f0198 direct frequency burst closing tdma_fb_clri bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type as long as the register is written, active buffer for fb indication will be reset then therefore the frequency burst indication will be forced to 0. address type width reset value name description 0x80000000 r [13:0] ? tdma_tqcnt read quarter bit counter 0x811f0004 r/w [13:0] 0x1387 tdma_wrap latched qbit counter reset position 0x811f0008 r/w [13:0] 0x1387 tdma_wrapimd direct qbit counter reset position 0x811f000c r/w [13:0] 0x0000 tdma_evtval event latch position 0x811f0010 r/w [13:0] ? tdma_dtirq dsp software control 0x811f0014 r/w [13:0] ? tdma_ctirq1 mcu software control 1 0x811f0018 r/w [13:0] ? tdma_ctirq2 mcu software control 2 0x811f0020 r/w [13:0] ? tdma_afc0 the 1 st afc control 0x811f0024 r/w [13:0] ? tdma_afc1 the 2 nd afc control 0x811f0028 r/w [13:0] ? tdma_afc2 the 3 rd afc control 0x811f002c r/w [13:0] ? tdma_afc3 the 4 th afc control 0x811f0030 r/w [13:0] ? tdma_bdlon0 0x811f0034 r/w [13:0] ? tdma_bdloff0 data serialization of the 1 st rx block 0x811f0038 r/w [13:0] ? tdma_bdlon1 0x811f003c r/w [13:0] ? tdma_bdloff1 data serialization of the 2 nd rx block 0x811f0040 r/w [13:0] ? tdma_bdlon2 0x811f0044 r/w [13:0] ? tdma_bdloff2 data serialization of the 3 rd rx block 0x811f0048 r/w [13:0] ? tdma_bdlon3 0x811f004c r/w [13:0] ? tdma_bdloff3 data serialization of the 4 th rx block free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 631 of 1535 0x811f0050 r/w [13:0] ? tdma_bdlon4 0x811f0054 r/w [13:0] ? tdma_bdloff4 data serialization of the 5 th rx block 0x811f0058 r/w [13:0] ? tdma_bdlon5 0x811f005c r/w [13:0] ? tdma_bdloff5 data serialization of the 6 th rx block 0x811f0060 r/w [13:0] ? tdma_bulon0 0x811f0064 r/w [13:0] ? tdma_buloff0 data serialization of the 1 st tx slot 0x811f0068 r/w [13:0] ? tdma_bulon1 0x811f006c r/w [13:0] ? tdma_buloff1 data serialization of the 2 nd tx slot 0x811f0070 r/w [13:0] ? tdma_bulon2 0x811f0074 r/w [13:0] ? tdma_buloff2 data serialization of the 3 rd tx slot 0x811f0078 r/w [13:0] ? tdma_bulon3 0x811f007c r/w [13:0] ? tdma_buloff3 data serialization of the 4 th tx slot 0x811f0090 r/w [13:0] ? tdma_apc0 the 1 st apc control 0x811f0094 r/w [13:0] ? tdma_apc1 the 2 nd apc control 0x811f0098 r/w [13:0] ? tdma_apc2 the 3 rd apc control 0x811f009c r/w [13:0] ? tdma_apc3 the 4 th apc control 0x811f00a0 r/w [13:0] ? tdma_apc4 the 5 th apc control 0x811f00a4 r/w [13:0] ? tdma_apc5 the 6 th apc control 0x811f00a8 r/w [13:0] ? tdma_apc6 the 7 th apc control 0x811f00b0 r/w [13:0] ? tdma_bsi0 bsi event 0 0x811f00b4 r/w [13:0] ? tdma_bsi1 bsi event 1 0x811f00b8 r/w [13:0] ? tdma_bsi2 bsi event 2 0x811f00bc r/w [13:0] ? tdma_bsi3 bsi event 3 0x811f00c0 r/w [13:0] ? tdma_bsi4 bsi event 4 0x811f00c4 r/w [13:0] ? tdma_bsi5 bsi event 5 0x811f00c8 r/w [13:0] ? tdma_bsi6 bsi event 6 0x811f00cc r/w [13:0] ? tdma_bsi7 bsi event 7 0x811f00d0 r/w [13:0] ? tdma_bsi8 bsi event 8 0x811f00d4 r/w [13:0] ? tdma_bsi9 bsi event 9 0x811f00d8 r/w [13:0] ? tdma_bsi10 bsi event 10 0x811f00dc r/w [13:0] ? tdma_bsi11 bsi event 11 0x811f00e0 r/w [13:0] ? tdma_bsi12 bsi event 12 0x811f00e4 r/w [13:0] ? tdma_bsi13 bsi event 13 0x811f00e8 r/w [13:0] ? tdma_bsi14 bsi event 14 0x811f00ec r/w [13:0] ? tdma_bsi15 bsi event 15 0x811f00f0 r/w [13:0] ? tdma_bsi16 bsi event 16 0x811f00f4 r/w [13:0] ? tdma_bsi17 bsi event 17 0x811f00f8 r/w [13:0] ? tdma_bsi18 bsi event 18 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 632 of 1535 0x811f00fc r/w [13:0] ? tdma_bsi19 bsi event 19 0x811f0100 r/w [13:0] ? tdma_bpi0 bpi event 0 0x811f0104 r/w [13:0] ? tdma_bpi1 bpi event 1 0x811f0108 r/w [13:0] ? tdma_bpi2 bpi event 2 0x811f010c r/w [13:0] ? tdma_bpi3 bpi event 3 0x811f0110 r/w [13:0] ? tdma_bpi4 bpi event 4 0x811f0114 r/w [13:0] ? tdma_bpi5 bpi event 5 0x811f0118 r/w [13:0] ? tdma_bpi6 bpi event 6 0x811f011c r/w [13:0] ? tdma_bpi7 bpi event 7 0x811f0120 r/w [13:0] ? tdma_bpi8 bpi event 8 0x811f0124 r/w [13:0] ? tdma_bpi9 bpi event 9 0x811f0128 r/w [13:0] ? tdma_bpi10 bpi event 10 0x811f012c r/w [13:0] ? tdma_bpi11 bpi event 11 0x811f0130 r/w [13:0] ? tdma_bpi12 bpi event 12 0x811f0134 r/w [13:0] ? tdma_bpi13 bpi event 13 0x811f0138 r/w [13:0] ? tdma_bpi14 bpi event 14 0x811f013c r/w [13:0] ? tdma_bpi15 bpi event 15 0x811f0140 r/w [13:0] ? tdma_bpi16 bpi event 16 0x811f0144 r/w [13:0] ? tdma_bpi17 bpi event 17 0x811f0148 r/w [13:0] ? tdma_bpi18 bpi event 18 0x811f014c r/w [13:0] ? tdma_bpi19 bpi event 19 0x811f01a0 r/w [13:0] ? tdma_bpi20 bpi event 20 0x811f01a4 r/w [13:0] ? tdma_bpi21 bpi event 21 0x811f01a8 r/w [13:0] ? tdma_bpi22 bpi event 22 0x811f01ac r/w [13:0] ? tdma_bpi23 bpi event 23 0x811f01b0 r/w [13:0] ? tdma_bpi24 bpi event 24 0x811f01b4 r/w [13:0] ? tdma_bpi25 bpi event 25 0x811f01b8 r/w [13:0] ? tdma_bpi26 bpi event 26 0x811f01bc r/w [13:0] ? tdma_bpi27 bpi event 27 0x811f01c0 r/w [13:0] ? tdma_bpi28 bpi event 28 0x811f01c4 r/w [13:0] ? tdma_bpi29 bpi event 29 0x811f01c8 r/w [13:0] ? tdma_bpi30 bpi event 30 0x811f01cc r/w [13:0] ? tdma_bpi31 bpi event 31 0x811f01d0 r/w [13:0] ? tdma_bpi32 bpi event 32 0x811f01d4 r/w [13:0] ? tdma_bpi33 bpi event 33 0x811f01d8 r/w [13:0] ? tdma_bpi34 bpi event 34 0x811f01dc r/w [13:0] ? tdma_bpi35 bpi event 35 0x811f01e0 r/w [13:0] ? tdma_bpi36 bpi event 36 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 633 of 1535 0x811f01e4 r/w [13:0] ? tdma_bpi37 bpi event 37 0x811f01e8 r/w [13:0] ? tdma_bpi38 bpi event 38 0x811f01ec r/w [13:0] ? tdma_bpi39 bpi event 39 0x811f01f0 r/w [13:0] ? tdma_bpi40 bpi event 40 0x811f01f4 r/w [13:0] ? tdma_bpi41 bpi event 41 0x811f0400 r/w [13:0] ? tdma_auxev0 auxiliary adc event 0 0x811f0404 r/w [13:0] ? tdma_auxev1 auxiliary adc event 1 0x811f0150 r/w [15:0] 0x0000 tdma_evtena0 event enable control 0 0x811f0154 r/w [15:0] 0x0000 tdma_evtena1 event enable control 1 0x811f0158 r/w [15:0] 0x0000 tdma_evtena2 event enable control 2 0x811f015c r/w [3:0] 0x0000 tdma_evtena3 event enable control 3 0x811f0160 r/w [15:0] 0x0000 tdma_evtena4 event enable control 4 0x811f0164 r/w [13:0] 0x0000 tdma_evtena5 event enable control 5 0x811f0168 r/w [1:0] 0x0000 tdma_evtena6 event enable control 6 0x811f016c r/w [11:0] 0x0000 tdma_evtena7 event enable control 7 0x811f0170 r/w [1:0] 0x0000 tdma_wrapofs tq counter offset control register 0x811f0174 r/w [13:0] 0x0000 tdma_regbias biasing control register 0x811f0180 r/w [3:0] ? tdma_dtxcon dtx control register 0x811f0184 r/w [15:0] ? tdma_rxcon receive interrupt control register 0x811f0188 r/w [15:0] ? tdma_bdlcon downlink control register 0x811f018c r/w [15:0] ? tdma_bulcon1 uplink control register 1 0x811f0190 r/w [7:0] ? tdma_bulcon2 uplink control register 2 0x811f0194 r/w [5:0] ? tdma_fb_flag fb indicator 0x811f0198 w ? tdma_fb_clri direct clear of fb indicator 0x811f0264 r [15:0] ? tdma_wrap_cnt wrap counter for sw la free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 634 of 1535 table 85 tdma timer register map 4.11.1.2 application note figure 95 rx timing set example the tdma timing and data setting are described in 2 parts. one part is that before turning on rx sport to receiving i/q data. and the other part is after turning off rx sport to finish receiving i/q data. to describe these two parts easily, the timing of turning on rx sport is taken as one base named r0 . and the timing of turning off rx sport is taken as one base named r1 . rx adc part: to setup the timing of rx adc and sport, 2 timings need to be defined in l1d_custom_rf.h . the time from rx adc enabling to rx sport turning on ( r0 ) is defined as qb_rx_fena_2_fsync .the time from rx sport turning on ( r1 ) to rx adc disabling is defined as qb_rx_fsync_2_fena . the value of this two aliases should be positive or zero. these two values is defined in the register tdma_bdlcon . bsi part: bsi data and events need to be set in serial to a 3-wire base rf module. each rx window is allocated 3 bsi events. usually 1'st bsi event is used to warm up the synthesizer and set its n-counter to lock the operation frequency. the 2'nd bsi is used to set the receiving amplifier gain of transceiver. the 3'rd bsi is used to command transceiver entering idle mode. bsi events are defined in the registers tdma_bsi0~19 . bpi part: the connection of hw signals of bpi data bus and rf module is flexible and depends on customer's design. the setting timing and data setting of bpi bus are used to specify at what time and which bpi states are changed. the bpi data may be varied by the operation band, so the dedicate bpi data of each band should be defined. the states transient of bpi signals are decided by the time of event, therefore the active time and the bpi states for each band shall be defined. bpi events are defined in the registers tdma_bpi0~41 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 635 of 1535 tx adc part: to setup the timing of tx dac and sport, 2 timings need to be defined in l1d_custom.h . the time from tx dac enabling to tx sport turning on ( t0 ) is defined as qb_tx_fena_2_fsync .the time from tx sport turning on ( t1 ) to tx dac disabling is defined as qb_tx_fsync_2_fena . the value of this two aliases should be positive or zero. these two values is defined in the register tdma_bulcon1 . bsi part: bsi data and events need to be set in order to sent serial data to 3-wire devices on rf module. each tx window is allocated 3 bsi events. usually 1'st bsi event is used to warm up the set synthesizer and set its n- counter to lock the operation frequency. the 2'nd bsi is used to set the transmit command and indicate the operation band. the 3'rd bsi is used to command transceiver entering idle mode. bsi events are defined in the registers tdma_bsi0~19 . bpi parts: the setting of bpi bus includes timing and data setting to specify at what time what bpi states are changed. the bpi data may be varied by operation band, so the bpi data of each band should be defined. the 1'st bpi event is usually used to activate the rf components on rf module in transmit mode. the 2'nd bpi event is usually used to select band and switch r/tx. the 3'rd bpi event is usually used to force the rf module into idle mode. bpi events are defined in the registers tdma_bpi0~41 . apc parts: in addition to tx dac, tx sport, bsi, bpi unit needs to be set, the control of pa is important for tx window. the pa is control by the apc unit of mt62xx. before the data transmission, apc ramps up the pa to the indicated power level. data is transmitted at that level. after finishing transmission, apc ramps down the pa. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 636 of 1535 before pa ramping up, a dc offset of pa is performed to let pa ramp up smoothly. apc events are defined in the registers tdma_apc0~6 . 4.11.2 slow clocking unit figure 96 the block diagram of the slow clocking unit the slow clocking unit is provided to maintain the synchronization to the base-station timing using a 32khz crystal oscillator while the 13mhz reference clock is switched off. as shown in figure 39, this unit is composed of frequency measurement unit, pause unit, and clock management unit. because of the inaccuracy of the 32khz oscillator, a frequency measurement unit is provided to calibrate the 32khz crystal taking the accurate 13mhz source as the reference. the calibration procedure always takes place prior to the pause period. the pause unit is used to initiate and terminate the pause mode procedure and it also works as a coarse time-base during the pause period. the clock management unit is used to control the system clock while switching between the normal mode and the pause mode. srclkena is used to turn on/off the clock squarer, dsp pll and off-chip tcvcxo. clock_off signal is used for gating the main mcu and dsp clock, and vcxo_off is used as the acknowledgement signal of the clock_off request. 4.11.2.1 register definitions 0x811f0218 slow clocking unit control register sm_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pause_star t fm_star t type w w reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 637 of 1535 fm_start initiate the frequency measurement procedure pause_start initiate the pause mode procedure at the next timer wrap position 0x811f021c slow clocking unit status register sm_sta bit 15 14 13 12 11 10 9 8 name pause_abo rt type r bit 7 6 5 4 3 2 1 0 name settle_cpl pause_cpl pause_int pause_rqst fm_cpl fm_rqst type r r r r r r fm_rqst frequency measurement procedure is requested fm_cpl frequency measurement procedure is completed pause_rqst pause mode procedure is requested pause_int asynchronous wake up from pause mode pause_cpl pause period is completed settle_cpl settling period is completed pause_abort pause mode is aborted because of the reception of interrupt prior to entering pause mode 0x811f022c slow clocking unit configuration register sm_cnf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ap2m d_cci f tp gpt msdc rtc eint kp sm fm type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1 1 fm enable interrupt generation upon completion of frequency measurement procedure sm enable interrupt generation upon completion of pause mode procedure kp enable asynchronous wake-up from pause mode by key press eint enable asynchronous wake-up from pause mode by external interrupt rtc enable asynchronous wake-up from pause mode by real time clock interrupt msdc enable asynchronous wake-up from pause mode by memory card insertion interrupt gpt enable asynchronous wake-up from pause mode by gpt timer tp enable asynchronous wake-up from pause mode by touch panel press ap2md_ccif enable asynchronous wake-up from pause mode by ccif 0x811f0238 wake_pll_setting (time & enable) wake_pll_ setting bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en time type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 time the time sleep control generates a reset signal for pll in the clk setting time. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 638 of 1535 en enable the generation of the reset signal 0 disable 1 enable 0x811f023c jump position of the first frame after sleep mode (time & enable) tqinit_sm bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en time type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 time the jump position of the first frame after sleep mode. tqcnt will jump from 0 to the pre-defined value, not 1 at the first frame after sleep mode. en enable if the wrap value applies to the first frame after sleep mode. 0 disable 1 enable 0x811f0250 wait-time setting for power-down strobe tdma_pdn_se quence bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g_iso2pwr_t1 md2g_iso2rst_t0 type r/w r/w reset 2 1 timing relationship of 2g modem system power on control. note the sm_clk_settle should be larger than (md2g_iso2pwr_t1 + 1) . otherwise the state machine for the power control gets out of sequence if receiving interrupt during the latency counting. md2g_iso2rst_t0 latency between isolation assert to reset activated, in unit of 32khz cycles md2g_iso2pdn_t1 latency between isolation assert to power-down activated, in unit of 32khz cycles. md2g_iso2pdn_t1 must be larger than md2g_iso2rst_t0 0x811f0254 power down duration tdma_pdn_du ration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g_pdn_duration type r/w reset 0x3ffff md2g_pdn_duration duration of power-down time after md2g_iso2pdn_t0 delay, in unit of 32khz cycles. if the value is too large so that the 26mhz is enabled first (awaken due to pause_cpl, sw_pause_int or pause_int), then md2gsys automatically powered-on without waiting md2g_pdn_duration expired 0x811f0258 reset duration tdma_rst_du ration bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g_rst_duration free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 639 of 1535 type r/w reset 0x3ffff md2g_rst_duration duration of reset time after md2g_iso2rst_t1 delay, in unit of 32khz cycles. if the value is too large so that the 26mhz is enabled first (awaken due to pause_cpl, sw_pause_int or pause_int), then md2gsys automatically reset-released without waiting md2g_rst_duration expired. typically md2g_rst_duration should be larger than md2g_pdn_duration 0x811f025c power-down control tdma_pdn_co n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g _hw_ pdn_e n md2g _pdn_ sw_e n md2g _rst_ sw_e n md2g _iso_ sw_e n md2g _pdn_ sel md2g _rst_ sel md2g _iso_ sel type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 md2g_iso_sel select the isolation scheme of md2gsys 0 software programming md2g_iso_sw_en 1 hardware control: isolation goes with clock gating signal md2g_rst_sel select the reset scheme of md2gsys 0 software programming md2g_rst_sw_en 1 hardware control: reset assert after md2g_iso2rst_t0 32khz cycles, reset de-assert according to either md2g_rst_duration or pause_cpl, or sw_pause_int/pause_int md2g_pdn_sel select the power-down scheme of md2gsys 0 software programming md2g_pdn_sw_en 1 hardware control: power-down activated after md2g_iso2pdn_t1 32khz cycles, power-on according to either md2g_rst_duration or pause_cpl, or sw_pause_int/pause_int md2g_iso_sw_en software programming for md2gsys isolation timing instance, the isolation signal assert/de-assert right after being programmed without any latency 0 isolation disabled 1 isolation enabled md2g_rst_sw_en software programming for md2gsys reset timing instance, the reset signal assert/de-assert right after being programmed without any latency 0 reset de-asserted 1 reset asserted md2g_pdn_sw_en software programming for md2gsys power-down timing instance, the power-down signal assert/de-assert right after being programmed without any latency 0 power-on 1 power-down md2g_hw_pdn_en enable hardware control sequence for the md2gsys isolation, reset and power- down process 0 hardware control disabled 1 hardware control enabled free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 640 of 1535 0x811f0260 wait-time setting for reset strobe tdma_pdn_se quence2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name md2g_pdn2rst_t2 type r/w reset 1 md2g_pdn2rst_t2 latency between pwr_on assert to reset released, in unit of 32khz cycles. sm_clk_settle should be larger than (md2g_pdn2rst_t2 + 2) hardware control se q uence for md2gsys p ower-down: a. power-on / reset-released due to md2g_pdn_duration/md2g_rst_duration expired md2gsys_pwr_on md2gsys_isolation_en md2gsys_pwr_rst_b pdn_duration_end rst_duration_end b. power-on / reset-released due to pause_cpl md2gsys_pwr_on md2gsys_isolation_en md2gsys_pwr_rst_b pause_cpl_rqst pause_cpl c. power-on / reset-released due to sw_pause_int/pause_int md2gsys_pwr_on md2gsys_isolation_en md2gsys_pwr_rst_b (sw_)pause_intr_rqst (sw_)pause_intr md2g_iso2rst_t0 md2g_iso2pdn_t1 md2g_pdn_duration md2g_rst_duration md2g_iso2rst_t0 md2g_iso2pdn_t1 sm_pause sm_clk_settle md2g_pdn2rst_t2 + 2 md2g_iso2rst_t0 md2g_iso2pdn_t1 sm_pause sm_clk_settle md2g_pdn2rst_t2 + 2 address type width reset value name description 0x811f0200 r/w [2:0] ? sm_pause_m msb of pause duration 0x811f0204 r/w [15:0] ? sm_pause_l 16 lsb of pause duration 0x811f0208 r/w [13:0] ? sm_clk_settle off-chip vcxo settling duration 0x811f020c r [2:0] ? sm_final_pause_ m msb of final pause count 0x811f0210 r [15:0] ? sm_final_pause_l 16 lsb of final pause count 0x811f0214 r [13:0] ? sm_qbit_start tq_ count value at the start of the pause 0x811f0218 w [1:0] 0x0000 sm_con sm control register 0x811f021c r [7:3,1:0] 0x0000 sm_sta sm status register 0x811f0220 r/w [15:0] ? sm_fm_duration 32khz measurement duration 0x811f0224 r [9:0] ? sm_fm_result_m 10 msb of frequency measurement result 0x811f0228 r [15:0] ? sm_fm_result_l 16 lsb of frequency measurement result 0x811f022c r/w [4:0] 0x0000 sm_cnf sm configuration register free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 641 of 1535 0x811f0230 r [23:0] 0x00000 0 rtccount rtc count 0x811f0238 r/w [15:0] 0x8020 wake_pll_settin g pll rst time in the clk settling time. 0x811f023c r/w [13:0] 0x1387 tqinit_sm jump value of the first frame after sleep mode 4.12 voice front-end 4.12.1 general description figure 97 shows the digital circuits block diagram of the audio front-end. the apb register block is an apb peripheral that stores settings from the mcu. the dsp audio port block interfaces with the dsp for control and data communications. the digital filter block performs filter operations for voice band and audio band signal processing. the digital audio interface (dai) block communicates with the system simulator for fta or external bluetooth modules. adc df df df if sdm adc iir iir downlink uplink 8000k 6.5m 4160k 8k/16k 6.5m if 8k/16k 500k 6.5m if 260k 8k/16k 8k/16k voice dap figure 97 block diagram of digital circuits of the voice front-end to communicate with the external bluetooth module, the master-mode pcm interface and master-mode i2s/eiaj interface are supported. the clock of pcm interface is 256 khz while the frame sync is 8 khz. both long sync and short sync interfaces are supported. the pcm interface can transmit 16-bit stereo or 32-bit mono 8 khz sampling rate voice signal. figure 98 shows the timing diagram of the pcm interface. note that the serial data changes when the clock is rising and is latched when the clock is falling. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 642 of 1535 dai_clk dai_tx dai_rx bt_sync(s) bt_sync(l) 2 131 03028 24 27 25 26 22 23 29 2 131 03028 24 27 25 26 22 23 29 3 3 figure 98 timing diagram of bluetooth application 4.12.1.1 dai, pcm and edi pin sharing dai, pcm, and edi interfaces share the same pins. the pin mapping is listed in table 86 . pin name dai pcm edi dai_clk (output) dai_clk pcm_clk edi_clk dai_tx (output) dai_tx pcm_out edi_dat dai_rx (input) dai_rx pcm_in bt_sync (output) - pcm_sync edi_ws table 86 pin mapping of dai, pcm, and edi interfaces. beside the shared pins, the edi interface can also use other dedicated pins. with the dedicated pins, pcm and edi interfaces can operate at the same time. 4.12.2 register definitions mcu apb bus registers in voice front-end are listed as follows. notes : it can be control either by arm7 or arm9. for arm7, the base address vfe = 820f0000; for arm9, the base address vfe = 8003b000 note : all mcu read/write of vfe should be done after voice clock powers on. 0x820f0000 voice mcu control register vfe_vmcu_co n0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vafe on type r/w reset 0 mcu sets this register to start afe voice operation. a synchronous reset signal is issued, then periodical interrupts of 8-khz frequency are issued. clearing this register stops the interrupt generation. vafeon turn on audio front-end operations. 0 off free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 643 of 1535 1 on 0x820f000c voice analog-circuit control register 1 vfe_vmcu_co n1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vfe_water_ lv vidwa dsp_c lkrat e vmod e4k vafec lr_en vrsd on vdl_iirmode vul_iirmode vdldith_val vdldi th_o n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00 0 0 0 0 1 00 00 00 0 set this register current operation mode. suggested value is 0x0881. vfe_water_lv voice buffer water level to dma vidwa voice sdm idwa enable signal 0 close idwa 1 enable idwa dsp_clkrate dsp clock rate selection 0 104 mhz 1 130 mhz vmode4k dsp data mode selection 0 8k mode 1 4k mode vafeclr_en enable signal to reset voice downlink buffer or not while vafe is powered down. 0 no reset voice downlink buffer while vafe is powered down 1 reset voice downlink buffer while vafe is powered down vrsdon turn on the voice-band redundant signed digit function. 0 1-bit 2-level mode 1 2-bit 3-level mode vdl_iirmode voice downlink iir coefficients set selection 00 4k : 90hz, 8k: 180hz. 01 4k : 160hz, 8k: 320hz. 10 4k : 200hz, 8k: 400hz 11 4k : 320hz, 8k: 640hz vul_iirmode voice uplink iir coefficients set selection 00 4k : 90hz, 8k: 180hz. 01 4k : 160hz, 8k: 320hz. 10 4k : 200hz, 8k: 400hz 11 4k : 320hz, 8k: 640hz vdithval voice downlink dither scaling setting 00 1/4x 01 1/2x 10 1x 11 2x vdithon turn on the voice downlink dither function. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 644 of 1535 0 turn off 1 turn on 0x820f0010 afe voice mcu control register 2 afe_vmcu_co n2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vtx_c k_pha se vrx_c k_pha se dwl_out_ga in dwl_in_gain vsdm_gain type r/w r/w r/w r/w r/w reset 0 0 00 00 010000 set this register current operation mode. suggested value is 0x0010. vtx_ck_phase phase selection of clock to vbitx. 0 original 1 inverse vrx_ck_phase phase selection of clock to vbirx. 0 original 1 inverse dwl_out_gain gain setting at gain stage input. 00 1x 01 2x 10 4x 11 1x dwl_in_gain gain setting at 8k/16k input. 00 1x 01 1/2x 10 1/4x 11 1x vsdm_gain gain settings at voice sdm input. 000000 0/32 000001 1/32 000010 2/32 000011 3/32 100000 32/32 111111 63/32 0x820f0014 voice dai bluetooth control register vfe_vdb_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdaib t_clr _en vdaio n vbto n vbtsy nc vbtslen type r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 645 of 1535 reset 0 0 0 0 000 set this register for dai test mode and bluetooth application. daibt_clr_en enable signal to reset daibt buffer or not while vafe is powered down. 0 no reset daibt buffer while vafe is powered down 1 reset daibt buffer while vafe is powered down vdaion turn on the dai function. vbton turn on the bluetooth pcm function. vbtsync bluetooth pcm frame sync type 0 : short 1 : long vbtslen bluetooth pcm long frame sync length = vbtslen+1 0x820f0018 voice look-back mode control register vfe_vlb_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdsp csmo de vbyp assiir vdapi nmod e vintin mode vdeci nmod e type r/w r/w r/w r/w r/w reset 0 0 0 0 0 set this register for afe voice digital circuit configuration control. several loop back modes are implemented for test purposes. default values correspond to the normal function mode. vdspcsmode dsp cosim only, to align data. 0 normal mode 1 dsp cosim mode vbypassiir bypass iir filter 0 normal mode 1 bypass vdapinmode dsp audio port input mode control 0 normal mode 1 loop back mode vintinmode interpolator input mode control 0 normal mode 1 loop back mode vdecinmode decimator input mode control 0 normal mode 1 loop back mode 0x820f0030 voice dac sinewave generator vfe_dac_test bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name von mute amp_div freq_div type r/w r/w r/w r/w reset 0 0 111 0000_0001 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 646 of 1535 this register is only for analog design verification on audio/voice dacs. von makes voice dac output the test sine wave. 0 voice dac inputs are normal voice samples 1 voice dac inputs are sine waves mute mute switch. 0 turn on the sine wave output in this test mode. 1 mute the sine wave output. amp_div amplitude setting. 111 full scale 110 1/2 full scale 101 1/4 full scale 100 1/8 full scale freq_div frequency setting, 1 hot. 0000_0001 1x frequency 0000_0010 2x frequency 0000_0100 3x frequency 0000_1000 4x frequency 0001_0000 8x frequency 0010_0000 16x frequency 0100_0000 32x frequency 1000_0000 64x frequency 0x820f0100 vfe agc control re gister 0 vfe_vagc_con0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name minpgagain pgagain frflg ratkf lg satkf lg agco n type r/w r/w r/w r/w r/w r/w reset 001010 101000 0 1 1 1 this register sets the control signals for agc. agcon switch of the agc 0 off 1 on satkflg sample attack flag 0 off 1 on ratkflg rms attack flag 0 off 1 on frflg free release flag 0 off 1 on pgagain pga gain settings (from -20db to 43 db), it is also the maximum pga gain settings while agc is on. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 647 of 1535 000000 -20db 000001 -19db 111110 42db 111111 43db minpgagain minima pga gain settings (from -20 to 43 db). pga gain is always larger than minpgagain. 000000 -20db 000001 -19db 111110 42db 111111 43db 0x820f0104 vfe agc control register 1 vfe_vagc_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vagc _sel vagc _ctrl ecntrrlzs ecntrrlzf ecntratk type r/w r/w r/w r/w r/w reset 1 0 1100 1100 1000 this register sets the control signals for agc. vagc_sel selection of agc output. 0 bypass agc. 1 agc compensation on. vagc_ctrl selection the agc gain control master. 0 control by afe. 1 control by dsp. ecntratk attack counter, control attack speed.(unit: n samples@52khz ). attach will be triggered if n samples amplitude exceed attack threshold (enthdatk) 0 always attack, please don?t set to this values. 1~15 n=1~15 ecntrrlzf fast release counter, control fast release speed.(unit: n samples@52khz ). release will be triggered if n samples amplitude lower than slow release threshold (enthdrls) 0 1 1 3 2 7 3 15 4 31 5 63 6 127 7 255 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 648 of 1535 8 511 9 1023 10 2043 11 4095 12 8191 13 16383 14 32767 15 65535 ecntrrlzs slow release counter, control slow release speed.(unit: n samples@52khz ). release will be triggered if n samples amplitude lower than hysteresis threshold (enthdhys) 0 1 1 3 2 7 3 15 4 31 5 63 6 127 7 255 8 511 9 1023 10 2043 11 4095 12 8191 13 16383 14 32767 15 65535 0x820f0108 vfe agc control re gister 2 vfe_vagc_con2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ermsfbattf ermsfbattr ermsfbf ermsfbr type r/w r/w r/w r/w reset 1010 0100 1011 0101 this register sets the control signals for agc. ermsfbr rms rising factor . the larger the number; the slower the signal energy estimation. 0 1x rms power estimation. 1 2x rms power estimation. 2 4x rms power estimation. 3 8x rms power estimation. 14 16384x rms power estimation. 15 32768x rms power estimation. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 649 of 1535 ermsfbf rms falling factor. the larger the number; the slower the signal energy estimation. 0 1x rms power estimation. 1 2x rms power estimation. 2 4x rms power estimation. 3 8x rms power estimation. 14 16384x rms power estimation. 15 32768x rms power estimation. ermsfbattr rms for attack rising factor. the larger the number; the slower the signal energy estimation. 0 1x rms power estimation. 1 2x rms power estimation. 2 4x rms power estimation. 3 8x rms power estimation. 14 16384x rms power estimation. 15 32768x rms power estimation. ermsfbattf rms for attack falling factor. the larger the number; the slower the signal energy estimation. 0 1x rms power estimation. 1 2x rms power estimation. 2 4x rms power estimation. 3 8x rms power estimation. 14 16384x rms power estimation. 15 32768x rms power estimation. 0x820f010c vfe agc control register 3 vfe_vagc_con3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name egaincomp_css egaincomp_csm egaincomp_csf egaincomp_fc_th d egaincomp_ lower egaincomp_ upper type r/w r/w r/w r/w r/w r/w reset 001 011 011 101 01 01 this register sets the control signals for agc. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 650 of 1535 figure 99 gain compensation procedures. egaincomp_upper gain compensation upper threshold, 32768 = 0db ( figure 99 gain compensation procedures.) 00 33095 01 33423 10 33751 11 34078 egaincomp_lower gain compensation lower threshold, 32768 = 0db ( figure 99 gain compensation procedures.) 00 32440 01 32112 10 31784 11 31457 egaincomp_fc_thd gain compensation convergence threshold ( figure 99 gain compensation procedures.). 000 34406 001 36044 010 37683 011 39321 100 40960 101 42598 110 44236 111 45875 egaincomp_fc_csf gain compensation fast converge speed. (while compensation gain is 0.3db far from 32768, the convergence speed is fast) 000 31948 (8x) 001 31129 (7x) 010 30310 (6x) 011 29491 (5x) 100 28672 (4x) 101 27852 (3x) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 651 of 1535 110 27033 (2x) 111 26214 (1x) egaincomp_fc_csm gain compensation converge speed middle. (while compensation gain is 0.15db ~ 0.3db from 32768, the convergence speed is middle) 000 32686 (8x) 001 32604 (7x) 010 32552 (6x) 011 32440 (5x) 100 32358 (4x) 101 32276 (3x) 110 32194 (2x) 111 32112 (1x) egaincomp_fc_css gain compensation converge speed slow. (while compensation gain is inside 0.15db from 32768, the convergence speed is slow) 000 32751 (8x) 001 32735 (7x) 010 32718 (6x) 011 32702 (5x) 100 32686 (4x) 101 32669 (3x) 110 32653 (2x) 111 32636 (1x) 0x820f0110 vfe agc control re gister 4 vfe_vagc_con4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enthdatkrms enthdatk esrelwinwidth1 type r/w r/w r/w reset 000100 000001 1000 this register sets the control signals for agc. esrelwinwidth1 speech release window width for strong vad 0 10 @ 52khz samples 1 20 @ 52khz samples 2 40 @ 52khz samples 3 80 @ 52khz samples 4 160 @ 52khz samples 5 325 @ 52khz samples 6 650 @ 52khz samples 7 1300 @ 52khz samples 8 2600 @ 52khz samples 9 5200 @ 52khz samples 10 10000 @ 52khz samples 11 15000 @ 52khz samples 12 20000 @ 52khz samples free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 652 of 1535 13 25000 @ 52khz samples 14 30000 @ 52khz samples 15 32767 @ 52khz samples enthdatk attack threshold [0~63] is map to [-63~0]db fs enthdatkrms rms attack threshold [0~63] is map to [-63~0]db fs 0x820f0114 vfe agc control re gister 5 vfe_vagc_con5 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enthdrls enthdhys esrelwinwidth2 type r/w r/w r/w reset 001101 000111 1000 this register sets the control signals for agc. esrelwinwidth2 speech release window width for weak vad 0 10 @ 52khz samples 1 20 @ 52khz samples 2 40 @ 52khz samples 3 80 @ 52khz samples 4 160 @ 52khz samples 5 325 @ 52khz samples 6 650 @ 52khz samples 7 1300 @ 52khz samples 8 2600 @ 52khz samples 9 5200 @ 52khz samples 10 10000 @ 52khz samples 11 15000 @ 52khz samples 12 20000 @ 52khz samples 13 25000 @ 52khz samples 14 30000 @ 52khz samples 15 32767 @ 52khz samples enthdhys hysteresis threshold [0~63] is map to [-63~0]db fs enthdrls slow release threshold [0~63] is map to [-63~0]db fs 0x820f0118 vfe agc control re gister 6 vfe_vagc_con6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name epattlimiter pattreld natkf lg pattr elflg enthdnoz type r/w r/w r/w r/w r/w reset 0100 0000 1 1 111101 this register sets the control signals for agc. enthdnoz idle threshold free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 653 of 1535 [0~63] is map to [-63~0]db fs pattrelflg post attack/release flag 0 off 1 on natkflg noise adaptive attenuation enable attack flag 0 off 1 on pattreld post attack/release latency 0~15 is map to 0~15 sample @260khz sampling rate epattlimiter post attack limiter [0,15] is map to [0,-7.5dbfs], the spacing is 0.5db 0x820f00f0 vfe dma read data register vfe_data bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vfe_data[31:16] type r/w reset 0000_0000_0000_0000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vfe_data[15:0] type r/w reset 0000_0000_0000_0000 virtual fifo for arm9 to access voice data from dma. vfe_data data received from voice a/d. 4.12.3 dsp register definitions 0x640 voice uplink data register 0 vfe_vul_dat0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vul_dat0 type ro reset 0 voice band uplink transmission data register 0. the content of this register is updated by uplink digital filter outputs. this register is read by dsp in an 8k isr. 0x641 voice uplink data register 1 vfe_vul_dat1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vul_dat1 type ro reset 0 voice band uplink transmission data register 1. the content of this register is updated by uplink digital filter outputs. this register is read by dsp in an 8k isr if vbypassiir of afe_lb_con is set. 0x642 voice downlink data register 0 vfe_vdl_dat0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdl_dat0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 654 of 1535 type wo reset 0 voice band downlink receiving data register 0. this register is written by dsp in an 8k isr. the content of this register is used as downlink digital filter inputs. 0x643 voice downlink data register 1 vfe_vdl_dat1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdl_dat1 type wo reset 0 voice band downlink receiving data register 1. this register is written by dsp in an 8k isr if vbypassiir of afe_vlb_con is set. the content of this register is used as downlink digital filter inputs. 0x644 voice dai bluetooth transmission data register 0 vfe_vdbtx_d at0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdbtx_dat0 type wo reset 0 dai bluetooth transmission data register 0. this register is written by dsp in an 8k isr if the bluetooth function is turned on. the content of this register is shifted out to the bluetooth interface. 0x645 voice dai bluetooth transmission data register 1 vfe_vdbtx_d at1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdbtx_dat 1 type wo reset 0 dai bluetooth transmission data register 1. this register is written by dsp in an 8k isr if the corresponding dai test is set or the bluetooth function is turned on. the content of this register is shifted out to the ss or bluetooth interface. 0x646 voice dai bluetooth receiving data register 0 vfe_vdbrx_d at0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdbrx_dat 0 type ro reset 0 dai bluetooth receiving data register 0. this register is read by dsp in an 8k isr if the bluetooth function is turned on. the content of this register is shifted in from the bluetooth interface. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 655 of 1535 0x647 voice dai bluetooth receiving data register 1 vfe_vdbrx_d at1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdbrx_dat 1 type ro reset 0 dai bluetooth receiving data register 1. this register is read by dsp in an 8k isr if the corresponding dai test is set or the bluetooth function is turned on. the content of this register is shifted in from the ss or bluetooth module. 0x648 voice dai bluetooth control register vfe_vdsp_co n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdsp_ rdy type r/w reset 0 dsp sets this register to inform hardware that it is ready for data transmission. in dai test modes, dsp starts a test by setting vdsp_rdy when speech samples are required or are ready. in normal mode, the dsp asserts this bit to ungate the downlink path data. otherwise, the downlink data remains zero. vdsp_rdy ready indication to start the voice band data path. 0 dsp data is not ready. 1 dsp data is ready. 0x64a afe agc dsp control aef_vagc_vad bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name nadpatt_dbgain ngat eope n vad2 vad type r/w r/w r/w r/w reset 000000 0 0 0 this register is for dsp to read/write the parameter of agc. vad strong vad flag 0 off 1 on vad2 weak vad flag 0 off 1 on ngateopen noise gate flag 0 noise gate close 1 noise gate open nadpatt_dbgain noise adaptive attenuation db gain free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 656 of 1535 [0,63] 0~63db 0x64b afe agc dsp control aef_vagc_cntr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cntr_rel_ff tone flg type r/w r/w reset 000000000000000 0 this register is for dsp to read/write the parameter of agc. toneflg tone flag 0 off 1 on cntr_rel_ff proceed very fast release if n samples value smaller than the fast release threshold 0~32767 n=0~32767 @ 52khz sampling rate. 0x64c afe agc dsp cont rol1 aef_vagc_cntr1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ncntrrlz ncntratk type ro ro reset 0000_0000 0000_0000 this register is for dsp to read the parameter of agc. ncntrrlz release counter (in unit of 52khz/256 sampling rate). ncntratk attack counter (in unit of 52khz/16 sampling rate). 0x64d afe agc dsp control aef_vagc_stete bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sstate fgaindb type ro ro reset 00 000000 this register is for dsp to read the parameter of agc. fgaindb current pga gain (from 0 to 63 db). sstate current agc state. 0x64e afe agc dsp control aef_vagc_rm s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sigrmsatt sigrms type ro ro reset 00000000 00000000 this register is for dsp to read the parameter of agc. sigrms rms of signal sigrmsatt rms of signal for attack usage free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 657 of 1535 0x651 vfe agc dsp gain vfe_vagc_gain bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vagc_gain type r/w reset 000000 agc gain setting by agc. it is only validate while vagc_ctrl is set to 1. 4.12.4 programming guide several cases ? including speech call, voice memo record, voice memo playback, melody playback and dai tests ? requires that partial or the whole audio front-end be turned on. the following are the recommended voice band path programming procedures to turn on voice front-end: 1. mcu programs the vfe_dai_con, vfe_lb_con, vfe_vag_con, vfe_vac_con0, vfe_vac_con1 and vfe_vapdn_con registers for specific operation modes. refer also to the analog chip interface specification. 2. mcu clears the vafe bit of the pdn_con2 register to ungate the clock for the voice band path. refer to the software power down control specification. 3. mcu sets vfe_vmcu_con to start operation of the voice band path. the following are the recommended voice band path programming procedures to turn off voice front-end: 1. mcu programs vfe_vapdn_con to power down the voice band path analog blocks. 2. mcu clears vfe_vmcu_con to stop operation of the voice band path. 3. mcu sets vfe bit of pdn_con2 register to gate the clock for the voice band path. note : all mcu read/write of vfe should be done after voice clock powers on. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 658 of 1535 5 multimedia subsystem MT6516 is a highly integrated multimedia-rich application processor offering an ultra low cost and high performance multimedia solution for smartphone. with MT6516, demanding multimedia functions such as recording and playing dvd quality video, video streaming, 5m pixels camera image capturing, 3d gaming, and high resolution true color lcd displaying can be easily implemented without additional multimedia companion chips. moreover, a high performance video dsp provides extended computing power to support a variety of video codec format and unpredictable multimedia application in the future. in MT6516, high performance hardware-based multimedia functions enable high quality and real-time display, graphics, image, and video features for multimedia-rich smartphone display ? lcd interface support host interface, rgb interface, and mipi dsi high speed display serial interface ? support up to 24-bit rgb888 true color panel ? dual panel (main and sub) support ? display color processing enhancement functions: gamma correction, color correction matrix, dithering ? image post-processing ? yuv/rgb color space conversion ? image rotation 90, 180, 270 ? tv out graphics ? 3d graphics, opengl es 1.1 and d3d mobiles, 3m triangle/sec, 32mpixel/sec, true color and vga resolution ? 2d graphics hw acceleration ? hardware png decoder image ? built-in image signal processing supporting 5m pixel camera sensor ? hardwired real-time image processing up to 5m pixels ? support yuv/rgb/bayer image input format ? 12-bit parallel interface support ? 2 channel mipi csi-2 high speed camera serial interface support ? non-circular based shading compensation ? auto defect and defect table compensation ? gradation enhancement ? noise reduction ? image stabilization ? rich image processing function and 32 special effect free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 659 of 1535 ? mechanical shutter support ? xenon flash support ? hardware jpeg encode/decode ? up to 5m pixels ? baseline yuv422/yuv420/yuv411 and grayscale format ? exif/jfif ? scaler support arbitrary size scaling up/down from 1/2048x to 64x with high quality bi-cubic algorithm video ? h.264 video decoder d1 30fps ? mpeg4/h.263 video encoder d1 30fps ? mpeg4/h.263 video decoder d1 30fps ? vc-1 video decoder cif 30fps (by dsp) ? realvideo decoder cif 30fps (by dsp) audio ? hardware wavetable coprocessor support at least 128 polyphony stereo real-time synthesis for midi ? sample rate conversion up to 48khz ? programmable low-pass iir filter that can eliminate noise from waveform re-sampling ? multiple data decompression methods to reduce wavetable size ? proprietary ?fractional looping? technology ? i2s interface ? audio encode: amr-nb ? audio decode: mp3, amr, wb-amr+, wma, wma+, bsac, aac, aac+, MT6516 multimedia architecture is shown in figure 1-1. it contains multimedia accelerators to enhance graphics, display, video, and camera features. high performance graphics bus connecting to 32-bit ddr memory provides very high bandwidth throughput. hardware multimedia data paths and image dma as shown in figure 1-2 are designed to make data transfer more efficient. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 660 of 1535 multi-media system 96kb sysram (96kb) image post proc 6? crz image dma0 2d engine png decode prz drz tv ctrl dsi csi host i/f rgb i/f 12-bit i/f 18 10 2 m m m mm m m m m m tv encode lcd ctrl image signal proc 6? camera sensor lcd nand 30 4 spi wifi gmc1 lcd tv out waveta ble src m m moto spi m mpeg- 4/jpeg codec 3d engine h.264 decode 144kb sysram (144kb) gmc2 mobile tv image_ dma1 mp4_de blk m to emi from mcu/dma bus fig 1-1 MT6516 multimedia architecture isp crz 7jefp &odpefs 8%." 701 'sbnf #vggfs 3fd 'sbnf #vggfs 7jefp %fdpefs 3%." rotator_0 13;ps$3; :67 3(#@ lcd 570vu #vggfsy -$% 'sbnf #vggfs -$% 'sbnf #vggfs %1* #vggfsy %fcmpdljoh 'jmufs ibw2 :67 3(#@ ipp1 +1&( 'jmf #vggfs prz ibw2 ovl *dpo #vggfs +1&( &odpefs +1&( %." :67 3(#@ drz ibw1 5ivncobjm #vggfs #.1ps 1jyfm #vggfs ibr1 3(# :67@ +1&( 'jmf #vggfs +1&( %fdpefs crz .1&($pefd ps )%fdpefs 570vu &yufsobm.fnpsz 570vu 570vu rotator_1 :67 3(#@ rotator_1 ipp1 #mpdlcbtfe $powfstjpo rotator_3 3(# :67@ ipp1 prz ipp2 ipp2 ibw1 *35 .0 *35 .0 07- .0 07- .0 dpi fig 1-2 MT6516 multimedia datapath free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 661 of 1535 5.1 2d acceleration 5.1.1 2d engine 5.1.1.1 general description to enhance mmi display and gaming experiences, a 2d acceleration engine is implemented. it supports argb8888, rgb888, argb4444, rgb565 and 8-bpp color modes. main features are listed as follows: z rectangle fill with color gradient. z bitblt: multi-bitblt without transform, 7 rotate, mirror (transparent) bitblt z alpha blending z rop3, rop4 z font caching: normal font, italic font z polygon fill with single color or image pattern z 1/2/4/8 bit index color bitblt z scaled bitblt z specific output color replacement mcu can program 2d engine registers via apb. however, mcu has to make sure that the 2d engine is not busy before any write to 2d engine registers occurs. an interrupt scheme is also provided for more flexibility. a command parser is implemented for further offloading of mcu. the command queue can be randomly assigned in the system memory, with a maximum depth of 2047 commands. if the command queue is enabled, mcu has to check if the command queue has free space before writing to the command queue. command queue parser will consume command queue entries upon 2d engine requests. figure 100 shows the command queue and 2d engine block diagram. please refer to the graphic command queue functional specification for more details. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 662 of 1535 2d engine command queue apb slave command parser dst memory read/write control src memory read control graphic memory interface figure 100 the command queue and 2d engine block diagram. 5.1.1.2 features introduction 5.1.1.2.1 2d coordinate the coordinates in the 2d engine are represented as 12-bit signed integers. the negative part is clipped during rendering. the maximum resolution can achieve 2047x2047 pixels. the programmed base address is mapped to the origin of the picture, which is illustrated in figure 101 . (0,0) dst_base_addr x y figure 101 the coordinate of the 2d engine. 5.1.1.2.2 color format the 2d engine supports the color format of 8bpp, rgb565, rgb888, argb4444, and argb 8888. the color formats of source and destination can be specified separately. note that when using the 8bpp format, free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 663 of 1535 the source and destination color formats have to be the same, since table-lookup of color palette is not provided in 2d engine. graphic modes of bitblt, bitblt with alpha blending, and bitblt with binary rop require color format setting for both source and destination. for other graphic modes, only destination color format needs to be specified. the possible settings are listed as table 87table 88 . bitblt (copy, rop) source color format destination color format 8bpp 8bpp rgb565 rgb565 rgb888 rgb565 rgb888 rgb888 argb4444 argb4444 argb8888 argb4444 argb8888 argb8888 table 87 source and destination color format setting for bitblt. bitblt with alpha blending source color format destination color format 8bpp 8bpp rgb565 rgb565 rgb888 rgb565 rgb888 rgb888 rgb565 argb4444 rgb888 rgb565 argb8888 rgb888 table 88 source and destination color format setting for alpha blending. when source image is used, the source key function could be enabled or disabled. when enabled, the source color key is in the same format of source color. be aware that the source key is still effective for alpha blending mode. if the color format of source and destination is the same, no color conversion is necessary. but if source and destination have different color formats, the color values are converted between different formats as followed. if the source color format has less bit number than the destination, the source color value is shifted left to align with the most significant bit of the destination color. and the lower significant bits of destination color are filled with the most significant bits of source color. for example, to convert from argb4444 (a3a2a1a0r3r2r1r0g3g2g1g0b3b2b1b0) to argb8888, the value a3a2a1a0 a3a2a1a0r3r2r1r0 r3r2r1r0g3g2g1g0 g3g2g1g0b3b2b1b0 b3b2b1b0 is gotten. the conversion between rgb565 source and free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 664 of 1535 rgb888 has another formula. a conversion factor is defined as followed: (2^d-1)/(2^s-1) in which d is the destination color format?s bit number and s is the source?s one. the destination color value is acquired by multiplying the source color value with the conversion factor and rounding to the nearest integer number. you can use wm_cpy_x control bit to select with conversion formula used when bitblt. if the source color format has more bit number than the destination, the destination color value is acquired with just truncating the lower significant bits of the source color. for example, an argb8888 color value a7a6a5a4 a3a2a1a0r7r6r5r4r3r2r1r0g7g6g5g4g3g2g1g0b7b6b5b4b3b2b1b0 becomes r7r6r5r4r3g7g6g5g4g3g2b7b6b5b4b3 if the destination color format is rgb565. 5.1.1.2.3 clipping window the setting for clipping window is effective for all the 2d graphics. a pair of minimum and maximum boundary is applied on destination side. the portion outside the clipping window will not be drawn to the destination, but the pixels on the boundary will be kept. the clipping operation is illustrated in figure 102 . (0,0) dst_base_addr g2d_clp_min g2d_clp_max figure 102 the clipping operation of the 2d engine. to get more efficiency of bitblt, or font drawing, the source clipping can be enabled to avoid that the additional pixels of source, destination, pattern, or mask are fetched but are not written back because they are outside the destination clipping window. the setup procedure is as followed. if (x_inc) { src_x = src_x; dst_x = dst_x; clp_diff_min_x = clp_min_x ? dst_x; if (clp_diff_min_x > 0) { src_clp_x = src_x + (clp_diff_min_x % src_w); dst_clp_x = clp_min_x; } else { clp_diff_min_x = 0; src_clp_x = src_x; dst_clp_x = dst_x; } } else { src_x = src_x + src_w -1; dst_x = dst_x + dst_w ? 1; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 665 of 1535 clp_diff_min_x = dst_x ? clp_max_x; if (clp_diff_min_x > 0) { src_clp_x = src_x ? (clp_diff_min_x % src_w); dst_clp_x = clp_max_x; } else { clp_diff_min_x = 0; src_clp_x = src_x; dst_clp_x = dst_x; } } dst_clp_w = dst_w ? clp_diff_min_x; dst_clp_w = (dst_clp_w <= 0)? 0 : dst_clp_w; you can replace the x?s and w?s above with y?s and h?s respectively to get relative parameters about y- coordinate. and if the pattern or mask is used, pat_clp_xy or msk_clp_xy is derived in the same way. the source clipping is enabled with src_clp_en. 5.1.1.2.4 bitblt operation the bitblt function copies the pixels from source picture to destination. to be more flexible, 4 copy directions and 7 kinds of rotations are provided when doing bitblt operation. figure 103 illustrates the bitblt operation and required settings. s src_base_addr (src_x,src_y) d dst_base_addr (dst_x,dst_y) src_w src_h src_x_pitch dst_x_pitch figure 103 the clipping operation of the 2d engine. note that the size of source and destination blocks can be different. if the source block is larger than destination block, the size of destination block is used instead of the source size. when source block size is smaller than destination block size, the pattern of source block is repeated horizontally and vertically in the destination block, which is illustrated as figure 104 below. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 666 of 1535 source destination figure 104 the bitblt operation when destination size > source size. 5.1.1.2.4.1 copy direction when the source block and destination blocks are on the same picture, they may be overlapped by each other. to prevent error from occurring, 4 directions for bitblt can be programmed. however, the copy direction shall not be enabled when doing rotation, or it will produce unwanted results. the 4 kinds of copy direction are shown in figure 105 . d d s s d s d s figure 105 the 4 directions of bitblt operation. 5.1.1.2.4.2 rotation to facilitate bitblt operation, 7 kinds of rotation can be set at the same time. the rotation operation is illustrated as figure 106 . here the rotation is done on the destination side, while the read sequence of pixels in source block is fixed. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 667 of 1535 8).270 degree rotation + vertical flip d s d (src_x,src_y) (dst_x,dst_y) 1).no rotation d 2).180 degree rotation d 3).horizontal flip d 4).vertical flip 5).90 degree rotation 6).270 degree rotation d 7).90 degree rotation + vertical flip d d figure 106 the rotations of bitblt operation. 5.1.1.2.5 bitblt with alpha blending similar to simple bitblt operation, alpha blending function is provided as well. the pixels in source block are blended onto destination block. blending is performed according the formula listed below: cd)/255 * alpha) - (255 cs * (alpha c + = , where cs is the source color, cd is the destination color, and alpha is an unsigned integer range from 0 to 255. the alpha value programmed into the 2d control registers is called constant alpha. when no alpha channel exists, the constant alpha is used to calculate blended color. if the alpha channel exists ( in argb color mode), the per-pixel alpha is used for blending operation instead of constant alpha. in addition, the setting of copy directions and rotations are also effective for alpha blending mode. also, the size and color format of source block can be different from destination. the alpha blending is approximated as followed in 2d accelerator: x = (alpha * cs) + (255 ? alpha) * cd c = ((x + 128 ) >> 8 + (x + 128)) >> 8 the additional round in inner shift operation (that is, the red 128) can be enabled with wm_alp_rnd. and wm_clr_x can control which color format being operated in the alpha blending pipeline. when wm_clr_x is equal to ?1?, all operands are converted to destination color format before the alpha blending operation is executed. otherwise, all operands are converted to argb8888 color format before the alpha blending operation. and the results are converted to destination color format after the alpha blending operation. 5.1.1.2.6 bitblt with rop the rop (raster operation) is another block-wise functional mode. here the 2d engine provides a set of rop2/rop3/rop4. the result of rop3 (ternary rop) is calculated by the bitwise logical operation of pixels of source, destination and pattern. the pattern is a maximum 64x64 block which could be programmed by g2d_pat_base. the rop code has 256 different combinations, which is listed in the definition of 2d control registers --- g2d_rop_code. please see sec.1.1.1.3 for detail descriptions. note that disable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 668 of 1535 rop3_en in rop mode can produce rop2 (binary rop) result. for rop4, the result is one the calculated value of two rop3 codes. the selection of rop3 code depends on the value of the mask block which starting address is g2d_msk_base. similar with other block-wise functions, the copy directions and rotations are also applicable in rop mode. the size and color format of source and destination do not need to be the same. 5.1.1.2.7 index color bitblt 1/2/4/8 bit index color bitblt is supported by 2d engine. the pixels in source block could be set as index color with 1, 2, 4, or 8 bits per pixel when doing bitblt. a lookup table is used to find the 32bits argb color of the source pixel. the starting address of the index color table can be specified by setting g2d_buf_sta_addr_0. 5.1.1.2.8 scaled bitblt the scaling operation is supported by 2d engine. simple repeat/drop algorithm is implemented for color key preservation. maximum 63x scale up/down could be used with other bitblt function, like alpha blending or copy direction selection. 5.1.1.2.9 rectangle fill with color gradient rectangle fill mode provides the configurations for color gradient for both x-direction and y-direction. each of the color gradient of component a, r, g, b is represented by 9.16 signed fixed point number. in order to prevent color crossing the boundary of 0 and 255, it is clipped to 0 and 255 when performing gradient fill. when the color gradient is disabled, the rectangle is filled by one color. an example of gradient fill is shown in figure 107 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 669 of 1535 start_clr x_gradient y_gradient figure 107 rectangle gradient fill. 5.1.1.2.10 font drawing the 2d engine helps to render fonts stored in one-bit-per-pixel format. it expends the zero bits to background color and expands one bits to foreground color. the background color can be set as transparent. the font drawing can be programmed as tilt, when given each line?s tilt value. the start bit of font drawing can be non-byte aligned to save memory usage for font caching. in addition, the rotations can be performed at the same time when drawing fonts. 5.1.1.2.11 polygon fill in MT6516, 2d engine supports the function of polygon fill with its edges specified in memory. the maximum number of edge is 2047, which will occupy 32kb memory space (16 bytes per edge) during polygon fill processing. software need to indicate the starting address of input edge list by setting g2d_buf_sta_addr_0 and allocate another memory space for the polygon fill processing by setting g2d_buf_sta_addr_1. it?s noted that filling a polygon with a list of cross edges will cause an un-expected result. dividing this kind of polygon into several ones without cross edges is recommended. polygon fill with image is also supported. the maximum image pattern size is 64x64 which is needed to be put in memory starting from buf_sta_addr_2. figure 108 polygon fill. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 670 of 1535 figure 109 cross edges. divide into 1 - 5 triangles is recommended. figure 110 polygon fill with image pattern. 5.1.1.2.12 g2d engine reset when the g2d function is abnormal or the current executed g2d operation needs to be interrupted for some reason, the register rst in g2d_com_con could be used to reset the internal state machine in g2d engine. the setting of g2d configuration registers is unchanged. but at the same time when g2d engine is being reset, the read or write memory access transaction might not complete yet. this may cause g2d engine works abnormally. it is suggested that the tidle status bit in g2d_com_sta needs to be checked before g2d engine is reset. that is, the completeness of r/w memory access transaction needs to be confirmed, then, the current executed g2d operation could be stopped. 5.1.1.3 register definitions table 1 the ap ccif register mapping summarizes the 2d engine register mapping on apb and through command queue. the base address of 2d engine is 80081000h. apb address cmq mapped address register function acronym g2d+0100h 100h 2d engine fire mode control register fmode_con 102h reserved g2d+0104h 104h 2d engine sub-mode control lower register smode_con_l 106h 2d engine sub-mode control higher register smode_con_h g2d+0108h 108h 2d engine common control register com_con 10ah reserved g2d+0110h 110h 2d engine status register sta 112h reserved g2d+0200h 200h source base address lower hword register src_base_l 202h source base address higher hword register src_base_h g2d+0204h 204h source pitch register src_pitch 206h reserved g2d+0208h 208h source y coordinate register src_y free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 671 of 1535 20ah source x coordinate register src_x g2d+020ch 20ch source height register src_h 20eh source width register src_w g2d+0210h 210h source color key lower hword register src_key_l 212h source color key higher hword register src_key_h g2d+0214h 214h destination avoid color lower hword register dst_avo_clr_l 216h destination avoid color higher hword register dst_avo_clr_h g2d+0218h 218h destination replacement color lower hword register dst_rep_clr_l 21ah destination replacement color higher hword register dst_rep_clr_h g2d+021ch 21ch source y coordinate after source clipping register src_clp_y 21eh source x coordinate after source clipping register src_clp_x g2d+0220h 220h destination height after source clipping register dst_clp_h 222h destination width after source clipping register dst_clp_w g2d+0300h 300h destination base address lower hword register dst_base_l 302h destination base address higher hword register dst_base_h g2d+0304h 304h destination pitch register dst_pitch 306h reserved g2d+0308h 308h destination y coordinate register 0 dst_y0 30ah destination x coordinate register 0 dst_x0 g2d+030ch 30ch destination y coordinate register 1 dst_y1 30eh destination x coordinate register 1 dst_x1 g2d+0310h 310h destination y coordinate register 2 dst_y2 312h destination x coordinate register 2 dst_x2 g2d+0318h 318h destination height register dst_h 31ah destination width register dst_w g2d+031ch 31ch destination y coordinate after source clipping register dst_clp_y 31eh destination x coordinate after source clipping register dst_clp_x g2d+0320h 320h pattern base address lower hword register pat_base_l 322h pattern base address higher hword register pat_base_h g2d+0324h 324h pattern pitch register pat_pitch 326h reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 672 of 1535 g2d+0328h 328h pattern width and high register pat_wh 32ah pattern x and y coordinate register pat_xy g2d+032ch 32ch pattern offset of x/y coordinate register pat_xyofs 32eh pattern xy coordinate after source clipping register pat_clp_xy g2d+0330h 330h mask base address lower hword register msk_base_l 332h mask base address high hword register msk_base_h g2d+0334h 334h mask picth register msk_picth 336h reserved g2d+0338h 338h mask y coordinate register msk_y 33ah mask x coordinate register msk_x g2d+033ch 33ch mask height register msk_h 33eh mask width register msk_w g2d+0340h 340h resize down scale register rsz_d 342h resize up scale register rsz_u g2d+0344h 344h rop code0 and code1 register rop_code 346h reserved g2d_348h 348h mask y coordinate after source clipping register msk_clp_y 34ah mask x coordinate after source clipping register msk_clp_x g2d+400h 400h foreground color lower hword register fgclr_l 402h foreground color high hword register fgclr_h g2d+404h 404h background color lower hword register bgclr_l 406h background color high hword register bgclr_h g2d+408h 408h clipping minimum y coordinate register clp_min_y 40ah clipping minimum x coordinate register clp_min_x g2d+40ch 40ch clipping maximum y coordinate register clp_max_y 40eh clipping maximum x coordinate register clp_max_x g2d+410h 410h rectangle color gradient of alpha component x lower hword register alpgr_x_l 412h rectangle color gradient of alpha component x higher hword register alpgr_x_h g2d+414h 414h rectangle color gradient of red component x lower hword register redgr_x_l 416h rectangle color gradient of red component x higher hword register redgr_x_h g2d+418h 418h rectangle color gradient of green component x lower hword register greengr_x_l 41ah rectangle color gradient of green component greengr_x_h free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 673 of 1535 x higher hword register g2d+41ch 41ch rectangle color gradient of blue component x lower hword register bluegr_x_l 41eh rectangle color gradient of blue component x higher hword register bluegr_x_h g2d+420h 420h rectangle color gradient of alpha component y lower hword register alpgr_y_l 422h rectangle color gradient of alpha component y higher hword register alpgr_y_h g2d+424h 424h rectangle color gradient of red component y lower hword register redgr_y_l 426h rectangle color gradient of red component y higher hword register redgr_y_h g2d+428h 428h rectangle color gradient of green component y lower hword register greengr_y_l 42ah rectangle color gradient of green component y higher hword register greengr_y_h g2d+42ch 42ch rectangle color gradient of blue component y lower hword register bluegr_y_l 42eh rectangle color gradient of blue component y higher hword register bluegr_y_h g2d+430h 430h buffer 0 start address lower hword register buf_sta_addr_ 0_l 432h buffer 0 start address higher hword register buf_sta_addr_ 0_h g2d+434h 434h buffer 1 start address lower hword register buf_sta_addr_ 1_l 436h buffer 1 start address higher hword register buf_sta_addr_ 1_h g2d+0700h ~ g2d+071fh 700h ~ 71fh tilt_0300 ~ tilt_1f1c table 89 the 2d engine register mapping. there are several function modes in 2d graphics engine. some registers are shared between different them. table 90 summarizes the settings under different function modes. apb address cmq addres s rectangle fill bitblt operations font caching polygon fill g2d+0200h 200h src_base src_base g2d+0204h 204h src_pitch g2d+0208h 208h src_xy g2d+020ch 20ch src_size g2d+0210h 210h src_key src_key free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 674 of 1535 g2d+214h 214h dst_avo_clr dst_avo_clr dst_avo_clr dst_avo_clr g2d+218h 218h dst_rep_clr dst_rep_clr dst_rep_clr dst_rep_clr g2d+0300h 300h dst_base dst_base dst_base dst_base g2d+0304h 304h dst_pitch dst_pitch dst_pitch dst_pitch g2d+0308h 308h dst_xy dst_xy dst_xy g2d+030ch 30ch g2d+0310h 310h g2d+0318h 318h dst_size dst_size dst_size g2d+320h 320h pat_base pat_base g2d+324h 324h pat_pitch pat_pitch g2d+328h 328h pat_xywh pat_xywh g2d+32ch 32ch pat_xyofs pat_xyofs g2d+330h 330h msk_base g2d+334h 334h msk_pitch g2d+338h 338h msk_xy g2d+33ch 33ch msk_size g2d+340h 340h rsz_ud g2d+344h 344h rop_code g2d+0400h 400h start_clr fgclr g2d+0404h 404h dst_key bgclr g2d+0408h 408h clp_min clp_min clp_min clp_min g2d+040ch 40ch clp_max clp_max clp_max clp_max g2d+0410h 410h alpgd_x g2d+0414h 414h red_gd_x g2d+0418h 418h green_gd_x g2d+041ch 41ch blue_gd_x g2d+0420h 420h alpgd_y g2d+0424h 424h red_gd_y g2d+0428h 428h green_gd_y g2d+042ch 42ch blue_gd_y g2d+0430h 430h buf_addr_0 edge_addr g2d+0434h 434h buf_addr_1 sort_addr g2d+0700h ~ g2d+071fh 700h ~ 71fh tilt_0300 ~ tilt_1f1c tilt_0300 ~ tilt_1f1c tilt_0300 ~ tilt_1f1c table 90 2d engine common registers below shows common control registers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 675 of 1535 g2d+0100h graphic 2d engine fire mode control register g2d_fmode_c on bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pat_clr_mode src_clr_mode dst_clr_mode g2d_eng_mode type r/w r/w r/w r/w reset 000 000 000 0000 write this register will fire the 2d engine according to the clr_mode and eng_mode field. pat_clr_mode pattern color mode 000 8-bpp, lut disabled 001 16-bpp, rgb 565 format 010 32-bpp, argb 8888 format 011 24-bpp, rgb 888 format 101 16-bpp, argb 4444 format src_clr_mode source color mode 000 8-bpp, lut disabled 001 16-bpp, rgb 565 format 010 32-bpp, argb 8888 format 011 24-bpp, rgb 888 format 101 16-bpp, argb 4444 format others reserved dst_clr_mode destination color mode 000 8-bpp, lut disabled 001 16-bpp, rgb 565 format 010 32-bpp, argb 8888 format 011 24-bpp, rgb 888 format 101 16-bpp, argb 4444 format others reserved g2d_eng_mode 2d engine function mode 0110 polygon fill. 1000 rectangle fill. 1001 bitblt. 1010 bitblt with alpha blending. 1011 bitblt with rop. 1100 font drawing. others not allowed g2d+0104h graphic 2d engine sub-mode control register g2d_smode_c on bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fita fnbg fmsb_ first rsz_e n clr_r ep_en rop4_ en rop3_ en alpha type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0000 0000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 676 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bidx_ en bidx limg dst_k ey_en clrg d_en bdir bita brot type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 11 0 111 write this register to set the 2d engine configuration. fita font italic enabled. fnbg font drawing with no background color fmsb_first font drawing from most significant bit rsz_en scaled bitblt mode enabled . clr_rep_en output color replacement enable. rop3_en ternary rop enabled. alpha bit 7-0 of constant alpha value.. bidx_en index color mode of bitblt. bidx index color selection of bitblt, only effective when bidx_en is enabled. 00 1 bit index color 01 2 bit index color 10 4 bit index color 11 8 bit index color limg polygon fill with image pattern. this function should not be enabled when clipping is enabled. dst_key_en destination key enabled for bitblt functions clrgr_en color gradient enabled for rectangle fill bdir bitblt direction: 00 from lower right corner 01 from lower left corner 10 from upper right corner 11 from upper left corner this field only takes effect when the bitblt rotation is set as none (111). when doing rotation the bitblt direction of source image is always from upper left corner. bita bitblt italic enabled, using the tilt value defined in g2d_tilt_00 ~ g2d_tilt_1f registers. the tilt function should not be enabled in alpha blending and rop mode. brot bitblt rotation: 000 mirror then rotate 90 001 rotate 90 010 rotate 270 011 mirror then rotate 270 100 rotate 180 101 mirror 110 mirror then rotate 180 111 none g2d+0108h graphic 2d engine common control register g2d_com_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 677 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tidle _rst wm_d st_xp wm_pi t_u wm_p mul wm_a lp_rn d wm_c py_x wm_c lr_x src_c lp_en wr_b uf_en rd_b uf_en clp_e n srck ey_en rst type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 write this register to set the 2d engine configuration. rst 2d engine reset, only the state machine is reset, the content of control registers will not be reset. srckey_en source key enabled. clp_en destination clipping enabled. rd_buf_en read buffer enabled. enable read buffer can improve read memory performance. wr_buf_en write buffer enabled. enable write buffer could improve write memory performance. src_clp_en source clipping enabled. wm_clr_x enable operation in destination color format with color format transform defined in windowsmobile. wm_cpy_x enable operation in 32bpp color format with color format transform defined in windowsmobile. wm_alp_rnd rounding before each shift operation in alpha blending. wm_pmul pre-multiplied source format enabled. only supported in argb8888. wm_pit_u reserved. wm_dst_xp destination transparency enabled. alpha blending operation on alpha channel when this bit is enabled. tidle_rst reset the r/w memory access transaction completeness status. g2d+010ch graphic 2d engine interru pt control register g2d_irq_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en type r/w reset 0 write this register to set the 2d engine irq configuration. en interrupt enable. the interrupt is negative edge sensitive. g2d+0110h graphic 2d engine common status register g2d_com_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tidle busy type ro ro reset 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 678 of 1535 read this register to get the 2d engine status. 2d engine may function abnormally if any 2d engine register is modified when busy. busy 2d engine is busy tidle read this register to get the completeness of r/w memory access transaction. if the transaction is completed, this register will be asserted. g2d+0200h graphic 2d source base address register g2d_src_bas e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_base[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_base[15:0] type r/w reset 0 src_base the base address of source image. g2d+0204h graphic 2d engine source pitch register g2d_src_pitc h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_pitch type r/w reset 0 src_pitch the width of source image in the unit of pixels. g2d+0208h graphic 2d engine source x and y register g2d_src_xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_y type r/w reset 0 src_y the starting y co-ordinate of source image. it must be positive although represented as 12-bit signed integer. src_x the starting x co-ordinate of source image. it must be positive although represented as 12-bit signed integer. g2d+020ch graphic 2d engine source size register g2d_src_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_w type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 679 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_h type r/w reset 0 src_h the source height for bitblt, alpha blending and rop. it must be positive although represented as 12- bit signed integer. src_w the source width for bitblt, alpha blending and rop. it must be positive although represented as 12-bit signed integer. g2d+0210h graphic 2d engine source color key register g2d_src_key bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_key[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_key[15:0] type r/w reset 0 src_key the source color key. the color will be transparent if color keying is enabled. g2d+0214h graphic 2d engine destination avoidance color g2d_dst_avo _clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_avo_clr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_avo_clr[15:0] type r/w reset 0 dst_avo_clr the output color with dst_avo_clr would be replaced with dst_rep_clr when clr_rep_en is enabled. g2d+0218h graphic 2d engine destination replacement color g2d_dst_rep_ clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_rep_clr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_rep_clr[15:0] type r/w reset 0 dst_rep_clr the output color with dst_avo_clr would be replaced with dst_rep_clr when clr_rep_en is enabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 680 of 1535 g2d+021ch graphic 2d engine source clipping x and y register g2d_src_clp _xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_clp_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_clp_y type r/w reset 0 src_clp_x the starting value of source x co-ordinate in clipping window, unsigned 12-bit integer. src_clp_y the starting value of source y co-ordinate in clipping window, unsigned 12-bit integer. g2d+0220h graphic 2d engine destination size after clipping register g2d_dst_clp_ size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_clp_w type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_clp_h type r/w reset 0 dst_clp_h the destination height for bitblt, alpha blending and rop after source clipping setup. it must be positive although represented as 12-bit unsigned integer. dst_clp_w the destination width for bitblt, alpha blending and rop after source clipping setup. it must be positive although represented as 12-bit unsigned integer. g2d+0300h graphic 2d destination base address register g2d_dst_bas e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_base[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_base[15:0] type r/w reset 0 dst_base the base address of destination image. g2d+0304h graphic 2d engine destination pitch register g2d_dst_pitc h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_pitch type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 681 of 1535 dst_pitch the width of destination image in the unit of pixels. g2d+0308h graphic 2d engine destination x and y register 0 g2d_dst_xy0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_x0 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_y0 type r/w reset 0 (dst_x0 , dst_y0) is used as the starting co-ordinate in bitblt, alpha blending, rop, and font drawing mode. dst_x0 represented by 12-bit signed integer. negative co-ordinate is allowed. dst_y0 represented by 12-bit signed integer. negative co-ordinate is allowed. g2d+0318h graphic 2d engine destination size register g2d_dst_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_w type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_h type r/w reset 0 dst_h the destination height for bitblt, alpha blending and rop. it must be positive although represented as 12-bit signed integer. dst_w the destination width for bitblt, alpha blending and rop. it must be positive although represented as 12-bit signed integer. g2d+031ch graphic 2d engine destination clipping x and y register g2d_dst_clp_ xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_clp_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_clp_y type r/w reset 0 src_clp_x the starting value of destination x co-ordinate in clipping window, unsigned 12-bit integer. src_clp_y the starting value of destination y co-ordinate in clipping window, unsigned 12-bit integer. g2d+0320h graphic 2d enginepattern base register g2d_pat_bas e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pat_base[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 682 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pat_base[15:0] type r/w reset 0 pat_base the base address of pattern image. g2d+0324h graphic 2d enginepattern pitch register g2d_pat_pitc h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pat_pitch type r/w reset 0 pat_pitch the width of pattern in the unit of pixels. the maximum width of pattern is 32. g2d+0328h graphic 2d engine pattern x y w h register g2d_pat_xyw h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pat_x pat_y type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pat_w pat_h type r/w r/w reset 0 0 pat_x the starting x co-ordinate of pattern image for ternary rop or polygon-fill. pat_y the starting y co-ordinate of pattern image for ternary rop or polygon-fill. pat_w the pattern width for ternary rop or polygon-fill. pat_h the pattern height for ternary rop or polygon-fill. g2d+032ch graphic 2d engine pattern x y clipping and offset register g2d_pat_xyo fs bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pat_clp_x pat_clp_y type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pat_xofs pat_yofs type r/w r/w reset 0 0 pat_clp_x the starting value of pattern x co-ordinate in clipping window, unsigned 6-bit integer. pat_clp_y the starting value of pattern y co-ordinate in clipping window, unsigned 6-bit integer. pat_xofs the offset of x co-ordinate of pattern image for ternary rop or polygon-fill. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 683 of 1535 pat_yofs the offset of y co-ordinate of pattern image for ternary rop or polygon-fill. g2d+0330h graphic 2d enginemask base register g2d_msk_bas e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name msk_base[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name msk_base[15:0] type r/w reset 0 msk_base the base address of mask image. g2d+0334h graphic 2d engine mask pitch register g2d_msk_pitc h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name msk_pitch type r/w reset 0 src_pitch the width of source image in the unit of pixels. g2d+0338h graphic 2d engine mask x and y register g2d_msk_xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name msk_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name msk_y type r/w reset 0 msk_y the starting y co-ordinate of mask image. it must be positive although represented as 12-bit signed integer. msk_x the starting x co-ordinate of mask image. it must be positive although represented as 12-bit signed integer. g2d+033ch graphic 2d engine mask size register g2d_msk_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name msk_w type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name msk_h type r/w reset 0 msk_h the mask height for bitblt, alpha blending and rop. it must be positive although represented as 12- bit signed integer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 684 of 1535 msk_w the mask width for bitblt, alpha blending and rop. it must be positive although represented as 12-bit signed integer. g2d+0340h graphic 2d engine resize up donw register g2d_rsz_ud bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g2d_rsz_up type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g2d_rsz_dn type r/w reset 0 g2d_rsz_up the scaling up factor for bitblt. g2d_rsz_dn the scaling down factor for bitblt. g2d+0344h graphic 2d engine rop code register g2d_rop_cod e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rop_code0 rop_code1 type r/w r/w reset 0 0 rop_code1 rop3 code, or rop4 code for mask bit is ?1?. rop_code0 rop4 code for mask bit is ?0?. bitblt rop code boolean function start bit position for font drawing 0000_0000 0 (black) bit 0 0000_0001 ~(s + d) bit 1 0000_0010 ~s . d bit 2 0000_0011 ~s bit 3 0000_0100 s . ~d bit 4 0000_0101 ~d bit 5 0000_0110 s ^ d bit 6 0000_0111 ~(s . d) bit 7 0000_1000 s . d bit 0 0000_1001 ~(s ^ d) bit 1 0000_1010 d bit 2 0000_1011 ~s + d bit 3 0000_1100 s bit 4 0000_1101 s + ~d bit 5 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 685 of 1535 0000_1110 s + d bit 6 0000_1111 1 (white) bit 7 s = source, d = destination. i = first quadrant, ii = second quadrant, iii = third quadrant, iv = fourth quadrant. rop code boolean function rop code boolean function rop code boolean function rop code boolean function 0000_0000 0 (black) 0000_0001 ~ ((p + s) + d) 0000_0010 (~ (p + s)) . d 0000_0011 ~ (p + s) 0000_0100 (~ (p + d)) . s 0000_0101 ~ (p + d) 0000_0110 ~ ((~ (d ^ s)) + p) 0000_0111 ~ ((d . s) + p) 0000_1000 (~ p) . d . s 0000_1001 ~ ((d ^ s) + p) 0000_1010 (~ p) . d 0000_1011 ~ (((~ d) . s) + p) 0000_1100 (~ p) . s 0000_1101 ~ (((~ s) . d) + p) 0000_1110 ~ ((~ (d + s)) + p) 0000_1111 ~ p 0001_0000 (~ (d + s)) . p 0001_0001 ~ (d + s) 0001_0010 ~ ((~ (d ^ p)) + s) 0001_0011 ~ ((d . p) + s) 0001_0100 ~ ((~ (p ^ s)) + d) 0001_0101 ~ ((p . s) + d) 0001_0110 (((~ (p . s)) . d) ^ s) ^ p 0001_0111 ~ (((s ^ p) . (d ^ s)) ^ s) 0001_1000 (s ^ p) . (d ^ p) 0001_1001 ~ (((~ (p . s)) . d) ^ s) 0001_1010 ((s . p) + d) ^ p 0001_1011 ~ (((p ^ s) . d) ^ s) 0001_1100 ((d . p) + s) ^ p 0001_1101 ~ (((p ^ d) . s) ^ d) 0001_1110 (d + s) ^ p 0001_1111 ~ ((d + s) . p) 0010_0000 (~ s) . p . d 0010_0001 ~ ((d ^ p) + s) 0010_0010 (~ s) . d 0010_0011 ~ (((~ d) . p) + s) 0010_0100 (s ^ p) . (d ^ s) 0010_0101 ~ (((~ (s . p)) . d) ^ p) 0010_0110 ((p . s) + d) ^ s 0010_0111 ((~ (p ^ s)) + d) ^ s 0010_1000 (p ^ s) . d 0010_1001 ~ ((((p . s) + d) ^ s) ^ p) 0010_1010 (~ (p . s)) . d 0010_1011 ~ (((s ^ p) . (p ^ d)) ^ s) 0010_1100 ((d + s) . p) ^ s 0010_1101 ((~ d) + s) ^ p 0010_1110 ((d ^ p) + s) ^ p 0010_1111 ~ (((~ d) + s) . p) 0011_0000 (~ s) . p 0011_0001 ~ (((~ p) . d) + s) 0011_0010 ((p + s) + d) ^ s 0011_0011 ~ s 0011_0100 ((d . s) + p) ^ s 0011_0101 ((~ (d ^ s)) + p) ^ s 0011_0110 (d + p) ^ s 0011_0111 ~ ((d + p) . s) 0011_1000 ((d + p) . s) ^ p 0011_1001 ((~ d) + p) ^ s 0011_1010 ((d ^ s) + p) ^ s 0011_1011 ~ (((~ d) + p) . s) 0011_1100 p ^ s 0011_1101 ((~ (d + s)) 0011_1110 (((~ s) . d) 0011_1111 ~ (p . s) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 686 of 1535 rop code boolean function rop code boolean function rop code boolean function rop code boolean function + p) ^ s + p) ^ s 0100_0000 (~ d) . s . p 0100_0001 ~ ((p ^ s) + d) 0100_0010 (s ^ d) . (p ^ d) 0100_0011 ~ (((~ (d . s)) . p) ^ s) 0100_0100 (~ d) . s 0100_0101 ~ (((~ s) . p) + d) 0100_0110 ((p . d) + s) ^ d 0100_0111 ~ (((d ^ p) . s) ^ p) 0100_1000 (d ^ p) . s 0100_1001 ~ (((p . d) + s) ^ d ^ p) 0100_1010 ((s + d) . p) ^ d 0100_1011 ((~ s) + d) ^ p 0100_1100 (~ (d . p)) . s 0100_1101 ~ (((s ^ p) + (s ^ d)) ^ s) 0100_1110 ((s ^ p) + d) ^ p 0100_1111 ~ (((~ s) + d) . p) 0101_0000 (~ d) . p 0101_0001 ~ (((~ p) . s) + d) 0101_0010 ((s . d) + p) ^ d 0101_0011 ~ (((d ^ s) . p) ^ s) 0101_0100 ~ ((~ (p + s)) + d) 0101_0101 ~ d 0101_0110 (p + s) ^ d 0101_0111 ~ ((p + s) . d) 0101_1000 ((s + p) . d) ^ p 0101_1001 ((~ s) + p) ^ d 0101_1010 d ^ p 0101_1011 ((~ (s + d)) + p) ^ d 0101_1100 ((s ^ d) + p) ^ d 0101_1101 ~ (((~ s) + p) . d) 0101_1110 (((~ d) . s) + p) ^ d 0101_1111 ~ (d . p) 0110_0000 (d ^ s) . p 0110_0001 ~ (((d . s) + p) ^ s ^ d) 0110_0010 ((p + d) . s) ^ d 0110_0011 ((~ p) + d) ^ s 0110_0100 ((p + s) . d) ^ s 0110_0101 ((~ p) + s) ^ d 0110_0110 d ^ s 0110_0111 ((~ (p + s)) + d) ^ s 0110_1000 ~ (((~ (d + s)) + p) ^ s ^ d) 0110_1001 ~ (d ^ s ^ p) 0110_1010 (p . s) ^ d 0110_1011 ~ (((p + s) . d) ^ s ^ p) 0110_1100 (d . p) ^ s 0110_1101 ~ (((p + d) . s) ^ d ^ p) 0110_1110 (((~ s) + p) . d) ^ s 0110_1111 ~ ((~ (d ^ s)) . p) 0111_0000 (~ (d . s)) . p 0111_0001 ~ (((s ^ d) . (p ^ d)) ^ s) 0111_0010 ((p ^ s) + d) ^ s 0111_0011 ~ (((~ p) + d) . s) 0111_0100 ((p ^ d) + s) ^ d 0111_0101 ~ (((~ p) + s) . d) 0111_0110 (((~ s) . p) + d) ^ s 0111_0111 ~ (s . d) 0111_1000 (d . s) ^ p 0111_1001 ~ (((d + s) . p) ^ s ^ d) 0111_1010 (((~ d) + s) . p) ^ d 0111_1011 ~ ((~ (d ^ p)) . s) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 687 of 1535 rop code boolean function rop code boolean function rop code boolean function rop code boolean function 0111_1100 (((~ s) + d) . p) ^ s 0111_1101 ~ ((~ (p ^ s)) . d) 0111_1110 (s ^ p) + (s ^ d) 0111_1111 ~ (p . s . d) 1000_0000 p . s . d 1000_0001 ~ ((s ^ p) + (s ^ d)) 1000_0010 (~ (p ^ s)) . d 1000_0011 ~ ((((~ s) + d) . p) ^ s) 1000_0100 (~ (d ^ p)) . s 1000_0101 ~ ((((~ p) + s) . d) ^ p) 1000_0110 ((d + s) . p) ^ s ^ d 1000_0111 ~ ((d . s) ^ p) 1000_1000 d . s 1000_1001 ~ ((((~ s) . p) + d) ^ s) 1000_1010 ((~ p) + s) . d 1000_1011 ~ (((p ^ d) + s) ^ d) 1000_1100 ((~ p) + d) . s 1000_1101 ~ (((p ^ s) + d) ^ s) 1000_1110 ((s ^ d) . (p ^ d)) ^ s 1000_1111 ~ ((~ (d . s)) . p) 1001_0000 (~ (d ^ s)) . p 1001_0001 ~ ((((~ s) + p) . d) ^ s) 1001_0010 ((d + p) . s) ^ p ^ d 1001_0011 ~ ((p . d) ^ s) 1001_0100 ((p + s) . d) ^ s ^ p 1001_0101 ~ ((p . s) ^ d) 1001_0110 p ^ s ^ d 1001_0111 ((~ (p + s)) + d) ^ s ^ p 1001_1000 ~ (((~ (p + s)) + d) ^ s) 1001_1001 ~ (d ^ s) 1001_1010 ((~ s) . p) ^ d 1001_1011 ~ (((p + s) . d) ^ s) 1001_1100 ((~ d) . p) ^ s 1001_1101 ~ (((p + d) . s) ^ d) 1001_1110 ((d . s) + p) ^ s ^ d 1001_1111 ~ ((d ^ s) . p) 1010_0000 d . p 1010_0001 ~ ((((~ p) . s) + d) ^ p) 1010_0010 ((~ s) + p) . d 1010_0011 ~ (((s ^ d) + p) ^ d) 1010_0100 ~ (((~ (s + p)) + d) ^ p) 1010_0101 ~ (p ^ d) 1010_0110 ((~ p) . s) ^ d 1010_0111 ~ (((p + s) . d) ^ p) 1010_1000 (p + s) . d 1010_1001 ~ ((p + s) ^ d) 1010_1010 d 1010_1011 (~ (p + s)) + d 1010_1100 ((d ^ s) . p) ^ s 1010_1101 ~ (((s . d) + p) ^ d) 1010_1110 ((~ p) . s) + d 1010_1111 (~ p) + d 1011_0000 ((~ s) + d) . p 1011_0001 ~ (((s ^ p) + d) ^ p) 1011_0010 ((s ^ p) + (s ^ d)) ^ s 1011_0011 ~ ((~ (d . p)) . s) 1011_0100 ((~ d) . s) ^ p 1011_0101 ~ (((s + d) . p) ^ d) 1011_0110 ((d . p) + s) ^ p ^ d 1011_0111 ~ ((d ^ p) . s) 1011_1000 ((d ^ p) . s) ^ p 1011_1001 ~ (((p . d) + s) ^ d) 1011_1010 ((~ s) . p) + d 1011_1011 (~ s) + d free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 688 of 1535 rop code boolean function rop code boolean function rop code boolean function rop code boolean function 1011_1100 ((~ (d . s)) . p) ^ s 1011_1101 ~ ((s ^ d) . (p ^ d)) 1011_1110 (p ^ s) + d 1011_1111 (~ (p . s)) + d 1100_0000 p . s 1100_0001 ~ ((((~ s) . d) + p) ^ s) 1100_0010 ~ (((~ (d + s)) + p) ^ s) 1100_0011 ~ (p ^ s) 1100_0100 ((~ d) + p) . s 1100_0101 ~ (((d ^ s) + p) ^ s) 1100_0110 ((~ p) . d) ^ s 1100_0111 ~ (((d + p) . s) ^ p) 1100_1000 (d + p) . s 1100_1001 ~ ((p + d) ^ s) 1100_1010 ((s ^ d) . p) ^ d 1100_1011 ~ (((d . s) + p) ^ s) 1100_1100 s 1100_1101 (~ (d + p)) + s 1100_1110 ((~ p) . d) + s 1100_1111 (~ p) + s 1101_0000 ((~ d) + s) . p 1101_0001 ~ (((d ^ p) + s) ^ p) 1101_0010 ((~ s) . d) ^ p 1101_0011 ~ (((d + s) . p) ^ s) 1101_0100 ((s ^ p) . (d ^ p)) ^ s 1101_0101 ~ ((~ (p . s)) . d) 1101_0110 ((p . s) + d) ^ s ^ p 1101_0111 ~ ((p ^ s) . d) 1101_1000 ((s ^ p) . d) ^ p 1101_1001 ~ (((p . s) + d) ^ s) 1101_1010 ((~ (s . d)) . p) ^ d 1101_1011 ~ ((s ^ p) . (s ^ d)) 1101_1100 ((~ d) . p) + s 1101_1101 (~ d) + s 1101_1110 (d ^ p) + s 1101_1111 (~ (d . p)) + s 1110_0000 (d + s) . p 1110_0001 ~ ((d + s) ^ p) 1110_0010 ((p ^ d) . s) ^ d 1110_0011 ~ (((d . p) + s) ^ p) 1110_0100 ((p ^ s) . d) ^ s 1110_0101 ~ (((s . p) + d) ^ p) 1110_0110 ((~ (p . s)) . d) ^ s 1110_0111 ~ ((s ^ p) . (d ^ p)) 1110_1000 ((s ^ p) . (d ^ s)) ^ s 1110_1001 ~ (((~(d . s)) . p) ^ s ^ d) 1110_1010 (p . s) + d 1110_1011 (~ (p ^ s)) + d 1110_1100 (d . p) + s 1110_1101 (~ (d ^ p)) + s 1110_1110 d + s 1110_1111 (~ p) + d + s 1111_0000 p 1111_0001 (~ (d + s)) + p 1111_0010 ((~ s) . d) + p 1111_0011 (~ s) + p 1111_0100 ((~ d) . s) + p 1111_0101 (~ d) + p 1111_0110 (d ^ s) + p 1111_0111 (~ (d . s)) + p 1111_1000 (d . s) + p 1111_1001 (~ (d ^ s)) + p 1111_1010 d + p 1111_1011 (~ s) + p + d 1111_1100 p + s 1111_1101 (~ d) + s + p 1111_1110 p + s + d 1111_1111 1 (wite) s = source, d = destination, p=pattern. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 689 of 1535 g2d+0348h graphic 2d engine mask clipping x and y register g2d_msk_clp _xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name msk_clp_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name msk_clp_y type r/w reset 0 msk_clp_x the starting value of mask x co-ordinate in clipping window, unsigned 12-bit integer. msk_clp_y the starting value of mask y co-ordinate in clipping window, unsigned 12-bit integer. g2d+0400h graphic 2d engine foreground color register g2d_ fgclr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fgclr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fgclr[15:0] type r/w reset 0 fgclr the foreground color used for font drawing. it is also the start color of rectangle fill. the format of foreground color depends on the source color mode set in g2d_fmode_con register. g2d+0404h graphic 2d engine backg round color register g2d_bgclr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bgclr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bgclr[15:0] type r/w reset 0 bgclr the background color of the source. the format of background color depends on the source color mode set in g2d_fmode_con register. g2d+0408h graphic 2d engine clipping minimum register g2d_clip_min bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clip_min_x type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_min_y type r/w reset 0 clip_min_x the minimum value of x co-ordinate in clipping window, signed 12-bit integer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 690 of 1535 clip_min_y the minimum value of y co-ordinate in clipping window, signed 12-bit integer.. g2d+040ch graphic 2d engine clipping maximum register g2d_clip_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clip_max_x type r/w reset 11111111111 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_max_y type r/w reset 11111111111 clip_max_x the maximum value of x co-ordinate in clipping window, signed 12-bit integer... clip_max_y the maximum value of y co-ordinate in clipping window, signed 12-bit integer.. g2d+0410h graphic 2d x alpha gradient register g2d_alpgr_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha_gr_x[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha_gr_x[15:0] type r/w reset 0 the color gradient of alpha in x direction for rectangle gradient fill. alpha_gr_x the color gradient of alpha channel, represented in signed 9.16 format. g2d+0414h graphic 2d x red gradient register g2d_redgr_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red_gr_x[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name red_gr_x[15:0] type r/w reset 0 the color gradient of red in x direction for rectangle gradient fill. red_gr_x the color gradient of red component, represented in signed 9.16 format. g2d+0418h graphic 2d x green gradient register g2d_ greengr_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name green_gr_x[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green_gr_x[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 691 of 1535 reset 0 green_gr_x the color gradient of blue component, represented in signed 9.16 format. g2d+041ch graphic 2d x blue gradient register g2d_bluegr_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name blue_gr_x[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blue_gr_x[15:0] type r/w reset 0 blue_gr_x the color gradient of blue component, represented in signed 9.16 format. g2d+0420h graphic 2d y alpha gradient register g2d_alpgr_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha_gr_y[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha_gr_y[15:0] type r/w reset 0 the color gradient of alpha in x direction for rectangle gradient fill. alpha_gr_y the color gradient of alpha channel, represented in signed 9.16 format. g2d+0424h graphic 2d y red gradient register g2d_redgr_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red_gr_y[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name red_gr_y[15:0] type r/w reset 0 the color gradient of red in x direction for rectangle gradient fill. red_gr_y the color gradient of red component, represented in signed 9.16 format. g2d+0428h graphic 2d y green gradient register g2d_ greengr_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name green_gr_y24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 692 of 1535 name green_gr_y15:0] type r/w reset 0 green_gr_y the color gradient of blue component, represented in signed 9.16 format. g2d+042ch graphic 2d y blue gradient register g2d_bluegr_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name blue_gr_y[24:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blue_gr_y[15:0] type r/w reset 0 blue_gr_y the color gradient of blue component, represented in signed 9.16 format. g2d+0430h graphic 2d engine buffer start address 0 g2d_buf_sta_ addr_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf_sta_addr_0[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf_sta_addr_0[15:0] type r/w reset 0 buf_sta_addr_0 the buffer 0 start address. buffer 0 is used for raw edge data for polygon-fill function, index color table for index-color bitblt mode. g2d+0434h graphic 2d engine buffer start address 1 g2d_buf_sta_ addr_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf_sta_addr_1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf_sta_addr_1[15:0] type r/w reset 0 buf_sta_addr_1 the buffer 1 start address. buffer 1 is used for storing edge processing temporal data for polygon-fill function. 5.1.2 command queue 5.1.2.1 general description to enhance mmi display and gaming experiences, a command queue controllrt is implemented for further offloading of mcu. if the command queue is enabled, software program has to check the command queue free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 693 of 1535 free space before writing to the command queue data register. command queue parser will consume command queue entries upon 2d engine requests. figure 100 shows the command queue and 2d engine block diagram. 3fhjtufs cbol % fohjof $pnnboervfvf "1# tmbwf $pnnboe qbstfs %45 nfnpsz sfbexsjuf dpouspm 43$ nfnpsz sfbe dpouspm figure 111 the command queue and 2d engine block diagram. 5.1.2.2 register definitions mcu apb bus registers are listed as followings. the base address of the command queue controller is 80082000h . gcmq+0000h graphic command queue control register gcmq_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tidle _rst wol en type r/w r/w r/w reset 0 0 0 en command queue enable. when en is low, the command queue controller will be reset. wol avoid reading when writing enable. when wol is high, prevent command queue reading command when mcu is writing command queue. tidle_rst reset the r/w memory access transaction completeness status. gcmq+0004h graphic command queue status register gcmq_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tidle empt y full type ro ro ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 694 of 1535 reset 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name free type ro reset 100000000 free number of free command queue entries full command queue full empty command queue empty tidle read this register to get the completeness of r/w memory access transaction. if the transaction is completed, this register will be asserted. gcmq+0008h graphic command queue data register gcmq_dat bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data type wo addr [11:0] write address for mapped 2d engine registers data [15:0] write data for mapped 2d engine registers gcmq+000ch graphic command queue base address register gcmq_base_a dd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base_add[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base_add[15:0] type r/w base_add the starting address of the command queue in the memory. note : this field only can be modified while the command queue is not enabled. otherwise the behavior of the command queue will be unpredictable. gcmq+0010h graphic command queue buffer length register gcmq_lengt h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name length type r/w length[9:0] the occupied space of the command queue in the memory is length *4bytes. note : this field only can be modified while the command queue is not enabled. otherwise the behavior of the command queue will be unpredictable. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 695 of 1535 gcmq+0014h graphic command queue current register gcmq_dma_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gcmq_dma_addr type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gcmq_dma_addr type ro gcmq_dma_addr the current read or write dma address of gcmq. 5.2 audio src mixer 5.2.1 general description audio src (sample rate conversion) mixer (asm) is am mcu coprocessor to convert the audio data from one sampling rate to another and mixed different sampled data together as shown in figure 112 architecture of audio src mixer. figure 112 architecture of audio src mixer the input sampling rate of pcm data may from 8k to 48k, mono or stereo, 8 bit or 16 bit, while the output data are at the sampling rate of 48k or 50.78125k (6.5mhz / 128) which is controlled by mcu. moreover, a gain stage is implemented to support gain control for converted signals. the implementation of src is to up-sample the input data to 16x sampling rate and followed by a third-order interpolator which converts the data to the desired rate (48 khz or 50.78125 khz). 5.2.2 register definitions the base address of asm is 0x0x8008f000 5.2.2.1 audio src mixer mcu apb bus registers in audio src mixer are listed as follows. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 696 of 1535 0x8008f000 asm pcm input ring buffer base register asm_ibuf_base 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ibuf_base0[31:16] type r/w reset 0000_0000_0000_0000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ibuf_base0[15:0] type r/w reset 0000_0000_0000_0000 the register indicates the starting address of the input pcm data for asm. please always set ibuf_base[3:0] = 4?h0 for the convenience of the hardware implementation. ibuf_base0 address of the starting point for the pcm input buffer. register address register function acronym 0x8008f020 asm pcm input ring buffer base register for block 1 asm_ibuf_base 1 0x8008f040 asm pcm input ring buffer base register for block 2 asm_ibuf_base 2 table 91 pcm input ring buffer base registers 0x8008f004 asm pcm input ring buffer end register asm_ibuf_end 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ibuf_end0[31:16] type r/w reset 0000_0000_0000_0000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ibuf_end0[15:0] type r/w reset 0000_0000_0000_0000 the register indicates the end address of the pcm ring buffer. the cursor for the pcm ring buffer will go back to the base address whenever the buffer-end is reached. please always set ibuf_end0[3:0] = 4?hf for the convenience of the hardware implementation. ibuf_end0 end address of the pcm input ring buffer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 697 of 1535 32'hxxx0 32'hxxxf ibuf_base[31:0] ibuf_end[31:0] go back to ibuf_base if ibuf_end is reached figure 113 example of input buffer address register address register function acronym 0x8008f024 asm pcm input ring buffer end register for block 1 asm_ibuf_end1 0x8008f044 asm pcm input ring buffer end register for block 2 asm_ibuf_end2 table 92 pcm input ring buffer end registers 0x8008f008 asm pcm input ring buffer cursor register asm_ibuf_cur0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ibuf_cur0[31:16] type ro reset - bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ibuf_cur0[15:0] type ro reset - this register indicates the address of the next pcm input ring buffer. ibuf_cur0 position of the pcm input ring buffer. register address register function acronym 0x8008f028 asm pcm input ring buffer cursor register for block 1 asm_ibuf_cur1 0x8008f048 asm pcm input ring buffer cursor register for block 2 asm_ibuf_cur2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 698 of 1535 table 93 pcm input ring buffer cursor registers 0x8008f100 asm mcu control register 0 asm_con0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blk2_ on blk1_ on blk0_ on asmo n type r/w r/w r/w r/w reset 0 0 0 0 this register is set to start asm operation. make sure there are at least one of blk0_on to blk2_on is raised while asm is asserted. never close all blocks if asmon is not released. asmon set this register to start the operation of the asm. all other registers should be set to the desired values before this register is asserted. 0 off 1 on blk0_on switch of block 0. 0 off 1 on blk1_on switch of block 1. 0 off 1 on blk2_on switch of block 2. 0 off 1 on 0x8008f104 asm mcu control register 1 asm_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_s witch _en ofs type r/w r/w reset 1 0 this register sets the configuration of asm. clk_switch_en enable signal for bus clock to speed down while asm is on. 0 disable. bus clock should be 104mhz while asm is on. 1 enable ofs output sampling rate of the asm. 0 50.78125 khz (to afe) 1 48 khz (to i2s) 0x8008f010 asm mcu setting register for block 0 asm_set0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ibit0 imode 0 ifs0 type r/w r/w r/w reset 0 0 0000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 699 of 1535 this register is the i/o settings of the asm for block 0. ibit0 bit number of the input data for block 0. 0 8 bit 1 16 bit imode0 input data mode for block 0. 0 stereo 1 mono ifs0 input sampling rate of the asm for block 0. 0000 48 khz 0001 44.1 khz 0010 32 khz 0011 24 khz 0100 22.05 khz 0101 16 khz 0110 12 khz 0111 11.025 khz 1000 8 khz others 48 khz register address register function acronym 0x8008f030 asm mcu setting register for block 1 asm_set1 0x8008f050 asm mcu setting register for block 2 asm_set2 table 94 block setting registers 0x8008f014 asm gain setting register for block 0 asm_gain0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gain0 type r/w reset 0001_0000_0000_0000 this register sets the gain in asm. it is coded in unsigned 2?s complement where bit 15 to bit12 indicates the integer part and bit 12 to bit 0 is the fractional part. the maximum gain setting is 15.99975586 (24.08 db) and the gain step is 0.0039. default gain setting is 1. gain0 unsigned gain setting of block 0 or asm [0:4:12]. register address register function acronym 0x8008f034 asm gain setting register for block 1 asm_gain1 0x8008f054 asm gain setting register for block 2 asm_gain2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 700 of 1535 table 95 gain setting registers 0x8008f018 asm interrupt counter setti ng register for block 0 asm_ir_cnt0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ir_cnt0 type r/w reset 0000_0000_0000_0000 this register sets the counter initialize value for asm to tell mcu to update the input pcm buffer0. the counter value is decided only according to the input data rate. the default value is 0 which will not generate interrupt to mcu. ir_cnt0 initial counter value for interrupt generation. register address register function acronym 0x8008f038 asm interrupt counter setting register for block 1 asm_ir_cnt1 0x8008f058 asm interrupt counter setting register for block 2 asm_ir_cnt2 table 96 gain setting registers 0x8008f108 asm interrupt status register asm_ir_statu s bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ir_edi ir_bl k2 ir_bl k1 ir_bl k0 type ro ro ro ro reset 0 0 0 0 this register is an indicator for mcu to see which interrupt are raised. 0x8008f10c asm interrupt clear register asm_ir_clr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ir_edi _clr ir_cl r2 ir_cl r1 ir_cl r0 type wo wo wo wo reset - - - - this register is for mcu to clear the asm_ir_status register contents while the interrupt is read by mcu. 0x8008f110 asm gmc input monitor register asm_gmc_read bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name arch_1x type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alch_1x type ro this register monitors the input of asm from gmc. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 701 of 1535 0x8008f11c asm state0 register asm_state0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asm_state out_stg_rdy type ro ro reset 0000000001 0000 this register is for mcu to clear the asm_ir_status register contents while the interrupt is read by mcu. 0x8008f120 asm output check su m register asm_check_sum bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asm_check_sum type ro reset - this register is for mcu to check the asm output. 0x8008f124 asm sine-table control register asm_sin_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sin_e n mute_ sw amp_div freq_div type r/w r/w r/w r/w reset 0 0 111 00000001 this register is for asm to generate sine wave directly to afe without other mcu control. sin_en sent sine wave to afe mute_sw mute sine-wave output 0 no mute 1 mute amp_div sine wave amplitude 000 1/128x 001 1/64x 010 1/32x 011 1/16x 100 1/8x 101 1/4x 110 1/2x 111 1x freq_div sine wave frequency 00000001 1x 00000010 2x 00000100 3x 00001000 4x 00010000 8x 00100000 16x free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 702 of 1535 5.2.2.2 afe 0x8008f200 afe audio mcu control register 0 asm_afe_con0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aafe on type r/w reset 0 mcu sets this register to start afe audio operation. a synchronous reset signal is issued. aafeon afe switch 0 off 1 on 0x8008f204 afe audio control register 1 asm_afe_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mono arampsp attgain amut el amut er eql_e n eqr_ en type r/w r/w r/w r/w r/w r/w r/w reset 0 00 100000 0 0 0 0 mcu sets this register for afe operation mono mono mode select. afe hw will do (left + right) / 2 operation to the audio sample pair. thus both dac at right/left channels will have the same inputs. 0 disable mono mode. 1 enable mono mode. arampsp ramp up/down speed selection. afs is 50.78125 khz. 00 8, 4096/afs 01 16, 2048/afs 10 24, 1024/afs 11 32, 512/afs amuter mute the audio r-channel, with a soft ramp up/down. 0 no mute 1 mute amutel mute the audio l-channel, with a soft ramp up/down. 0 no mute 1 mute eqr_en enable signal for right channel equalizer. 0 disable 1 enable eql_en enable signal for left channel equalizer. 0 disable 1 enable attgain gain setting for afe input (0/32 ~ 63/32), please set to 20. 111111 63/32 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 703 of 1535 100000 32/32 0x8008f208 afe audio control register 2 asm_afe_con2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rlsw t sdm_ signe xt asdm ck_ph ase sdms el sel_i dwa adith_val adith _on type r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 1 00 0 mcu sets this register for sdm settings. adithon turn on the audio dither function. 0 off 1 on adithval dither scaling setting. 00 1/4 01 1/2 10 1 11 2 sel_idwa idwa function selection. 0 disable idwa 1 enable idwa sdmsel selection of sdm 0 original 3rd order sdm. 1 new 2nd order sdm. asdmck_phase output clock phase to analog. 0 normal phase 1 inverse phase sdm_signext sign extension for internal data processing of 3rd order sdm. rlswt switch of r/l channel. 0 no switch 1 switch 0x8008f240 ~0x8008f2f0 afe audio equalizer filter coefficient register afe_eqcoef bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name a type wo audio front-end provides a 45-tap equalizer filter. the filter is shown below. note: please make sure that abs(a44) + abs(a43) + ? + abs(a1) + abs(a0) < 32768 x 16. do = (a44 x di44 + a43 x di43 ? + a1 x di1 + a0 x di0)/32768. din is the input data, and an is the coefficient of the filter, which is a 16-bit 2?s complement signed integer. di0 is the last input data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 704 of 1535 the coefficient cannot be programmed when the audio path is enabled, or unpredictable noise may be generated. if coefficient programming is necessary while the audio path is enabled, the audio path must be muted during programming. after programming is complete, the audio path is not to be resumed (unmated) for 100 sampling periods. a coefficient of the filter. address coefficient address coefficient address coefficient 0x8008f240 a0 0x8008f27c a15 0x8008f2b8 a30 0x8008f244 a1 0x8008f280 a16 0x8008f2bc a31 0x8008f248 a2 0x8008f284 a17 0x8008f2c0 a32 0x8008f24c a3 0x8008f288 a18 0x8008f2c4 a33 0x8008f250 a4 0x8008f28c a19 0x8008f2c8 a34 0x8008f254 a5 0x8008f290 a20 0x8008f2cc a35 0x8008f258 a6 0x8008f294 a21 0x8008f2d0 a36 0x8008f25c a7 0x8008f298 a22 0x8008f2d4 a37 0x8008f260 a8 0x8008f29c a23 0x8008f2d8 a38 0x8008f264 a9 0x8008f2a0 a24 0x8008f2dc a39 0x8008f268 a10 0x8008f2a4 a25 0x8008f2e0 a40 0x8008f26c a11 0x8008f2a8 a26 0x8008f2e4 a41 0x8008f270 a12 0x8008f2ac a27 0x8008f2e8 a42 0x8008f274 a13 0x8008f2b0 a28 0x8008f2ec a43 0x8008f278 a14 0x8008f2b4 a29 0x8008f2f0 a44 0x8008f120 afe output check su m register afe_checksum bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name afe_checksum type ro reset - this register is for mcu to check the afe output 5.2.2.3 i2s 0x8008f300 afe edi control register afe_edi_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dir src wcycle fmt en type r/w r/w r/w r/w r/w reset 0 0 01111 0 0 this register is used to control the edi en enable edi. when edi is disabled, edi_dat and edi_ws hold low. 0 disable edi 1 enable edi fmt edi format 0 eiaj 1 i2s free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 705 of 1535 wcycle clock cycle count in a word. cycle count = wcycle + 1, and wcycle can be 15 or 31 only. any other values result in an unpredictable error. 15 cycle count is 16. 31 cycle count is 32. src i2s clock and ws signal source. 0 internal mode. the clock and word select signals are fed to external device from afe. 1 external mode. the clock and word select signals are fed externally from the connected device. there is a buffer control mechanism to deal with the clock mismatch between internal and external clocks. dir serial data bit direction 0 output mode. audio data is fed out to the external device. 1 input mode or recording mode. by this recording mechanism, mcu can do some post processing or voice memos. edi_clk edi_ws left channel right channel edi_dat 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 16 cycles 16 cycles figure 114 cycle count is 16 for i2s format. edi_clk edi_ws left channel right channel edi_dat 6 5 4 3 2 1 0 15 14 13 12 2 1 0 15 14 13 12 2 1 0 15 14 13 32 cycles 32 cycles figure 115 cycle count is 32 for i2s format. 0x8008f304 afe edi output ring buffer base asm_edi_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name edi_base[31:16] type r/w reset 0000_0000_0000_0000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_base[15:0] type r/w reset 0000_0000_0000_0000 the register indicates the starting address of the output data for arm9. please always set edi_base[3:0] = 4?h0 for the convenience of the hardware implementation. edi_base starting address of output edi data ring buffers. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 706 of 1535 0x8008f308 afe edi output ring buffer end asm_edi_end bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name edi_end[31:16] type r/w reset 0000_0000_0000_0000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_end[15:0] type r/w reset 0000_0000_0000_0000 the register indicates the starting address of the output data for arm9. please always set edi_end[3:0] = 4?hf for the convenience of the hardware implementation. edi_end end address of output edi data ring buffers. 0x8008f30c afe edi control register 1 asm_edi_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_num type r/w reset 00_0111_1000_0000 this register sets the numerator for edi enable signals. for edi output mode, please always set edi_num = 13?h0780 for 48 khz sampling rate data. for edi input mode, 3 settings are suggested: edi_num = 13?h0500 for 32 khz input data rate; edi_num = 13?h06e4 for 44.1 khz input data rate; and edi_num = 13?h0780 for 48 khz input data rate. please make sure the setting is correct before edi is opened. edi_num numerator for edi enable signals 0x8008f310 asm interrupt counter setti ng register for edi asm_edi_ir_cnt bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_ir_cnt type r/w reset 0000_0000_0000_0000 this register sets the counter initialize value for asm to tell mcu to get the output edi buffer. the counter value is decided only according to the edi output data rate. the default value is 0 which will not generate interrupt to mcu. edi_ir_cnt initial counter value for interrupt generation. 0x8008f314 asm edi output moni tor register asm_ebit_rdata bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ebit_rdata[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ebit_rdata[15:0] type ro this register monitors the output of edi to arm9. 0x8008f318 afe edi output ring buffer cursor asm_edi_cur bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 707 of 1535 name edi_cur[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_cur[15:0] type ro the register indicates the current address of the output data for arm9. 0x8008f31c asm edi input monitor register asm_edi_data bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name edi_data[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name edi_data[15:0] type ro this register monitors the output of edi to arm9. 5.2.3 programming guide 1. the input buffer length of the mcu must longer than the desired length for the hardware margin. 2. power on asm ,afe and gmc1 clock by setting graph1sys_cg_clr (0x80092340) = 0x00120001. 3. asm will start whenever the asmon in asm_con0 comes, please set all registers before the asmon is raised 4. the settings in asm_set and asm_gain of each block can?t be changed until an audio wave is finished. 5. the operation sequence for asm and afe (i2s) is to start afe (i2s) before asm. while the operation is finished, stop afe (i2s) before stopping asm. 6. asm stopping sequence a e close all asm blocks (asm_con0 = 0x0000). b e clear all irq status (asm_ir_status). c e power down asm clock. 7. afe and i2s output can?t be opened at the same time. 8. i2s input mode : a e power on asm by setting graph1sys_cg_clr (0x80092340) = 0x00100000. b e set asm_edi_base, asm_edi_end, asm_edi_con1 and asm_edi_ir_cnt to the desired settings. c e set dir, src and en of afe_edi_con to 1 to start i2s input mode operation. 9. once asm is closed, please wait at least 100us to reopen it. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 708 of 1535 5.3 backlight scaling 5.3.1 introduction back light scaling is used to modify content and back light to preserve original luminance and save the power. we provide the path for lcd and dpi. . 5.3.2 architecture of bls lcd dpi gmc nfi arbiter lcm host interface rgb interface emi external memory internel qvga frame buffer bls dpi interface: lcd interface: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 709 of 1535 rgb_valid rgb[23:0] hclk_ck stall p3 p5 p4 p6 sample rgb at these edges adjust_ok adjusted_rgb [23:0] p2 p0 p1 pa3 pa5 pa4 pa6 pa2 pa0 pa1 sample adjusted_rgb at these edges backlight scaling module input backlight scaling module output if stall asserts, do not samp le data at this cycle, and all signals (rgb_valid, rgb, adjust_ok and adjusted_rgb) shall hold to next cycle. frame_en at least 3cycles from frame_en asserted to the first rgb_valid keep asserting in a whole frame 5.3.3 register definitions 1. table0 bls + 0000h bls_pwm_max_cont enta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_max_content00[7:0] pwm_max_content01[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_max_content02[7:0] pwm_max_content03[7:0] type r/w r/w reset 0 0 2. table0 bls + 0004h bls_pwm_max_cont entb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_max_content04[7:0] pwm_max_content05[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_max_content06[7:0] pwm_max_content07[7:0] type r/w r/w reset 0 0 3. table0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 710 of 1535 bls + 0008h bls_pwm_max_cont entc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_max_content08[7:0] pwm_max_content09[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_max_content10[7:0] pwm_max_content11[7:0] type r/w r/w reset 0 0 4. table0 bls + 000ch bls_pwm_max_cont entd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_max_content12[7:0] pwm_max_content13[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_max_content14[7:0] pwm_max_content15[7:0] type r/w r/w reset 0 0 comments: we divide the curve of content vs. luminance with pwm=maximum at most 16 pieces and records the content of each piece. the software can decide the level num of the table. 5. table1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 711 of 1535 bls + 0010h bls_pwm_applied_conte nta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_ applied _content00[7:0] pwm_ applied _content01[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_ applied _content02[7:0] pwm_ applied _content03[7:0] type r/w r/w reset 0 0 6. table1 bls + 0014h bls_pwm_ applied _contentb bit 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 name pwm_ applied _content04[7:0] pwm_ applied _content05[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_ applied _content06[7:0] pwm_ applied _content07[7:0] type r/w r/w reset 0 0 7. table1 bls + 0018h bls_pwm_ applied _contentc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm applied _content08[7:0] pwm_ applied _content09[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_ applied _content10[7:0] pwm_ applied _content11[7:0] type r/w r/w reset 0 0 8. table1 bls + 001ch bls_pwm_ applied _contentd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pwm_ applied _content12[7:0] pwm_ applied _content13[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_ applied _content14[7:0] pwm_ applied _content15[7:0] type r/w r/w reset 0 0 comments: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 712 of 1535 we divide the curve of content vs. luminance with pwm=applied at most 16 pieces and records the content of each piece. the untouched region when content reached its max (255) all fill with 255. 00 01 02 03 04 05 06 07 08 09 101112 13 14 15 content15=255 content14=255 content13=255 content12=255 content11=255 content10 content09 content08 content07 content06 content05 content04 content03 content02 content01 content00 pwm=applied luminance content pwm=max. pwm=applied 255 level=16 content7=255 content05 content04 content03 content02 content01 content00 pwm=applied 255 level=8 content6=255 content3=255 content02 content01 content00 pwm=applied 255 level=4 9. table2 bls + 0020h bls_applied_contra sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast00[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast01[15:0] type r/w reset 0 10. table2 bls + 0024h bls_applied_contra stb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast02[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast03[15:0] type r/w reset 0 11. table2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 713 of 1535 bls + 0028h bls_applied_contra stc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast04[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast05[15:0] type r/w reset 0 12. table2 bls + 002ch bls_applied_contra std bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast06[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast07[15:0] type r/w reset 0 13. table2 bls + 0030h bls_applied_contra ste bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast08[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast09[15:0] type r/w reset 0 14. table2 bls + 0034h bls_applied_contra stf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast10[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast11[15:0] type r/w reset 0 15. table2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 714 of 1535 bls + 0038h bls_applied_contra stg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast12[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast13[15:0] type r/w reset 0 16. table2 bls + 003ch bls_applied_contra sth bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_applied_contrast14[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_applied_contrast15[15:0] type r/w reset 0 comments: we calculate the contrast using the table0 and table1 according to the following formula. ) ( ) ( 1 2 3 4 x x x x contrast ? ? = , where 3 4 , x x means table1 (applied pwm)?s content where 1 2 , x x means table0 (max. pwm)?s content 3 1 1 2 3 4 ) ( ) ( ) ( x x x x x x x x pre cur + ? ? ? = 255 content luminance (x1,y1) (x2,y2) (x3,y3) (x4,y4) 16 32 48 64 80 96 112 luma pre x cur x free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 715 of 1535 17. machine1 contrast bls + 0040h bls_machine1_contr ast bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m1_contrast[15:0] type r/w reset 0 comment: m1_contrast: 16 bits unsigned floating point, 8 bits unsigned integer 8 bits unsigned decimal. 18. machine1 brightness bls + 0044h bls_machine1_brightne ss bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m1_brightness1[8:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m1_brightness0[8:0] type r/w reset 0 comment: m1_brightness1: 9 bits signed integer with 2?s complement. m1_brightness0: 9 bits signed integer with 2?s complement. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 716 of 1535 19. machine1 selector bls + 0048h bls_machine1_selec tor bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m1_mode_sel[2:0] m1_src_sel[2:0] type r/w r/w reset 0 0 comment: m1_mode_sel[0]: 1->rgb_in_content, 0->sat1 output m1_mode_sel[1]: 1->sat3 output, 0->sat4 output m1_mode_sel[2]: 1->mux output, 0->rgb_in_content m1_src_sel[0] : 1->table output content(-), 0->m1_brightness0 m1_src_sel[1] : 1->table output contrast, 0->m1_contrast m1_src_sel[2] : 1->table output content(+), 0->m1_brightness1 20. machine2 contrast bls + 004ch bls_machine2_contr ast bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m2_contrast[15:0] type r/w reset 0 comment: m2_contrast: 16 bits unsigned floating point, 8 bits unsigned integer 8 bits unsigned decimal. 21. machine2 brightness bls + 0050h bls_machine2_brightne ss bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m2_brightness1[8:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m2_brightness0[8:0] type r/w reset 0 comment: m2_brightness1: 9 bits signed integer with 2?s complement. m2_brightness0: 9 bits signed integer with 2?s complement. 22. machine2 selector free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 717 of 1535 bls + 0054h bls_machine2_selec tor bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m2_mode_sel[2:0] m2_src_sel[2:0] type r/w r/w reset 0 0 comment: m2_mode_sel[0]: 1->rgb_in_content, 0->sat1 output m2_mode_sel[1]: 1->sat3 output, 0->sat4 output m2_mode_sel[2]: 1->mux output, 0->rgb_in_content m2_src_sel[0] : 1->table output content(-), 0->m2_brightness0 m2_src_sel[1] : 1->table output contrast, 0->m2_contrast m2_src_sel[2] : 1->table output content(+), 0->m2_brightness1 comment: 23. path selector bls + 0058h bls_setting bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bls_level_num[3:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bls_path_sel[1:0] type r/w reset 0 comment: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 718 of 1535 contrast/brightness machine1 r contrast/brightness machine1 g contrast/brightness machine1 b lcd_data_in [23:16] [15: 8] [ 7: 0] contrast/brightness machine2 r contrast/brightness machine2 g contrast/brightness machine2 b [23:16] [15: 8] [ 7: 0] dpi_data_in bls_path_sel[0] histogram ff ff ff ff frame_en [23:16] [15: 8] [ 7: 0] [23:16] [15: 8] [ 7: 0] dpi_data_out lcd_data_out bls_path_sel[1] 1 0 1 0 1 0 1 0 1 0 1 0 bls_level_num: 1~16 levels. 0 means 1 level, 15 means 16 levels bls_path_sel[0]: 0->dpi, 1->machine1 bls_path_sel[1]: 0->machine1, 1-> machine2 24. histogram bin00 bls + 005ch bls_histogram bin0 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin00[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin00[15:0] type r reset 0 25. histogram bin01 bls + 0060h bls_histogram bin0 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin01[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin01[15:0] type r reset 0 26. histogram bin02 bls + 0064h bls_histogram bin0 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 719 of 1535 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin02[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin02[15:0] type r reset 0 27. histogram bin03 bls + 0068h bls_histogram bin0 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin03[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin03[15:0] type r reset 0 28. histogram bin04 bls + 006ch bls_histogram bin0 4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin04[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin04[15:0] type r reset 0 29. histogram bin05 bls + 0070h bls_histogram bin0 5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin05[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin05[15:0] type r reset 0 30. histogram bin06 bls + 0074h bls_histogram bin0 6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 720 of 1535 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin06[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin06[15:0] type r reset 0 31. histogram bin07 bls + 0078h bls_histogram bin0 7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin07[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin07[15:0] type r reset 0 32. histogram bin08 bls + 007ch bls_histogram bin0 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin08[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin08[15:0] type r reset 0 33. histogram bin09 bls + 0080h bls_histogram bin0 9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin09[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin09[15:0] type r reset 0 34. histogram bin00 bls + 0084h bls_histogram bin1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 721 of 1535 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin10[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin10[15:0] type r reset 0 35. histogram bin11 bls + 0088h bls_histogram bin1 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin11[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin11[15:0] type r reset 0 36. histogram bin12 bls + 008ch bls_histogram bin1 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin12[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin12[15:0] type r reset 0 37. histogram bin13 bls + 0090h bls_histogram bin1 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin13[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin13[15:0] type r reset 0 38. histogram bin14 bls + 0094h bls_histogram bin1 4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 722 of 1535 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin14[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin14[15:0] type r reset 0 39. histogram bin15 bls + 0098h bls_histogram bin1 5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bin15[20:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin15[15:0] type r reset 0 comment: 40. histogram enable bls + 009ch bls_histogram ena ble bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name his_en free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 723 of 1535 type r/w reset 0 comment: en=1: histogram start to active en=0: histogram not work 41. histogram clear bls + 00a0h bls_histogram_cle ar bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name his_clr type r/w reset 0 comment: clr=1: clear the bin00~bin15 to 0, should be turn on when en=0 clr=0: no clear 42. histogram done bls + 00a4h bls_histogram_don e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name his_done type r/w reset 0 comment: done=1: histogram has finished one frame done=0: histogram hasn?t finished one frame the done should be clear when software finish his job. 43. histogram done mask bls + 00a8h bls_histogram_done_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name his_done_en type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 724 of 1535 comment: histogram?s interrupt mask it will be active when his_done = 1 and his_done_en = 1 44. histogram setting bls + 00ach bls_histogram_set ting bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 his_donec his_aclr r/w r/w 0 0 comment: donec: done auto continue. when histogram finish one frame and turn on this bit it will auto continue to calculate next frame?s histogram. aclr: auto clear. when histogram finish one frame and turn on this bit it will auto clear the bin data when next frame is start. 5.4 camera interface sensor tg lens/ sensor compensation color process *41 MT6516 isp incorporates a feature rich image signal processor to connect with a variety of image sensor components. this processor consists of timing generated unit (tg) and lens/sensor compensation unit and image process unit. timing generated unit (tg) cooperates with master type image sensor only. that means sensor should send vertical and horizontal signals to tg. tg offers sensor required data clock and receive sensor bayer pattern raw data by internal auto synchronization or external pixel clock synchronization. the main purpose of tg is to create data clock for master type image sensor and accept vertical/horizontal synchronization signal and sensor data, and then generate grabbed area of bayer data or yuv422/rgb565 data to the lens/sensor compensation unit. lens/sensor compensation unit generates compensated raw data to the color process unit in bayer raw data input mode. in yuv422/rgb565 input mode, this stage is bypassed. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 725 of 1535 color process unit accepts bayer pattern raw data or yuv422/rgb565 data that is generated by lens/sensor compensation unit. the output of isp is ycbcr 888 data format which can be easily encoded by the compress engine (jpeg encoder and mpeg4 encoder). it can be the basic data domain of other data format translation such as r/g/b domain. the isp is pipelined, and during processing stages isp hardware can auto extract meaningful information for further ae/af/awb calculation. these information are temporary stored on isp registers or memory and can be read back by mcu. 5.4.1 register table register address register name synonym cam + 0000h tg phase counter register cam_phscnt cam + 0004h sensor size configuration register cam_camwin cam + 0008h tg grab range start/end pixel configuration register cam_grabcol cam + 000ch tg grab range start/end line configuration register cam_grabrow cam + 0010h sensor mode configuration register cam_csmode cam + 0014h component r, gr, b, gb, offset adjustment register cam_rgboff cam + 0018h view finder mode control register cam_vfcon cam + 001ch camera module interrupt enable register cam_inten cam + 0020h camera module interrupt status register cam_intsta cam + 0024h camera module path config register cam_path cam + 0028h camera module input address register cam_inaddr cam + 002ch camera module output address register cam_outaddr cam + 0030h preprocessing control register 1 cam_ctrl1 cam + 0034h awb r,g, b gain control register 1 cam_rgbgain1 cam + 0038h awb r,g, b gain control register 2 cam_rgbgain2 cam + 003ch histogram boundary control register 1 cam_his0 cam + 0040h histogram boundary control register 2 cam_his1 cam + 0044h preprocessing control register 2 cam_ctrl2 cam + 0048h ae window 1 register cam_aewin1 cam + 004ch ae histogram window register cam_ aewin2 cam + 0050h ae histogram gain register cam_ aewin3 cam + 0054h global shutter control register cam_gsctrl cam + 0058h mechanical shutter control register cam_msctrl cam + 005ch mechanical shutter m1 setting register cam_ms1time cam + 0060h mechanical shutter m2 setting register cam_ms2time cam + 0064h reserved reserved cam + 0068h reserved reserved cam + 006ch awb window register cam_awbwin cam + 0070h color processing stage control register cam_cpscon1 cam + 0074h interpolation register 1 cam_inter1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 726 of 1535 cam + 0078h interpolation register 2 cam_inter2 cam + 007ch edge core register cam_edgcore cam + 0080h edge gain register 1 cam_edggain1 cam + 0084h edge gain register 2 cam_edggain2 cam + 0088h edge threshold register cam_edgthre cam + 008ch edge vertical control register cam_edgvcon cam + 0090h reserved reserved cam + 0094h reserved reserved cam + 0098h reserved reserved cam + 009ch color matrix 1 register cam_matrix1 cam + 00a0h color matrix 2 register cam_matrix2 cam + 00a4h color matrix 3 register cam_matrix3 cam + 00a8h reserved reserved cam + 00ach color process stage control register 2 cam_cpscon2 cam + 00b0h flare gain register cam_flregain cam + 00b4h flare offset register cam_flreoff cam + 00b8h y channel configuration register cam_ychan cam + 00bch rgb2ycc control register rgb2ycc_con cam + 00c0h reserved reserved cam + 00c4h reserved reserved cam + 00c8h reserved reserved cam + 00cch reserved reserved cam + 00d0h reserved reserved cam + 00d4h reserved reserved cam + 00d8h reserved reserved cam + 00dch reserved reserved cam + 00e0h reserved reserved cam + 00e4h mipi csi2 status register 1 cam_csi2sta1 cam + 00e8h mipi csi2 status register 2 cam_csi2sta2 cam + 00ech reserved reserved cam + 00f0h reserved reserved cam + 00f4h reserved reserved cam + 00f8h reserved reserved cam + 00fch reserved reserved cam + 0100h reserved reserved cam + 0104h reserved reserved cam + 0108h flare histogram 1 result cam_his_rlt0 cam + 010ch flare histogram 2 result cam_his_rlt1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 727 of 1535 cam + 0110h flare histogram 3 result cam_his_rlt2 cam + 0114h flare histogram 4 result cam_his_rlt3 cam + 0118h flare histogram 5 result cam_his_rlt4 cam + 011ch reserved reserved cam + 0120h reserved reserved cam + 0124h reserved reserved cam + 0128h vertical subsample control register cam_vsub cam + 012ch horizontal subsample control register cam_hsub cam + 0130h reserved reserved cam + 0134h reserved reserved cam + 0138h reserved reserved cam + 013ch reserved reserved cam + 0140h reserved reserved cam + 0144h reserved reserved cam + 0148h reserved reserved cam + 014ch reserved reserved cam + 0150h reserved reserved cam + 0154h defect pixel configuration register cam_defect0 cam + 0158h defect pixel table address register cam_defect1 cam + 015ch defect pixel table debug register cam_defect2 cam + 0160h reserved reserved cam + 0164h reserved reserved cam + 0168h reserved reserved cam + 016ch raw gain register 1 cam_rawgain0 cam + 0170h raw gain register 2 cam_rawgain1 cam + 0174h result window vertical size register rwinv_sel cam + 0178h result window horizontal size register rwinh_sel cam + 017ch reserved reserved cam + 0180h camera interface debug mode control register cam_debug cam + 0184h camera module debug information write out destination address cam_dstaddr cam + 0188h camera module debug information last transfer destination address cam_lstaddr cam + 018ch camera module frame buffer transfer out count register cam_xfercnt cam + 0190h sensor test module configuration register 1 cam_mdlcfg1 cam + 0194h sensor test module configuration register 2 cam_mdlcfg2 cam + 0198h reserved reserved cam + 019ch reserved reserved cam + 01a0h reserved reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 728 of 1535 cam + 01a4h reserved reserved cam + 01a8h gamma register 1 gma_reg1 cam + 01ach gamma register 2 gma_reg2 cam + 01b0h gamma register 3 gma_reg3 cam + 01b4h gamma register 4 gma_reg4 cam + 01b8h gamma register 5 gma_reg5 cam + 01bch raw data accumulation config register rawacc cam + 01c0h raw data accumulation window rawwin cam + 01c4h raw data accumulation result 1 rawsum0 cam + 01c8h raw data accumulation result 2 rawsum1 cam + 01cch raw data accumulation result 3 rawsum2 cam + 01d0h raw data accumulation result 4 rawsum3 cam + 01d4h reserved reserved cam + 01d8h cam reset register cam_reset cam + 01dch tg status register tg_status cam + 01e0h flash control 1 register flash_ctrl0 cam + 01e4h flash control 2 register flash_ctrl1 cam + 01e8h flashb control 1 register flashb_ctrl0 cam + 01ech flashb control 2 register flashb_ctrl1 cam + 01f0h flare histogram 6 result cam_his_rlt5 cam + 01f4h flare histogram 7 result cam_his_rlt6 cam + 01f8h flare histogram 8 result cam_his_rlt7 cam + 01fch flare histogram 9 result cam_his_rlt8 cam + 0200h flare histogram 10 result cam_his_rlt9 cam + 0204h reserved reserved cam + 0208h reserved reserved cam + 020ch reserved reserved cam + 0210h reserved reserved cam + 0214h shading control 1 register cam_shading1 cam + 0218h shading control 2 register cam_shading2 cam + 021ch shading read address register sd_raddr cam + 0220h shading last block config register sd_lblock cam + 0224h shading ratio config register sd_ratio cam + 0228h reserved reserved cam + 022ch reserved reserved cam + 0230h ee control register ee_ctrl cam + 0234h ed lut x configuration ed_lut_x cam + 0238h ed lut y configuration ed_lut_y free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 729 of 1535 cam + 023ch reserved reserved cam + 0240h reserved reserved cam + 0244h reserved reserved cam + 0248h reserved reserved cam + 024ch af window 1 register cam_afwin0 cam + 0250h af window 2 register cam_afwin1 cam + 0254h af window 3 register cam_afwin2 cam + 0258h af window 4 register cam_afwin3 cam + 025ch af window 5 register cam_afwin4 cam + 0260h af threshold 1 register cam_afth0 cam + 0264h af threshold 2 register cam_afth1 cam + 0268h af window 6 register cam_afwin5 cam + 026ch af window 7 register cam_afwin6 cam + 0270h af window 8 register cam_afwin7 cam + 0274h cam version register cam_version cam + 027ch awb sum window config register awbsum_win cam + 0280h awb control register awb_ctrl cam + 0284h awb threshold config register awb_th cam + 0288h awb color space h1 config register awbxy_h1 cam + 028ch awb color space h2 config register awbxy_h2 cam + 0290h awb color edge window horizontal config register awbce_winh cam + 0294h awb color edge window vertical config register awbce_winv cam + 0298h awb xy window 1 horizontal config register awbxy_winh0 cam + 029ch awb xy window 1 vertical config register awbxy_winv0 cam + 02a0h awb xy window 2 horizontal config register awbxy_winh1 cam + 02a4h awb xy window 2 vertical config register awbxy_winv1 cam + 02a8h awb xy window 3 horizontal config register awbxy_winh2 cam + 02ach awb xy window 3 vertical config register awbxy_winv2 cam + 02b0h awb xy window 4 horizontal config register awbxy_winh3 cam + 02b4h awb xy window 4 vertical config register awbxy_winv3 cam + 02b8h awb xy window 5 horizontal config register awbxy_winh4 cam + 02bch awb xy window 5 vertical config register awbxy_winv4 cam + 02c0h awb xy window 6 horizontal config register awbxy_winh5 cam + 02c4h awb xy window 6 vertical config register awbxy_winv5 cam + 02c8h awb xy window 7 horizontal config register awbxy_winh6 cam + 02cch awb xy window 7 vertical config register awbxy_winv6 cam + 02d0h awb xy window 8 horizontal config register awbxy_winh7 cam + 02d4h awb xy window 8 vertical config register awbxy_winv7 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 730 of 1535 cam + 02d8h awb xy window 9 horizontal config register awbxy_winh8 cam + 02dch awb xy window 9 vertical config register awbxy_winv8 cam + 02e0h awb xy window 10 horizontal config register awbxy_winh9 cam + 02e4h awb xy window 10 vertical config register awbxy_winv9 cam + 02e8h awb xy window 11 horizontal config register awbxy_winha cam + 02ech awb xy window 11 vertical config register awbxy_winva cam + 02f0h awb xy window 12 horizontal config register awbxy_winhb cam + 02f4h awb xy window 12 vertical config register awbxy_winvb cam + 02f8h awb sum window paxel count awbsum_pcnt cam + 02fch awb sum window r sum awbsum_rsum cam + 0300h awb sum window g sum awbsum_gsum cam + 0304h awb sum window b sum awbsum_bsum cam + 0308h awb color edge window paxel count awbce_pcnt cam + 030ch awb color edge window r sum awbce_rsum cam + 0310h awb color edge window g sum awbce_gsum cam + 0314h awb color edge window b sum awbce_bsum cam + 0318h awb xy window 1 paxel count awbxy_pcnt0 cam + 031ch awb xy window 1 r sum awbxy_rsum0 cam + 0320h awb xy window 1 g sum awbxy_gsum0 cam + 0324h awb xy window 1 b sum awbxy_bsum0 cam + 0328h awb xy window 2 paxel count awbxy_pcnt1 cam + 032ch awb xy window 2 r sum awbxy_rsum1 cam + 0330h awb xy window 2 g sum awbxy_gsum1 cam + 0334h awb xy window 2 b sum awbxy_bsum1 cam + 0338h awb xy window 3 paxel count awbxy_pcnt2 cam + 033ch awb xy window 3 r sum awbxy_rsum2 cam + 0340h awb xy window 3 g sum awbxy_gsum2 cam + 0344h awb xy window 3 b sum awbxy_bsum2 cam + 0348h awb xy window 4 paxel count awbxy_pcnt3 cam + 034ch awb xy window 4 r sum awbxy_rsum3 cam + 0350h awb xy window 4 g sum awbxy_gsum3 cam + 0354h awb xy window 4 b sum awbxy_bsum3 cam + 0358h awb xy window 5 paxel count awbxy_pcnt4 cam + 035ch awb xy window 5 r sum awbxy_rsum4 cam + 0360h awb xy window 5 g sum awbxy_gsum4 cam + 0364h awb xy window 5 b sum awbxy_bsum4 cam + 0368h awb xy window 6 paxel count awbxy_pcnt5 cam + 036ch awb xy window 6 r sum awbxy_rsum5 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 731 of 1535 cam + 0370h awb xy window 6 g sum awbxy_gsum5 cam + 0374h awb xy window 6 b sum awbxy_bsum5 cam + 0378h awb xy window 7 paxel count awbxy_pcnt6 cam + 037ch awb xy window 7 r sum awbxy_rsum6 cam + 0380h awb xy window 7 g sum awbxy_gsum6 cam + 0384h awb xy window 7 b sum awbxy_bsum6 cam + 0388h awb xy window 8 paxel count awbxy_pcnt7 cam + 038ch awb xy window 8 r sum awbxy_rsum7 cam + 0390h awb xy window 8 g sum awbxy_gsum7 cam + 0394h awb xy window 8 b sum awbxy_bsum7 cam + 0398h awb xy window 9 paxel count awbxy_pcnt8 cam + 039ch awb xy window 9 r sum awbxy_rsum8 cam + 03a0h awb xy window 9 g sum awbxy_gsum8 cam + 03a4h awb xy window 9 b sum awbxy_bsum8 cam + 03a8h awb xy window 10 paxel count awbxy_pcnt9 cam + 03ach awb xy window 10 r sum awbxy_rsum9 cam + 03b0h awb xy window 10 g sum awbxy_gsum9 cam + 03b4h awb xy window 10 b sum awbxy_bsum9 cam + 03b8h awb xy window 11 paxel count awbxy_pcnta cam + 03bch awb xy window 11 r sum awbxy_rsuma cam + 03c0h awb xy window 11 g sum awbxy_gsuma cam + 03c4h awb xy window 11 b sum awbxy_bsuma cam + 03c8h awb xy window 12 paxel count awbxy_pcntb cam + 03cch awb xy window 12 r sum awbxy_rsumb cam + 03d0h awb xy window 12 g sum awbxy_gsumb cam + 03d4h awb xy window 12 b sum awbxy_bsumb cam + 03d8h reserved reserved cam + 03dch reserved reserved cam + 03e0h reserved reserved cam + 03e4h reserved reserved cam + 03e8h reserved reserved cam + 03ech reserved reserved cam + 03f0h reserved reserved cam + 03f4h reserved reserved cam + 03f8h reserved reserved cam + 03fch reserved reserved cam + 0400h af window 1 threshold 1 focus value af0_sum0 cam + 0404h af window 1 threshold 2 focus value af0_sum1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 732 of 1535 cam + 0408h af window 1 threshold 3 focus value af0_sum2 cam + 040ch af window 1 threshold 4 focus value af0_sum3 cam + 0410h af window 1 threshold 5 focus value af0_sum4 cam + 0414h af window 2 threshold 1 focus value af1_sum0 cam + 0418h af window 2 threshold 2 focus value af1_sum1 cam + 041ch af window 2 threshold 3 focus value af1_sum2 cam + 0420h af window 2 threshold 4 focus value af1_sum3 cam + 0424h af window 2 threshold 5 focus value af1_sum4 cam + 0428h af window 3 threshold 1 focus value af2_sum0 cam + 042ch af window 3 threshold 2 focus value af2_sum1 cam + 0430h af window 3 threshold 3 focus value af2_sum2 cam + 0434h af window 3 threshold 4 focus value af2_sum3 cam + 0438h af window 3 threshold 5 focus value af2_sum4 cam + 043ch af window 4 threshold 1 focus value af3_sum0 cam + 0440h af window 4 threshold 2 focus value af3_sum1 cam + 0444h af window 4 threshold 3 focus value af3_sum2 cam + 0448h af window 4 threshold 4 focus value af3_sum3 cam + 044ch af window 4 threshold 5 focus value af3_sum4 cam + 0450h af window 5 threshold 1 focus value af4_sum0 cam + 0454h af window 5 threshold 2 focus value af4_sum1 cam + 0458h af window 5 threshold 3 focus value af4_sum2 cam + 045ch af window 5 threshold 4 focus value af4_sum3 cam + 0460h af window 5 threshold 5 focus value af4_sum4 cam + 0464h af window 6 threshold 1 focus value af5_sum0 cam + 0468h af window 6 threshold 2 focus value af5_sum1 cam + 046ch af window 6 threshold 3 focus value af5_sum2 cam + 0470h af window 6 threshold 4 focus value af5_sum3 cam + 0474h af window 6 threshold 5 focus value af5_sum4 cam + 0478h af window 7 threshold 1 focus value af6_sum0 cam + 047ch af window 7 threshold 2 focus value af6_sum1 cam + 0480h af window 7 threshold 3 focus value af6_sum2 cam + 0484h af window 7 threshold 4 focus value af6_sum3 cam + 0488h af window 7 threshold 5 focus value af6_sum4 cam + 048ch af window 8 threshold 1 focus value af7_sum0 cam + 0490h af window 8 threshold 2 focus value af7_sum1 cam + 0494h af window 8 threshold 3 focus value af7_sum2 cam + 0498h af window 8 threshold 4 focus value af7_sum3 cam + 049ch af window 8 threshold 5 focus value af7_sum4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 733 of 1535 cam + 04a0h af window 1 g accumulation value af0_gsum cam + 04a4h af window 2 g accumulation value af1_gsum cam + 04a8h af window 3 g accumulation value af2_gsum cam + 04ach af window 4 g accumulation value af3_gsum cam + 04b0h af window 5 g accumulation value e af4_gsum cam + 04b4h af window 6 g accumulation value af5_gsum cam + 04b8h af window 7 g accumulation value af6_gsum cam + 04bch af window 8 g accumulation value e af7_gsum cam + 0500h nr2 control register nr2_con cam + 0504h reserved reserved cam + 0508h nr2 configuration register 2 nr2_cfg2 cam + 050ch nr2 configuration register 3 nr2_cfg3 cam + 0510h nr2 configuration register 4 nr2_cfg4 cam + 0514h reserved reserved cam + 0518h reserved reserved cam + 051ch reserved reserved cam + 0520h gdc control register gdc_con cam + 0524h gdc weighting table configuration gdc_wtbl cam + 0528h gdc manual curve configuration 1 gdc_mmc1 cam + 052ch gdc manual curve configuration 2 gdc_mmc2 cam + 0530h gdc manual curve configuration 3 gdc_mmc3 cam + 0534h gdc manual curve configuration 4 gdc_mmc4 cam + 0538h gdc manual curve configuration 5 gdc_mmc5 cam + 053ch gdc manual curve configuration 6 gdc_mmc6 cam + 0540h hst control register hst_con cam + 0544h hst configuration register 1 hst_cfg1 cam + 0548h hst configuration register 2 hst_cfg2 cam + 054ch hst configuration register 3 hst_cfg3 cam + 0550h nr1 control register nr1_con cam + 0554h nr1 defective pixel configuration register 1 nr1_dp1 cam + 0558h nr1 defective pixel configuration register 2 nr1_dp2 cam + 055ch nr1 defective pixel configuration register 3 nr1_dp3 cam + 0560h nr1 defective pixel configuration register 4 nr1_dp4 cam + 0564h nr1 crosstalk compensation configuration register nr1_ct cam + 0568h nr1 noise reduction configuration register 1 nr1_nr1 cam + 056ch nr1 noise reduction configuration register 2 nr1_nr2 cam + 0570h nr1 noise reduction configuration register 3 nr1_nr3 cam + 0574h nr1 noise reduction configuration register 4 nr1_nr4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 734 of 1535 cam + 0578h nr1 noise reduction configuration register 5 nr1_nr5 cam + 057ch nr1 noise reduction configuration register 6 nr1_nr6 cam + 0580h nr1 noise reduction configuration register 7 nr1_nr7 cam + 0584h nr1 noise reduction configuration register 8 nr1_nr8 cam + 0588h nr1 noise reduction configuration register 9 nr1_nr9 cam + 058ch nr1 noise reduction configuration register 10 nr1_nr10 cam + 0600h yccgo control register yccgo_con cam + 0604h yccgo configuration register 1 yccgo_cfg1 cam + 0608h yccgo configuration register 2 yccgo_cfg2 cam + 060ch yccgo configuration register 3 yccgo_cfg3 cam + 0610h yccgo configuration register 4 yccgo_cfg4 cam + 0614h yccgo configuration register 5 yccgo_cfg5 cam + 0618h yccgo configuration register 6 yccgo_cfg6 cam +(1000h ~ 104ch) ae window result 1~20 aemem(0~19) cam + (1050h ~ 105ch) ae block count, bayer size, awb debug 1,awb debug 2 cam + (1060h ~ 1084h) flare histogram result (1-10) flaremem(0~9) cam + (1088h ~ 1124h) af filter (1-48) cam + (1128h ~ 1144h) af mean (1-8) cam + (1148h ~1204h) awb xy window result(1-12) (count, rsum, gsum, bsum) cam + (1208h ~ 1214h) awb sum window result (count, rsum, gsum, bsum) cam + (1218h ~ 1224h) awb color edge window result (count, rsum, gsum, bsum) cam + (1228h ~ 1324h) ae histogram result (1-64) aehis(0~63) cam + 2000h reserved reserved cam + 3000h awb r histogram memory awbrhis cam + 4000h awb g histogram memory awbghis cam + 5000h awb b histogram memory awbbhis cam + 6000h gdc histogram memory gdchis free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 735 of 1535 table 97 camera interface register map 5.4.1.1 tg register definitions cam+0000h tg phase counter register cam_phscnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcen clke n clkp ol clkcnt clkrs clkfl type r/w r/w r/w r/w r/w r/w reset 0 0 0 1 0 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hvali d_en pxclk _en pxclk _inv pxclk _in clkfl _pol tgcl k_sel pixcnt dlatch type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 1 1 pcen tg phase counter enable control clken enable sensor master clock (mclk) output to sensor. note that to set sensor master clock driving, please set 0x80001500 bit[12] (add 8ma), bit[13] (add 4ma), bit[15] (slew rate fast). clkpol sensor master clock polarity control clkcnt sensor master clock frequency divider control. sensor master clock will be 104mhz/clkcnt, where clkcnt >=1. clkrs sensor master clock rising edge control clkfl sensor master clock falling edge control hvalid_en sensor hvalid or href enable pxclk_en sensor clock input monitor. pxclk_inv pixel clock inverse pxclk_in pixel clock sync enable. if sensor master based clock is camera pll, pxclk_in must be enabled. for mipi csi2, pxclk_in must be enabled, too. clkfl_pol sensor clock falling edge polarity tgclk_sel sensor master based clock selection (0: 104 mhz, 1: camera pll) pixcnt sensor data latch frequency control dlatch sensor data latch position control example waveform( clkcnt=1,clkrs=0,clkfl=1,pixcnt=3,dlatch=2 ) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 736 of 1535 *oufsobm$mpdl4zod 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 52mhz mclk pclk bclk $-,$/5 $-,34 $-,'- sensor output signals isp output signals 1*9$/5 %-"5$) hsync 1 2 3 1jyfm@*% 4 5 0 1 0 cam+0004h sensor size config uration register cam_camwin bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pixels type r/w reset fffh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lines type r/w reset fffh pixel total input pixel number line total input line number cam+0008h tg grab range start/end pixel configuration register cam_grabco l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name start type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end type r/w reset 0 start grab start pixel number (first pixel start from 0) end grab end pixel number (first pixel start from 0) cam+000ch tg grab range start/end line configuration register cam_grabro w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 737 of 1535 name start type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end type r/w reset 0 start grab start line number (first line start from 0) end grab end line number (first line start from 0) cam+0010h sensor mode configuration register cam_csmode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memin_dummyline[21:16] type r/w reset 48 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csi2_ ph_se l csi2_ ecc_e n dlan e4_en dlan e2_en csi2_ en vspol hspo l pwro n rst auto en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 memin_dummyline memory input dummy line count csi2_ph_sel mipi csi2 packet header selection. 0 packet header decoded as {di_byte[7:0],wc_number[7:0],wc_number[15:8]} 1 packet header decoded as {wc_number[15:0],di_byte[7:0]} csi2_ecc_en mipi csi2 error correct code enable dlane4_en mipi csi2 4 data lane enable dlane2_en mipi csi2 2 data lane enable csi2_en mipi csi2 eanble vspol sensor vsync input polarity hspol sensor hsync input polarity auto auto lock sensor input horizontal pixel numbers enable en sensor process counter enable cam+0014h component offset adjustment register cam_rgboff bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name s00 off00 s01 off01 type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name s10 off10 s11 off11 type r/w r/w r/w r/w reset 0 0 0 0 s00 sign of raw data (0,0) offset adjustment control, 0 : positive 1: negative off00 raw data (0,0) offset adjustment s01 sign of raw data (0,1) offset adjustment control, 0 : positive 1: negative free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 738 of 1535 off01 raw data (0,1) offset adjustment s10 sign of raw data (1,0) offset adjustment control, 0 : positive 1: negative off10 raw data (1,0) offset adjustment s11 sign of raw data (1,1) offset adjustment control, 0 : positive 1: negative off11 raw data (1,1) offset adjustment 'jstu4ubsu 1jyfm cam+0018h view finder mode control register cam_vfcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name av_sy nc_se l vd_in t_pol av_sync_lineno[11:0] type r/w r/w r/w reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sp_delay[2:0] sp_m ode take_ pic fr_con type r/w r/w r/w r/w reset 0 0 0 0 av_sync_sel av_sync start point selection 0 start from av_sync_lineno 1 start from vsync vd_int_pol vsync interrupt polarity 0 vsync rising edge 1 vsync falling edge av_sync_lineno av_sync desired line counts sp_delay[2:0] still picture mode frame delay. when sp_delay is nonzero, take_pic will start to trigger after sp_delay frames sp_mode still picture mode 0 preview mode, isp will process every frame sensor send 1 capture mode, isp will only process first frame sensor send after take_pic is set take_pic take picture request fr_con frame sampling rate control 000 every frame is sampled 001 one frame is sampled every 2 frames 010 one frame is sampled every 3 frames 011 one frame is sampled every 4 frames 100 one frame is sampled every 5 frames 101 one frame is sampled every 6 frames 110 one frame is sampled every 7 frames free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 739 of 1535 111 one frame is sampled every 8 frames cam+001ch camera module interrupt enable register cam_inten bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vsyn c_int _en reszl b_en type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name av_sy nc_in t flash _int atf_i nt aedo ne ispdo ne idle gmco vrun rezo vrun expd o type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 vsync_int_en vsync interrupt and flash interrupt switch 0 flash interrupt 1 vsync interrupt reszlb_en resz_lb (resizer dedicate line buffer) enable. note that crz and prz should turn off resz_lb when isp use it 0 use demo-saic line buffer as raw data dump buffer 1 use resz_lb as raw data dump buffer av_sync_int av sync interrupt enable flash_int flash interrupt enable, note that vsync_int_en switch flash and vsync interrupt aedone ae done interrupt enable ispdone isp done interrupt enable idle returning idle state interrupt enable gmcovrun gmc port over run interrupt enable rezovrun crz overrun interrupt enable expdo exposure done interrupt enable cam+0020h camera module interrupt status register cam_intsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name av_sy nc_in t flash _int atf_i nt aedo ne ispdo ne idle gmco vrun rezo vrun expd o type r/w r r r r r r r r reset 0 0 0 0 0 0 0 0 0 av_sync_int av sync interrupt status, occurred when desired line count equal av_sync_lineno in cam_vfcon(cam+0018h), read clear flash_int tg interrupt status, occurred when flash light pulse is done, read clear aedone ae done interrupt status, occurred when 3a statistic is ok for current frame, read clear free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 740 of 1535 ispdone isp done interrupt status, occurred when isp finish full frame process, read clear idle returning idle state interrupt status, occurred when isp is in idle state, read clear gmcovrun gmc port overrun interrupt status, occurred when isp to memory buffer is overrun, read clear rezovrun resizer over run interrupt status, occurred when isp to crz buffer is overrun, read clear expdo exposure done interrupt status, occurred when sensor send full frame, read clear cam+0024h camera module path config register cam_path bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cnto n cntmode write_level baye r10_o ut rez_d iscon n outpath_ty pe memw_gburst[2:0] outp ath_ en type r/w r/w r/w r/w rw r/w r/w r/w reset 0 0 3 0 0 0 3 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name swap _y swap _cbc r indat a_for mat intype_sel inpath_rate baye r10_in inpat h_lin e_dis inpat h_thr ot_di s inpat h_se l type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 cnton enable debug mode data transfer counter cntmode data transfer count selection 00 srgb count 01 ycbcr count others reserved write_level isp output buffer level, used when isp dump data to memory rez_disconn crz disconnect enable, used when isp dump data to memory 0 connect crz to isp output 1 disconnect crz to isp output bayer10_out bayer output format selection, note that outpath_type should be set to 00 0 dump 8-bit bayer data. for 8-bit bayer output, memory format is { pixel3[7:0],pixel2[7:0],pixel1[7:0],pixel0[7:0]} 1 dump 10-bit bayer data. for 10-bit bayer output, memory format is {2?b0,pixel2[9:0],pixel1[9:0],pixel0[9:0]} outpath_type output path type selection 00 bayer format, note that reszlb_en (001c[24]) should be set to 1 01 isp output 02 rgb888 format 03 rgb565 format memw_gburst memory write burst setting. (burst 16-4 setting is recommended) 00 single access 03 burst4-4 access 07 burst16-4 access, only available in bayer output mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 741 of 1535 for bayer 8-bit output mode, output pixel number must be multiples of 4*4, while for bayer 10-bit output mode, output pixel number must be multiples of 3*4. outpath_en 0 isp dump data to memory disable 1 isp dump data to memory enable swap_y ycbcr in swap y, note that intype_sel should be set to 001 or 101 swap_cbcr ycbcr in swap cb cr, note that intype_sel should be set to 001 or 101 indata_format sensor input data bit-order selection, used in isp yuv422/ycbcr422/rgb565 format. data input in isp is 10-bit, datain[9:0] 0 datain[7:0] as raw data input 1 datain[9:2] as raw data input intype_sel input type selection 000 bayer format 001 yuv422 format 101 ycbcr422 format 010 rgb565 format others reserved to enable yuv422/ycbcr422 input fast mode, refer to cam + 011c bit 20 inpath_rate input type rate control bayer10_in memory input path bayer data memory format 0 8-bit bayer data, 4 bayer data packed in one word(32-bit) as (bayer3[7:0],bayer2[7:0],bayer1[7:0],bayer0[7:0]) 1 10-bit bayer data, 2 bayer data packed in one word(32-bit) as (6?b0,bayer1[9:0],6?b0,bayer0[9:0]) inpath_line_dis input path line mode disable. inpath_throt_dis input path throttle disable inpath_sel input path selection 0 sensor input 1 from memory note that when memory input enable, bayer output is not supported. cam+0028h camera module input address register cam_inaddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_inaddr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_inaddr[15:0] type r/w reset 0 cam_inaddr input memory address, used when isp is in memory mode ( inpath_sel =1) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 742 of 1535 cam+002ch camera module ou tput address register cam_outadd r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_outaddr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_outaddr[15:0] type r/w reset 0 cam_outaddr output memory address, used when isp dump data to memory ( outpath_en =1) 5.4.1.2 color process register definition cam+0030h preprocessing control register 1 cam_ctrl1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gain_comp p_limit type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pgain _db pixelid pgain_int pgain_frac type r/w r/w r/w r/w reset 0 0 1 0 gain_comp[7:0] raw data compensation gain (1.7) p_limit[7:0] edge detection input data upper bond. edge detection applications (eg. edge ehancemnent) will not be applied on pixels those luminance above this value(0~255 range) pgain_db pre-gain debug, set 0 for normal operation pixelid first pixel type selection (bayer data input) 00 b 01 gb 02 gr 03 r pgain_int[1:0] pre-gain multiplier integer part pgain_frac[6:0] pre-gain multiplier fraction part cam+0034h awb r,g,b gain control register 1 cam_rgbgain1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_gain type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gb_gain type r/w reset 80h free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 743 of 1535 b_gain[8:0] awb b gain (2.7) gb_gain[8:0] awb gb gain (2.7) cam+0038h awb r,g,b gain control register 2 cam_rgbgain2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_gain type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gr_gain type r/w reset 80h r_gain[8:0] awb r gain (2.7) gr_gain[8:0] awb gr gain (2.7) cam+0044h preprocessing control register 2 cam_ctrl2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aehis _en aeaw g_en aecc m_en cnte n rawa ccm_ mode dfdb fhis_ en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 1 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af_en af_se l rlen inten type r/w r/w r/w r/w reset 1 0 0 0 aehis_en ae histogram enable aeawg_en ae histogram awb gain compensation enable 0 ae histogram count from shading output without awb gain compensation 1 ae histogram count from shading output with awb gain compensation aeccm_en ae histogram ccm enable 0 ae histogram count from shading output without ccm process 1 ae histogram count from shading output with ccm process cnten ae luminance statistic window enable 0 ae luminance statistic window disable 1 ae luminance statistic window enable, only enable in bayer input mode rawaccm_mode raw data accumulation mode selection 0 raw data accumulation reset when rawaccm_en (cam+01bch) set from 0 to 1 1 raw data accumulation reset every frame dfdb defect table debug enable, set 0 for normal operation fhis_en flare histogram enable af_en auto focus statistic window enable, frame double buffered af_sel af filter selection, frame double buffered 0 smd filter 1 tenengrad filter free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 744 of 1535 rlen flare histogram input selection 0 from awb de-mosaic output only 1 from awb de-mosaic output with window selection(cam+0x4ch) and ae_gain (cam+0x50h) compensation inten demo-saic internal fifo enable, set 1 for normal operation cam+0048h ae window horizontal width cam_aewinh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae_hoffset[6:0] ae_width type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ae_voffset[6:0] ae_height type r/w r/w reset 0 0 ae_hoffset ae window horizontal offset pixel count, bit 7,8 refer to (cam+0050h),frame double buffered ae_voffset ae window vertical offset line count, bit 7,8 refer to (cam+0050h),frame double buffered ae_width ae window block width, multiple of 2 pixels, frame double buffered ae_height ae window block height, multiple of 2 lines, frame double buffered example : if width of image is 84, then [(84/2)/5] = 8 => ae_width = 7 (count from 0) (84/2)- 8*4 = 10 => ae_lwidth = 9 (count from 0) (notes : ae window is fixed to 5x5) ae window partition "&@8*%5) win10 win20 win30 win40 win11 win21 win31 win41 win12 win22 win32 win42 win13 win23 win33 win43 win14 win24 win34 win44 win02 win03 win04 "&@)0''4&5 "&@70''4&5 "&@)&*()5 3bx*nbhfxjeui 3bx*nbhfifjhiu ae window memory allocation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 745 of 1535 win01[7:0],win00[23:16] win00[15:0] win02[15:0] win01[23:8] win03[23:16] win03[7:0],win02[23:16] 0xae,win04[23:16] win04[15:0] win11[7:0],win10[23:16] win10[15:0] win12[15:0] win11[23:8] win13[23:16] win13[7:0],win12[23:16] 0xae,win14[23:16] win14[15:0] $". y $". y win21[7:0],win20[23:16] win20[15:0] win22[15:0] win22[23:8] win23[23:16] win23[7:0],win22[23:16] 0xae,win24[23:16] win24[15:0] $". y win31[7:0],win30[23:16] win30[15:0] win32[15:0] win32[23:8] win33[23:16] win33[7:0],win32[23:16] 0xae,win34[23:16] win34[15:0] $". y win41[7:0],win40[23:16] win40[15:0] win42[15:0] win42[23:8] win43[23:16] win43[7:0],win42[23:16] 0xae,win44[23:16] win44[15:0] $". y cam+004ch ae histogram window vertical height cam_aehiswin bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aehis_winl aehis_winr type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aehis_winu aehis_wind type r/w r/w reset 0 0 aehis_winl ae histogram window left boundary, multiples of 4 pixels aehis_winr ae histogram window right boundary, multiples of 4 pixels aehis_winu ae histogram window up boundary, multiples of 4 lines aehis_wind ae histogram window down boundary, multiples of 4 lines "&)*4@8*/3 "&)*4@8*/- "&)*4@8*/6 3bx*nbhfxjeui 3bx*nbhfifjhiu "&)*4@8*/% cam+0050h ae gain register cam_aegain bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 746 of 1535 name ae_hoffset[ 8:7] ae_voffset [8:7] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ae_gain type r/w reset 0 ae_gain ae histogram gain (1.8) cam+0054h global shutter c ontrol register cam_gsctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name stro be_po l gsct rl_en gs_eptime[9:0] type r/w r/w r/w reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gs_trtime[7:0] gs_eptimeu[7:0] type r/w r/w reset 0 0 strobe_pol global shutter strobe polarity gsctrl_en global shutter control enable, global shutter will be triggered by ms_swtr (cam+0058h), gsctrl_en must be set first. gs_eptime global shutter exposure time, time unit refer to gs_eptimeu gs_trtime global shutter trigger time, time unit equals ms_timeu gs_eptimeu global shutter exposure time = [256 * (1/104m)] * gs_eptimeu free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 747 of 1535 expl1 expl2 expl3 expl4 expl5 m1 m2 open $mptf open trigger point1 tuspcf 7tzod )tzod open hold close hold open hold trigger point trigger point3 gs_eptime[9:0] gs_eptimeu[7:0] gs_trtime[7:0] ms1t1[7:0] ms1t2[7:0] 1 2 3 4 1 2 ms1t3[7:0] ms1t4[7:0] ms1t1[7:0] ms1t2[7:0] ms2t1[7:0] ms2t2[7:0] ms2t3[7:0] ms2t4[7:0] ms2t1[7:0] ms2t2[7:0] gs_eptime[9:0] exp_done 1.sw_trigger 2.pad_trigger hw_trigger frame readout *256(104 mhz cycle) global shutter mode cam+0058h mechanical shutter control register cam_msctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mech sh0_p ol mech sh1_p ol singl etr_e n msct rl_en ms_gs mode msctrl_mod e ms_s wtr_ en ms_ swt r type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ms_timeu[7:0] type r/w reset 0 mechsh0_pol mechanical shutter 0 polarity mechsh1_pol mechanical shutter 1 polarity singletr_en mechanical shutter single trigger enable msctrl_en mechanical shutter control enable ms_gsmode mechanical shutter global shutter mode msctrl_mode mechanical shutter control mode 0 mechsh0 e mechsh1 both on 1 mechsh0 on during phase1 and phase3, mechsh1 on during phase2 2 mechsh0 on during phase2,mechsh1 on during phase1 and phase3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 748 of 1535 3 simple mechanical shutter mode. mechsh0 = 1 in trigger phase 2, 0 in phase1 and phase 3 and mechsh1 = 0 in trigger phase 2, 1 in phase1 and phase 3 ms_swtr_en mechanical shutter software enable ms_swtr mechanical shutter software trigger ms_timeu mechanical shutter exposure time unit setting, n. exposure time unit = [4 * (1/104m)] * n expl1 expl2 expl3 expl4 expl5 m1 m2 open $mptf open trigger point1 5sjhhfs 7tzod )tzod open hold close hold open hold trigger point trigger point3 gs_eptime[9:0] gs_eptimeu[7:0] gs_trtime[7:0] ms1t1[7:0] ms1t2[7:0] 1 2 3 4 1 2 ms1t3[7:0] ms1t4[7:0] ms1t1[7:0] ms1t2[7:0] ms2t1[7:0] ms2t2[7:0] ms2t3[7:0] ms2t4[7:0] ms2t1[7:0] ms2t2[7:0] gs_eptime[9:0] exp_done 1.sw_trigger 2. 7tzod _trigger hw_trigger frame readout *256(104 mhz cycle) $mptf rolling shutter mode cam+005ch mechanical shutter m1 setting register cam_ms1time bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ms1t1[7:0] ms1t2[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ms1t3[7:0] ms1t4[7:0] type r/w r/w reset 0 0 ms1t1 mechanical shutter pad1 time 1 ms1t2 mechanical shutter pad1 time 2 ms1t3 mechanical shutter pad1 time 3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 749 of 1535 ms1t4 mechanical shutter pad1 time 4 cam+0060h mechanical shutter m2 setting register cam_ms2time bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ms2t1[7:0] ms2t2[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ms2t3[7:0] ms2t4[7:0] type r/w r/w reset 0 0 ms2t1 mechanical shutter pad2 time 1 ms2t2 mechanical shutter pad2 time 2 ms2t3 mechanical shutter pad2 time 3 ms2t4 mechanical shutter pad2 time 4 (note that in phase 3, after trigger point 3, mechanical shutter pad2 tied to 0 when mechanical shutter pad1 waveform end) cam+0070h color processing stage control register cam_cpscon 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dm_bp cmp_e n hled gen vled gen dislj type r/w r/w r/w r/w reset 0 1 1 0 dm_bpcmp_en demosaic black point compensation enable hledgen edge detection parameter, hoorizontal line edge enable vledgen edge detection parameter, vertical line edge enable dislj demosaic parameter, line judge function in g disable cam+0074h interpolation register1 cam_inter1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name thre_v rb_s moot h_en thre_sm type r/w r/w r/w reset 0ah 1 05h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thre_dhv edgeb_rt type r/w r/w reset 19h 10h thre_v demosaic parameter rb_smooth_en demosaic parameter, enable rb smooth mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 750 of 1535 thre_sm demosaic parameter, value increase will cause picture smoother thre_dhv demosaic parameter edgeb_rt edge detection parameter, edgeb threshold(2.3) cam+0078h interpolation register 2 cam_inter2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name line_rbthd thre_ledge type r/w r/w reset 05h 14h line_rbthd demosaic parameter, rb line threshold thre_ledge edge detection parameter cam+007ch edge core register cam_edgcore bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coreh[6:0] embo ss1_e n embo ss2_e n coreh2[5:0] type r/w r/w r/w r/w reset 08h 0 0 1fh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name speci al_en sdn_h[1:0] sup_h[1:0] top_s lope core_con[6:0] type r/w r/w r/w r/w r/w reset 0 2 0 0 14h coreh edge detection parameter, horizontal edge core function threshold emboss1_en edge detection parameter, emboss effect mode 1 enable emboss2_en edge detection parameter, emboss effect mode 2 enable coreh2 edge detection parameter, horizontal edge core function parameter special_en special effect enable sdn_h edge detection parameter, horizontal edge core function negative slope sup_h edge detection parameter, horizontal edge core function positive slope top_slope edge detection parameter core_con edge detection parameter cam+0080h edge gain register 1 cam_edggain1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name specigain speciponly egain_h csi2d phy_p woff egain_h2 type r/w r/w r/w r/w r/w reset 0 0 1 0 3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name egain_vb oilen kneesel egainlilne type r/w r/w r/w r/w reset 3 0 3 2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 751 of 1535 specigain[1:0] special effect parameter, special power gain 00 unit gain 01 x2 10 x4 11 x8 speciponly special effect parameter, p only enable egain_h[3:0] edge detection parameter, horizontal edge gain a csi2dphy_pwoff power down dphy rx. please set this value to 1 to save power when dphy is not used. egain_h2 edge detection parameter, horizontal edge gain b egain_vb edge detection parameter, vertical edge gain b oilen special effect parameter ,oil effect enable kneesel[1:0] edge detection parameter, edge knee threshold egainline edge detection parameter, edge line gain cam+0084h edge gain register 2 cam_edggain2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name egain_va[3:0] egain_vc[4:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name speci abs specii nv egain_hc[4:0] type r/w r/w r/w reset 0 0 fh egain_va edge detection parameter, vertical edge gain a egain_vc edge detection parameter, vertical edge gain c speciabs special effect parameter, special absolute value enable speciinv special effect parameter, special invert enable egain_hc edge detection parameter, horizontal edge gain c cam+0088h edge threshold register cam_edgthr e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name eth3 eth_con type r/w r/w reset 32h 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name only c thre_edge_sup thrl_edge_sup type r/w r/w r/w reset 0 07h 07h eth3 edge detection parameter eth_con edge detection parameter onlyc edge detection parameter, only c enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 752 of 1535 thre_edge_sup edge detection parameter thrl_edge_sup edge detection parameter cam+008ch edge vertical control register cam_edgvcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hpen e_th1_v half_v type r/w r/w r/w reset 0 18h 1fh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vpen sup_v sdn_v e_th3_v type r/w r/w r/w r/w reset 0 0 2 32h hpen edge detection parameter, horizontal edge high pass enable e_th1_v edge detection parameter half_v edge detection parameter vpen edge detection parameter, vertical edge high pass enable sup_v edge detection parameter, vertical edge core function positive slope sdn_v edge detection parameter, vertical edge core function negative slope e_th3_v edge detection parameter cam+009ch color matrix 1 register cam_matrix1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m11 type r/w reset 20h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m12 m13 type r/w r/w reset 80h 80h m11[7:0] color matrix 11 value,s2.5 m12[7:0] color matrix 12 value,s2.5 m13[7:0] color matrix 13 value,s2.5 process r = m11 * r + m12 * g + m13 * b cam+00a0h color matrix 2 register cam_matrix2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m21 type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m22 m23 type r/w r/w reset 20h 80h m21[7:0] color matrix 21 value,s2.5 m22[7:0] color matrix 22 value,s2.5 m23[7:0] color matrix 23 value,s2.5 process g = m21 * r + m22 * g + m23 * b free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 753 of 1535 cam+00a4h color matrix 3 register cam_matrix3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m31 type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m32 m33 type r/w r/w reset 80h 20h m31[7:0] color matrix 31 value,s2.5 m32[7:0] color matrix 32 value,s2.5 m33[7:0] color matrix 33 value,s2.5 process b = m31 * r + m32 * g + m33 * b cam+00ach color process stage c ontrol register 2 cam_cpscon2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bypg m oprg m_ivt y_egain type r/w r/w r/w reset 1 0 2 bypgm piece-wise linear gamma table bypass 0 piece-wise linear gamma operation enable, setting as (cam + 01a8h ~ 01b8h) 1 piece-wise linear gamma operation bypass opdgm_ivt piece-wise linear gamma table output inverse enable y_egain edge enhancement parameter, gain of edge enhancement after rgb2yuv process, available only when yedge_en in (cam + 0230h) set 1 cam+00b0h flare gain register cam_flregain bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flare_rgain type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flare_ggain flare_bgain type r/w r/w reset 80h 80h flare_rgain flare r gain (1.7) flare_ggain flare g gain (1.7) flare_bgain flare b gain (1.7) cam+00b4h flare offset register cam_flreoff bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 754 of 1535 name sign_ r flare_r type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sign_ g flaire_g sign_ b flare_b type r/w r/w r/w r/w reset 0 0 0 0 sign_r flare r offset sign, 0 positive, 1 negative flare_r flare r offset magnitude sign_g flare g offset sign, 0 positive, 1 negative flare_g flare g offset magnitude sign_b flare b offset sign, 0 positive, 1 negative flare_b flare b offset magnitude cam+00b8h y channel configuration register cam_ychan bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vsup_ en uv_lp _en csup_edge_gain type r/w r/w r/w reset 0 0 10h vsup_en chroma suppression enable uv_lp_en yuv domain uv low-pass enable csup_edge_gain chroma suppression edge gain value(1.3) cam+00bch rgb2ycc control register rgb2ycc_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ygain yofst type r/w r/w reset ff 01 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ugain vgain type r/w r/w reset 90 b7 r/g/b to y/cb/cr equation is as follows cam+00e4h mipi csi2 status register 1 cam_csi2sta1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csi2_frame_no[15:0] () [] () () 128 vgain y - r cr 128 ugain y - b cb yofst ygain 8 29b 150g 77r y + = + = + >> + + = free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 755 of 1535 type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csi2_line_no[15:0] type r reset csi2_frame_no csi2 frame number. available if sensor support additional information for frame number. csi2_line_no csi2 line number. available if sensor support additional information for line number. cam+00e8h mipi csi2 status register 2 cam_csi2sta2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csi2_wc_number[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csi2_data_type[5:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 0 0 csi2_wc_number csi2 word count number. csi2 packet word count. csi2_data_type csi2 data type. csi2 packet data type. note that raw8( 0x2a ), raw10( 0x2b ), yuv422 8-bit( 0x1e ), rgb565 ( 0x22 ) cam+0108h flare histogram result 1 cam_hisrlt0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt0[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt0[15:0] type ro reset 0 cam_hisrlt0[21:0] flare histogram bin 1 result cam+010ch flare histogram result 2 cam_hisrlt1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt1[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt1[15:0] type ro reset 0 cam_hisrlt1[21:0] flare histogram bin 2 result cam+0110h flare histogram result 3 cam_hisrlt2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt2[21:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 756 of 1535 type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt2[15:0] type ro reset 0 cam_hisrlt2[21:0] flare histogram bin 3 result cam+0114h flare histogram result 4 cam_hisrlt3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt3[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt3[15:0] type ro reset 0 cam_hisrlt3[21:0] flare histogram bin 4 result cam+0118h flare histogram result 5 cam_hisrlt4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt4[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt4[15:0] type ro reset 0 cam_hisrlt4[21:0] flare histogram bin 5 result cam+0128h vertical subsample control register cam_vsub bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name v_sub _en v_sub_in type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name v_sub_out type r/w reset 0 v_sub_en vertical sub-sample enable v_sub_in sub-sample source vertical size v_sub_out sub-sample output vertical size cam+012ch horizontal subsampl e control register cam_hsub bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name h_sub _en h_sub_in type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 757 of 1535 reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h_sub_out type r/w reset 0 h_sub_en horizontal sub-sample enable h_sub_in sub-sample source horizontal size h_sub_out sub-sample output horizontal size cam+00154h defect pixel configuration register cam_defect0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name defec t_en defect_fifo_level type r/w r/w reset 0 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type reset defect_en defect table correct enable defect_fifo_level defect table fifo level, recommend value 4 cam+0158h defect pixel table address register cam_defect1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name deffect_addr[31:16] type rw reset 2000h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name defect_addr[15:0] type rw reset 0 defect_addr[31:0] defect table location address, bit0 and bit1 are fixed to 0 for word alignment cam+015ch defect pixel table debug register cam_defect2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name defect_count deffect_yloc[11:0] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name defect_xloc[11:0] type r reset this debug register show current status of defect table fifo defect_count defect table counter defect_yloc defect table y location defect_xloc defect table x location free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 758 of 1535 cam+016ch raw gain control register 1 cam_rawgain 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name raw_rgain type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name raw_grgain type r/w reset 80h raw_rgain raw r gain (2.7), note that 0 equal unity gain raw_grgain raw gr gain (2.7), note that 0 equal unity gain cam+0170h raw gain control register 2 cam_rawgain 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name raw_bgain type r/w reset 80h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name raw_gbgain type r/w reset 80h raw_bgain raw b gain (2.7), note that 0 equal unity gain raw_gbgain raw gb gain (2.7), note that 0 equal unity gain cam+0174h result window vertical size register rwinv_sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rwin_ en rwinv_start type r/w r/w reset 0h 0h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rwinv_end type r/w reset 0h rwin_en result window enable rwinv_start result window vertical start line rwinv_end result window vertical end line, end line number + 1 cam+0178h result window horizo ntal size register rwinh_sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rwinh_start type r/w reset 0h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rwinh_end free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 759 of 1535 type r/w reset 0h rwinh_start result window horizontal start pixel rwinh_end result window horizontal end pixel, end pixel number + 1 cam+0180h memory input de bug control memindb_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memin _paus e_en memin _paus e_co nt memin_phcount type r/w r/w r/w reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memin_pvcount type r/w reset 0 memin_pause_en memory input pause enable memin_pause_cont memory input pause continue, only active when pause enable is on. memin_phcount memory input pause width count, 1 represent first pixel memin_pvcount memory input pause height count, 0 represent first line example : if you want to 1. stop at (0,0) : 0x80010000 2. go to (1,0) : 0xc0020000 3. go to (0,1) : 0x80010001 -> 0xc0010001 cam+0184h memory input debug register 1 memindb1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memin_hcount type r reset 0h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memin_vcount type r reset 0h memin_hcount memory input horizontal counter memin_vcount memory input vertical counter cam+0188h camera module debug information last transfer destination address cam_lastadd r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name last_add[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name last_add[15:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 760 of 1535 last_add debug information last transfer destination address cam+018ch camera module frame buffer transfer out count register cam_xfercnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name xfer_count [31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xfer_count[15:0] type ro reset 0 xfer_count pixel transfer count per frame cam+0190h sensor test model configuration register 1 cam_mdlcfg1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vsync idle_pixel_per_line type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name linec hg_e n full_ rang e on rst still patte rn pixel_sel clk_div type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 vsync vsync high duration in line unit(idle_pixel_per_line + pixel) idle_pixel_per_line hsync low duration in pixel unit linechg_en pattern 0 2 lines change mode enable full_range sensor model full range enable. when full range is enable, pattern data value will increase progressively every line output. on enable sensor model. rst reset sensor model still still picture mode pattern sensor model test pattern selection pixel_sel sensor model output pixel selection. 00 all pixels 01 01 pixel 10 10 pixel 11 00 and 11 pixels clk_div pixel_clock/system_clock ratio cam +0194h sensor test model configuration register 2 cam_mdlcfg2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name line type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 761 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pixel type r/w reset 0 line sensor model line number pixel sensor model pixel number (hsync high duration in pixel unit) cam+01a0h cam to crz interface control register camcrz_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_ crz_i nit_e n cam_crz_init_period rez_o vrun_ flimit _en rez_ovrun_flimit_no type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_crz_fcnt_th type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 cam_crz_inint_en cam to crz and mdp frame initialization function enable. when this function is enable, cam will assert frame initialization signal to mdp to indicate that frame must be initialized. cam_crz_init_period cam to crz and mdp frame initialization period. set cam initialization frame signal period. crz_ovrun_flimit_en crz overrun frame limited enable. crz_ovrun_flimit_no crz overrun frame number setting. crz overrun interrupt will assert when rez_ovrun_flimit_en = 0 or when rez_ovrun_flimit_en = 1 and resizer overrun occurred ( rez_ovrun_flimit_no + 1) frames. cam_crz_fcnt_th cam to crz fifo count threshold . cam+01a8h gamma register 1 gma_reg1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y04 y03 type r/w r/w reset 72 (0x40) 50 (0x32) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y02 y01 type r/w r/w reset 32 (0x20) 20 (0x14) cam+01ach gamma register 2 gma_reg2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y08 y07 type r/w r/w reset 120 (0x78) 110 (0x6e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y06 y05 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 762 of 1535 type r/w r/w reset 100 (0x64) 88 (0x58) cam+01b0h gamma register 3 gma_reg3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y12 y11 type r/w r/w reset 164 (0xa4) 150 (0x96) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y10 y09 type r/w r/w reset 138 (0x8a) 128 (0x80) cam+01b4h gamma register 4 gma_reg4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y16 y15 type r/w r/w reset 206 (0xcc) 196 (0xc4) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y14 y13 type r/w r/w reset 186 (0xba) 176 (0xb0) cam+01b8h gamma register 5 gma_reg5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y20 y19 type r/w r/w reset 248 (0xf8) 240 (0xf0) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y18 y17 type r/w r/w reset 232 (0xe8) 224(0xe0) cam+01bch raw data accumulation config register rawacc_reg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rawacc_en type r/w reset 0 rawacc_en raw data accumulation enable cam+01c0h raw data accumulation window register rawwin_reg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rawwin_l rawwin_r type r/w r/w reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 763 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rawwin_u rawwin_d type r/w r/w reset 0 0 rawwin_l raw accumulation left window rawwin_r raw accumulation right window rawwin_u raw accumulation up window rawwin_d raw accumulation down window cam+01c4h raw data accumulation b result rawsum_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rawsum_b[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rawsum_b[15:0] type r reset rawsum_b raw accumulation b channel result cam+01c8h raw data accumulation gb result rawsum_gb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rawsum_gb[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rawsum_gb[15:0] type r reset rawsum_gb raw accumulation gb channel result cam+01cch raw data accumulation gr result rawsum_gr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rawsum_gr[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rawsum_gr[15:0] type r reset rawsum_gr raw accumulation gr channel result cam+01d0h raw data accumulation r result rawsum_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rawsum_r[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 764 of 1535 name rawsum_r[15:0] type r reset rawsum_r raw accumulation r channel result cam +01d8h cam reset register cam_reset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_cs type r reset 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isp_frame_count[7:0] isp_r eset type rw rw reset 0 0 cam_cs camera status, read only. 1 idle 2 vfon_idle 4 vfon_exp 8 vfon_wait 16 capon_exp 32 capon_don isp_frame_count isp frame counter isp_reset isp reset. note that reset should be assert longer than 100us to make sure gmc command done. cam +01dch tg status register tg_status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name syn_v fon line_count[11:0] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pixel_count[11:0] type r reset syn_vfon tg view finder status line_count tg line counter pixel_count tg pixel counter cam+01e0h flash control register 1 flash_ctrl0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flash _out flash_cont _frame[1:0] flash _en flash _pol flash _star tpnt flash_lnunit[3:0] flash_lnunit_no[19:16] type r rw rw rw rw rw rw reset 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 765 of 1535 name flash_lnunit_no[15:0] type rw reset 0 flash_out flash out status flash_cont_frame flash frame delay flash_en flash enable flash_pol flash line polarity flash_startpnt flash start point 0 start from vsync start 1 start from expdone flash_lnunit flash line unit, 0~15 lines flash_lnunit_no flash line unit count cam+01e4h flash control register 2 flash_ctrl1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flash_line[11:0] type rw reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flash_pixel[11:0] type rw reset 0 flash_line flash start line flash_pixel flash start pixel cam+01e8h flashb control register 1 flashb_ctrl 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flashb_start_frame[3:0] flashb_line[11:0] type rw rw reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flashb_cont_fra me[2:0] flashb_pixel[11:0] type rw rw reset 0 0 flashb_start_frame flash b start frame count flashb_line flash b start line flash_cont_frame flash b continuous frame count flash_pixel flash b start pixel cam+01ech flashb control register 2 flashb_ctrl 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flashb_lnunit[3:0] flashb_lnunit_no[19:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 766 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flash_lnunit_no[15:0] type rw reset 0 flashb_lnunit flash line unit, 0~15 lines flashb_lnunit_no flash line unit count cam+01f0h flare histogram result 6 cam_hisrlt5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt5[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt5[15:0] type ro reset 0 cam_hisrlt5[21:0] flare histogram bin 6 result cam+01f4h flare histogram result 7 cam_hisrlt6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt6[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt6[15:0] type ro reset 0 cam_hisrlt6[21:0] flare histogram bin 7 result cam+01f8h flare histogram result 8 cam_hisrlt7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt7[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt7[15:0] type ro reset 0 cam_hisrlt7[21:0] flare histogram bin 8 result cam+01fch flare histogram result 9 cam_hisrlt8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt8[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt8[15:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 767 of 1535 type ro reset 0 cam_hisrlt8[21:0] flare histogram bin 9 result cam+0200h flare histogram result 10 cam_hisrlt9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cam_hisrlt9[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_hisrlt9[15:0] type ro reset 0 cam_hisrlt9[21:0] flare histogram bin 10 result cam+00214h shading cotrol 1 register cam_shading1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sdbl k_tri g shadi ng_e n shadingblk_xoffset[5:0] type r/w rw rw reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name shadingblk_yoffset[5:0] type rw reset 0 sdblk_trig shading parameter loaded trigger. when sdblk_trig is set, shading block parameter will be loaded before next frame vsync. note that sdblk_trig and shading_en must be set simultaneously, and must be close after isp_idle asserted. shading_en shading enable shadingblk_xoffset shading block x offset shadingblk_yoffset shading block y offset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 768 of 1535 shadingblk_xoffset shadingblk_yoffset *nbhf8jeui *nbhf)fjhiu shadingblk_width shadingblk_height sdblk_lwidth sdblk_lheight cam+0218h shading control 2 register cam_shading 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name shadingblk_xnum[3:0] shadingblk_width[11:0] type rw rw reset 6 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name shadingblk_ynum[3:0] sh adingblk_height[11:0] type rw r/w reset 4 0 shading configuration is based on raw data channel (r,gr,b,gb). 1. assume raw_width represents raw data channel width, and raw_height represents raw data channel height, then raw_width = (image_width/2) and raw_height = (image_height/2); 2. assume there are m block in horizontal and n block in vertical , (include cam+0220h shading last block), raw_width = m* shadingblk_width + sdblk_lwidth, raw_height = n* shadingblk_height + sdblk_lheight shadingblk_xnum shading block x number in horizontal, count from 0, eg, if there are m blocks in horizontal (include cam+0220h shading last block) then shadingblk_xnum = m -1. shadingblk_ynum shading block y number in vertical, count from 0, eg. if there are n blocks in vertical(include cam+0220h shading last block), then shadingblk_ynum = n -1. shadingblk_width shading block width. shadingblk_height shading block height. cam+021ch shading read addr register sd_raddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 769 of 1535 name shading_raddr[31:16] type r/w reset 20h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name shading_raddr[15:0] type r/w reset 60h shading_raddr[31:0] shading coefficient read address. format : block0 r 12 coefficient, block0 gr 12 coefficient, block0 gb 12 coefficient, block0 b 12 coefficient, block1 ??? cam+0220h shading last block config register sd_lblock bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sdblk_lwidth[11:0] type r/w reset ffh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sdblk_lheight[11:0] type r/w reset ffh sd_lwidth[11:0] shading horizontal last block width, last horizontal block can set different width. sd_lheight[11:0] shading vertical last block height, last vertical block can set different height cam+0224h shading ratio config register sd_ratio bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sdblk_ratio00 sdblk_ratio01 type r/w r/w reset 20h 20h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sdblk_ratio10 sdblk_ratio11 type r/w r/w reset 20h 20h sdblk_ratio00[5:0] shading block location 00 ratio gain (1.5) sdblk_ratio01[5:0] shading block location 00 ratio gain (1.5) sdblk_ratio10[5:0] shading block location 00 ratio gain (1.5) sdblk_ratio11[5:0] shading block location 00 ratio gain (1.5) cam+0230h edge enhancement control register ee_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ed_gain_th clip_under_th type r/w r/w reset 0x20 0x64 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_over_th ed_ba nd_en filte r_sel clip_ unde r_en clip_ over_ en rgbe dge _en yedg e_en type r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 770 of 1535 reset 0x24 0 0 0 0 0 0 the register is for global control of edge enhancement ed_gain_th[7:0] edge gain threshold, data range 0-255 (=32x real gain threshold) clip_under_th[7:0] undershoot clipping threshold, data range 0-127 clip_over_th[7:0] overshoot clipping threshold, data range 0-127 ed_bound_en edge detection boundary enable 0 disable 1 enable filter_sel ? mid-band only? or ?mid-band and high-band? in edge detection 0 use mid-band detectors only 1 use both mid-band and high-band detectors clip_under_en undershoot clipping enable 0 disable 1 enable clip_over_en overshoot clipping enable 0 disable 1 enable rgbedge_en ee on g pixels (after gdc) 0 disable 1 enable yedge_en ee on y pixels (after rgb-to-yuv) 0 disable 1 enable cam+0234h edge detection lut x configuration ed_lut_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ed_lut_x3 type r/w reset 0x0a bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ed_lut_x2 ed_lut_x1 type r/w r/w reset 0x07 0x04 the register is for edge detection look-up table (lut) input level configuration. ed_lut_x1[7:0] input level 1 for the ed lut, data range is 0-63 (in 8-bit) ed_lut_x2[7:0] input level 2 for the ed lut, data range is 0-63 (in 8-bit) ed_lut_x3[7:0] input level 3 for the ed lut, data range is 0-63 (in 8-bit) cam+0238h edge detection lut y configuration ed_lut_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ed_lut_y4 ed_lut_y3 type r/w r/w reset 0x16 0x08 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ed_lut_y2 ed_lut_y1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 771 of 1535 type r/w r/w reset 0x04 0x02 the register is for edge detection lut output factor configuration ed_lut_y1[7:0] output factor 1 for the ed lut, data range is 0-63 (=32 x the real intended factor) ed_lut_y2[7:0] output factor 2 for the ed lut, data range is 0-63 (=32 x the real intended factor) ed_lut_y3[7:0] output factor 3 for the ed lut, data range is 0-63 (=32 x the real intended factor) ed_lut_y4[7:0] output factor 4 for the ed lut, data range is 0-63 (=32 x the real intended factor) cam+024ch af window 1 register cam_afwin0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 1 th window left side right[7:0] atf 1 th window right side top[7:0] atf 1 th window top side bottom[7:0] atf 1 th window bottom side cam+0250h af window 2 register cam_afwin1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 2 th window left side right[7:0] atf 2 th window right side top[7:0] atf 2 th window top side bottom[7:0] atf 2 th window bottom side cam+0254h af window 3 register cam_afwin2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 772 of 1535 type r/w r/w reset 0 0 left[7:0] atf 3 th window left side right[7:0] atf 3 th window right side top[7:0] atf 3 th window top side bottom[7:0] atf 3 th window bottom side cam+0258h af window 4 register cam_afwin3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 4 th window left side right[7:0] atf 4 th window right side top[7:0] atf 4 th window top side bottom[7:0] atf 4 th window bottom side cam+025ch af window 5 register cam_afwin4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 5 th window left side right[7:0] atf 5 th window right side top[7:0] atf 5 th window top side bottom[7:0] atf 5 th window bottom side cam+0260h af threshold 1 register cam_afth0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af_th3 af_th2 type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af_th1 af_th0 type r/w r/w reset 0 0 af_th0[7:0] af focus value threshold 1 af_th1[7:0] af focus value threshold 2 af_th2[7:0] af focus value threshold 3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 773 of 1535 af_th3[7:0] af focus value threshold 4 cam+0264h af threshold 2 register cam_atfth1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af_th4 type r/w reset 0 af_th4[7:0] af focus value threshold 5 cam+0268h af window 6 register cam_afwin5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 6 th window left side right[7:0] atf 6 th window right side top[7:0] atf 6 th window top side bottom[7:0] atf 6 th window bottom side cam+026ch af window 7 register cam_afwin6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom type r/w r/w reset 0 0 left[7:0] atf 7 th window left side right[7:0] atf 7 th window right side top[7:0] atf 7 th window top side bottom[7:0] atf 7 th window bottom side cam+026ch af window 8 register cam_afwin7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left right type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name top bottom free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 774 of 1535 type r/w r/w reset 0 0 left[7:0] atf 8 th window left side right[7:0] atf 8 th window right side top[7:0] atf 8 th window top side bottom[7:0] atf 8 th window bottom side cam +0274h cam version register cam_version bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name year[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name month[7:0] date[7:0] type r r reset year[15:0] year ascii month[7:0 ] month ascii date[7:0] date ascii cam +027ch awb sum window config register awbsum_win bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbsum_winl awbsum_winr type r/w r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbsum_winu awbsum_wind type r/w r/w reset awbsum_winl[7:0] awb sum window left corner awbsum_winr[7:0] awb sum window right corner awbsum_winu[7:0] awb sum window up corner awbsum_wind[7:0] awb sum window down corner cam +0280h awb control register awb_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awb_ en neut ral_e n colo redg e_en smar ea_en smarea_no awb dm_d ebug type r/w r/w r/w r/w r/w r/w r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name paxel_rgbh paxel_yl type r/w r/w reset awb_en awb enable neutral_en neural color selection enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 775 of 1535 coloredge_en color edge selection enable smarea_en smooth area enable smarea_no[2:0] smooth area pixel count awbdm_debug awb demosaic debug output, available when 0x80620024 bit16 set 1, and not bayer output paxel_rgbh[7:0] paxel r,g,b high limit paxel_yl[7:0] paxel luminance low level cam +0284h awb threshold config awbth bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cedgex_th cedgey_th type r/w r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name neutral_th type r/w reset cedgex_th[7:0] color edge x threshold cedgey_th[7:0] color edge y threshold neutral_th[11:0] neural flag threshold cam +0288h awb color space h1 config regsiter awbxyh1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbh11 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbh12 type r/w reset awbh11[8:0] awb xy color space h11 parameter awbh12[8:0] awb xy color space h12 parameter cam +028ch awb sum window h2 config register awbxyh2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbh21 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbh22 type r/w reset awbh21[8:0] awb xy color space h21 parameter awbh22[8:0] awb xy color space h22 parameter cam +0290h awb color edge window horizontal config register awbce_winh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 776 of 1535 name awbce_winl type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_winr type r/w reset awbce_winl[11:0] awb color edge window left corner awbce_winr[11:0] awb color edge window right corner cam +0294h awb color edge window vertical config register awbce_winv bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbce_winu type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_wind type r/w reset awbce_winu[11:0] awb color edge window up corner awbce_wind[11:0] awb color edge window down corner cam +0298h awb xy window 1 horizontal config register awbxy_winh0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winl0 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr0 type r/w reset awbxy_winl0[11:0] awb color space window 1 left corner awbxy_winr0[11:0] awb color space window 1 right corner cam +029ch awb xy window 1 vert ical config register awbxy_winv0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu0 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind0 type r/w reset awbxy_winu0[11:0] awb color space window 1 up corner awbxy_winl0[11:0] awb color space window 1 down corner cam +02a0h awb xy window 2 horizontal config register awbxy_winh1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 777 of 1535 name awbxy_winl1 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr1 type r/w reset awbxy_winl1[11:0] awb color space window 2 left corner awbxy_winr1[11:0] awb color space window 2 right corner cam +02a4h awb xy window 2 vert ical config register awbxy_winv1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu1 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind1 type r/w reset awbxy_winu1[11:0] awb color space 2 window up corner awbxy_winl1[11:0] awb color space 2 window down corner cam +02a8h awb xy window 3 horizontal config register awbxy_winh2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winl2 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr2 type r/w reset awbxy_winl2[11:0] awb color space window 3 left corner awbxy_winr2[11:0] awb color space window 3 right corner cam +02ach awb xy window 3 vert ical config register awbxy_winv2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu2 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind2 type r/w reset awbxy_winu2[11:0] awb color space 2 window up corner awbxy_winl2[11:0] awb color space 2 window down corner cam +02b0h awb xy window 4 horizontal config register awbxy_winh3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 778 of 1535 name awbxy_winl3 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr3 type r/w reset awbxy_winl3[11:0] awb color space window 4 left corner awbxy_winr3[11:0] awb color space window 4 right corner cam +02b4h awb xy window 4 vert ical config register awbxy_winv3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu3 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind3 type r/w reset awbxy_winu3[11:0] awb color space 4 window up corner awbxy_winl3[11:0] awb color space 4 window down corner cam +02b8h awb xy window 5 horizontal config register awbxy_winh4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winl4 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr4 type r/w reset awbxy_winl4[11:0] awb color space window 5 left corner awbxy_winr4[11:0] awb color space window 5 right corner cam +02bch awb xy window 5 vert ical config register awbxy_winv4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu4 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind4 type r/w reset awbxy_winu4[11:0] awb color space 5 window up corner awbxy_winl4[11:0] awb color space 5 window down corner cam +02c0h awb xy window 6 horizontal config register awbxy_winh5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 779 of 1535 name awbxy_winl5 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr5 type r/w reset awbxy_winl5[11:0] awb color space window 6 left corner awbxy_winr5[11:0] awb color space window 6 right corner cam +02c4h awb xy window 6 vert ical config register awbxy_winv5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu5 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind5 type r/w reset awbxy_winu5[11:0] awb color space 6 window up corner awbxy_winl5[11:0] awb color space 6 window down corner cam +02c8h awb xy window 7 horizontal config register awbxy_winh6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winl6 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr6 type r/w reset awbxy_winl6[11:0] awb color space window 7 left corner awbxy_winr6[11:0] awb color space window 7 right corner cam +02cch awb xy window 7 vert ical config register awbxy_winv6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu6 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind6 type r/w reset awbxy_winu6[11:0] awb color space 7 window up corner awbxy_winl6[11:0] awb color space 7 window down corner cam +02d0h awb xy window 8 horizontal config register awbxy_winh7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 780 of 1535 name awbxy_winl7 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr7 type r/w reset awbxy_winl7[11:0] awb color space window 8 left corner awbxy_winr7[11:0] awb color space window 8 right corner cam +02d4h awb xy window 8 vert ical config register awbxy_winv7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu7 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind7 type r/w reset awbxy_winu7[11:0] awb color space 8 window up corner awbxy_winl7[11:0] awb color space 8 window down corner cam +02d8h awb xy window 9 horizontal config register awbxy_winh8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winl8 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr8 type r/w reset awbxy_winl8[11:0] awb color space window 9 left corner awbxy_winr8[11:0] awb color space window 9 right corner cam +02dch awb xy window 9 vert ical config register awbxy_winv8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu8 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind8 type r/w reset awbxy_winu8[11:0] awb color space 9 window up corner awbxy_winl8[11:0] awb color space 9 window down corner cam +02e0h awb xy window 10 horizontal config register awbxy_winh9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 781 of 1535 name awbxy_winl9 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winr9 type r/w reset awbxy_winl9[11:0] awb color space window 10 left corner awbxy_winr9[11:0] awb color space window 10 right corner cam +02e4h awb xy window 10 vertical config register awbxy_winv9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winu9 type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_wind9 type r/w reset awbxy_winu9[11:0] awb color space 10 window up corner awbxy_winl9[11:0] awb color space 10 window down corner cam +02e8h awb xy window 11 horizontal config register awbxy_winh a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winla type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winra type r/w reset awbxy_winla[11:0] awb color space window 11 left corner awbxy_winra[11:0] awb color space window 11 right corner cam +02ech awb xy window 11 vertical config register awbxy_winv a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winua type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winda type r/w reset awbxy_winua[11:0] awb color space 11 window up corner awbxy_winla[11:0] awb color space 11 window down corner free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 782 of 1535 cam +02f0h awb xy window 12 horizontal config register awbxy_winh b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winlb type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_winrb type r/w reset awbxy_winlb[11:0] awb color space window 12 left corner awbxy_winrb[11:0] awb color space window 12 right corner cam +02f4h awb xy window 12 vertical config register awbxy_winv b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_winub type r/w reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_windb type r/w reset awbxy_winub[11:0] awb color space 12 window up corner awbxy_winlb[11:0] awb color space 12 window down corner cam +02f8h awb sum windo w paxel count awbsum_pcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbsum_pcnt[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbsum_pcnt[15:0] type r reset awbsum_pcnt[21:0] awb summation window paxel count cam +02fch awb sum window r sum awbsum_rsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbsum_rsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbsum_rsum[15:0] type r reset awbsum_rsum[28:0] awb summation window r sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 783 of 1535 cam +0300h awb sum window g sum awbsum_gsu m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbsum_gsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbsum_gsum[15:0] type r reset awbsum_gsum[28:0] awb summation window g sum cam +0304h awb sum window b sum awbsum_bsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbsum_bsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbsum_bsum[15:0] type r reset awbsum_bsum[28:0] awb summation window b sum cam +0308h awb color edge window paxel count awbce_pcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbce_pcnt[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_pcnt[15:0] type r reset awbce_pcnt[21:0] awb color edge window paxel count cam +030ch awb color edge window r sum awbce_rsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbce_rsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_rsum[15:0] type r reset awbce_rsum[28:0] awb color edge window r sum cam +0310h awb color edge window g sum awbce_gsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 784 of 1535 name awbce_gsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_gsum[15:0] type r reset awbce_gsum[28:0] awb color edge window g sum cam +0314h awb color edge window b sum awbce_bsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbce_bsum[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbce_bsum[15:0] type r reset awbce_bsum[28:0] awb color edge window b sum cam +0318h awb xy window 1 paxel count awbxy_pcnt0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt0[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt0[15:0] type r reset awbxy_pcnt0[21:0] awb xy window paxel count cam +031ch awb xy window 1 r sum awbxy_rsum 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum0[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum0[15:0] type r reset awbxy_rsum0[28:0] awb xy window 1 r sum cam +0320h awb xy window 1 g sum awbxy_gsum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum0[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 785 of 1535 name awbxy_gsum0[15:0] type r reset awbxy_gsum0[28:0] awb xy window 1 g sum cam +0324h awb xy window 1 b sum awbxy_bsum 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum0[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum0[15:0] type r reset awbxy_bsum0[28:0] awb xy window 1 b sum cam +0328h awb xy window 2 paxel count awbxy_pcnt1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt1[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt1[15:0] type r reset awbxy_pcnt1[21:0] awb xy window 2 paxel count cam +032ch awb xy window 2 r sum awbxy_rsum 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum1[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum1[15:0] type r reset awbxy_rsum1 awb xy window 2 r sum cam +0330h awb xy window 2 g sum awbxy_gsum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum1[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum1[15:0] type r free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 786 of 1535 reset awbxy_gsum1[28:0] awb xy window 2 g sum cam +0334h awb xy window 2 b sum awbxy_bsum 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum1[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum1[15:0] type r reset awbxy_bsum1[28:0] awb xy window 2 b sum cam +0338h awb xy window 3 paxel count awbxy_pcnt2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt2[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt2[15:0] type r reset awbxy_pcnt2[21:0] awb xy window 3 paxel count cam +033ch awb xy window 3 r sum awbxy_rsum 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum2[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum2[15:0] type r reset awbxy_rsum2[28:0] awb xy window 3 r sum cam +0340h awb xy window 3 g sum awbxy_gsum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum2[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum2[15:0] type r reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 787 of 1535 awbxy_gsum2[28:0] awb xy window 3 g sum cam +0344h awb xy window 3 b sum awbxy_bsum 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum2[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum2[15:0] type r reset awbxy_bsum2[28:0] awb xy window 3 b sum cam +0348h awb xy window 4 paxel count awbxy_pcnt3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt3[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt3[15:0] type r reset awbxy_pcnt3[21:0] awb xy window 4 paxel count cam +034ch awb xy window 4 r sum awbxy_rsum 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum3[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum3[15:0] type r reset awbxy_rsum3[28:0] awb xy window 4 r sum cam +0350h awb xy window 4 g sum awbxy_gsum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum3[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum3[15:0] type r reset awbxy_gsum3[28:0] awb xy window 4 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 788 of 1535 cam +0354h awb xy window 4 b sum awbxy_bsum 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum3[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum3[15:0] type r reset awbxy_bsum3[28:0] awb xy window 4 b sum cam +0358h awb xy window 5 paxel count awbxy_pcnt4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt4[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt4[15:0] type r reset awbxy_pcnt4[21:0] awb xy window 5 paxel count cam +035ch awb xy window 5 r sum awbxy_rsum 4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum4[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum4[15:0] type r reset awbxy_rsum4[28:0] awb xy window 5 r sum cam +0360h awb xy window 5 g sum awbxy_gsum 4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum4[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum4[15:0] type r reset awbxy_gsum4[28:0] awb xy window 5 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 789 of 1535 cam +0364h awb xy window 5 b sum awbxy_bsum 4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum4[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum4[15:0] type r reset awbxy_bsum4[28:0] awb xy window 5 b sum cam +0368h awb xy window 6 paxel count awbxy_pcnt5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt5[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt5[15:0] type r reset awbxy_pcnt5[21:0] awb xy window 6 paxel count cam +036ch awb xy window 6 r sum awbxy_rsum 5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum5[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum5[15:0] type r reset awbxy_rsum5[28:0] awb xy window 6 r sum cam +0370h awb xy window 6 g sum awbxy_gsum 5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum5[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum5[15:0] type r reset awbxy_gsum5[28:0] awb xy window 6 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 790 of 1535 cam +0374h awb xy window 6 b sum awbxy_bsum 5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum5[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum5[15:0] type r reset awbxy_bsum5[28:0] awb xy window 6 b sum cam +0378h awb xy window 7 paxel count awbxy_pcnt6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt6[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt6[15:0] type r reset awbxy_pcnt6[21:0] awb xy window 7 paxel count cam +037ch awb xy window 7 r sum awbxy_rsum 6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum6[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum6[15:0] type r reset awbxy_rsum6[28:0] awb xy window 7 r sum cam +0380h awb xy window 7 g sum awbxy_gsum 6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum6[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum6[15:0] type r reset awbxy_gsum6[28:0] awb xy window 7 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 791 of 1535 cam +0384h awb xy window 7 b sum awbxy_bsum 6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum6[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum6[15:0] type r reset awbxy_bsum6[28:0] awb xy window 7 b sum cam +0388h awb xy window 8 paxel count awbxy_pcnt7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt7[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt7[15:0] type r reset awbxy_pcnt7[21:0] awb xy window 8 paxel count cam +038ch awb xy window 8 r sum awbxy_rsum 7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum7[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum7[15:0] type r reset awbxy_rsum7[28:0] awb xy window 8 r sum cam +0390h awb xy window 8 g sum awbxy_gsum 7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum7[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum7[15:0] type r reset awbxy_gsum7[28:0] awb xy window 8 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 792 of 1535 cam +0394h awb xy window 8 b sum awbxy_bsum 7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum7[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum7[15:0] type r reset awbxy_bsum7[28:0] awb xy window 8 b sum cam +0398h awb xy window 9 paxel count awbxy_pcnt8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt8[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt8[15:0] type r reset awbxy_pcnt8[21:0] awb xy window 9 paxel count cam +039ch awb xy window 9 r sum awbxy_rsum 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum8[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum8[15:0] type r reset awbxy_rsum8[28:0] awb xy window 9 r sum cam +03a0h awb xy window 9 g sum awbxy_gsum 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum8[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum8[15:0] type r reset awbxy_gsum8[28:0] awb xy window 9 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 793 of 1535 cam +03a4h awb xy window 9 b sum awbxy_bsum 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum8[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum8[15:0] type r reset awbxy_bsum8[28:0] awb xy window 9 b sum cam +03a8h awb xy window 10 paxel count awbxy_pcnt9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnt9[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnt9[15:0] type r reset awbxy_pcnt9[21:0] awb xy window 10 paxel count cam +03ach awb xy window 10 r sum awbxy_rsum 9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsum9[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsum9[15:0] type r reset awbxy_rsum9[28:0] awb xy window 10 r sum cam +03b0h awb xy window 10 g sum awbxy_gsum9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsum9[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsum9[15:0] type r reset awbxy_gsum9[28:0] awb xy window 10 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 794 of 1535 cam +03b4h awb xy window 10 b sum awbxy_bsum 9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsum9[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsum9[15:0] type r reset awbxy_bsum9[28:0] awb xy window 10 b sum cam +03b8h awb xy window 11 paxel count awbxy_pcnt a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcnta[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcnta[15:0] type r reset awbxy_pcnta[21:0] awb xy window 11 paxel count cam +03bch awb xy window 11 r sum awbxy_rsuma bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsuma[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsuma[15:0] type r reset awbxy_rsuma[28:0] awb xy window 11 r sum cam +03c0h awb xy window 11 g sum awbxy_gsuma bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsuma[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsuma[15:0] type r reset awbxy_gsuma[28:0] awb xy window 11 g sum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 795 of 1535 cam +03c4h awb xy window 11 b sum awbxy_bsuma bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_bsuma[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsuma[15:0] type r reset awbxy_bsuma[28:0] awb xy window 11 b sum cam +03c8h awb xy window 12 paxel count awbxy_pcnt b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_pcntb[21:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_pcntb[15:0] type r reset awbxy_pcntb[21:0] awb xy window 12 paxel count cam +03cch awb xy window 12 r sum awbxy_rsumb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_rsumb[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_rsumb[15:0] type r reset awbxy_rsumb[28:0] awb xy window 12 r sum cam +03d0h awb xy window 12 g sum awbxy_gsumb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbxy_gsumb[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_gsumb[15:0] type r reset awbxy_gsumb[28:0] awb xy window 12 g sum cam +03d4h awb xy window 12 b sum awbxy_bsumb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 796 of 1535 name awbxy_bsumb[28:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbxy_bsumb[15:0] type r reset awbxy_bsumb[28:0] awb xy window 12 b sum 5.5 camera interface sensor tg lens/ sensor compensation color process *41 MT6516 isp incorporates a feature rich image signal processor to connect with a variety of image sensor components. this processor consists of timing generated unit (tg) and lens/sensor compensation unit and image process unit. timing generated unit (tg) cooperates with master type image sensor only. that means sensor should send vertical and horizontal signals to tg. tg offers sensor required data clock and receive sensor bayer pattern raw data by internal auto synchronization or external pixel clock synchronization. the main purpose of tg is to create data clock for master type image sensor and accept vertical/horizontal synchronization signal and sensor data, and then generate grabbed area of raw data or yuv422/rgb565 data to the lens/sensor compensation unit. lens/sensor compensation unit generates compensated raw data to the color process unit in bayer raw data input mode. in yuv422/rgb565 input mode, this stage is bypassed. color process unit accepts bayer pattern raw data or yuv422/rgb565 data that is generated by lens/sensor compensation unit. the output of isp is ycbcr 888 data format which can be easily encoded by the compress engine (jpeg encoder and mpeg4 encoder). it can be the basic data domain of other data format translation such as r/g/b domain. the isp is pipelined, and during processing stages isp hardware can auto extract meaningful information for further ae/af/awb calculation. these information are temporary stored on isp registers or memory and can be read back by mcu. 5.5.1 register table register address register name synonym cam + 0000h tg phase counter register cam_phscnt cam + 0004h sensor size configuration register cam_camwin free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 797 of 1535 cam + 0008h tg grab range start/end pixel configuration register cam_grabcol cam + 000ch tg grab range start/end line configuration register cam_grabrow cam + 0010h sensor mode configuration register cam_csmode cam + 0014h component r, gr, b, gb, offset adjustment register cam_rgboff cam + 0018h view finder mode control register cam_vfcon cam + 001ch camera module interrupt enable register cam_inten cam + 0020h camera module interrupt status register cam_intsta cam + 0024h camera module path config register cam_path cam + 0028h camera module input address register cam_inaddr cam + 002ch camera module output address register cam_outaddr cam + 0030h preprocessing control register 1 cam_ctrl1 cam + 0034h awb r,g, b gain control register 1 cam_rgbgain1 cam + 0038h awb r,g, b gain control register 2 cam_rgbgain2 cam + 003ch histogram boundary control register 1 cam_his0 cam + 0040h histogram boundary control register 2 cam_his1 cam + 0044h preprocessing control register 2 cam_ctrl2 cam + 0048h ae window 1 register cam_aewin1 cam + 004ch ae histogram window register cam_ aewin2 cam + 0050h ae histogram gain register cam_ aewin3 cam + 0054h reserved reserved cam + 0058h reserved reserved cam + 005ch reserved reserved cam + 0060h reserved reserved cam + 0064h reserved reserved cam + 0068h reserved reserved cam + 006ch awb window register cam_awbwin cam + 0070h color processing stage control register cam_cpscon1 cam + 0074h interpolation register 1 cam_inter1 cam + 0078h interpolation register 2 cam_inter2 cam + 007ch edge core register cam_edgcore cam + 0080h edge gain register 1 cam_edggain1 cam + 0084h edge gain register 2 cam_edggain2 cam + 0088h edge threshold register cam_edgthre cam + 008ch edge vertical control register cam_edgvcon cam + 0090h axis rgb gain register cam_axgain cam + 0094h awb configuration register cam_opdcfg cam + 0098h awb component parameter register cam_opdpar cam + 009ch color matrix 1 register cam_matrix1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 798 of 1535 cam + 00a0h color matrix 2 register cam_matrix2 cam + 00a4h color matrix 3 register cam_matrix3 cam + 00a8h color matrix rgb gain register cam_mtxgain cam + 00ach color process stage control register 2 cam_cpscon2 cam + 00b0h color rgb gain register cam_cgain cam + 00b4h gamma rgb flare register cam_gamflre cam + 00b8h y channel configuration register cam_ychan cam + 00bch rgb2ycc control register rgb2ycc_con cam + 00c0h reserved reserved cam + 00c4h reserved reserved cam + 00c8h reserved reserved cam + 00cch reserved reserved cam + 00d0h reserved reserved cam + 00d4h awb y result register cam_opdy cam + 00d8h awb mg result register cam_opdmg cam + 00dch awb rb result register cam_opdrb cam + 00e0h awb pixel counter register cam_opdcnt cam + 00e4h reserved reserved cam + 00e8h reserved reserved cam + 00ech reserved reserved cam + 00f0h reserved reserved cam + 00f4h reserved reserved cam + 00f8h reserved reserved cam + 00fch reserved reserved cam + 0100h reserved reserved cam + 0104h reserved reserved cam + 0108h flare histogram 1 result cam_his_rlt0 cam + 010ch flare histogram 2 result cam_his_rlt1 cam + 0110h flare histogram 3 result cam_his_rlt2 cam + 0114h flare histogram 4 result cam_his_rlt3 cam + 0118h flare histogram 5 result cam_his_rlt4 cam + 011ch low pass filter control register cam_lpfcon cam + 0120h y low pass filter control register cam_ylpf cam + 0124h cbcr low pass filter control register cam_clpf cam + 0128h vertical subsample control register cam_vsub cam + 012ch horizontal subsample control register cam_hsub cam + 0130h reserved reserved cam + 0134h reserved reserved free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 799 of 1535 cam + 0138h reserved reserved cam + 013ch reserved reserved cam + 0140h reserved reserved cam + 0144h reserved reserved cam + 0148h reserved reserved cam + 014ch reserved reserved cam + 0150h reserved reserved cam + 0154h defect pixel configuration register cam_defect0 cam + 0158h defect pixel table address register cam_defect1 cam + 015ch defect pixel table debug register cam_defect2 cam + 0160h reserved reserved cam + 0164h reserved reserved cam + 0168h reserved reserved cam + 016ch raw gain register 1 cam_rawgain0 cam + 0170h raw gain register 2 cam_rawgain1 cam + 0174h result window vertical size register rwinv_sel cam + 0178h result window horizontal size register rwinh_sel cam + 017ch reserved reserved cam + 0180h camera interface debug mode control register cam_debug cam + 0184h camera module debug information write out destination address cam_dstaddr cam + 0188h camera module debug information last transfer destination address cam_lstaddr cam + 018ch camera module frame buffer transfer out count register cam_xfercnt cam + 0190h sensor test module configuration register 1 cam_mdlcfg1 cam + 0194h sensor test module configuration register 2 cam_mdlcfg2 cam + 0198h reserved reserved cam + 019ch reserved reserved cam + 01a0h ae address register cam_aeaddr cam + 01a4h ae window size register cam_aesize cam + 01a8h gamma register 1 gma_reg1 cam + 01ach gamma register 2 gma_reg2 cam + 01b0h gamma register 3 gma_reg3 cam + 01b4h gamma register 4 gma_reg4 cam + 01b8h gamma register 5 gma_reg5 cam + 01bch reserved reserved cam + 01c0h reserved reserved cam + 01c4h reserved reserved cam + 01c8h ae area register cam_aearea free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 800 of 1535 cam + 01cch reserved reserved cam + 01d0h reserved reserved cam + 01d4h flash control register flash_ctrl cam + 01d8h cam reset register cam_reset cam + 01dch tg status register tg_status cam + 01e0h reserved reserved cam + 01e4h reserved reserved cam + 01e8h reserved reserved cam + 01ech flare histogram 6 result cam_his_rlt5 cam + 01f0h flare histogram 7 result cam_his_rlt6 cam + 01f4h flare histogram 8 result cam_his_rlt7 cam + 01f8h flare histogram 9 result cam_his_rlt8 cam + 01fch flare histogram 10 result cam_his_rlt9 cam + 0200h reserved reserved cam + 0204h reserved reserved cam + 0208h reserved reserved cam + 020ch reserved reserved cam + 0210h reserved reserved cam + 0214h shading control 1 register cam_shading1 cam + 0218h shading control 2 register cam_shading2 cam + 021ch shading read address register sd_raddr cam + 0220h shading last block config register sd_lblock cam + 0224h shading ratio config register sd_ratio cam + 0228h reserved reserved cam + 022ch reserved reserved cam + 0230h ee control register ee_ctrl cam + 0234h ed lut x configuration ed_lut_x cam + 0238h ed lut y configuration ed_lut_y cam + 023ch reserved reserved cam + 0240h reserved reserved cam + 0244h reserved reserved cam + 0248h gmc debug register cam_gmcdebug cam + 024ch af window 1 register cam_afwin0 cam + 0250h af window 2 register cam_afwin1 cam + 0254h af window 3 register cam_afwin2 cam + 0258h af window 4 register cam_afwin3 cam + 025ch af window 5 register cam_afwin4 cam + 0260h af threshold 1 register cam_afth0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 801 of 1535 cam + 0264h af threshold 2 register cam_afth1 cam + 0268h reserved reserved cam + 026ch reserved reserved cam + 0270h reserved reserved cam + 0274h cam version register cam_version cam + 027ch awb sum window config register awbsum_win cam + 0280h awb control register awb_ctrl cam + 0284h awb threshold config register awb_th cam + 0288h awb color space h1 config register awbxy_h1 cam + 028ch awb color space h2 config register awbxy_h2 cam + 0290h awb color edge window horizontal config register awbce_winh cam + 0294h awb color edge window vertical config register awbce_winv cam + 0298h awb xy window 1 horizontal config register awbxy_winh0 cam + 029ch awb xy window 1 vertical config register awbxy_winv0 cam + 02a0h awb xy window 2 horizontal config register awbxy_winh1 cam + 02a4h awb xy window 2 vertical config register awbxy_winv1 cam + 02a8h awb xy window 3 horizontal config register awbxy_winh2 cam + 02ach awb xy window 3 vertical config register awbxy_winv2 cam + 02b0h awb xy window 4 horizontal config register awbxy_winh3 cam + 02b4h awb xy window 4 vertical config register awbxy_winv3 cam + 02b8h awb xy window 5 horizontal config register awbxy_winh4 cam + 02bch awb xy window 5 vertical config register awbxy_winv4 cam + 02c0h awb xy window 6 horizontal config register awbxy_winh5 cam + 02c4h awb xy window 6 vertical config register awbxy_winv5 cam + 02c8h awb xy window 7 horizontal config register awbxy_winh6 cam + 02cch awb xy window 7 vertical config register awbxy_winv6 cam + 02d0h awb xy window 8 horizontal config register awbxy_winh7 cam + 02d4h awb xy window 8 vertical config register awbxy_winv7 cam + 02d8h awb xy window 9 horizontal config register awbxy_winh8 cam + 02dch awb xy window 9 vertical config register awbxy_winv8 cam + 02e0h awb xy window 10 horizontal config register awbxy_winh9 cam + 02e4h awb xy window 10 vertical config register awbxy_winv9 cam + 02e8h awb xy window 11 horizontal config register awbxy_winha cam + 02ech awb xy window 11 vertical config register awbxy_winva cam + 02f0h awb xy window 12 horizontal config register awbxy_winhb cam + 02f4h awb xy window 12 vertical config register awbxy_winvb cam + 02f8h awb sum window paxel count awbsum_pcnt cam + 02fch awb sum window r sum awbsum_rsum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 802 of 1535 cam + 0300h awb sum window g sum awbsum_gsum cam + 0304h awb sum window b sum awbsum_bsum cam + 0308h awb color edge window paxel count awbce_pcnt cam + 030ch awb color edge window r sum awbce_rsum cam + 0310h awb color edge window g sum awbce_gsum cam + 0314h awb color edge window b sum awbce_bsum cam + 0318h awb xy window 1 paxel count awbxy_pcnt0 cam + 031ch awb xy window 1 r sum awbxy_rsum0 cam + 0320h awb xy window 1 g sum awbxy_gsum0 cam + 0324h awb xy window 1 b sum awbxy_bsum0 cam + 0328h awb xy window 2 paxel count awbxy_pcnt1 cam + 032ch awb xy window 2 r sum awbxy_rsum1 cam + 0330h awb xy window 2 g sum awbxy_gsum1 cam + 0334h awb xy window 2 b sum awbxy_bsum1 cam + 0338h awb xy window 3 paxel count awbxy_pcnt2 cam + 033ch awb xy window 3 r sum awbxy_rsum2 cam + 0340h awb xy window 3 g sum awbxy_gsum2 cam + 0344h awb xy window 3 b sum awbxy_bsum2 cam + 0348h awb xy window 4 paxel count awbxy_pcnt3 cam + 034ch awb xy window 4 r sum awbxy_rsum3 cam + 0350h awb xy window 4 g sum awbxy_gsum3 cam + 0354h awb xy window 4 b sum awbxy_bsum3 cam + 0358h awb xy window 5 paxel count awbxy_pcnt4 cam + 035ch awb xy window 5 r sum awbxy_rsum4 cam + 0360h awb xy window 5 g sum awbxy_gsum4 cam + 0364h awb xy window 5 b sum awbxy_bsum4 cam + 0368h awb xy window 6 paxel count awbxy_pcnt5 cam + 036ch awb xy window 6 r sum awbxy_rsum5 cam + 0370h awb xy window 6 g sum awbxy_gsum5 cam + 0374h awb xy window 6 b sum awbxy_bsum5 cam + 0378h awb xy window 7 paxel count awbxy_pcnt6 cam + 037ch awb xy window 7 r sum awbxy_rsum6 cam + 0380h awb xy window 7 g sum awbxy_gsum6 cam + 0384h awb xy window 7 b sum awbxy_bsum6 cam + 0388h awb xy window 8 paxel count awbxy_pcnt7 cam + 038ch awb xy window 8 r sum awbxy_rsum7 cam + 0390h awb xy window 8 g sum awbxy_gsum7 cam + 0394h awb xy window 8 b sum awbxy_bsum7 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 803 of 1535 cam + 0398h awb xy window 9 paxel count awbxy_pcnt8 cam + 039ch awb xy window 9 r sum awbxy_rsum8 cam + 03a0h awb xy window 9 g sum awbxy_gsum8 cam + 03a4h awb xy window 9 b sum awbxy_bsum8 cam + 03a8h awb xy window 10 paxel count awbxy_pcnt9 cam + 03ach awb xy window 10 r sum awbxy_rsum9 cam + 03b0h awb xy window 10 g sum awbxy_gsum9 cam + 03b4h awb xy window 10 b sum awbxy_bsum9 cam + 03b8h awb xy window 11 paxel count awbxy_pcnta cam + 03bch awb xy window 11 r sum awbxy_rsuma cam + 03c0h awb xy window 11 g sum awbxy_gsuma cam + 03c4h awb xy window 11 b sum awbxy_bsuma cam + 03c8h awb xy window 12 paxel count awbxy_pcntb cam + 03cch awb xy window 12 r sum awbxy_rsumb cam + 03d0h awb xy window 12 g sum awbxy_gsumb cam + 03d4h awb xy window 12 b sum awbxy_bsumb cam + 03d8h reserved reserved cam + 03dch reserved reserved cam + 03e0h reserved reserved cam + 03e4h reserved reserved cam + 03e8h reserved reserved cam + 03ech reserved reserved cam + 03f0h reserved reserved cam + 03f4h reserved reserved cam + 03f8h reserved reserved cam + 03fch reserved reserved cam + 0400h af window 1 threshold 1 focus value af0_sum0 cam + 0404h af window 1 threshold 2 focus value af0_sum1 cam + 0408h af window 1 threshold 3 focus value af0_sum2 cam + 040ch af window 1 threshold 4 focus value af0_sum3 cam + 0410h af window 1 threshold 5 focus value af0_sum4 cam + 0414h af window 2 threshold 1 focus value af1_sum0 cam + 0418h af window 2 threshold 2 focus value af1_sum1 cam + 041ch af window 2 threshold 3 focus value af1_sum2 cam + 0420h af window 2 threshold 4 focus value af1_sum3 cam + 0424h af window 2 threshold 5 focus value af1_sum4 cam + 0428h af window 3 threshold 1 focus value af2_sum0 cam + 042ch af window 3 threshold 2 focus value af2_sum1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 804 of 1535 cam + 0430h af window 3 threshold 3 focus value af2_sum2 cam + 0434h af window 3 threshold 4 focus value af2_sum3 cam + 0438h af window 3 threshold 5 focus value af2_sum4 cam + 043ch af window 4 threshold 1 focus value af3_sum0 cam + 0440h af window 4 threshold 2 focus value af3_sum1 cam + 0444h af window 4 threshold 3 focus value af3_sum2 cam + 0448h af window 4 threshold 4 focus value af3_sum3 cam + 044ch af window 4 threshold 5 focus value af3_sum4 cam + 0450h af window 5 threshold 1 focus value af4_sum0 cam + 0454h af window 5 threshold 2 focus value af4_sum1 cam + 0458h af window 5 threshold 3 focus value af4_sum2 cam + 045ch af window 5 threshold 4 focus value af4_sum3 cam + 0460h af window 5 threshold 5 focus value af4_sum4 cam + 0500h nr2 control register nr2_con cam + 0504h reserved reserved cam + 0508h nr2 configuration register 2 nr2_cfg2 cam + 050ch nr2 configuration register 3 nr2_cfg3 cam + 0510h nr2 configuration register 4 nr2_cfg4 cam + 0514h reserved reserved cam + 0518h reserved reserved cam + 051ch reserved reserved cam + 0520h gdc control register gdc_con cam + 0524h gdc weighting table configuration gdc_wtbl cam + 0528h gdc manual curve configuration 1 gdc_mmc1 cam + 052ch gdc manual curve configuration 2 gdc_mmc2 cam + 0530h gdc manual curve configuration 3 gdc_mmc3 cam + 0534h gdc manual curve configuration 4 gdc_mmc4 cam + 0538h gdc manual curve configuration 5 gdc_mmc5 cam + 053ch gdc manual curve configuration 6 gdc_mmc6 cam + 0540h hst control register hst_con cam + 0544h hst configuration register 1 hst_cfg1 cam + 0548h hst configuration register 2 hst_cfg2 cam + 054ch hst configuration register 3 hst_cfg3 cam + 0550h nr1 control register nr1_con cam + 0554h nr1 defective pixel configuration register 1 nr1_dp1 cam + 0558h nr1 defective pixel configuration register 2 nr1_dp2 cam + 055ch nr1 defective pixel configuration register 3 nr1_dp3 cam + 0560h nr1 defective pixel configuration register 4 nr1_dp4 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 805 of 1535 cam + 0564h nr1 crosstalk compensation configuration register nr1_ct cam + 0568h nr1 noise reduction configuration register 1 nr1_nr1 cam + 056ch nr1 noise reduction configuration register 2 nr1_nr2 cam + 0570h nr1 noise reduction configuration register 3 nr1_nr3 cam + 0574h nr1 noise reduction configuration register 4 nr1_nr4 cam + 0578h nr1 noise reduction configuration register 5 nr1_nr5 cam + 057ch nr1 noise reduction configuration register 6 nr1_nr6 cam + 0580h nr1 noise reduction configuration register 7 nr1_nr7 cam + 0584h nr1 noise reduction configuration register 8 nr1_nr8 cam + 0588h nr1 noise reduction configuration register 9 nr1_nr9 cam + 058ch nr1 noise reduction configuration register 10 nr1_nr10 cam + 0600h yccgo control register yccgo_con cam + 0604h yccgo configuration register 1 yccgo_cfg1 cam + 0608h yccgo configuration register 2 yccgo_cfg2 cam + 060ch yccgo configuration register 3 yccgo_cfg3 cam + 0610h yccgo configuration register 4 yccgo_cfg4 cam + 0614h yccgo configuration register 5 yccgo_cfg5 cam + 0618h yccgo configuration register 6 yccgo_cfg6 cam +(1000h ~ 104ch) ae window result 1~20 aemem(0~19) cam + (1050h ~ 105ch) ae block count, bayer size, awb debug 1,awb debug 2 cam + (1060h ~ 1084h) flare histogram result (1-10) flaremem(0~9) cam + (1088h ~ 1124h) af filter (1-48) cam + (1128h ~ 1144h) af mean (1-8) cam + (1148h ~1204h) awb xy window result(1-12) (count, rsum, gsum, bsum) cam + (1208h ~ 1214h) awb sum window result (count, rsum, gsum, bsum) cam + (1218h ~ 1224h) awb color edge window result (count, rsum, gsum, bsum) cam + (1228h ~ 1324h) ae histogram result (1-64) aehis(0~63) cam + 2000h reserved reserved cam + 3000h awb r histogram memory awbrhis cam + 4000h awb g histogram memory awbghis cam + 5000h awb b histogram memory awbbhis cam + 6000h gdc histogram memory gdchis free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 806 of 1535 table 98 camera interface register map cam+0400h af window 1 threshold 1 focus value af0_sum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af0_sum0[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af0_sum0[15:0] type ro reset 0 af0_sum0 af window 1 threshold 1 focus value cam+0404h af window 1 threshold 2 focus value af0_sum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af0_sum1[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af0_sum1[15:0] type ro reset 0 af0_sum1 af window 1 threshold 2 focus value cam+0408h af window 1 threshold 3 focus value af0_sum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af0_sum2[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af0_sum2[15:0] type ro reset 0 af0_sum2 af window 1 threshold 3 focus value cam+040ch af window 1 threshold 4 focus value af0_sum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af0_sum3[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af0_sum3[15:0] type ro reset 0 af0_sum3 af window 1 threshold 4 focus value cam+0410h af window 1 threshold 5 focus value af0_sum4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 807 of 1535 name af0_sum4[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af0_sum4[15:0] type ro reset 0 af0_sum4 af window 3 threshold 5 focus value cam+0414h af window 2 threshold 1 focus value af1_sum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af1_sum0[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af1_sum0[15:0] type ro reset 0 af1_sum0 af window 2 threshold 1 focus value cam+0418h af window 2 threshold 2 focus value af1_sum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af1_sum1[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af1_sum1[15:0] type ro reset 0 af0_sum1 af window 2 threshold 2 focus value cam+041ch af window 2 threshold 3 focus value af1_sum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af1_sum2[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af1_sum2[15:0] type ro reset 0 af1_sum2 af window 2 threshold 3 focus value cam+0420h af window 2 threshold 4 focus value af1_sum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af1_sum3[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af1_sum3[15:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 808 of 1535 type ro reset 0 af1_sum3 af window 2 threshold 4 focus value cam+0424h af window 2 threshold 5 focus value af1_sum4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af1_sum4[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af1_sum4[15:0] type ro reset 0 af1_sum4 af window 2 threshold 5 focus value cam+0428h af window 3 threshold 1 focus value af2_sum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af2_sum0[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af2_sum0[15:0] type ro reset 0 af2_sum0 af window 3 threshold 1 focus value cam+042ch af window 3 threshold 2 focus value af2_sum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af2_sum1[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af2_sum1[15:0] type ro reset 0 af2_sum1 af window 3 threshold 2 focus value cam+0430h af window 3 threshold 3 focus value af2_sum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af2_sum2[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af2_sum2[15:0] type ro reset 0 af2_sum2 af window 3 threshold 3 focus value free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 809 of 1535 cam+0434h af window 3 threshold 4 focus value af2_sum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af2_sum3[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af2_sum3[15:0] type ro reset 0 af2_sum3 af window 3 threshold 4 focus value cam+0438h af window 3 threshold 5 focus value af2_sum4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af2_sum4[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af2_sum4[15:0] type ro reset 0 af2_sum4 af window 3 threshold 5 focus value cam+043ch af window 4 threshold 1 focus value af3_sum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af3_sum0[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af3_sum0[15:0] type ro reset 0 af3_sum0 af window 4 threshold 1 focus value cam+0440h af window 4 threshold 2 focus value af3_sum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af3_sum1[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af3_sum1[15:0] type ro reset 0 af3_sum1 af window 4 threshold 2 focus value cam+0444h af window 4 threshold 3 focus value af3_sum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af3_sum2[31:16] type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 810 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af3_sum2[15:0] type ro reset 0 af3_sum2 af window 4 threshold 3 focus value cam+0448h af window 4 threshold 4 focus value af3_sum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af3_sum3[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af3_sum3[15:0] type ro reset 0 af3_sum3 af window 4 threshold 4 focus value cam+044ch af window 4 threshold 5 focus value af3_sum4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af3_sum4[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af3_sum4[15:0] type ro reset 0 af3_sum4 af window 4 threshold 5 focus value cam+0450h af window 5 threshold 1 focus value af4_sum0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af4_sum0[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af4_sum0[15:0] type ro reset 0 af4_sum0 af window 5 threshold 1 focus value cam+0454h af window 5 threshold 2 focus value af4_sum1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af4_sum1[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af4_sum1[15:0] type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 811 of 1535 af4_sum1 af window 5 threshold 2 focus value cam+0458h af window 5 threshold 3 focus value af4_sum2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af4_sum2[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af4_sum2[15:0] type ro reset 0 af4_sum2 af window 5 threshold 3 focus value cam+045ch af window 5 threshold 4 focus value af4_sum3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af4_sum3[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af4_sum3[15:0] type ro reset 0 af4_sum3 af window 5 threshold 4 focus value cam+0460h af window 5 threshold 5 focus value af4_sum4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name af4_sum4[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name af4_sum4[15:0] type ro reset 0 af4_sum4 af window 5 threshold 5 focus value cam+0500h nr2 control register nr2_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc eny type r/w r/w reset 0 0 enc enable bit of chroma (u/v) channel noise reduction 0 disable 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 812 of 1535 eny enable bit of luma (y) channel noise reduction 0 disable 1 enable cam+0508h nr2 configuration register 2 nr2_cfg2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name uv_smpl s2 s3 type r/w r/w r/w reset 2 2 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sy1 sc1 gny gnc type r/w r/w r/w r/w reset 2 2 4 4 uv_smpl mode selection of u/v down-sample 00 right 01 left 10 average s2 weighting factor s2. (s2 is valid from 0 to 4. normalized gain = s2/4) s3 weighting factor s3. (s3 is valid from 0 to 4. normalized gain = s3/4) sy1 weighting factor sy1. (sy1 is valid from 0 to 8. the normalized gain = sy1/4.) sc1 weighting factor sc1. (sc1 is valid from 0 to 8. the normalized gain = sc1/4.) gny gain y of luma channel. (gny is valid from 0 to 8. normalized gain = gny/8.) gnc gain c of chroma channel. (gnc is valid from 0 to 8. normalized gain = gnc/8.) cam+050ch nr2 configuratio n register 3 nr2_cfg3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pty1 pty2 type r/w r/w reset 2 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pty3 pty4 type r/w r/w reset 6 8 pty1 y1 point. (0-255) pty2 y2 point. (0-255) pty3 y3 point. (0-255) pty4 y4 point. (0-255) note: the four values are valid from 0 to 255, and pty1<=pty2<=pty3<=pty4 cam+0510h nr2 configuratio n register 4 nr2_cfg4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ptc1 ptc2 type r/w r/w reset 4 6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ptc3 ptc4 type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 813 of 1535 reset 8 10 ptc1 c1 point. ptc2 c2 point. ptc3 c3 point. ptc4 c4 point. note: the four values are valid from 0 to 255, and ptc1<=ptc2<=ptc3<=ptc4 cam+0520h gdc control register gdc_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pnum mode lpfen en type r/w r/w r/w r/w reset 0 1 1 0 pnum selection of the pixel number of image histogram. pnum should be consistent with hst setting. the register should be configured correctly when auto mode is selected mode mode of gdc operation 0 auto 1 manual lpfen enable bit of 1-d lpf function 0 disable 1 enable en enable bit of gdc function 0 disable 1 enable cam+0524h gdc weighting tabl e configuration gdc_wtbl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wty1 wty2 type r/w r/w reset 2 12 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wty3 wtx1 wtx2 type r/w r/w r/w reset 4 4 13 the register is for the configuration of the weighting table f(x). wty1, wty2, wty3 data is valid from 0 to 63. the normalized gain is wty/64. wtx1, wtx2 data is valid from 0 to 15. the scaled value is wtx * 256 in 12-bit data domain. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 814 of 1535 cam+0528h gdc manual curve configuration 1 gdc_mmc1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x01 x02 type r/w r/w reset 4 8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x03 x04 type r/w r/w reset 16 24 cam+052ch gdc manual curve configuration 2 gdc_mmc2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x05 x06 type r/w r/w reset 32 48 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x07 x08 type r/w r/w reset 64 96 cam+0530h gdc manual curve configuration 3 gdc_mmc3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x09 x10 type r/w r/w reset 128 160 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x11 x12 type r/w r/w reset 192 224 cam+0534h gdc manual curve configuration 4 gdc_mmc4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y01 y02 type r/w r/w reset 4 8 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y03 y04 type r/w r/w reset 16 24 cam+0538h gdc manual curve configuration 5 gdc_mmc5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y05 y06 type r/w r/w reset 32 48 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y07 y08 type r/w r/w reset 64 96 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 815 of 1535 the register is used to set the mapping curve while operating in manual mode. cam+053ch gdc manual curve configuration 6 gdc_mmc6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y09 y10 type r/w r/w reset 128 160 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y11 y12 type r/w r/w reset 192 224 the register is used to set the mapping curve while operating in manual mode. the following figure shows an example of the mapping curve. cam+0540h hst control register hst_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto mode en type r/w r/w r/w reset 0 0 0 auto hardware auto sub-sample for histogram. 0 disable. the sample point is calculated according to hst_cfg1, hst_cfg2 and hst_cfg3. 1 auto resize, hst_cfg3 is meaningless. hardware will auto sub-sample points for histogram to fit gdc_con.pnum. note that the window of histogram defined in hst_cfg1 and hst_cfg2 should be larger than gdc_con.pnum. mode select the type of image source 0 calculate the y histogram (y=r/4+g/2+b/4) 1 calculate the histogram of r only 2 calculate the histogram of g only 3 calculate the histogram of b only en enable bit of hst function. 0 disable 1 enable cam+0544h hst configuration register 1 hst_cfg1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sta_h type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end_h type r/w reset 639 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 816 of 1535 sta_h the position of the starting pixel of each row end_h the position of the ending pixel of each row cam+0548h hst configuration register 2 hst_cfg2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name sta_v type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end_v type r/w reset 479 the register is for global configuration of hst. sta_v the position of the starting pixel of each column end_v the position of the ending pixel of each column cam+054ch hst configuration register 3 hst_cfg3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name skp_h skp_v type r/w r/w reset 3 3 the register is for global configuration of hst. skp_h down-sample ratio of each row (e.g. if the down-sample ratio = 1/n, skp_h should be set to n-1) skp_v down-sample ratio of each column cam+0550h nr1 control register nr1_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bwd bht type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bht mdct binop binmd enbin ennr enct endp type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3 0 0 0 0 0 0 bwd[9:0] the register is used to set the image width of nr1 output in 3x3 binning mode bht [9:0] the register is used to set the image height of nr1 output in 3x3 binning mode mdct the register bit is used to configure the mode of crosstalk compensation 0 use noise reduction table to determine on or off 3 use threshold to determine on or off binop the register bit is used to select the method of pixel binning 0 accumulation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 817 of 1535 1 average binmd the register bit is used to select the size of pixel binning 0 2x2 pixel binning 1 3x3 pixel binning enbin enable bit of pixel binning 0 disable 1 enable (note: when the bit is ?1?, functions of noise reduction, crosstalk and auto defect pixel detection are turned off automatically.) ennr enable bit of noise reduction 0 disable 1 enable (note: when the bit is ?1?, the output resolution will decrease by 2 horizontally and vertically.) enct enable bit of crosstalk compensation 0 disable 1 enable endp enable bit of auto defective pixel detection & correction 0 disable 1 enable note: the input width and height is not the same with output width and height if nr or binning is enabled. and the input size has certain kind of restriction. please refer to the following table. input (widt h and heig ht) o ( a h ) binning 3x3 6n 2 binning 2x2 4n+2 2 nr n+2 n ps. n is an integer cam+0554h nr1 defective pixel configuration register 1 nr1_dp1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dp_thrd2 dp_thrd0 type r/w r/w reset 5 40 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dp_thrd3 dp_thrd1 type r/w r/w reset 5 80 the register is for global configuration of defective pixel detection. dp_thrd2 ? threshold2?. data is valid from 0 to 15. dp_thrd0 ? threshold0?. data is valid from 0 to 1023. dp_thrd3 ? threshold3?. data is valid from 0 to 15. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 818 of 1535 dp_thrd1 ? threshold1?. data is valid from 0 to 1023. cam+0558h nr1 defective pixel configuration register 2 nr1_dp2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dp_thrd4 type r/w reset 96 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dp_thrd5 type r/w reset 928 dp_thrd4 ? threshold4?. data is valid from 0 to 1023. dp_thrd5 ? threshold5?. data is valid from 0 to 1023. note: dp_thrd5 should be larger than threshold4. cam+055ch nr1 defective pixel configuration register 3 nr1_dp3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dp_thrd6 type r/w reset 48 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dp_thrd7 type r/w reset 80 dp_thrd6 ? threshold6?. data is valid from 0 to 1023. dp_thrd7 ? threshold7?. data is valid from 0 to 1023. cam+0560h nr1 defective pixel configuration register 4 nr1_dp4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dp_num dp_sel dp_cd 7 dp_c d6 dp_cd 5 dp_cd 4 dp_cd 3 dp_cd 2 dp_c d1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 2 1 0 0 0 0 0 0 0 dp_num the max number of defective pixel in the 5x5 window (2 is the recommended value.) dp_sel choose which pixel value to compensate. dp_cd1-7 enable bits of the conditions for defective pixel detection. when all the enabled conditions are met, the pixel is considered as the defective one. 0 disable 1 enable cam+0564h nr1 crosstalk compensati on configuration register nr1_ct bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 819 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ct_div ct_thrd type r/w r/w reset 1 128 ct_div selection of the ct compensation value when ct detection is off 0 compensation value is clipped to zero. 1 compensation value is half of the value. ct_thrd crosstalk threshold. cam+0568h nr1 noise reduction configuration register 1 nr1_nr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gnf type r/w reset 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name s1 s2 mbnd type r/w r/w r/w reset 2 4 160 the register is for global configuration of noise reduction gnf gain x value. data is valid from 0 to 8. the normalized gain is gnf/8. s1 weighting value s1. data is valid from 0 to 4. the normalized gain is s1/4. s2 weighting value s2. data is valid from 0 to 4. the normalized gain is s2/4. mbnd threshold value cam+056ch nr1 noise reduction configuration register 2 nr1_nr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gn1 gn2 gn3 type r/w r/w r/w reset 6 8 10 the register is for global configuration of noise reduction. gn1, gn2, gn3 gain value 1, 2, 3. the data is valid from 5 to 15. the normalized gain is gn/4. note: there is a constraint for these parameters. gn3 > gn2 > gn1 > 4 cam+0570h nr1 noise reduction configuration register 3 nr1_nr3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlr1 vlr2 type r/w r/w reset 4 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlr3 vlr4 type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 820 of 1535 reset 4 4 vlr1, vlr2, vlr3, vlr4 g(0), g(32), g(64), g(96) values of r channel. cam+0574h nr1 noise reduction configuration register 4 nr1_nr4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlr5 vlr6 type r/w r/w reset 6 6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlr7 vlr8 type r/w r/w reset 8 8 vlr5, vlr6, vlr7, vlr8 g(128), g(160), g(192), g(224) values of r channel. cam+0578h nr1 noise reduction configuration register 5 nr1_nr5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlgr1 vlgr2 type r/w r/w reset 2 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlgr3 vlgr4 type r/w r/w reset 4 4 vlgr1, vlgr2, vlgr3, vlgr4 g(0), g(32), g(64), g(96) values of gr channel. cam+057ch nr1 noise reduction co nfiguration register 6 nr1_nr6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlgr5 vlgr6 type r/w r/w reset 4 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlgr7 vlgr8 type r/w r/w reset 6 6 vlgr5, vlgr6, vlgr7, vlgr8 g(128), g(160), g(192), g(224) values of gr channel. cam+0580h nr1 noise reduction configuration register 7 nr1_nr7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlgb1 vlgb2 type r/w r/w reset 2 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlgb3 vlgb4 type r/w r/w reset 4 4 vlgb1, vlgb2, vlgb3, vlgb4 g(0), g(32), g(64), g(96) values of gb channel. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 821 of 1535 cam+0584h nr1 noise reduction configuration register 8 nr1_nr8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlgb5 vlgb6 type r/w r/w reset 4 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlgb7 vlgb8 type r/w r/w reset 6 6 vlgb5, vlgb6, vlgb7, vlgb8 g(128), g(160), g(192), g(224) values of gb channel. cam+0588h nr1 noise reduction configuration register 9 nr1_nr9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlb1 vlb2 type r/w r/w reset 4 4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlb3 vlb4 type r/w r/w reset 4 4 vlb1, vlb2, vlb3, vlb4 g(0), g(32), g(64), g(96) values of b channel. cam+058ch nr1 noise reduction configuration register 10 nr1_nr10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlb5 vlb6 type r/w r/w reset 6 6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlb7 vlb8 type r/w r/w reset 8 8 vlb5, vlb6, vlb7, vlb8 g(128), g(160), g(192), g(224) values of b channel. cam+0600h yccgo control register yccgo_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eny1 eny2 eny3 enc1 enc2 enc3 type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 eny1 enable bit of luma-knee effect. 0 disable 1 enable eny2 enable bit of luma-inversion effect 0 disable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 822 of 1535 1 enable eny3 enable bit of brightness and contrast adjustments 0 disable 1 enable enc1 enable bit of manual chroma setting 0 disable 1 enable enc2 enable bit of hue adjustment 0 disable 1 enable enc3 enable bit of saturation adjustment 0 disable 1 enable note 1: only one of eny1, eny2, and eny3 can be ?1?. note 2: if enc1 is enabled, enc2 and enc3 should be disabled. cam+0604h yccgo configuration register 1 yccgo_cfg1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mu mv type r/w r/w reset 128 128 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h11 h12 type r/w r/w reset 127 1 mu, mv cb and cr values when enc1 is enabled. h11, h12 ycc_h11 and ycc_h12 in the following figure (represented by the format of 2?s complement) note: mu and mv is valid from 0 to 255. cam+0608h yccgo configuration register 2 yccgo_cfg2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y1 y2 type r/w r/w reset 16 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y3 y4 type r/w r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? 128 128 cr cb v u 1 ycc_h1 ycc_h12 ycc_h12 - ycc_h11 sin 127 ycc_h12 cos 127 ycc_h11 ? = ? = free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 823 of 1535 reset 224 240 y1, y2, y3, y4 ycc_y1, ycc_y2, ycc_y3, and ycc_y4 in the following figure cam+060ch yccgo configuration register 3 yccgo_cfg3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1 g2 type r/w r/w reset 64 64 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g3 g4 type r/w r/w reset 64 64 g1, g2, g3, g4 ycc_g1, ycc_g2, ycc_g3, and ycc_g4 in the above figure cam+0610h yccgo configuration register 4 yccgo_cfg4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g5 ofsty type r/w r/w reset 64 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ofstu ofstv type r/w r/w reset 0 0 g5 ycc_g5 in the above figure ofsty ycc_ofsty in the following figure (represented by the format of 2?s complement) ofstu, ofstv ycc_ofstu and ycc_ofstv in the above figure (represented by the format of 2?s complement) note: ycc_g1 <= ycc_g2 <= ycc_g3; ycc_g5 <= ycc_g4 <= ycc_g3 cam+0614h yccgo configuration register 5 yccgo_cfg5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ybndh ybndl type r/w r/w reset 255 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gainy type r/w reset 64 ybndh the upper clipping value of y ybndl the lower clipping value of y gainy ycc_gainy in the above figure cam+0618h yccgo configuration register 6 yccgo_cfg6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ubndh ubndl type r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 824 of 1535 reset 255 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vbndh vbndl type r/w r/w reset 255 0 ubndh the upper clipping value of u ubndl the lower clipping value of u vbndh the upper clipping value of v vbndl the lower clipping value of v cam+1000h ae window result 1 aemem0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum1[7:0] aesum0[23:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum0[15:0] type r reset aesum0 ae window 0 summation aesum1 ae window 1 summation low byte cam+1004h ae window result 2 aemem1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum2[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum1[23:8] type r reset aesum1 ae window 1 summation high bytes aesum2 ae window 2 summation low bytes cam+1008h ae window result 3 aemem2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum3[23:8] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum3[7:0] aesum2[23:16] type r r reset aesum3 ae window 0 summation aesum2 ae window 1 summation high byte free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 825 of 1535 cam+100ch ae window result 4 aemem3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae aesum4[23:16] type r r reset 0xae bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum4[15:0] type r reset aesum4 ae window 4 summation cam+1010h ae window result 5 aemem4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum6[7:0] aesum5[23:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum5[15:0] type r reset aesum5 ae window 5 summation aesum6 ae window 6 summation low byte cam+1014h ae window result 6 aemem5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum7[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum6[23:8] type r reset aesum6 ae window 6 summation high bytes aesum7 ae window 7 summation low bytes cam+1018h ae window result 7 aemem6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum8[23:8] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum8[7:0] aesum7[23:16] type r r reset aesum8 ae window 0 summation aesum7 ae window 1 summation high byte free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 826 of 1535 cam+101ch ae window result 8 aemem7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae aesum9[23:16] type r r reset 0xae bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum9[15:0] type r reset aesum9 ae window 9 summation cam+1020h ae window result 9 aemem8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum11[7:0] aesum10[23:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum10[15:0] type r reset aesum10 ae window 10 summation aesum11 ae window 11 summation low byte cam+1024h ae window result 10 aemem9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum12[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum11[23:8] type r reset aesum11 ae window 11 summation high bytes aesum12 ae window 12 summation low bytes cam+1028h ae window result 11 aemem10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum13[23:8] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum13[7:0] aesum12[23:16] type r r reset aesum12 ae window 12 summation aesum13 ae window 13 summation high byte free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 827 of 1535 cam+102ch ae window result 12 aemem11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae aesum14[23:16] type r r reset 0xae bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum14[15:0] type r reset aesum14 ae window 9 summation cam+1030h ae window result 13 aemem12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum16[7:0] aesum15[23:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum15[15:0] type r reset aesum15 ae window 10 summation aesum16 ae window 11 summation low byte cam+1034h ae window result 14 aemem13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum17[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum16[23:8] type r reset aesum16 ae window 16 summation high bytes aesum17 ae window 17 summation low bytes cam+1038h ae window result 15 aemem14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum18[23:8] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum18[7:0] aesum17[23:16] type r r reset aesum17 ae window 17 summation high byte aesum18 ae window 18 summation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 828 of 1535 cam+103ch ae window result 16 aemem15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae aesum19[23:16] type r r reset 0xae bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum19[15:0] type r reset aesum19 ae window 19 summation cam+1040h ae window result 17 aemem16 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum21[7:0] aesum20[23:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum20[15:0] type r reset aesum20 ae window 20 summation aesum21 ae window 21 summation low byte cam+1044h ae window result 18 aemem17 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum22[15:0] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum21[23:8] type r reset aesum21 ae window 21 summation high bytes aesum22 ae window 22 summation low bytes cam+1048h ae window result 19 aemem18 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aesum23[23:8] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum23[7:0] aesum22[23:16] type r r reset aesum22 ae window 22 summation high byte aesum23 ae window 23 summation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 829 of 1535 cam+104ch ae window result 20 aemem19 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ae aesum24[23:16] type r r reset 0xae bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aesum24[15:0] type r reset aesum24 ae window 24 summation cam+(1050~1074)h flare histogram (1 ~ 10) flaremem(0~9) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name flareb(0~9)[21:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flareb(0~9)[15:0] type r reset flareb(0~9) flare histogram bin (0~9) cam+(1078~1174)h ae histogram (1 ~ 64) aehis(0~63) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name aehis(0~63)[19:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aehis(0~63)[15:0] type r reset aehis(0~63) ae histogram bin (0~63) cam+(1178~1234)h awb xy window result (1 ~ 12) (count) awbxy_rlt (0~12) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_wcount(0~11)[19:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_wcount(0~11)[15:0] type r reset awbout_wcount(0~11) awb xy window count cam+(1178~1234)h awb xy window result (1 ~ 12) (rsum) awbxy_rlt (0~12) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_wrsum(0~11)[31:16] type r free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 830 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_wrsum(0~11)[15:0] type r reset awbout_wrsum(0~11) awb xy window r sum cam+(1178~1234)h awb xy window result (1 ~ 12) (gsum) awbxy_rlt (0~12) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_wgsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_wgsum(0~11)[15:0] type r reset awbout_wgsum(0~11) awb xy window g sum cam+(1178~1234)h awb xy window result (1 ~ 12) (bsum) awbxy_rlt (0~12) bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_wbsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_wbsum(0~11)[15:0] type r reset awbout_wbsum(0~11) awb xy window b sum cam+1238h awb sum window r esult (1 ~ 12) (count) awbsum_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_fcount[19:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_fcount[15:0] type r reset awbout_fcount awb sum window count cam+123ch awb sum win dow result (rsum) awbsum_rsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_frsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_frsum(0~11)[15:0] type r reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 831 of 1535 awbout_frsum awb sum window r sum cam+1240h awb sum window result (gsum) awbsum_gsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_fgsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_fgsum(0~11)[15:0] type r reset awbout_fgsum awb sum window g sum cam+1244h awb sum win dow result (bsum) awbsum_bsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_fbsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_fbsum(0~11)[15:0] type r reset awbout_fbsum awb sum window b sum cam+1248h awb color edge window result (1 ~ 12) (count) awbce_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_cecount[19:16] type r r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_cecount[15:0] type r reset awbout_cecount awb color edge window count cam+124ch awb color edge window result (rsum) awbce_rsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_cersum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_cersum(0~11)[15:0] type r reset awbout_cersum awb color edge window r sum cam+1250h awb color edge window result (gsum) awbce_gsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 832 of 1535 name awbout_cegsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_cegsum(0~11)[15:0] type r reset awbout_cegsum awb color edge window g sum cam+1254h awb color edge window result (bsum) awbce_bsum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name awbout_cebsum(0~11)[31:16] type r reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name awbout_cebsum(0~11)[15:0] type r reset awbout_cebsum awb color edge window b sum cam+6000 - 6100h hst bin01 - 64 hst_bin01 - 64 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bin01 ? 64 type r reset 0 the registers are used to read the histogram from bin01 to bin64, which is used by gdc note: the enable bit of hst function (hst_con/cam+0x540) should be set as low ?0?, while reading the values 5.6 capture resize 5.6.1 general description this block provides the image resizing function for image and video capturing scenarios. it receives image data from the isp module, performs the image resizing function and outputs to the img_dma module. figure 116 shows the block diagram. the capture resize is composed of horizontal and vertical resizing blocks. it can scale up or down the input image by any ratio. however, the maximum sizes of input and output images are limited to 4095x4095 with limitation specified on chapter 1.1.3 application notes. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 833 of 1535 vertical resize isp yuv444 vert. buffer yuv444 img_dma yuv422 horizontal resize figure 116 block diagram of the capture resize the main algorithm of resizing function is cubic interpolation. the input and output format are both yuv444. but the internal working memory format is yuv422 to mitigate memory and bandwidth requirements. 5.6.2 register definitions register address register name synonym crz+ 0000h capture resize configuration register crz_cfg crz + 0004h capture resize control register crz_con crz + 0008h capture resize status register crz_sta crz + 000ch capture resize interrupt register crz_int crz + 0010h capture resize source image size register 1 crz_srcsz1 crz + 0014h capture resize target image size register 1 crz_tarsz1 crz + 0018h capture resize horizontal ratio register 1 crz_hratio1 crz + 001ch capture resize vertical ratio register 1 crz_vratio1 crz + 0040h capture resize coefficient table crz_frcfg 5.6.2.1 capture resize configuration register crz+0000h capture resize configuration register crz_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lbmax type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name norf db vsrst en ecv inten[ 1] inten [0] lbsel pcon o_y2r 1 o_ipp 1 o_ovl src type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 1 0 0 0 0 0 the register is for global configuration of capture resize. src the register field specifies which source is serviced. 0 camera interface 1 image rotator 0 2 mpeg4 deblocking free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 834 of 1535 3 prz 4 r2y 0 others reserved o_ovl the register field determines output target 0 disable output to overlay 1 enable output to overlay o_ipp1 the register field determines output target 0 disable output to ipp 1 1 enable output to ipp 1 o_y2r1 the register field determines output target 0 disable output to y2r 1 1 enable output to y2r 1 pcon the register bit specifies whether resizing continues or not whenever an image finishes processing. if to stop immediately is desired, reset capture resize directly. if the last image is desired, set the register bit to ?0? first. then wait until image resizer is not busy again. finally reset image resizer. 0 single run 1 continuous run lbsel line buffer selection. 0 crz cant work! 1 use resz_lb (resizer dedicated line buffer) as temporary buffer. inten[0] frame end interrupt enable. when interrupt is enabled, an interrupt is generated whenever crz finishes. 0 interrupt for frame done is disabled. 1 interrupt for frame done is enabled. inten[1] frame start interrupt enable. when interrupt is enabled, an interrupt is generated whenever crz receives vsync signal from isp. 0 interrupt for frame start is disabled. 1 interrupt for frame start is enabled. ecv the register field determines whether using ?ec? algorithm for vertical downscaling 0 use cubic algorithm 1 use ec algorithm. it helps when bandwidth is very critical. vsrsten the register field determines whether force crz reset when vsync arise but previous frame not done yet. 0 not force reset 1 force reset when vsync norfdb the register field determines not double buffer some registers. 0 double buffering registers 1 no double buffering registers lbmax number of lines used in upsampling scenario : wmin = ((ws > wt) ? wt : ws); // use for width down, and height up wmin_even = wmin + wmin%2; lb = (int)(2688 / wmin_even) * 6; lbmax = lb > 1023 ? 1023 : lb; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 835 of 1535 5.6.2.2 capture resize control register crz+0004h capture resize control register crz_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rst type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 name ena type r/w reset 0 the register is for global control of capture resize. note that software reset does not reset all register settings. remember to trigger capture resize first before triggering image sources to capture resize. ena writing ?1? to the register bit causes crz proceed to work. rst writing ?1? to the register causes crz to stop immediately and keep in reset state. in order to go to normal state, write ?0? to the register bit. 5.6.2.3 capture resize status register crz+0008h capture resize status register crz_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busyi busy o type ro ro reset the register indicates global status of capture resize. busyi input interface busy. busyo output interface busy. 5.6.2.4 capture resize interrupt register crz+000ch capture resize in terrupt register crz_int bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fstin t fedin t type rc rc reset 0 0 the register shows up the interrupt status of resizer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 836 of 1535 fedint interrupt for crz. no matter the register bit crz_cfg.inten[0] is enabled or not, the register bit is active whenever crz completes. it could be as software interrupt by polling the register bit. clear it by reading the register. fstint interrupt for crz. no matter the register bit crz_cfg.inten[1] is enabled or not, the register bit is active whenever crz start working. it could be as software interrupt by polling the register bit. clear it by reading the register. 5.6.2.5 capture resize source image size register 1 crz+0010h capture resize source im age size register 1 crz_srcsz1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hs type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ws type r/w the register specifies the size of source image after coarse shrink process. the allowable maximum size is 4095x4095 with limitation written in application notes. ws the register field specifies the width of source image after coarse shrink process. 1 the width of source image after coarse shrink process is 1. 2 the width of source image is 2. ? hs the register field specifies the height of source image after coarse shrink process. 1 the height of source image after coarse shrink process is 1. 2 the height of source image after coarse shrink process is 2. ? 5.6.2.6 capture resize target image size register 1 crz+0014h capture resize target image size register 1 crz_tarsz1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ht type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wt type r/w the register specifies the size of target image. the allowable maximum size is 4095x4095 with limitation written in application notes. wt the register field specifies the width of target image. 1 the width of target image is 1. 2 the width of target image is 2. ? ht the register field specifies the height of target image. 1 the height of target image is 1. 2 the height of target image is 2. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 837 of 1535 ? 5.6.2.7 capture resize horizontal ratio register 1 crz+0018h capture resize horizont al ratio register crz_hratio1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ratio [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ratio [15:0] type r/w the register specifies horizontal resizing ratio. it is obtained by crz_srcsz.hs > crz_tarsz.ht ? ((crz_tarsz.ht - 1)* 2 20 + (crz_srcsz.hs -1)/2) / (crz_srcsz.hs -1) : ((crz_srcsz.hs - 1)* 2 20 + (crz_tarsz.ht-1)/2) / (crz_tarsz.ht-1). 5.6.2.8 capture resize vertical ratio register 1 crz+001ch capture resize vertical ratio register 1 crz_vratio1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ratio [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ratio [15:0] type r/w the register specifies vertical resizing ratio. it is obtained by crz_srcsz.vs > crz_tarsz.vt ? ((crz_tarsz.vt - 1)* 2 20 + (crz_srcsz.vs -1)/2) / (crz_srcsz.vs -1) : ((crz_srcsz.vs - 1)* 2 20 + (crz_tarsz.vt-1)/2) / (crz_tarsz.vt-1). 5.6.2.9 capture resize coefficient table register crz+0040h capture resize coefficient table crz_frcfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name usel dsel type r/w r/w reset 0 1 1 0 0 0 1 1 0 0 the register specifies the coefficient table for resizing. valid number is form 0 to 19. while ?1? is the most blur and ?19? is the sharpest. ?0? is a special case, linear interpolation rather than cubic interpolation is used. usel choose ?usel? > 12 may get undesirable result, ?8? is recommended. dsel ?15? is recommended. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 838 of 1535 5.6.2.10 capture resize busy register crz+0044h capture resize busy crz_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dth uth type r/w r/w reset 0 0 the register specifies when to issues a busy signal to inform image dma that the buffer in crz is nearly full. uth threshold setting for upsampling 0xff crz_busy when used line buffer >=6 0xfe crz_busy when used line buffer >=8 0xfc crz_busy when used line buffer >=16 0xf8 crz_busy when used line buffer >=32 0xf0 crz_busy when used line buffer >=64 0xe0 crz_busy when used line buffer >=128 0xc0 crz_busy when used line buffer >=256 0x80 crz_busy when used line buffer >=512 0x00 crz_busy always low recommended: 0xff or half of max line buffer dth threshold setting for downsampling bit 7 crz_busy when write pointer and read pointer are not at the same line buffer bit 6 crz_busy when write pointer bit 10 = 1 bit 5 crz_busy when write pointer bit 9 = 1 bit 4 crz_busy when write pointer bit 8 = 1 bit 3 crz_busy when write pointer bit 7 = 1 bit 2 crz_busy when write pointer bit 6 = 1 bit 1 crz_busy when write pointer bit 5 = 1 bit 0 crz_busy when write pointer bit 4 = 1 recommended: 0x80 or 0xc0 5.6.3 application notes z srcsz and tarsz limitation for upscaling 3 <= crz_srcsz.ws <= 2688; 3 <= crz_srcsz.hs <= 2688; (crz_tarsz.wt-1) / (crz_srcsz.ws-1) <= 64; z srcsz and tarsz limitation for downcaling 2 <= crz_tarsz.wt <= 2688; 2 <= crz_tarsz.ht <= 2688; (crz_tarsz.wt-1) / (crz_srcsz.ws-1) >= 1/2048; z configuration procedure for pixel-based image sources free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 839 of 1535 crz_srcsz = source image size; crz_tarsz = target image size; crz_cfg.lbsel = 1; // must be 1, crz cant work when set to 0 crz_cfg.src = 0~4 ; crz_cfg.o_ovl = 1 or 0; crz_cfg.o_ipp1 = 1 or 0; crz_cfg.o_y2r1 = 1 or 0; wmin = (ws > wt) ? wt : ws; // use for width down and height up wmin_even = wmin + wmin%2; lb = (int)(2688/ wmin_even) * 6; crz_cfg.lbmax = (lb > 1023) ? 1023 : lb; crz_hratio = horizontal ratio; crz_vratio = vertical ratio; crz_con = 0x1; 5.7 cevasys subsystem the cevasys subsystem consists of three modules, namely cevax1620, cevaxs1200_sys, and ceva_ap. the cevax1620 itself is a high performance dsp. the cevaxs1200_sys is the circuit surrounding the cevax1620. the ceva_ap is the interface between cevaxs1200_sys and the system. some important operating information for cevasys is under the control of arm9. here defines these control registers. 5.7.1 cevasys ap configure registers register address register name synonym ceva_cfg + 0000h ceva dsp control register 0 ceva_con0 ceva_cfg + 0004h ceva dsp control register 1 ceva_con1 ceva_cfg + 0008h ceva cg_con register ceva_cg_con ceva_cfg + 000ch ceva external memory offset ceva_emo ceva_cfg + 0010h ceva delsel control register 0 ceva_delsel0 ceva_cfg + 0014h ceva delsel control register 1 ceva_delsel1 ceva_cfg + 0018h ceva delsel control register 2 ceva_delsel2 ceva_cfg + 0000h ceva dsp control register 0 ceva_con0 table 99 cevasys ap configure registers 5.7.2 register definition ceva_cfg +0000h ceva control 0 register ceva_con0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wake cxrst n glob rstn boot free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 840 of 1535 type r/w r/w r/w r/w r/w r/w r/w reset 0x0 0 0 0 ceva control 0 register. boot the cevax1620 booting selection bit. 0 the cevax1620 boots from address 0x0000. 1 takes ext_vector[31:0], defined in ceva_con1 register, as the booting address. globrstn the global reset bit of cevaxs1200, including cevax1620 and cevaxs1200_sys. cxrstn the reset bit of cevax1620. wake the wake signals. ceva_cfg +0004h ceva control 1 register ceva_con1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ext_vector[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ext_vector[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 the booting vector when the boot bit is set. ceva_cfg +0008h ceva cg_con register ceva_cg_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ccif_ cg_c on ahb_ cg_c on type r/w r/w reset 1 1 the cevasys clock gating control bits. ahb_cg_con the clock gating control bit of the ahb clock. 0 release the clock. 1 stop the clock. ccif_cg_con the clock gating control bit of the ahb clock for the ccif module 0 release the clock. 1 stop the clock. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 841 of 1535 ceva_cfg +000ch ceva external memory offset ceva_emo bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_emo[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xc000 the external memory offset register for cevaxs1200. it defines how the address should be translated from cevasys domain to the system bus. ceva_cfg +0010h ceva delsel control register 0 ceva_delsel 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ceva_delsel0[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xaaaa bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_delsel0[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xaaaa ceva_delsel0 this register is related to the speed configuration of sram. ceva_cfg +0014h ceva delsel control register 1 ceva_delsel 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ceva_delsel1[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xaaaa bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_delsel1[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xaaaa ceva_delsel1 this register is related to the speed configuration of sram. ceva_cfg +0018h ceva delsel control register 2 ceva_delsel 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ceva_delsel2[11:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 842 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0x6ff ceva_delsel2 this register is related to the speed configuration of sram. 5.8 display pixel in terface controller 5.8.1 features rg b rgb rgb rgb rgb figure 117 the block diagram of display pixel interface controller figure 12 gives the block diagram of display pixel interface (abbreviated to dpi) controller. the dpi controller generates appropriate timing signals for generic lcd module with digital rgb interface and moves the display data from the frame buffer to the interface. it has the following features: 1. supports lcd panel with resolution up to 1024x1024 (frame buffer in off-chip sdram) 2. supports rgb888 and rgb565 color mode 3. supports block reading (for hardware scrolling) 4. supports one 32x32 or four 16x16 4 bit indexed hardware cursor with transparent color key 5. supports 2x or 4x temporal dithering for 6-bit lcd panel free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 843 of 1535 5.8.2 control registers 5.8.2.1 regist er definition +0000h dpi control register dpi_cntl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_o en_of f intf_ rgb_ orde r dsi_m ode fbc_e n dbs_e n intf_6 8_en src_r gb_o rder pixel _fmt fb_ch ken adp_f ifo_e n fast_ rc_en fs_en fb2_e nabl e fb1_e nabl e dpi_e n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dpi_en turn the dpi controller on/off 0 dpi controller off 1 dpi controller on fb1_enable enable/disable external frame buffer 1 0 off 1 on fb2_enable enable/disable external frame buffer 2 0 off 1 on fs_en frame synchronization enable. when more than 1023 pixels are lost, this function performs synchronization between frame data and dpi protocol. 0 off 1 on fast_rc_en fast recovery enable. this function speeds up frame synchronization by dropping frame data to find the starting of the frame. fs_en should also be enabled for this function to work. 0 off 1 on adp_fifo_en adaptive fifo high/low threshold control. fifo high/low threshold would automatically increase by fifo_th_inc when gmc fifo is empty. 0 off 1 on fb_chken keep reading current frame buffer if next frame buffer is not completely prepared by lcd. 0 disable 1 enable pixel_fmt specify the pixel color format 0 rgb565 1 rgb888 src_rgb_order specify the source rgb color order (from msb to lsb) 0 rgb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 844 of 1535 1 bgr intf_68_en sequential 6-/8-bit output interface enable 0 off 1 on dbs_en display backlight scaling path enable. dpi_cusr_cntl.cursor_en shall be 0 if dbs_en is on. 0 off 1 on fbc_en frame buffer decompression path enable. dpi_cusr_cntl.cursor_en and dpi_dither.dither_mode shall be 0 if fbc_en is on. 0 off 1 on dsi_mode display serial interface (dsi) path enable 0 off 1 on intf_rgb_order output interface rgb order selection 0 rgb 1 bgr dpi_oen_off turn off dpi output enable 0 do not turn off 1 turn off +0004h dpi irq enable register dpi_inten bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name over spec_ en fbc_e rr_en vsyn c_en frm_e rr_en line_ err_e n cnt_e rr_en b_em pty_e n g_em pty_e n r_em pty_e n gmc_ full_ en gmc_ empy _en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 this register sets the interrupt enable of individual interrupt source generated by dpi controller. gmc_empty_en interrupt issues when source data fifo is empty. 0 disable 1 enable gmc_full_en interrupt issues when source data fifo is full. 0 disable 1 enable r_empty_en interrupt issues when red fifo is empty 0 disable 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 845 of 1535 g_fifo_empty_en interrupt issues when green fifo is empty 0 disable 1 enable b_fifo_empty_en interrupt issues when blue fifo is empty 0 disable 1 enable cnt_err_en total lost pixels due to bandwidth shortage exceed 1024, an interrupt request will be generated 0 disable 1 enable line_err_en if there are still lost pixels when hsync is activated, an interrupt request will be generated 0 disable 1 enable frame_err_en if there are still lost pixels when vsync is activated, an interrupt request will be generated 0 disable 1 enable vsync_en if vsync is activated, an interrupt request will be generated 0 disable 1 enable fbc_err_en an interrupt issues when frame buffer decompression error. 0 disable 1 enable overspec_en if adp_fifo_en is enabled, an interrupt issues when fifo_high_th is larger than or equal to fifo_th_max. 0 disable 1 enable +0008h dpi irq status register dpi_intsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name over psec fbc_e rr vsyn c fram e_err line_ err cnt_e rr bfifo _empt y gfifo _empt y rfifo _empt y gmc_ full gmc_ empt y type rc rc rc rc rc rc rc rc rc rc rc this read only register gives the current interrupt request status of the dpi controller. each field is corresponded to the previous dpi_inten register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 846 of 1535 +0010h dpi size register dpi_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name v_size type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h_size type r/w reset 0 this register sets the horizontal (x-axis) and vertical (y-axis) resolution of the currently used lcd panel. for an lcd panel with resolution 320x240 , the h_size field should be set to (320-1) = 319 and the v_size field should be set to (240-1) 239 . h_size set the horizontal pixel number. v_size set the vertical pixel number. +0014h dpi clock control register dpi_clkcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_c k_pol type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_ck_dut dpi_ck_div type r/w r/w reset 1 1 dpi_ck_div set the divisor of the pixel pll clock for dpi clock generation. 0 dpi_clock stops 1 freq dpi_clock = freq pll_clock / 2 2 freq dpi_clock = freq pll_clock / 3 3 freq dpi_clock = freq pll_clock / 4 4 freq dpi_clock = freq pll_clock / 5 5 freq dpi_clock = freq pll_clock / 6 6 freq dpi_clock = freq pll_clock / 7 7 freq dpi_clock = freq pll_clock / 8 ? 31 freq dpi_clock = freq pll_clock / 32 dpi_ck_dut set the output dpi clock duty cycle, should be less than or equal to dpi_ck_div 0 dpi_clock stops 1~31 wave form of dpi_clock is {dpi_ck_dut, dpi_ck_div ? dpi_ck_dut + 1} dpi_ck_pol set the polarity of the output dpi clock 0 the same as the internal dpi clock 1 inverse to the internal dpi clock free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 847 of 1535 +0018h dpi dither control register dpi_dither bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_lbits_sel type r/w reset 000 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_lbits_sel b_lbits_sel impose_sel dither_mod e type r/w r/w r/w r/w reset 000 000 010 0 dither_mode specify the temporal dithering mode. dpi_cntl.fbc_en shall be 0 if dither_mode is not off. 1x 4x mode 01 2x mode 00 off impose_sel select the intensity of dithering 000 impose the dither effect on bit0 001 impose the dither effect on bit1 010 impose the dither effect on bit2 011 impose the dither effect on bit3 100 impose the dither effect on bit4 101 impose the dither effect on bit5 110 impose the dither effect on bit6 111 impose the dither effect on bit7 b_lbits_sel select the dithering reference bits of blue component 000 bit[1:0] 001 bit[2:1] 010 bit[3:2] 011 bit[4:3] 100 bit[5:4] 101 bit[6:5] 110 bit[7:6] 111 bit[7:6] g_lbits_sel select the dithering reference bits of green component 000 bit[1:0] 001 bit[2:1] 010 bit[3:2] 011 bit[4:3] 100 bit[5:4] 101 bit[6:5] 110 bit[7:6] 111 bit[7:6] r_lbits_sel select the dithering reference bits of red component free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 848 of 1535 000 bit[1:0] 001 bit[2:1] 010 bit[3:2] 011 bit[4:3] 100 bit[5:4] 101 bit[6:5] 110 bit[7:6] 111 bit[7:6] +001ch dpi frame buffer addres s change register dpi_fb_chg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fb_ad dr_ chg type r/w reset 0 fb_addr_chg waiting for frame buffer address changing. it is used when single frame buffer. when software changes the single frame buffer address (register dpi_fb0_addr) for a new frame, fb_addr_chg should also be set. and then after dpi starts to display the new frame, this bit will be clear. software reads this bit to check if the new frame starts to display. if the value of this bit is 0, it means dpi starts to display the new frame, and it is ok to change dpi_fb0_addr for the next frame. if the value of this bit is 1, it means dpi still displays old frame, and doesn?t use the new value of dpi_fb0_addr. software can?t change dpi_fb0_addr for the next frame. please see figure 2. = 0 set dpi_fb0_addr for new frame set dpi_fb_chg.fb_addr_chg read dpi_fb_chg.fb_addr_chg no yes dpi displays the new frame, it?s ok to set dpi fb0 addr for new frame free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 849 of 1535 figure 118 frame buffer address change flow for single frame buffer +0020h dpi frame buffer 0 address register dpi_fb0_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_fb0_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb0_addr[15:0] type r/w reset 0 this register gives the display start address of the external frame buffer 0. +0024h dpi frame buffer 0 line step register dpi_fb0_step bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb0_step type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 this register gives the horizontal line length (line incremental step) in byte of the external frame buffer 0. +0028h dpi frame buffer 1 address register dpi_fb1_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_fb1_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb1_addr[15:0] type r/w reset 0 this register gives the display start address of the external frame buffer 1. +002ch dpi frame buffer 1 line step register dpi_fb1_step bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb1_step type r/w reset 0 this register gives the horizontal line length (line incremental step) in byte of the external frame buffer 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 850 of 1535 +0030h dpi frame buffer 2 address register dpi_fb2_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_fb2_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb2_addr[15:0] type r/w reset 0 this register gives the display start address of the external frame buffer 2. +0034h dpi frame buffer 2 line step register dpi_fb2_step bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_fb2_step type r/w reset 0 this register gives the horizontal line length (line incremental step) in byte of the external frame buffer 2. +0038h dpi overlay engine co ntrol register dpi_ovl_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fb_line_th type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fb_word_th type r/w reset 0 this register control the timing of overlay engine start to update frame buffer once dpi read ?fb_line_th? line and ?fb_word_th? words(4bytes) from any frame buffer. +003ch dpi fbc line length register dpi_fbcd_lin e_l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name line_w type r/w reset 0 line_w line length of compressed frames, in unit of byte. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 851 of 1535 +0040h dpi fifo threshold cont rol register dpi_ fifo_th bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_high_th type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_low_th type r/w reset 0 dpi internal fifo high/low thresholds control. when the number of fifo valid entries is smaller than fifo_low_th, dpi will request external memory bandwidth with ultra-high priority until the number of fifo valid entries is greater than or equal to fifo_high_th. note the fifo threshold is in unit of entry. each entry is 8 bytes. the maximum value of fifo threshold is 512. it?s suggested that the fifo_high_th should not be greater than 496 (512-16) since the number of valid entries may never greater be than 496. +0044h dpi fifo threshold increm ent register dpi_ fifo_inc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name test_ sum_ sel fifo_th_inc type r/w r/w reset 0 0 fifo_th_inc dpi internal fifo high/low thresholds increment control. the fifo high/low thresholds will be automatically increased by dpi_fifo_inc when dpi internal fifo is empty when adp_fifo_en is enabled. note the fifo increment setting is in unit of entry. test_sum_sel select read value of ral_rdata/cksum. refer to dpi_mon for more detail. 0 the read value is pal_rdata 1 the read value is cksum +0048h dpi fifo read/write po inter register dpi_ fifo_ptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_wptr type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_rptr type ro reset 0 read/write pointer of dpi internal fifo. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 852 of 1535 +004ch dpi fifo valid size register dpi_ fifo_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_size type ro reset 0 the number of current dpi internal fifo valid entries. +0050h dpi fifo maximum allowable high threshold register dpi_ fifo_th_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_th_max type r/w reset 0 this register is used for testing the maximum requirement of dpi internal fifo size. once fifo_high_th is larger than fifo_max in adaptive fifo threshold control mode, interrupt with overspec status will be issued. note the maximum settings of this register is 512. +0054h dpi fifo max register dpi_fifo_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_max type r/w reset 512 fifo_max internal fifo size, in unit of entry. +0058h dpi observe register dpi_obs_reg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fifo_ae_th type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pre_fifo_size type ro pre_fifo_size number of valid entries in internal fifo after the current gmc transfer is complete. fifo_ae_th the number of entries for the incoming gmc transfer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 853 of 1535 +0060h dpi timing generator ho rizontal control register dpi_tgen_hc ntl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name de_po l hsyn c_pol hfp type r/w r/w r/w reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hbp hpw type r/w r/w reset 0 0 dpi timing generator horizontal sync control register. hpw horizontal sync pulse width. (in pixel clock). for lcm with horizontal sync pulse width 6 , hpw should be set to 5 (6-1). hbp horizontal back porch width. (in pixel clock) for lcm with horizontal back porch width 6 , hbp should be set to 5 (6-1). hfp horizontal front porch width. (in pixel clock). for lcm with horizontal front porch width 6 , hfp should be set to 5 (6-1). hsync_pol hsync polarity 0 negative 1 positive de_pol data enable polarity 0 positive 1 negative +0064h dpi timing generator vertical control register dpi_tgen_vcn tl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vsyn c_pol vfp type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vbp vpw type r/w r/w reset 0 0 dpi timing generator vertical sync control register vpw vertical sync pulse width. (in horizontal sync pulse). for lcm with vertical sync pulse width 6 , the vpw should be set to 5 (6-1). vbp vertical back porch width. (in horizontal sync pulse) for lcm with vertical back porch width 6 , the vbp should be set to 5 (6-1). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 854 of 1535 vfp vertical front porch width. (in horizontal sync pulse) for lcm with vertical front porch width 6 , the vfp should be set to 5 (6-1). vsync_pol vsync polarity 0 negative 1 positive +0070h dpi hardware cursor control register dpi_cusr_cnt l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name curs or_ld type wo reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cursor_set curs or_si ze curs or_e n type r/w r/w r/w reset 0 0 0 the register controls the cursor format, set number and cursor pattern auto-load. cursor_en hardware cursor enable. dpi_cntl.fbc_en and dpi_cntl.dbs_en shall be 0 if cursor_en is on. 0 disable 1 enable cursor_size select the cursor size 0 16x16 1 32x32 cursor_set in 16x16 cursor size configuration, 4 set of cursors are supported. in 32x32 mode, this field is ignored. 0 select cursor set 0 1 select cursor set 1 2 select cursor set 2 3 select cursor set 3 cursor_ld write 1 to this field will activate the cursor pattern dma. the cursor pattern and palette will be copied from specified memory address to the internal cursor memory. +0074h dpi hardware cursor coordinate register dpi_cusr_co rd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name v_cord type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h_cord type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 855 of 1535 reset 0 set cursor set coordinate. h_cord horizontal (x-axis) coordinate of cursor v_cord vertical (y-axis) coordinate of cursor +0078h dpi hardware cursor memory address register dpi_cusr_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_cusr_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_cusr_addr[15:0] type r/w reset 0 this register gives the memory address where the cursor data placed. +0080h dpi status register dpi_status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fb_inuse line_cnt type ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name oute n hwc_ dma_ busy tgen_ start dp_st art busy type ro ro ro ro ro the read only register gives the current status of the dpi controller. busy dpi is started dp_start dpi data prepare is started tgen_start dpi timing generation is started hwc_dma_busy hardware cursor dma is ongoing outen output pad of dpi signals is enabled to output line_cnt line number read of current frame fb_inuse the number of frame buffer being read +0084h dpi error counter dpi_errcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dpi_errcnt type ro this register gives the pixel lost due to buffer underrun of rgb fifo. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 856 of 1535 +0090h dpi test mode register dpi_tmode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dpi_o en_o n type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pal_rsel gmc_state fifo_ test_ oen fifo_ test_ en mfix_ en ifix_e n ofix_ en type r/w ro r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 ofix_en enable fix output instead of dpi input 0 disable 1 enable ifix_en enable fix input instead of gmc input 0 disable 1 enable mfix_en enable fix data instead of intermediate r/g/b fifo output 0 disable 1 enable fifo_test_en fifo test enable. when this bit is enabled, the pop action of internal fifo is taken control by fifo_test_oen. 0 disable 1 enable fifo_test_oen fifo test output enable. each transition from 0 to 1 of this bit pops 1 entry out from internal fifo. gmc_state gmc state machine. pal_rsel palette select for read. dpi_oen_on turn on dpi output enable. it only takes effect when dpi_oen_off and dsi_mode are 0. +0094h dpi monitor register dpi_mon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gmc_ full gmc_ empt y rpsh_ err gpsh_ err bpsh_ err rpop_ err gpop _err bpop_ err pal_rdata/cksum[23:16] type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pal_rdata/cksum[15:8] pal_rdata/cksum[7:0] type ro ro pal_rdata / cksum the read data are selected by test_sum_sel. pal_rdata palette data read from bus. which palette data would be read can be selected by pal_rsel. cksum checksum value of dpi r/g/b bus of 1 st frame whenever dpi_en is enabled. the formula is as follows: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 857 of 1535 cksum[7:0](n) = cksum[7:0](n-1) + dpi_b[7:0](n) cksum[15:8](n) = cksum[15:8](n-1) + dpi_g[7:0](n) + cksum[7](n-1) cksum[23:16](n) = cksum[23:16](n-1) + dpi_r[7:0](n) + cksum[15](n-1) cksum(0) = 24?b0, and the carry is ignored. bpop_err b fifo pop error. gpop_err g fifo pop error. rpop_err r fifo pop error. bpsh_err b fifo push error. gpsh_err g fifo push error. rpsh_err r fifo push error. gmc_empty dpi internal fifo empty. gmc_full dpi internal fifo full. 5.8.2.2 dpi clock settings examples the frequency of the pixel clock in the dpi controller is depending on the panel display resolution and the pixel clock generation pll. 5.8.2.3 dpi register settings examples here is an example for setting the dpi controller registers. in the following figure, consider a virtual frame buffer fb0 in 24bpp format with resolution 1024 * 768 and an lcd panel with resolution 320 * 240. the virtual frame buffer resides at the external memory address 0x3010_0000 and we would like to display the rectangle area (x 0 , y 0 ) to (x 0 +h_size, y 0 +v_size) in the virtual frame buffer. the following register values should be calculated and set by software: 1. dpi_size: h_size = 319, v_size = 239 2. dpi_fb0_addr: 0x3100_0000 + y 0 * 1024 * 3 + x 0 * 3 3. fb0_line_step: 1024 * 3 (24bpp) = 3072 4. dpi_tgen_hcntl: refer to the specification of your lcd panel module and fill the correct register values. 5. dpi_tgen_vcntl: the same as dpi_tgen_vcntl 6. enable the dpi module by setting both the register bits dpi_cntl[1] and dpi_cntl[0] to 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 858 of 1535 240 pixels (v_size = 239) line offset 768 pixels figure 119 a frame buffer example for dpi register settings. 5.8.2.4 hardware cursor settings to enable the hardware cursor, user should prepare the appropriate cursor data in the memory and trigger the dpi controller to move the cursor data in. figure 120 shows the cursor memory organization. the pixel data is arranged in the scan line order. for a 32x32 hardware cursor, the pixel data occupies 32*32*0.5 = 512 bytes. for a 16x16 cursor, the pixel data occupies 16*16*0.5 = 128 bytes. thus the four 16x16 cursor pixel data should be put consecutively in the 512 byte memory space. since the pixel data stored in the 4-bit indexed color mode, a color palette is needed. for memory alignment, the 24-bit rgb value is stored in an 32-bit word with 8-bit msb not used. moreover, the palette contains only 14 colors since the color index 0 is reserved as the transparent color key and color index 1 is used as the inverse of background color. suppose we would like to use the 16x16 cursor set 1, the hardware cursor could be enabled in the following steps: 1. dpi_cusr_addr: set to the correct address of the cursor memory. 2. dpi_cusr_cntl: set bit 31 to 1 for auto moving the cursor memory into the dpi controller. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 859 of 1535 3. dpi_cusr_cord: set the coordinate of the left-upper corner of the cursor 4. dpi_cusr_cntl: set cursor_set to 1, cursor_fmt to 0, and cursor_en to 1 figure 120 cursor memory organization. 5.9 drop resize 5.9.1 general description this block provides a simple scaling down function by performing pixel and line dropping. it receives data, performs the image resizing function and outputs to the image process engine module. it can scale down the input image by any ratio > 1/2047. however, the maximum sizes of input and output images are limited to 4096x4096. 5.9.2 register definitions 5.9.2.1 register map table 100 shows the register map. register address register name synonym drz+ 0000h drop resize start register drz_str drz+ 0004h drop resize control register drz_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 860 of 1535 drz + 0008h drop resize status register drz_sta drz + 000ch drop resize interrupt acknowledge register drz_ackint drz + 0010h drop resize source image size register drz_src_size drz + 0014h drop resize target image size register drz_tar_size drz + 0020h drop resize horizontal ratio register drz_rat_h drz + 0024h drop resize vertical ratio register drz_rat_v table 100 register map. 5.9.2.2 register description followings are detail descriptions of each register. drz+0000h drop resize start register drz_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of drop resize. note that before setting str to ?1?, all the configurations shall be done by giving proper values. str start the drop resize engine. write 1 to this bit will start the fsm of drop resize. write 0 to this bit will reset the fsm of drop resize. drz+0004h drop resize configuration register drz_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name auto rstr it type r/w r/w reset 0 0 the register specifies the configuration of drop resize. it interrupt enabling 0 disable 1 enable auto rstr automatic restart. drop resize automatically restarts itself while current frame is finished. 0 disable 1 enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 861 of 1535 drz+0008h drop resize status register drz_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name run type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name it type ro reset 0 this register helps software program being well aware of the global status of drop resize. it interrupt status for drop resize 0 no interrupt is generated. 1 an interrupt is pending and waiting for service. run drop resize status 0 drop resize is stopped or has completed the transfer already. 1 drop resize is currently running. drz+000ch drop resize interrupt acknowledge register drz_ackint bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ack type wo this register is used to acknowledge the current interrupt request associated with the completion event of drop resize by software program. note that this is a write-only register, and any read to it will return a value of ?0?. ack interrupt acknowledge for the drop resize 0 no effect 1 interrupt request is acknowledged and should be relinquished. drz+0010h drop resize source image size register drz_src_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name v[11:0] type r/w reset x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h[11:0] type r/w reset x the register specifies the size of source image. the maximum allowable size is 4096x4096 . v the height of source image-1 h the width of source image-1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 862 of 1535 drz+0014h drop resize target image size register drz_tar_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name v[11:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h[11:0] type r/w reset 0 the register specifies the size of target image. the maximum allowable size is 4096x4096 . v the height of target image-1 h the width of target image-1 drz+0020h drop resize horizontal ratio register drz_rat_h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i [10:0] type r/w reset x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name q [11:0] type r/w reset x the register specifies horizontal resizing ratio. it is obtained by (the width of source image/the width of target image) = i + q/p = i + q/the width of target image. i the integer part q the denominator drz+0024h drop resize vertical ratio register drz_rat_v bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i [10:0] type r/w reset x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name q [11:0] type r/w reset x the register specifies horizontal resizing ratio. it is obtained by (the height of source image/the height of target image) = i + q/p = i + q/the height of target image. i the integer part q the denominator 5.10 display serial interface controller 5.10.1 features MT6516 dsi controller is compliant to dsi specification v1.01r5 and d-phy specification v0.9. the display serial interface controller supports two lanes with up-to 540mb/s for each. both command mode and video free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 863 of 1535 mode are provided for flexible link to versatile mipi compliant display. the dsi controller also supports both high speed and low power transmission for forward link and low power transmission for reverse link. in command mode, a dedicated command queue is designed for easy sw manipulation of all possible dsi commands and transmission modes for batch transfer. in video mode, all traffic sequences and all packet stream formats are supported. z compliant to dsi specification v1.01r5 z two lanes, 540mb/sec for each z command, and video modes z high speed, low power forward transmission z bus-turn-around and low power reverse transmission z ecc and checksum capabilities z video packet stream: 16-bpp, 18-bpp, packed 18-bpp, and 24-bpp z video traffic sequences: sync pulse, sync event and burst modes z multiple peripheral support z command queue free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 864 of 1535 5.10.2 block diagram free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 865 of 1535 5.10.3 control registers 5.10.3.1 register defini tion of dsi controller dsi_base in MT6516 is 0x80140000. +0000h dsi start register dsi_start bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_s tart type r/w reset 0 dsi_start start dsi controller operation 0 dsi controller off 1 dsi controller on +0004h dsi status dsi_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy type r reset 0 busy dsi busy status 0 dsi controller is idle. 1 dsi controller is busy. +0008h dsi interrupt enable register dsi_inten bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_o ut_di s cmd_ done rd_r dy type r/w r/w r/w reset 0 0 0 rd_rdy dsi command mode read data ready interrupt enable. it is recommended to turn on this interrupt if there are read commands in command queue. after read command is send by dsi tx, the read response will be received in a short time. to avoid the read data being overwritten by next read response when there are multiple read commands in command queue, the interrupt will notify sw to free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 866 of 1535 read the data and make sure it?s ready to receive next read response packet by setting mcu_rack before leaving the interrupt service routine. 0 disable 1 enable cmd_done dsi command queue finish interrupt enable. after all commands in command queue have been done, the interrupt will be issued. 0 disable 1 enable dsi_out_dis dsi output disable. 0 dsi output enable. when dsi active, this bit should be clear to 0. 1 dsi output disable. when dsi disable, this bit should be set to 1 to power down mipi analog macro. +000ch dsi interrupt enable register dsi_intsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cmd_ done rd_r dy type r r reset 0 0 this read only register gives the current interrupt request status of the dsi controller. each field is corresponded to the previous dsi_inten register. +0010h dsi common contro l register dsi_com_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_r eset type r/w reset 0 dsi_reset dsi software reset 0 de-assert dsi software reset. 1 assert dsi software reset. +0014h dsi mode control register dsi_mode_co n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 867 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mode_con type r/w reset 0 mode_con dsi mode control 00 command mode. 01 sync-pulse video mode. 10 sync-event video mode. 11 burst video mode. +0018h dsi tx rx contro l register dsi_txrx_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max_rtn_size corr _en cksm _en ecc_e n null_ en lane_num vc_num type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 1 0 vc_num virtual channel number in video mode lane_num lane number 00 not allowed. 01 one lane. 10 two lanes. others not allowed. null_en enable null packet transfer in bllp 0 disable. 1 enable. ecc_en enable receive packet ecc decode 0 disable. 1 enable. cksm_en enable receive packet checksum calculation 0 disable. 1 enable. corr_en enable receive packet error correction 0 disable. 1 enable. max_rtn_size maximum return packet size. this register constrains maximum return packet that slave side will send back to host. it will take effect after host send ?set maximum return packet size? packet to slave. +001ch dsi pixel stream control register dsi_pscon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 868 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_ps_sel dsi_ps_wc type r/w r/w reset 0 0 ps_wc the word count of the long packet in valid pixel data duration in unit of byte. this value must be (h_size*bpp). take the qvga display as an example, the value of ps_wc is (240*3) = 720 in decimal. ps_sel select the pixel stream type, please also refer to dsi specification. 00 packed pixel stream with 16-bit rgb 5-6-5 format. 01 loosely pixel stream with 18-bit rgb 6-6-6 format. 10 packed pixel stream with 24-bit rgb 8-8-8 format. 11 packed pixel stream with 18-bit rbg 6-6-6 format. +0020h dsi vertical sync active register dsi_vsa_nl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vsa_nl type r/w reset 0 vsa_nl vertical sync active duration which is in unit of line. +0024h dsi vertical back porch register dsi_vbp_nl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vbp_nl type r/w reset 0 vbp_nl vertical back porch duration which is in unit of line. +0028h dsi vertical front porch register dsi_vfp_nl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vfp_nl type r/w reset 0 vfp_nl vertical front porch duration which is in unit of line. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 869 of 1535 +002ch dsi vertical active register dsi_vact_nl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vact_nl type r/w reset 0 0 0 0 0 0 0 0 0 0 vact_nl vertical active duration which is in unit of line. +0030h dsi line byte register dsi_line_nb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_line_nb type r/w reset 0 line_nb line duration in unit of byte. this value is ( hpw + hbp + rgb + hfp ) * bpp in sync pulse mode and ( hbp + rgb_hfp ) * bpp in sync event mode with or without burst mode. please also refer to section 5.10.4. +0034h dsi horizontal sync acti ve byte register dsi_hsa_nb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hsa_nb type r/w reset 0 hsa_nb horizontal sync active duration in unit of byte. this register is needed to be set in sync pulse mode only. the value is ( hpw * bpp ? 4 ). please also refer to section 5.10.4. +0038h dsi horizontal back porc h byte register dsi_hbp_nb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hbp_nb type r/w reset 0 hbp_nb horizontal back porch duration in unit of byte. the value is ( hbp * bpp ) in sync pulse mode and is ( hbp * bpp ? 4 ) in sync event mode and burst mode. please also refer to section 5.10.4. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 870 of 1535 +003ch dsi horizontal front po rch byte register dsi_hfp_nb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hfp_nb type r/w reset 0 hfp_nb horizontal front porch duration in unit of byte. the value is ( hfp * bpp ? 6 ). please also refer to section 5.10.4. +0040h dsi rgb byte register dsi_rgb_nb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_rgb_nb type r/w reset 0 rgb_nb line valid pixel data duration in unit of byte. it is the length of pixel stream data including packet header, packet data (payload), and packet footer. the value is ( rgb * bpp + 6 ). please also refer to section 5.10.4. +0050h dsi horizontal sync active word count register dsi_hsa_wc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hsa_wc type r/w reset 0 hsa_wc the word count of the long packet in horizontal sync active duration. this register must be ( hsa_nb ? 6 ). please also refer to section 1.4. +0054h dsi horizontal back porch word count register dsi_hbp_wc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hbp_wc type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 871 of 1535 hbp_wc the word count of the long packet in horizontal back porch duration. this register must be ( hbp_nb ? 6 ). please also refer to section 1.4. +0058h dsi horizontal front porch word count register dsi_hfp_wc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_hfp_wc type r/w reset 0 hfp_wc the word count of the long packet in horizontal front porch duration. this register must be ( hfp_nb ? 6 ). please also refer to section 1.4. +0060h dsi command queue control register dsi_cmdq_co n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cmdq _sel cmdq_size type r/w r/w reset 0 0 cmdq_size number of commands in command queue. cmdq_sel select the current usage of command queue. there are two dedicated command queue for dsi controller. ps. the usage of the dsi command queue is described in section 5.10.7 in detail. +0070h dsi receiver status register dsi_rx_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dir type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trig dec2_ en mb_e rr2 sb_er r2 dec_ ok2 cksm _err mb_e rr1 sb_er r1 dec_ ok1 pkt_len long busy type r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 busy dsi controller is receiving data. long received a long packet. pkt_len received packet length in unit of byte. dec_ok1 received packet is decoded and no error found. sb_err1 received packet is decoded and has single-bit error. mb_err1 received packet is decoded and has multiple-bit error. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 872 of 1535 cksm_err received long packet has check-sum error. dec_ok2 received acknowledge with error report packet is decoded and no error found. sb_err2 received acknowledge with error report packet is decoded and has single-bit error. mb_err2 received acknowledge with error report packet is decoded and has multiple-bit error. dec2_en received acknowledge with error report packet is decoded. trig received low level trigger message. if this bit is 1, please ignore the other status and read dsi_trig_sta for determine the trigger command. dir current bus direction of data lane 0. if this bit is 1, there is reverse direction transmissions on data lane 0 in low power mode. otherwise, it is a forward direction transmissions. +0074h dsi receive packet data byte 0 ~ 3 register dsi_rx_data0 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name byte3 byte2 type r r reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name byte1 byte0 type r r reset 0 0 data bytes 0 ~ 3 received from slave. +0078h dsi receive packet data byte 4 ~ 7 register dsi_rx_data4 7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name byte7 byte6 type r r reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name byte5 byte4 type r r reset 0 0 data bytes 4 ~ 7 received from slave. +007ch dsi receive packet data byte 8 ~ b register dsi_rx_data8 b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name byteb bytea type r r reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name byte9 byte8 type r r reset 0 0 data bytes 8 ~ b received from slave. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 873 of 1535 +0080h dsi receive packet data byte c register dsi_rx_datac bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bytec type r reset 0 data byte c received from slave. +0084h dsi read data acknowledge register dsi_rack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rack type wc reset 0 when current read command is executed and requested read data is completely received by dsi controller, the irq with rd_rdy status will be issued to inform sw to get the receiving status and received data from register dsi_rx_sta and dsi_rx_data* respectively. it?s mandatory to write this register to keep doing next command. +0088h dsi trigger message status register dsi_trig_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trig_ 3 trig_ 2 trig_ 1 trig_ 0 type r r r r reset 0 0 0 0 trig_0 reserved by dsi specification. trig_1 acknowledge. trig_2 te. trig_3 remote application reset. +0090h dsi memory continue command register dsi_mem_con ti bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dsi_wmem_conti type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 874 of 1535 name dsi_rmem_conti type r/w reset 0 rmem_conti read memory continue command. wmem_conti write memory continue command. +0094h dsi frame byte count register dsi_frm_bc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name frm_bc[20:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name frm_bc[15:0] type r/w reset 0 frm_bc the total number of byte is expected to be read for type-3 command. please also refer to section 5.10.7 for the usage of type-3 command. +0100h dsi phy control register dsi_phy_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bta_t o_rst lrx_t o_rst htx_t o_rst phy_ rst type r/w r/w r/w r/w reset 0 0 0 0 phy_rst reset phy related control circuit. htx_to_rst high speed tx time-out reset. force current hstx finish and go to lp-11 state. lrx_to_rst low power rx time-out reset. abort current lprx finish and go to lp-11 state. bta_to_rst bus-turn-around time-out reset. abort current bta and go to lp-11 state +0104h dsi phy lane clock control register dsi_phy_lcco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lc_w akeu p_en lc_ul pm_e n lc_hs _tx_e n type r/w r/w r/w reset 0 0 0 lc_hs_tx_en start clock lane high speed transmission. lc_ulpm_en make the clock lane go to ultra-low power mode. lc_wakeup_en make the clock lane wake-up from ultra-low power mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 875 of 1535 ps. please also refer to section 5.10.4 for the register setting sequence to enter/exit ultra-low power mode +0108h dsi phy lane 0 control register dsi_phy_ld0c on bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name l0_wa keup_ en l0_ul pm_e n l0_rm _trig _en type r/w r/w r/w reset 0 0 0 l0_rm_trig_en send application trigger to slave side. l0_ulpm_en make the data lane 0 go to ultra-low power mode. l0_wakeup_en make the data lane 0 wake-up from ultra-low power mode. +0110h dsi phy timing control 0 register dsi_phy_timc on0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hs_trail hs_zero type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hs_prpr lpx type r/w r/w reset 0 0 please refer to section 5.10.5 for more detail. all these timing are counted by dsi_nx_ck, and the frequency of dsi_nx_ck is specified by dsi_phy_anacon0.rg_nx_ck_sel, dsi_phy_anacon0.pll_div1, dsi_phy_anacon1.pll_div2, and dsi_phy_anacon1.pll_clkr, please refer to figure 1. +0114h dsi phy timing control 1 register dsi_phy_timc on1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ta_sack ta_get type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ta_sure ta_go type r/w r/w reset 0 0 please refer to section 5.10.5 for more detail. all these timing are counted by dsi_nx_ck, and the frequency of dsi_nx_ck is specified by dsi_phy_anacon0.rg_nx_ck_sel, dsi_phy_anacon0.pll_div1, dsi_phy_anacon1.pll_div2, and dsi_phy_anacon1.pll_clkr, please refer to figure 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 876 of 1535 +0118h dsi phy timing control 2 register dsi_phy_timc on2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clk_trail clk_zero type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lpx_wait cont_det type r/w r/w reset 0 0 please refer to section 5.10.5 for more detail. all these timing are counted by dsi_nx_ck, and the frequency of dsi_nx_ck is specified by dsi_phy_anacon0.rg_nx_ck_sel, dsi_phy_anacon0.pll_div1, dsi_phy_anacon1.pll_div2, and dsi_phy_anacon1.pll_clkr, please refer to figure 1. +011ch dsi phy timing control 3 register dsi_phy_timc on3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clk_hs_prpr type r/w reset 0 please refer to section 5.10.5 for more detail. all these timing are counted by dsi_nx_ck, and the frequency of dsi_nx_ck is specified by dsi_phy_anacon0.rg_nx_ck_sel, dsi_phy_anacon0.pll_div1, dsi_phy_anacon1.pll_div2, and dsi_phy_anacon1.pll_clkr, please refer to figure 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 877 of 1535 5.10.3.2 register definition of analog phy pll_base in MT6516 is 0x80060000. 80060b00h dsi analog phy control 0 register dsi_phy_ana con0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name phy_b ist_m ode dsi_bi st_en dsi_fi x_pat rg_pll_div1 rg_nx_ck_s el rg_ck_sel rg_pll_ln pll_ en type r/ w r/ w r/ w r/w r/w r/w r/w r/w reset 0 0 0 001110 00 00 00 0 pllen pll clk enable pll_ln lane number, please see figure 1 ck_sel ck selection for dsi controller, please see figure 1 nx_ck_sel ck selection for dsi phy, please see figure 1 pll_div1 vco output frequency (fvco) = reference_clock*div1, please see figure 1 dsi_fix_pat make dsi to send fixed test pattern when bist test. the fixed test pattern sequence is 0x00, 0x01, 0x02, 0x04, 0x08, 0xff, 0xfe, 0xfd,0xfb, 0xf7, 0x00, 0xff, 0x55, 0xaa, 0x88, 0xff. dsi_bist_en bist test enable phy_bist_mode bist test enable. dsi_bist_en and phy_bist_mode must be set to 1 when bist mode 80060b04h dsi analog phy control 1 register dsi_phy_ana con1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_lnt_loopback rg_pl l_clk r rg_pll_clf rg_pll_cvc ob rg_pll_ccp rg_pll_div2 type r/w r/w r/w r/w r/w r/w reset 000 0 01 00 0101 0000 pll_div2 p lease see figure 1.1 pll_ccp pll cp control pll_cvcob pll vco bias control pll_clf pll vco loop filter free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 878 of 1535 pll_clkr selecting reference clock, please see figure 1 0 reference clock = 26mhz 1 reference clock = 13mhz lnt_loopback lane loopback mux control figure 121 clock structure of mipi macro 80060b08h dsi analog phy control 2 register dsi_phy_ana con2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_lnt_lpcd_cali rg_lnt_hsrx_cali rg_lnt_bgr _dout2_sel rg_lnt_bgr _dout1_sel rg_lnt_bgr _div rg_l nt_b gr_s elph rg_ln t_bgr _chpe n rg_l nt_b gr_e n type r/w r/w r/w r/w r/w r/w r/w r/w reset 010 010 0 0 0 0 1 1 rg_lnt_bgr_en bgr enable rg_lnt_bgr_chpen bgr chop enable rg_lnt_bgr_selph bgr clock phase sel rg_lnt_bgr_div bgr clock div rg_lnt_bgr_dout1_sel bgr debug output1 sel /1, /2 f in =26mhz /rg_pll_ln f ref f vco pll /pll_div2 digital clock gen f out f bit_data_rat f glcd_ck f dsi_ck f dsi_nx_ck pll_clkr 0: f ref =fin/1 1: f ref =fin/2 f vco =f ref *pll_div1 300mhz MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 879 of 1535 rg_lnt_bgr_dout2_sel bgr debug output2 sel rg_lnt_hsrx_cali lane hsrx calibration rg_lnt_lpcd_cali lane lpcd calibration 80060b0ch dsi analog phy control 3 register dsi_phy_ana con3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_lnt_lptx_cali rg_lp _bias _en rg_lnt_aio_sel rg_lnt_cire rg_lnt_calz_cz rg_l nt_c alz_ en type r/w r/w r/w r/w r/w r/w reset 010 0 000 01 0110 0 rg_lnt_calz_en lane enable hs impedance calibration. active high rg_lnt_calz_cz lane hs impedance calibration rg_lnt_cire lane vreg (output swing) control. 00: 0.38v; 01: 0.4v; 10: 0.42v; 11: 0.44v rg_lnt_aio_sel lane analog i/o debug sel rg_lp_bias_en lane lp bias enable rg_lnt_lptx_cali lane lptx slew rate calibration 80060b10h dsi analog phy control 4 register dsi_phy_ana con4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_ln t1_hs tx_sp t rg_ln t0_hs tx_sp t rg_lnt1_hs_cz rg_lnt0_hs_cz rg_lntc_hs_cz type r/w r/w r/w r/w r/w reset 0 0 0110 0110 0110 rg_lntc_hs_cz lane clk hs impedance calibration rg_lnt0_hs_cz lane0 hs impedance calibration rg_lnt1_hs_cz lane1 hs impedance calibration rg_lnt0_hstx_spt lane0 hstx sync sample point rg_lnt1_hstx_spt lane1 hstx sync sample point 80060b14h dsi analog phy control 5 register dsi_phy_ana con5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 880 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved fglcd _sel mipi_o ut_is o_en pat_e n mipi_i so rg_ln t_hst x_edg e_sel rg_t mode rg_force_tx_d rg_force_ en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 000 00 force_en force enable:'00'=original '01'=hstx mode '10'=lptx mode '11'=rx mode 00 original 01 hstx mode 10 lptx mode 11 rx mode force_tx_d tx data 000 original 001 lp all 1 010 lp all 0 011 reserved 100 hs prbs 101 hs all 1 110 hs all 0 111 reserved tmode analog test mode, '0'=disable, '1'=enable 0 disable 1 enable lnt_hstx_edge_sel select the synchronization between clock lane & 1st bit of one word. 0 sync 1st bit with rising edge 1 sync with falling edge mipi_iso mipi isolation test mode. all mipi phy input output ports are connected to chip pads pat_en enable dsi to send test patterns specified in mipitx_con6 and mipitx_con7. mipi_out_iso_en isolate mipi macro output when mipi macro power down. fglcd_sel clock selection 0 fglcd_ck, fdsi_ck and fdsi_nx_ck come from mipi macro output. 1 fglcd_ck, fdsi_ck and fdsi_nx_ck all come from clock square 26mhz. reserved reserved 80060b18h mipitx configuration 6 mipitx_con6 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bist_pattern[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80060b1ch mipitx configuration 7 mipitx_con7 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bist_pattern[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 881 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bist_pattern dsi will send this bist pattern[31:0] again and again when mipitx_con5.pat_en = 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 882 of 1535 5.10.4 clock control in MT6516, the clock source of dsi and d-phy are driven from internal pll. before turning on this pll, all dsi and d-phy circuits are inactive. to enable dsi display, it?s necessary to enable the pll first and adjust the pll to output a suitable clock frequency. since our internal pll maximum clock frequency is 540 mhz which cannot support to operate on one data lane for 24-bpp vga resolution in 60fps. table. 5-1 gives an example to show how to select a suitable clock frequency. table. 5-1: clock related parameters of vga display d-phy cycle time *1 (ns) for rg_nx_ck_sel (phy_anacon1[6:5]) pixel rate (mhz) bp p bit clock frequency (mhz) required pll output clock frequency (mhz) rg_pll_l n (phy_andcon1[2:1 ]) lane num (txrx_con [4:2]) 0 1 2 1 lane 400 0 1 2.5 5 7.5 400 1 2 2.5 5 7.5 2 25*2*8 = 400 2 lanes 200 0 2 5 10 15 1 lane 600 (n/a) - - - - - 25 3 25*3*8 = 600 2 lanes 300 0 2 3.3 6.7 10 *1 d-phy cycle time is selected by rg_nx_ck_sel. d-phy clock is equal to pll output clock divided by 2 rg_nx_ck_sel . the registers dsi_timcon0 ~ dsi_timcon3 are counted by this clock. after enabling the clock and properly setting the related registers, it?s necessary to the enable clock lane before starting high speed data transmission by setting the dsi_phy_lccon[0] as 1. if we are going to stop high speed transmission enter ultra-low power mode, the register sequence is described as table. 5-2 . the wake-up sequence is also shown in table. 5-3 . for more detail about the relationship between register setting and d+/d- on the lane, please see the timing diagram illustrated in fig. 5-1 and fig. 5-2 . similar to clock lane, data lane 0 also supports ultra-low power mode. for some reason, data lane 0 may need to enter ultra-low power mode, it should be prior to clock lane. in MT6516, entering ultra-low power mode on data lane has no essential power saving on host side. table. 5-2: the sequence to enter ultra-low power mode on clock lane step description register setting i stop the high speed transmission on clock lane write dsi_phy_lccon[0] = 0 ii enable ultra-low power mode write dsi_phy_lccon[1] = 1 iii disable pll clock write phy_anacon1[0] (rg_pll_en) = 0 table. 5-3: the sequence to exit ul tra-low power mode on clock lane step description register setting i turn-on pll clock write phy_anacon1[0] (rg_pll_en) = 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 883 of 1535 step description register setting ii wait for pll stable, than disable ultra-low power mode write dsi_phy_lccon[1] = 0 iii wait for at least 1ms, enable wake-up write dsi_phy_lccon[2] = 1 iv disable wake-up write dsi_phy_lccon[2] = 0 v enable high speed clock if necessary write dsi_phy_lccon[0] = 1 fig. 5-1: sequence of entering ultra-low power mode on clock lane fig. 5-2: sequence of exiting ultra-low power mode on clock lane free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 884 of 1535 5.10.5 d-phy timing control the d-phy timing control is clock-based. all timing parameters defined in d-phy specification is counted by d-phy internal clock. in table. 5-1 , it?s shown that the d-phy clock cycle time is related to pll clock settings and rg_nx_ck_sel. for more precise timing control, the d-phy clock should be selected as fast as possible, however, the faster the clock, the more power wasted. to select a suitable d-phy clock is also important for optimizing the system power consumption. for example, the timing of t hs-prepare is mandatory to be the value between 40ns+4*ui to 85ns +6*ui. in the case of vga display shown in table. 5-1 , ui is 300 mhz cycle time. in other words, the value of the timing parameter t hs-prepare must be 53.2 ~ 104.8ns which could be inferred to our register settings as shown in table. 5-4 . please see section 5.10.8 for the detail of d-phy timing specification. table. 5-4: d-phy timing parameters register settings timing settings for rg_nx_ck_sel timing specification absolute time for ui is 3.3ns 0 1 2 t hs-prepare 40ns+4*ui ~ 85ns +6*ui 53.2 ns ~ 104.8 ns 17 ~ 31 8 ~ 15 6 ~ 10 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 885 of 1535 5.10.6 video mode operation MT6516 dsi controller supports all of the dsi video mode traffic sequences including sync pulse mode, sync event mode and burst mode. to facilitate the translation of the parameters of the packets, the timing diagrams and corresponding register settings are illustrated below. fig. 5-3: sync pulse mode timing diagram fig. 5-4: sync pulse mode register settings fig. 5-5: sync event mode timing diagram free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 886 of 1535 fig. 5-6: sync event mode register settings free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 887 of 1535 5.10.7 command queue operation MT6516 dsi controller has two dedicated command queue which is 32-bit wide and 16-entry depth for each, please refer to fig. 5-7 . to simplify the settings for transmitting a packet in command mode, this command queue is designed to categorize all possible transmission types and commands into four main instructions and unify all the dsi specification commands into one or several 32-bit wide instructions. fig. 5-7 also illustrates the 32-bit instruction structure where the confg byte gives the instruction format. main instruction (4 bytes) confg. data id data 0 data 1 cl bta rpt hs type[1:0] te rsv bit 0 bit 4 bit 2 bit 3 bit 6 bit 1 bit 5 bit 7 command queue 32-bit instruction 0 instruction 1 instruction 2 fig. 5-7: dsi command queue instruction type table. 5-5 shows the detail descriptions of the config. field of the main instruction. for more detail, please refer to section 5.10.7.1 to 5.10.7.4. for convenience, we use virtual channel 0 for all packet in all examples of this document. the real virtual channel numbers depends on the definition of slave side which needs to be specially taken care by sw programmer. table. 5-5: config. field descr iption of main instruction value function description 00 - used for dsi short packet read/write command 01 - used for dsi frame buffer write command (long packet) 10 - used for dsi generic long packet write command type[1:0] 11 - used for dsi frame buffer read command (short packet) 0 off bta 1 on turn-around the dsi link after this dsi command is transmitted 0 off hs 1 on enable hs tx transmission for this packet, otherwise transmit packet via lp tx 0 8-bit cl 1 16-bt command length selection for frame buffer read/write instruction, only effective for type1 and type3 instructions. te 0 on 1 off enable te request, which will only turn-around the dsi link without any packet transmission resv - - reserved for further use free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 888 of 1535 value function description 0 on rpt 1 off repeat the payload data ?0? wc times, where wc is the packet word count defined by dsi specification 5.10.7.1 type-0 instruction type-0 instruction is used to transmit short packets. fig. 5-8 shows type-0 instruction format, where (data id + data 0 + data 1) is constructed by a dsi short packet command (without ecc). fig. 5-8: type-0 instruction format suppose that we are going to send ?turn on peripheral? and ?color mode on? commands which are transmitted via lp tx and hs tx respectively. in addition, we want to request slave response after the second command finished. these descriptions could be translated into two 32-bit instructions and achieved by the steps shown in table. 5-6 . table. 5-6: type-0 tx example step description r/w address value i fill the command queue entry-0 with value ?0x0000_3200? w 0xc000 0x0000_3200 ii fill the command queue entry-1 with value ?0x0000_120c? w 0xc004 0x0000_120c iii set the command count as 2 w 0x60 0x2 iv start command w 0x0 0x1 v interrupt issued, received slave response r 0xc 0x1 vi read status r 0x70 bit-15 = 0x1 vii read trigger status r 0x88 0x2 viii go to next instruction in dsi command queue w 0x84 0x1 ix interrupt issued, all instructions done r 0xc 0x2 5.10.7.2 type-1 instruction type-1 command is used to write data into frame buffer. as shown in fig. 5-9 , there are four bytes constructing this type of instruction where mem_start_0 and mem_start_1 could be generic commands defined by slave vendors or dcs commands. mem_start_1 is optional, that is, the memory start/continue command could be single byte like dcs defined. to indicate the dsi controller whether the mem_start_1 is sent or not depends on the cl bit of the confg. byte. since the length we are going to update the frame buffer is not a constant, this type of instruction may send several long packets to slave side. the payload data and length of each packet (excluding the mem_start_0 and mem_start_1) is prepared by lcd controller which free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 889 of 1535 couples the output of image data path or layer overlay result to dsi controller. for the first packet, mem_start_0 and mem_start_1 (if cl = 1) is used as the parameters to inform slave side that host is starting to write the frame buffer. for the remaining packets, the register value mem_conti[31:16] will be used as the parameters to tell slave side write these data following the last pixel of previous packet. for more flexibility, mem_start_0, mem_start_1, mem_conti[31:16] and cl are all programmable, however, it consumes only one entry of command queue. fig. 5-9: type-1 instruction format here gives an example to write frame buffer via dcs command in hs tx mode. table. 5-7: type-1 tx example step description r/w address value i fill the command queue entry-0 with value ?0x002c3909? w 0xc000 0x002c_3909 ii set the command count as 1 w 0x60 0x1 iii set memory continue bytes w 0x90 [31:16] = 0x3c iv start command w 0x0 0x1 v interrupt issued, all instructions done r 0xc 0x2 5.10.7.3 type-2 instruction type-2 instruction is used to send a long packet. as shown in fig. 5-10 , this type of main-instruction requires several sub-instructions which don?t have config. it?s obviously that host needs to prepare the content of the packet (excluding ecc and checksum) in the command queue to send a generic long packet. in fig. 5-10 , the byte2 and byte3 will be ignored and the next slot of instruction will be treated as a main-instruction which byte 0 will be parsed as a config. byte. according to this type of instruction, it?s strongly recommended to send a long packet to slave side in lp tx mode because the command since there is cross clock domain latency on reading the sub-instructions. fig. 5-10: type-2 instruction format for example, we are going to send a ?0x112233? using a dsi generic write command. please refer to table. 5-8 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 890 of 1535 table. 5-8: type-2 tx example step description r/w address value i fill the command queue entry-0 with value ?0x00032902? w 0xc000 0x0003_2902 ii fill the command queue entry-1 with value ?0x00112233? w 0xc004 0x0011_2233 iii set the command count as 2 w 0x60 0x2 iv start command w 0x0 0x1 v interrupt issued, all instructions done r 0xc 0x2 it?s notice that the rpt bit of config. is designed for this type of instruction. it?s useful for null packet or blanking packet. for example, if a null packet is going to be sent, only the main-instruction (entry-0 of command queue) is needed, the following payload data will be sent as ?0?. 5.10.7.4 type-3 instruction type-3 instruction is used for frame buffer read. as shown in fig. 5-11 , the format is the same as that of type- 1. when executing this instruction, host will firstly send a short packet with memory start parameter given in byte2 and byte3 and automatically issues next packet by memory continue parameters which is programmed in mem_conti[15:0]. the number of total packets required to be sent depends on the frm_bc and ?maximum return packet size?. for example, if we are going to read 1024 bytes from the frame buffer in slave side and the ?maximum return packet size? is set as ?4?, after the first short packet described in main- instruction is sent, there are another 255 short packets with memory continue parameters needed to be sent successively. fig. 5-11: type-3 instruction format table. 5-9 gives a example of using type-3 instruction to perform frame buffer read. table. 5-9: type-3 tx example step description r/w address value i fill the command queue entry-0 with value ?0x002e0603? w 0xc000 0x002e_0603 ii set the command count as 1 w 0x60 0x1 iii set memory continue bytes w 0x90 [15:0] = 0x3e iv start command w 0x0 0x1 v interrupt issued, received slave response r 0xc 0x1 vi read status r 0x70 - vii start next read or go to next instruction w 0x84 0x1 viii interrupt issued, all instructions done r 0xc 0x2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 891 of 1535 5.10.8 appendix fig. 5-12: d-phy hs tx timing specification fig. 5-13: d-phy bta timing specification fig. 5-14: d-phy clock lane timing specification free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 892 of 1535 fig. 5-15: d-phy timing parameters 5.11 graphics memory interface 5.11.1 introduction for providing graphic engines an easier bus protocol, we develop another protocol named gmc used for all the graph related engines. gmc will dispatch the data transaction command to 3 slavers they are internal sram, external memory and ceva sram. each slaver owns their arbiter, the arbiter using two free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 893 of 1535 layer arbitration one is normal priority the other is ultra high priority. for preventing from error base address access (such as some gmc engine access internal rom), the gmc provide a function to stop this illegal access to wrong base address, it will hang on the port to prevent it from corrupting the other data and report it in the register and issue an interrupt to cpu. the base address for gmc is list as follow: ? 0x0000_0000 128mb external ram ? 0x1000_0000 128mb external ram ? 0x2000_0000 128mb external ram ? 0x3000_0000 128mb external ram ? 0x4000_0000 ~ 0x4001_7fff 96 kb internal gmc1 sram ? 0x4002_0000 ~ 0x4004_3fff 144kb internal gmc2 sram ? 0xb020_0000 ~ 0xb020_7fff 32kb sram ceva ? 0xb040_0000 ~ 0xb040_7fff 32kb sram ceva the 36 master engines on gmc1 is list as follows: [0] tvc_pfh_rd [1] dpi [2] defect (cam) [3] imgdma0 [4] ap_gmc1 [5] lcd_r [6] lcd_w [7] tvc [8] asm [9] cam [10] g1fake free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 894 of 1535 [11] tvc_pfh_wr [12] dpi_hwc [13] gmc2_gmc1 [14] imgdma1 [15] imgdma2 [16] imgdma3 [17] imgdma4 [18] g2d_rd [19] spi [20] wave [21] g2d_wr [22] gcmq [23] png1 [24] png2 [25] png3 [26:35] not used the 42 master engines on gmc2 is list as follows: [39] reserved [38] reserved [37] mp4_deblk_0 [36] mp4_deblk_1 [35] fake_eng [34] imgdma1_1 [33] imgdma1_2 [32] imgdma1_3 [31] prz_blkr [30] prz_blkw [29] prz_pxl [28] m3d_index [27] m3d_vc [26] m3d_mvtx [25] m3d_hvtx [24] m3d_ez [23] m3d_txc [22] m3e_cc_wb [21] m3d_cc_lf [20] m3d_zc_wb [19] m3d_zc_lf [18] m3d_sc_lf [17] mux[0] (mp4 or h264) [16] jpg_dec0 [15] jpg_dec1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 895 of 1535 [14:4] mux[11:1] (mp4 or h264) [3] jpg_enc [2] imgdma1 [1] apmcu_gmc2 [0] gmc1_gmc2 5.11.2 performance counter active window idle cycle free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 896 of 1535 5.11.3 gmc1 register definitions 45. gmc1 arbitration mode gmc1 + 0000h gmc1_arb_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arb_mode type r/w reset 0 comment: 1: allow normal to join arbitration 0: only ultra high can join to arbitrate 46. gmc1 interrupt enable gmc1 + 0004h gmc1_int_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name int_en type r/w reset 0 comment: 1: allow gmc issue interrupt 0: not allow gmc issue interrupt 47. gmc1 interrupt flag1 gmc1 + 0008h gmc1_int_flag1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 897 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p15 p14 p13 p12 p11 p10 p09 p08 p07 p06 p05 p04 p03 p02 p01 p00 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 comment: specify the error happened in which ports. 1: error 0: no 48. gmc1 interrupt flag2 gmc1 + 000ch gmc1_int_flag2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p35 p34 p33 p32 type r/w r/w r/w r/w reset 0 0 0 0 comment: specify the error happened in which ports. 49. gmc1 performance counter enable gmc1 + 0010h gmc1_pcnt_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_en type r/w reset 0 comment: 1: start to count 0: stop counting 50. gmc1 performance counter clear gmc1 + 0014h gmc1_pcnt_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_clr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 898 of 1535 type r/w reset 0 comment: 1: start to clear 0: stop clearing 51. gmc1 performance counter selector gmc1 + 0018h gmc1_ pcnt_psel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_psel type r/w reset 0 comment: psel == 0 will choose port[0] and so on 52. gmc1 performance counter r/w selector gmc1 + 001ch gmc1_ pcnt_rwsel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_rwsel type r/w reset 0 comment: 3?b000: count internal and external r and w transaction 3?b001: count external r and w 3?b010: count internal r and w 3?b011: count external r only 3?b100: count external w only 3?b101: count internal r only 3?b110: count internal w only 53. gmc1 performance counter idle selector gmc1 + 0020h gmc1_pcnt_isel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 899 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_isel type r/w reset 0 comment: 1: read data phase don?t count in idle if no greq 0: read data phase will count in idle if no greq 54. gmc1 performance counter max selector gmc1 + 0024h gmc1_pcnt_max _sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_max_ sel type r/w reset 0 comment: 1: count command phase max 0: count data phase max 55. gmc1 performance counter active count gmc1 + 0028h gmc1_ pcnt_acnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_acnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_acnt type r/w reset 0 comment: pcnt_acnt will start to count how many cycles when pcnt_en = 1, it will saturate when reach 32?h ffffffff, and it will be cleared when pcnt_clr = 1 56. gmc1 performance counter idle count gmc1 + 002ch gmc1_ pcnt_icnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_icnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 900 of 1535 name pcnt_icnt type r/w reset 0 comment: pcnt_icnt will count the cycles when pcnt_en = 1 and no any bus transaction is in active, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 57. gmc1 performance counter greq count gmc1 + 0030h gmc1_ pcnt_gcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_gcnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_gcnt type r/w reset 0 comment: gcnt will start to count how many times greq has been issued when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 58. gmc1 performance counter gultra count gmc1 + 0034h gmc1_ pcnt_ucnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_ucnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_ucnt type r/w reset 0 comment: gcnt will start to count how many times gultra has been issued when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 59. gmc1 performance counter command phase cycle accumulation count gmc1 + 0038h gmc1_ pcnt_cpcacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_cpcacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_cpcacnt type r/w reset 0 comment: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 901 of 1535 ccacnt will start to accumulate the cycles from greq=1 to this command phase end when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it will be cleared when pcnt_clr = 1 60. gmc1 performance counter data phase cycle accumulation count gmc1 + 003ch gmc1_ pcnt_dpcacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dpcacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dpcacnt type r/w reset 0 comment: dcacnt will start to accumulate the cycles from the start of the data phase to its end when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 61. gmc1 performance counter data beats accumulation count gmc1 + 0040h gmc1_ pcnt_dbeacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dbeacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dbeacnt type r/w reset 0 comment: dbeacnt will start to accumulate the beat number of each transaction when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 62. gmc1 performance counter data bytes accumulation count gmc1 + 0044h gmc1_ pcnt_dbyacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dbyacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dbyacnt type r/w reset 0 comment: dbyacnt will start to accumulate the byte number of each transaction when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 63. gmc1 performance counter hang maximum free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 902 of 1535 gmc1 + 0048h gmc1_ pcnt_hang_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_hang_max type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_hang_max type r/w reset 0 comment: hang_max will record the max latency cycles for each transaction when pcnt_en = 1, it will be cleared when pcnt_clr = 1 64. gmc1 performance counter maximum gmc1 + 004ch gmc1_ pcnt_ max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_ max type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_ max type r/w reset 0 comment: pcnt_max will record the max cycles for command phase or data phase determined by psel of each transaction when pcnt_en = 1, it will be cleared when pcnt_clr = 1 65. gmc1 performance counter latch gmc1 + 0050h gmc1_pcnt_latch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_latch type w reset 0 comment: 1: latch the counter value to register 66. gmc1 performance counter latch clear gmc1 + 0054h gmc1_pcnt_latch_clear bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 903 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_latch_ clr type r/w reset 0 comment: 1: latch and no clear, 0: latch and clear 67. gmc1 gmc direction gmc1 + 0058h gmc1_gmc_dir bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gmc_dir type r/w reset 0 comment: 1: allow gmc2 -> gmc1 0: allow gmc1 -> gmc2 5.11.4 gmc2 register definitions 1. gmc2 arbitration mode gmc2 + 0000h gmc2_arb_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arb_mode type r/w reset 0 comment: 1: allow normal to join arbitration 0: only ultra high can join to arbitrate 2. gmc2 interrupt enable gmc2 + 0004h gmc2_int_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 904 of 1535 name int_en type r/w reset 0 comment: 1: allow gmc issue interrupt 0: not allow gmc issue interrupt 3. gmc2 interrupt flag1 gmc2 + 0008h gmc2_int_flag1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p15 p14 p13 p12 p11 p10 p09 p08 p07 p06 p05 p04 p03 p02 p01 p00 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 comment: specify the error happened in which ports. 1: error 0: no 4. gmc2 interrupt flag2 gmc2 + 000ch gmc2_int_flag2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name p41 p40 p39 p38 p37 p36 p35 p34 p33 p32 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 comment: specify the error happened in which ports. 5. gmc2 performance counter enable gmc2 + 0010h gmc2_pcnt_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_en type r/w reset 0 comment: 1: start to count free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 905 of 1535 0: stop counting 6. gmc2 performance counter clear gmc2 + 0014h gmc2_pcnt_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_clr type r/w reset 0 comment: 1: start to clear 0: stop clearing 7. gmc2 performance counter selector gmc2 + 0018h gmc2_ pcnt_psel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_psel type r/w reset 0 comment: psel == 0 will choose port[0] and so on 8. gmc2 performance counter r/w selector gmc2 + 001ch gmc2_ pcnt_rwsel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_rwsel type r/w reset 0 comment: 3?b000: count internal and external r and w transaction 3?b001: count external r and w 3?b010: count internal r and w 3?b011: count external r only free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 906 of 1535 3?b100: count external w only 3?b101: count internal r only 3?b110: count internal w only 9. gmc2 performance counter idle selector gmc2 + 0020h gmc2_pcnt_isel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_isel type r/w reset 0 comment: 1: read data phase don?t count in idle if no greq 0: read data phase will count in idle if no greq 10. gmc2 performance counter max/min selector gmc2 + 0024h gmc2_pcnt_max _sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_max_ sel type r/w reset 0 comment: 1: count command phase max 0: count data phase max 11. gmc2 performance counter active count gmc2 + 0028h gmc2_ pcnt_acnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_acnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_acnt type r/w reset 0 comment: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 907 of 1535 pcnt_acnt will start to count how many cycles when pcnt_en = 1, it will saturate when reach 32?h ffffffff, and it will be cleared when pcnt_clr = 1 12. gmc2 performance counter idle count gmc2 + 002ch gmc2_ pcnt_icnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_icnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_icnt type r/w reset 0 comment: pcnt_icnt will count the cycles when pcnt_en = 1 and no any bus transaction is in active, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 13. gmc2 performance counter greq count gmc2 + 0030h gmc2_ pcnt_gcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_gcnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_gcnt type r/w reset 0 comment: gcnt will start to count how many times greq has been issued when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 14. gmc2 performance counter gultra count gmc2 + 0034h gmc2_ pcnt_ucnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_ucnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_ucnt type r/w reset 0 comment: gcnt will start to count how many times gultra has been issued when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 15. gmc2 performance counter command phase cycle accumulation count free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 908 of 1535 gmc2 + 0038h gmc2_ pcnt_cpcacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_cpcacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_cpcacnt type r/w reset 0 comment: ccacnt will start to accumulate the cycles from greq=1 to this command phase end when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it will be cleared when pcnt_clr = 1 16. gmc2 performance counter data phase cycle accumulation count gmc2 + 003ch gmc2_ pcnt_dpcacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dpcacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dpcacnt type r/w reset 0 comment: dcacnt will start to accumulate the cycles from the start of the data phase to its end when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 17. gmc2 performance counter data beats accumulation count gmc2 + 0040h gmc2_ pcnt_dbeacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dbeacnt type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dbeacnt type r/w reset 0 comment: dbeacnt will start to accumulate the beat number of each transaction when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 18. gmc2 performance counter data bytes accumulation count gmc2 + 0044h gmc2_ pcnt_dbyacnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_dbyacnt type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 909 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_dbyacnt type r/w reset 0 comment: dbyacnt will start to accumulate the byte number of each transaction when pcnt_en = 1, it will saturate when reach 32?hffffffff, and it w ill be cleared when pcnt_clr = 1 19. gmc2 performance counter hang maximum gmc2 + 0048h gmc2_ pcnt_hang_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_hang_max type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_hang_max type r/w reset 0 comment: hang_max will record the max latency cycles for each transaction when pcnt_en = 1, it will be cleared when pcnt_clr = 1 20. gmc2 performance counter maximum gmc2 + 004ch gmc2_ pcnt_ max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnt_ max type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_ max type r/w reset 0 comment: pcnt_max will record the max cycles for command phase or data phase determined by psel of each transaction when pcnt_en = 1, it will be cleared when pcnt_clr = 1 21. gmc2 performance counter latch gmc2 + 0050h gmc2_pcnt_latch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_latch type w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 910 of 1535 reset 0 comment: 1: latch the counter value to register 22. gmc2 performance counter latch clear gmc2 + 0054h gmc2_pcnt_latch_clear bit 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnt_latch_ clr type r/w reset 0 comment: 1: latch and no clear, 0: latch and clear 23. gmc2 mux port sel gmc2 + 0058h gmc2_mux_port_sel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mux_port_se l type r/w reset 0 comment: 5.12 gmc fake engine 5.12.1 introduction because of lack of gmc master engines, the fpga verification for gmc is using fake engine to simulate the gmc behavior. it will issue all kinds of burst and size type plus 8 kinds of address to test the gmc design. first the engine will write a set of data to the gmc and then read it back and compare it. if the data is correct, the engine will issue next data till the whole kinds of data is issued and loop again. software can specify the loop count to order fake engine to loop. following is the fpga diagram. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 911 of 1535 emi ddr32 nnnn gmc1 96kb graph1sys gmc1_emi_greq1 gmc1_emi_greq2 gmc2_emi_greq1 gmc2_emi_greq2 arm9 gmc1_ceva_hsel gmc2_ceva_hsel fake engine fake engine nnnn gmc2 142kb graph2sys fake engine fake engine cevasys gmc1_gmc2_greq gmc2_gmc1_greq ahb2gmc apmcusys mdmcusys mcusys 32kb 32kb arm7 graph1sys_confg graph2sys_confg apmcusys_confg mdmcusys_confg gmc64 ahb32 gmc64 ahb64 ahb64 ahb32 gmc64 gmc64 gmc64 gmc64 cevasys 32kb 32kb gmc64 no connect no connect no connect no connect no connect fpga1 fpga2 5.12.2 fake engine fake engine is a synthesizable rtl hardware design. it is used on fpga to test gmc engine and the connection between gmc. it will start to work when software enables the ?act_en?. it will auto issue all kinds of request to access int./ext./ceva memory, and auto compare the data correctness. software need to configure the loop number for engine to loop, the number at least larger or equal to 1. the ultra signal is used to test weather the ultra high is take effect, if the bit is turn on fake engine will always issue ultra high request to gmc engine and gmc engine will serve it to higher priority and result in fewer active count. however for hardware limitation we only implement 4 ultra high port on gmc engine so only fake engine 26~29 for gmc1 and engine 37~40 for gmc2 the bit will take effect. software need to clear the fake engine before each start. there will 3 situation the fake will occur when start, error, hang, done. only done is the correct situation. no matter what happen the act_en will be turn off, softwa re just need to polling this bit and then to see what happen and go to the next test. each engine will occupy 128 bytes address range and no two engine can free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 912 of 1535 overlap, software need to configure the eng_offset to separate the engine?s address include gmc1 and gmc2. each engine will issue following type of transaction. burst type: 1, 2, 4, 8, 16 = five kinds size type: 1, 2, 4, 8 = four kinds address[1:0] type: 0~7 = eight kinds base address type: = eight kinds 0x0040_0000 0x1040_0000 0x2040_0000 0x3040_0000 0x4000_0000 0x4002_0000 0xb020_0000 0xb040_0000 base address can be programmed to decide weather to run, because fpga may not have the corresponding device for that address such as 0x3000_0000. each engine will issue (5 x 4 x 8 x enabled external address) transactions for each loop. the max number of transaction for a loop is 5x4x8x8 = 1280. software need to avoid placing your code on above address region, otherwise fake engine will corrupt the code. the engine will issue address start from base_addr + eng_offset. as we know that the longest data size is 16*8=128 bytes, each engine will occupy such size and none can be overlapped. 5.12.3 fake engine register base address gmc1: engine00: 0x8009_f000 engine01: 0x8009_e000 engine02: 0x8009_d000 engine03: 0x8009_c000 engine04: 0x8009_b000 engine05: 0x8009_a000 engine06: 0x8009_9000 engine07: 0x8009_8000 engine08: 0x8009_7000 engine09: 0x8009_6000 engine10: 0x8009_5000 engine11: 0x8009_4000 engine12: 0x8009_3000 engine13: 0x8009_2000 engine14: 0x8009_1000 engine15: 0x8009_0000 engine16: 0x8008_f000 engine17: 0x8008_e000 engine18: 0x8008_d000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 913 of 1535 engine19: 0x8008_c000 engine20: 0x8008_b000 engine21: 0x8008_a000 engine22: 0x8008_9000 engine23: 0x8008_8000 engine24: 0x8008_7000 engine25: 0x8008_6000 engine26: 0x8008_5000 engine27: 0x8008_4000 engine28: 0x8008_3000 engine29: 0x8008_2000 gmc1 : 0x8008_1000 global1 : 0x8008_0000 gmc2: engine00: 0x800c_a000 engine01: 0x800c_9000 engine02: 0x800c_8000 engine03: 0x800c_7000 engine04: 0x800c_6000 engine05: 0x800c_5000 engine06: 0x800c_4000 engine07: 0x800c_3000 engine08: 0x800c_2000 engine09: 0x800c_1000 engine10: 0x800c_0000 engine11: 0x800b_f000 engine12: 0x800b_e000 engine13: 0x800b_d000 engine14: 0x800b_c000 engine15: 0x800b_b000 engine16: 0x800b_a000 engine17: 0x800b_9000 engine18: 0x800b_8000 engine19: 0x800b_7000 engine20: 0x800b_6000 engine21: 0x800b_5000 engine22: 0x800b_4000 engine23: 0x800b_3000 engine24: 0x800b_2000 engine25: 0x800b_1000 engine26: 0x800b_0000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 914 of 1535 engine27: 0x800a_f000 engine28: 0x800a_e000 engine29: 0x800a_d000 engine30: 0x800a_c000 engine31: 0x800a_b000 engine32: 0x800a_a000 engine33: 0x800a_9000 engine34: 0x800a_8000 engine35: 0x800a_7000 engine36: 0x800a_6000 engine37: 0x800a_5000 engine38: 0x800a_4000 engine39: 0x800a_3000 engine40: 0x800a_2000 gmc2 : 0x800a_1000 global2 : 0x800a_0000 the number of fake engine for gmc1 is 30 the number of fake engine for gmc2 is 41 the ultra high engine for gmc1 is engin29, engine28, engine27, engine26 the ultra high engine for gmc2 is engin40, engine39, engine38, engine37 the base address of global1 is used to set the act_en for fake engines on gmc1 the base address of global2 is used to set the act_en for fake engines on gmc2 5.12.4 register definitions 68. engine offset fake_eng + 0000h fake_eng_eng_offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name eng_offset[15:0] type r/w reset 0 comment: this offset is used to separate each fake engine?s occupied address. each engine will occupy 128 bytes that is the minimum number of the offset is 128 bytes. software should very care that no one engine can overlap in address otherwise the data may be corrupted by other engine and result in compare fail. ex. eng1: offset = 0x0 eng2: offset = 0x80 eng3: offset = 0x100 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 915 of 1535 in fpga1 and fpga2 the offset is also need to be separated. 69. engine loop number fake_eng + 0004h fake_eng_loop_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name loop_num[7:0] type r/w reset 0 comment: specify the loop number for each fake engine. a reasonable number is 10. it can?t be 0 when turn on fake engine. 70. engine ultra fake_eng + 0008h fake_eng_ultra bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ultra type r/w reset 0 comment: it specify weather this engine issue ultra high signal to require more bandwidth. this bit is only effective on engine0 ~ engine3. this bit is used to test the ultra high function. when turn on the ultra high, the number of active counter would be dramatically decreased. 71. engine active enable fake_eng + 000ch fake_eng_act_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name act_en type r/w reset 0 comment: act_en = 1,start the fake engine. act_en= 0, stop the fake engine 72. engine clear enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 916 of 1535 fake_eng + 0010h fake_eng_clr_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clr_en type r/w reset 0 comment: clr_en = 1, reset the fake engine. clr_en= 0, normal mode. remember to reset the fake engine before normal function. 73. engine error fake_eng + 0014h fake_eng_err bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name err type r/w reset 0 comment: err=1, data compare error. err=0, data compare ok. 74. engine done fake_eng + 0018h fake_eng_done bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name done type r/w reset 0 comment: done=1, fake engine finish all the loop. done=0, have not finish. 75. engine hang fake_eng + 001ch fake_eng_hang bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 917 of 1535 name hang type r/w reset 0 comment: hang=1, fake engine is hang over 100000 cycles hang=0, fake engine is not hang 76. engine active counter fake_eng + 0020h fake_eng_act_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name act_cnt[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name act_cnt[15:0] type r/w reset 0 comment: a counter counts when act_en == 1. 77. engine hang counter fake_eng + 0024h fake_eng_hang_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hang_cnt[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hang_cnt[15:0] type r/w reset 0 comment: a counter counts when greq == 1 and reset when data transfer complete. 78. engine greq fake_eng + 0028h fake_eng_greq bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name greq type r reset 0 comment: for debug. 79. engine gaddr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 918 of 1535 fake_eng + 002ch fake_eng_gaddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gaddr[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gaddr[15:0] type r reset 0 comment: for debug. 80. engine gburst fake_eng + 0030h fake_eng_gburst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gburst type r reset 0 comment: for debug. 81. engine gsize fake_eng + 0034h fake_eng_gsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gsize type r reset 0 comment: for debug. 82. engine gwrite fake_eng + 0038h fake_eng_gwrite bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gwrite type r free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 919 of 1535 reset 0 comment: for debug. 83. engine gwdata1 fake_eng + 003ch fake_eng_gwdata1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gwdata1[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gwdata1[15:0] type r reset 0 comment: for debug. 84. engine gwdata0 fake_eng + 0040h fake_eng_gwdata0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gwdata0[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gwdata0[15:0] type r reset 0 comment: for debug. 85. engine loop counter fake_eng + 0044h fake_eng_loop_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name loop_cnt[7:0] type r reset 0 comment: current engine loop count. 86. engine base counter fake_eng + 0048h fake_eng_base_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 920 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base_cnt type r reset 0 comment: for debug. 87. engine burst counter fake_eng + 004ch fake_eng_burst_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name burst_cnt type r reset 0 comment: for debug. 88. engine size counter fake_eng + 0050h fake_eng_size_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name size_cnt type r reset 0 comment: for debug. 89. engine address counter fake_eng + 0054h fake_eng_addr_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr_cnt type r reset 0 comment: for debug. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 921 of 1535 90. engine write counter fake_eng + 0058h fake_eng_w_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_cnt type r reset 0 comment: for debug. 91. engine read counter fake_eng + 005ch fake_eng_r_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_cnt type r reset 0 comment: for debug. 92. base address enable fake_eng + 0060h fa ke_eng_base_addr_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base_addr_en[7:0] type r/w reset 0 comment: enable for external memory address. 1: turn on, 0: turn off base_addr_en[0]: 0x0040_0000 base_ addr_en[1]: 0x1040_0000 base_ addr_en[2]: 0x2040_0000 base_ addr_en[3]: 0x3040_0000 base_ addr_en[4]: 0x4000_0000 base_ addr_en[5]: 0x4002_0000 base_ addr_en[6]: 0xb020_0000 base_ addr_en[7]: 0xb040_0000 when act_en = 1, at least one should be turn on. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 922 of 1535 93. engine hang counter maximum fake_eng + 0064h fa ke_eng_hang_cnt_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hang_cnt_max[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hang_cnt_max[15:0] type r/w reset 0 comment: will preserve the maximum number of hang counter 94. same mode fake_eng + 0068h fa ke_eng_same_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name same_mode type r reset 0 comment: 1?b0: auto check mode 1?b1: the same type mode 95. read write mode fake_eng + 006ch fake_eng_rw_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rw_mode type r reset 0 comment: 2?b00 r-r 2?b01 r-w 2?b10 w-r 2?b11 w-w 96. request mode fake_eng + 0070h fake_eng_req_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 923 of 1535 name req_mode type r/w reset 0 comment: 5?h0 : burst = 1 beats, size = 1 bytes 5?h1 : burst = 1 beats, size = 2 bytes 5?h2 : burst = 1 beats, size = 4 bytes 5?h3 : burst = 1 beats, size = 8 bytes 5?h4 : burst = 2 beats, size = 1 bytes 5?h5 : burst = 2 beats, size = 2 bytes 5?h6 : burst = 2 beats, size = 4 bytes 5?h7 : burst = 2 beats, size = 8 bytes 5?h8 : burst = 4 beats, size = 1 bytes 5?h9 : burst = 4 beats, size = 2 bytes 5?ha : burst = 4 beats, size = 4 bytes 5?hb : burst = 4 beats, size = 8 bytes 5?hc : burst = 8 beats, size = 1 bytes 5?hd : burst = 8 beats, size = 2 bytes 5?he : burst = 8 beats, size = 4 bytes 5?hf : burst = 8 beats, size = 8 bytes 5?h10: burst = 16 beats, size = 1 bytes 5?h11: burst = 16 beats, size = 2 bytes 5?h12: burst = 16 beats, size = 4 bytes 5?h13: burst = 16 beats, size = 8 bytes others: burst = 16 beats, size = 8 bytes 97. engine active enable0 (global1) global1+ 0000h fake_eng_act_en0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en29 en28 en27 en26 en25 en24 en23 en22 en21 en20 en19 en18 en17 en16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en15 en14 en13 en12 en11 en10 en09 en08 en07 en06 en05 en04 en03 en02 en01 en00 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 comment: act_en = 1, turn of fake engine and it will start to send gmc request. act_en= 0, fake engine finish the job. software keep polling this bit to see if the fake engine is done its job no matter error occurred or gmc was hanged this bit will be turn off. 98. engine active enable0 (global2) global2+ 0000h fake_eng_act_en0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en31 en30 en29 en28 en27 en26 en25 en24 en23 en22 en21 en20 en19 en18 en17 en16 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en15 en14 en13 en12 en11 en10 en09 en08 en07 en06 en05 en04 en03 en02 en01 en00 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99. engine active enable1 (global2) global2+ 0004h fake_eng_act_en1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 924 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en40 en39 en38 en37 en36 en35 en34 en33 en32 type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 comment: act_en = 1, turn of fake engine and it will start to send gmc request. act_en= 0, fake engine finish the job. software keep polling this bit to see if the fake engine is done its job no matter error occurred or gmc was hanged this bit will be turn off. 5.13 graph1sys config register register address register name synonym confg_base + 300h clock gating control status register graph1sys_cg_con confg_base + 320h clock gating set register graph1sys_cg_set confg_base + 340h clock gating clear register graph1sys_cg_clr confg_base + 400h lcd io selection graph1sys_lcd_io_sel confg_base + 600h memory delsel control regsiter 0 graph1sys_delsel0 confg_base + 604h memory delsel control regsiter 1 graph1sys_delsel1 confg_base + 608h memory delsel control regsiter 2 graph1sys_delsel2 confg_base + 60ch memory delsel control register 3 graph1sys_delsel3 table 101 apb bridge register map 5.13.1 register definitions confg_base + 300h clock gating control status register graph1sys_c g_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 925 of 1535 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 1 1 0 graph1 sub-system clock gating control status register (read only), value 1 represents clock gating. gmc1 status of the gmc1 clock gating. g2d status of the g2d clock gating. gcmq status of the gcmq clock gating. bls status of the bls clock gating. imgdma0 status of the imgdma0 clock gating. png status of the png clock gating. dsi status of the dsi clock gating. tve status of the tve clock gating. tvc status of the tvc clock gating. isp status of the isp clock gating. ipp status of the ipp clock gating. prz status of the prz clock gating. crz status of the crz clock gating. drz status of the drz clock gating. wt status of the wt clock gating. afe status of the afe clock gating. spi status of the spi clock gating. asm status of the asm clock gating. resz_lb status of the resz_lb clock gating. lcd status of the lcd clock gating. dpi status of the dpi clock gating. g1fake status of the g1fake clock gating. confg_base + 320h clock gating set register graph1sys_c g_set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo graph1 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_cond registers. eg. if pdn_cond = 16?h0f0f, writing pdn_cond = 16?f0f0 will result in pdn_cond = 16?hffff. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 926 of 1535 gmc1 set gmc1 clock gating. g2d set g2d clock gating. gcmq set gcmq clock gating. bls set bls clock gating. imgdma0 set imgdma0 clock gating. png set png clock gating. dsi set dsi clock gating. tve set tve clock gating. tvc set tvc clock gating. isp set isp clock gating. ipp set ipp clock gating. prz set prz clock gating. crz set crz clock gating. drz set drz clock gating. wt set wt clock gating. afe set afe clock gating. spi set spi clock gating. asm set asm clock gating. resz_lb set resz_lb clock gating. lcd set lcd clock gating. dpi set dpi clock gating. g1fake set g1fake clock gating. confg_base + 340h clock gating clear register graph1sys_c g_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g1fak e dpi lcd resz_ lb asm spi afe wt type wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz crz prz ipp isp tvc tve dsi png imgd ma0 bls gcmq g2d gmc1 type wo wo wo wo wo wo wo wo wo wo wo wo wo wo graph1 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding pdn_cond registers. eg. if pdn_cond = 16?hffff, writing pdn_cond = 16?f0f0 will result in pdn_cond = 16?h0f0f. gmc1 clear gmc1 clock gating. g2d clear g2d clock gating. gcmq clear gcmq clock gating. bls clear bls clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 927 of 1535 imgdma0 clear imgdma0 clock gating. png clear png clock gating. dsi clear dsi clock gating. tve clear tve clock gating. tvc clear tvc clock gating. isp clear isp clock gating. ipp clear ipp clock gating. prz clear prz clock gating. crz clear crz clock gating. drz clear drz clock gating. wt clear wt clock gating. afe clear afe clock gating. spi clear spi clock gating. asm clear asm clock gating. resz_lb clear resz_lb clock gating. lcd clear lcd clock gating. dpi clear dpi clock gating. g1fake clear g1fake clock gating. confg_base + 400h lcd io selection graph1sys_l cd_io_sel bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lcd_io_sel type r/w reset 0 0 lcd_io_sel pin nld[25:0] are shared between cpu interface and rgb interface. use lcd_io_sel to select the sharing mode as table 2. lcd_io_sel nld bits 0~7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2'b00 cpu if only d0~7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 2'b01 8-bit cpu+18-bit rgb d0~7 b0 b1 b2 b3 b4 b5 g0 g1 g2 g3 g4 g5 r0 r1 r2 r3 r4 r5 2'b10 9-bit cpu+16-bit rgb d0~7 b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 g5 r0 r1 r2 r3 r4 d8 2'b11 18-bit cpu+8-bit rgb d0~7 d8 d9 d10 d11 d12 d13 d14 d15 b0 b1 b2 b3 b4 b5 b6 b7 d16 d17 : cpu if : rgb if table 102 lcd_io_sel mapping table confg_base + 600h memory delsel control register 0 graph1sys_d elsel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isp_nr1mem_delsel[5:0] isp_shadme m_delsel[1: 0] resz_lb_de lsel[1:0] imgdma_del sel[1:0] lcd_cache_ delsel[1:0] lcd_wbuf_ delsel[1:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 928 of 1535 type rw rw rw rw rw rw reset 6?h22 2?h2 2?h3 2?h2 2?h3 2?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lcd_pal_de lsel[1:0] lcd_dsififo _delsel[1:0] tvc_ram_de lsel[1:0] wave_delse l[1:0] asm_delsel [1:0] afe_delsel[ 1:0] delsel_fifo _mem[1:0] delsel_cur sor_mem[1: 0] type rw rw rw rw rw rw rw rw reset 2?h3 2?h1 2?h3 2?h2 2?h2 2?h2 2?h1 2?h2 confg_base + 604h memory delsel control register 1 graph1sys_d elsel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isp_dmmem0_delsel[5:0] is p_dmmem1_delsel[15:6] type rw rw reset 6?h22 10?h88 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isp_dmmem1_delsel[5:0] isp_nr1mem_delsel[15:6] type rw rw reset 6?h22 10?h88 confg_base + 608h memory delsel control register 2 graph1sys_d elsel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isp_awbhisg mem_delsel [1:0] isp_awbhisr mem_delel[ 1:0] isp_awbmem _delsel[1:0] isp_colormem_delsel[7:0] isp_dmmem0 _delsel[23: 22] type rw rw rw rw rw reset 2?h2 2?h2 2?h2 8?h3a 2?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isp_dmmem0_delsel[21:6] type rw reset 16?h88 confg_base + 60ch memory delsel control register 3 graph1sys_d elsel3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi_delsel[ 1:0] gm1_delsel[7:0] isp_3amem_ delsel[1:0] isp_aehisme m_delsel[1: 0] isp_awbhis bmem_dels el[1:0] type rw rw rw rw rw reset 2?h2 8?hff 2?h2 2?h2 2?h2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 929 of 1535 5.13.2 graph1sys application note 5.13.2.1 power up sequence for lcd, dp i, and dsi (clocked at ahb domain) for registers clocked at ahb clock domain (lcd, dpi, and dsi), please follow below power up sequence to ensure availability of register read. 1. clear power down bits of lcd, dpi, or dsi 2. add 40 nops 3. register read (standard processes) 5.14 graph2sys config register register address register name synonym confg_base + 000h clock gating control status register graph2sys_cg_con confg_base + 004h clock gating set register graph2sys_cg_set confg_base + 008h clock gating clear register graph2sys_cg_clr confg_base + 010h memory delsel control regsiter 0 graph2sys_delsel0 confg_base + 014h memory delsel control regsiter 1 graph2sys_delsel1 confg_base + 018h memory delsel control regsiter 2 graph2sys_delsel2 table 103 apb bridge register map 5.14.1 register definitions confg_base + 000h clock gating control status register graph2sys_c g_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 type ro ro ro ro ro ro ro ro ro reset 1 1 1 1 1 1 1 1 0 graph2 sub-system clock gating control status register (read only), value 1 represents clock gating. gmc2 status of the gmc2 clock gating. image_dma_1 status of the image_dma_1 clock gating. prz status of the prz clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 930 of 1535 m3d status of the m3d clock gating. h264 status of the h264 clock gating. dct status of the dct clock gating. jpeg status of the jpeg clock gating. mp4 status of the mp4 clock gating. mp4_deblk status of the mp4_deblk clock gating. confg_base + 004h clock gating set register graph2sys_c g_set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 type w/o wo wo wo wo wo wo wo wo graph2 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?set? register will perform a bit-wise or function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con = 16?h0f0f, writing cg_set = 16?f0f0 will result in cg_con = 16?hffff. gcu set the gcu controller power down. gmc2 set the gmc2 clock gating. image_dma_1 set the image_dma_1 clock gating. prz set the prz clock gating. m3d set the m3d clock gating. h264 set the h264 clock gating. dct set the dct clock gating. jpeg set the jpeg clock gating. mp4 set the mp4 clock gating. mp4_deblk set the mp4_deblk clock gating. confg_base + 008h clock gating clear register graph2sys_c g_clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_d eblk mp4 jpeg dct h264 m3d prz image _dma_ 1 gmc2 type wo wo wo wo wo wo wo wo wo free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 931 of 1535 graph2 sub-system clock gating set register, value 1 represents clock gating. for all registers addresses listed above, writing to the corresponding ?clear? register will perform a bit-wise and-not function between the 32bit written value and the 32bit register value already existing in the corresponding cg_con registers. eg. if cg_con = 16?hffff, writing cg_clr = 16?f0f0 will result in cg_con = 16?h0f0f. gcu clear the gcu controller power down. gmc2 clear the gmc2 clock gating. image_dma_ clear the image_dma_1 clock gating. prz clear the prz clock gating. m3d clear the m3d clock gating. h264 clear the h264 clock gating. dct clear the dct clock gating. jpeg clear the jpeg clock gating. mp4 clear the mp4 clock gating. mp4_deblk clear the mp4_deblk clock gating. confg_base + 010h memory delsel control register 0 graph2sys_d elsel0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d[31:16] type rw reset 16?h002a bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d[15:0] type rw reset 16?haaa9 confg_base + 014h memory delsel control register 1 graph2sys_d elsel1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d[63:48] type rw reset 16?h5500 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d[47:32] type rw reset 16?h0000 confg_base + 018h memory delsel control register 2 graph2sys_d elsel2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gmc2[11:10] type rw reset 2?h3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 932 of 1535 name gmc2[9:0] m3d[69:64] type rw rw reset 10?h3ff 6?h2d 5.15 h.264 decoder 5.15.1 general description the h.264 videos, is getting more and more popular in today?s application for its high coding efficiency. in order to play the h.264 videos in high quality, the hardware h.264 decoder is developed. for the mobile application, we implemented the whole scope of the baseline profile in h.264 standard including i-slice, p- slice, cavlc, slice-group, aso, redundant slices, and so on. we also made our h.264 decoder standard compliant. the scope of h.264 hardware decoder is from slice data layer and below, which are the main part of the h.264 standard. thus, before trigger this h.264 decoder to decode, software have to parse and processing the part of slice header and above. for a multiple-slice with slice group video, the slice header and above contain information of video size, reference frames ordering, slice length of each slice, and slice index of each macroblock (slice map), and so on. after parsing the information in slice-layer and above, software has to fill the following information to hardware for decoding this frame. (1) the memory address of ?slice_configuration? : h264_dec_slice_conf (2) for each slice, fill a 32-bytes data into memory from the start address of ?slice_configuration?. 32- bytes by 32-bytes continuous in memory address. (3) each ?slice_configuration? contains the following information (fig. 2): (a) slice starting address (b) slice starting bitcnt (c) slice length (d) reference frame index list for this slice (e) some parameters like filteroffset, qp, and etc in slice header. (4) decoding the slice map and fill the slice map into memory starting from ? h264_dec_slice_map_addr ? (5) fill the reference frame starting address 4-bytes by 4-bytes starting from ? h264_ref_frame_addr ? (6) allocate working memory for hardware: (a) ? h264_mc_line_buf_addr ?: 16-bytes aligned, size=? width_in_mb*16 * 48 *1.5 bytes ?, internal memory, this memory is only for prefetch enabled case. (b) ? h264_mc_mv_buffer_addr ?: 16-bytes aligned, size=3328 bytes, internal memory recommended. (c) ? h264_dec_rec_addr ?: 16-bytes aligned, size=? width_in_mb *16* height_in_mb*16 *1.5 bytes ?, external memory recommended. (d) ? h264_dec_deb_buf_addr ?: 16-bytes aligned, size=? (width_in_mb *8 +8)*16 bytes ?, internal memory recommended (e) ? h264_dec_deb_dat_buf0_addr ?: 512-bytes aligned, size=384 bytes, internal memory free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 933 of 1535 recommended. (f) ? h264_dec_deb_dat_buf1_addr ?: 512-bytes aligned, size=384 bytes, internal memory recommended. (g) ? h264_cavlc_base_addr ?: 32-bytes aligned, size=520 bytes, internal memory recommended. after programming the above information, the operation of h.264 hardware decoder will be described as the follows: (1) for each macroblock, first read the slice index of this macroblock from slicemap. (2) reading the associated slice configuration for this macroblock according to slice index. (3) if this macroblock is i-block, then do the scaling, idct. (4) if this macroblock is p-block, besides residual value decoded same to i-block, motion compensation is applied. the motion compensation procedure are: (a) read reference frame index from first 8 bytes in the associated slice configuration according to the decoded ref_idx. (b) read the reference frame start address from the ? h264_ref_frame_addr ? according to the reference frame index read at (a). (c) doing motion compensation from the frame of base address read at (b) (5) performing de-blocking filter operation. to speed up the memory access of motion compensation, the h.264 decoder supports memory prefetch scheme. a hardware module moves pixel data from external memory to internal memory continuously in decoding pipeline, such that the motion compensation module can do memory fetching from internal memory if the motion vector lies in the prefetch memory. to set ?mc_pfhen?=1 in ? h264_mc_line_buf_offset ? to enable this function. after h.264 decoder is being triggered, the decoder will send interrupt in the following case: (1) decoding complete successfully : ?dec_done? flag will be set to 1 (2) dma reached dma_limit and paused : ?dma_pause? flag will be set to 1 (3) vld decoding error : ?vld_error? flag will be set to 1 (4) idct overflow error : ?overflow? flag will be set to 1 (5) invalid mb type decoded : ?mb_type_err? flag will be set to 1 (6) macroblock location just hit the mb_pos set : ?mb_pos_irq? flag will be set to 1 these flags can be observed in the register ? h264_dec_irq_sts ?. after receiving these interrupt from hardware, software have to acknowledge these interrupt by setting ?h264_dec_irq_ack? to clear the interrupt status, and then perform associated actions. 5.15.2 registers definitions register address register function acronym h264+0000h h264 decoder command register h264_dec_comd free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 934 of 1535 h264+0004h h264 decoder dma command register h264_dec_dma_comd h264+0008h h264 decoder slice group mapping register h264_dec_slice_map_addr h264+000ch h264 decoder picture level configuration register h264_dec_pic_conf h264+0010h h264 decoder slice level configuration register h264_dec_slice_conf h264+0020h h264 decoder dma limit register h264_dec_dma_limit h264+0030h h264 reference frame address register h264_ref_frame_addr h264+0034h h264 mc line buffer address register h264_mc_line_buf_addr h264+0038h h264 mc line buffer offset register h264_mc_line_buf_offset h264+003ch h264 mc line buffer size register h264_mc_line_buf_size h264+0040h h264 mc motion vector buffer address register h264_mc_mv_buffer_addr h264+0044h h264 reconstruction address register h264_dec_rec_addr h264+0048h h264 deblk buffer address register h264_dec_deb_buf_addr h264+004ch h264 reconstruction luma size register h264_dec_rec_y_size h264+0050h h264 deblk data buffer0 address register h264_dec_deb_dat_buf0_addr h264+0054h h264 deblk data buffer1 address register h264_dec_deb_dat_buf1_addr h264+0060h h264 cavlc base address register h264_cavlc_base_addr h264+0070h h264 decoder interrupt status register h264_dec_irq_sts h264+0074h h264 decoder interrupt mask register h264_dec_irq_mask h264+0078h h264 decoder interrupt acknowledge register h264_dec_irq_ack h264+007ch h264 decoder mb_ irq_pos setting h264_dec_mb_irq_pos h264+0100h h264 decoder dma status register h264_dec_dma_sts h264+0104h h264 decoder debug info0 register h264_dec_debug_info0 h264+0108h h264 decoder debug info1 register h264_dec_debug_info1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 935 of 1535 h264+010ch h264 decoder debug info2 register h264_dec_debug_info2 h264+0110h h264 decoder debug info3 register h264_dec_debug_info3 h264+0114h h264 decoder debug info4 register h264_dec_debug_info4 h264+0118h h264 decoder debug info5 register h264_dec_debug_info5 h264+011ch h264 decoder debug info6 register h264_dec_debug_info6 h264+0120h h264 decoder debug info7 register h264_dec_debug_info7 h264+0124h h264 decoder debug info8 register h264_dec_debug_info8 h264+0128h h264 decoder debug info9 register h264_dec_debug_info9 h264+012ch h264 decoder debug info10 register h264_dec_debug_info10 h264+0130h h264 decoder debug info11 register h264_dec_debug_info11 table 104 h.264 decoder registers 5.15.2.1 main conf iguration & commands h264+0000h h264 decoder comman d register h264_dec_comd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dec_s tart dec_ rst type wo wo dec_rst software reset control for h.264 video decoder. the device driver software must always set this bit to 1 before starting decoding procedure. dec_start start the decoding operation. set this bit will trigger h.264 decoder. h264+0004h h264 decoder dma command register h264_dec_dm a_comd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name resu me stop type wo wo stop stop the dma. stop dma activities through sw rather than hw state machine free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 936 of 1535 resume resume the dma access. dma state machine will go to a pending state if the maximum allowed write count to target memory is reached and then an interrupt has occured. after re-allocating the target address, sw writes resume to unfreeze the encoding process. h264+0008h h264 decoder slice group mapping register h264_dec_slice_ map_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name slice_map_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slice_map_addr[1 5:13] type r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro slice_map_addr the address of memory buffer storing slice group mapping; note that the lower 13 bits of this address must be all zeros. the buffer size to store slice group mapping is (1024/16) * height_in_mb * 2 bytes . (3840bytes for vga) h264+000ch h264 decoder picture level configuration register h264_dec_pic_conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mf_c ache dma_ cach e last_ref_idx[3:0] ref_c ur_fr ame fram e_typ e err_s tall_ en intr_ flag irq_e n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pic_height pic_width type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 pic_width picture width in the unit of macroblocks is n , please program (n-1) . pic_height picture height in the unit of macroblocks is m , please program (m-1 ). note : the maximum supported picture width and height is 992 pixels, and the maximum number of macroblock supported is 2047. irq_en set to 1 is to enable interrupt. intra_flag constrained intra perdition flag extract from header. err_stall_en set to 1 to stall h.264 decoder when vld_error or idct_overflow =1 frame_type set to 1 if any slice in this frame is p slice ref_cur_frm 1 bit to indicate if the current frame is used for reference. last_ref_idx indicate the last reference frame in the current reference list. dm a_cache this bit should be set to 0. mf_cache this bit should be set to 1. h264+0010h h264 decoder slice level configuration register h264_dec_slice_conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name slice_conf_addr[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 937 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slice_conf_addr[15:5] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro reset 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 slice_conf_addr starting address in memory storing slice level configurations for all slices and must be 32-bytes aligned. this register contains the slice-level configuration information for all slices. each slice will consume 32 bytes to store its configuration. so the first 32 bytes is the configuration field for slice with slice index equal to 0; the next 32 bytes is for slice with slice index equal to 1, and so on. in each configuration field, the following information is put in the order of ascending address: ref_frame_index_list 8 bytes for 16 reference frames and lsb-4bit of 1 st byte to indicate the idex0 of l0. each reference frame index is 4 bits. the reference frame index at position 0 in this field is for the first reference frame in reference frame list l0; the reference frame index at position 1 in this field is for the second reference frame in reference frame list l0, and so on. slice_length slice bit stream length in bytes; used for error handling. 4 bytes in length. slice_start_addr the real starting 4-byte aligned address of slice bit stream in memory. 4 bytes in length. slice_start_bit_cnt with slice_start_addr defining the start byte address of slice bit stream, slice_start_bit_cnt specifies which bit in this address hardware should begin to parse. 6-bit in length. filteroffseta signed number. 5-bit in length. in standard, filteroffseta = slice_alpha_c0_offset_div2 << 1, where slice_alpha_c0_offset_div2 is directly parsed from slice header. filteroffsetb signed number. 5-bit in length. in standard, filteroffsetb = slice_beta_offset_div2 << 1, where slice_beta_offset_div2 is directly parsed from slice header. init_slice_qp 1 byte in length. init_slice_qp is the initial slice quantization parameter used for scaling & transform. init_slice_qp = 26 + pic_init_qp_minus26 + slice_qp_delta. pic_init_qp_minus26 is directly parsed from pic_parameter_set_rbsp and slice_qp_delta is directly parsed from slice header. rec_list_idx 4 bits in length. indicate the reference list0 index in the current slice of the last reconstruction frame. valid 1bits to indicate if the rec_list_idx is valid disable_deblocking_filter_idc 2 bit in length. disable_deblocking_filter_idc can be directly parsed from slice header. slice_type 1 bit in length. slice_type is directly parsed from slice header. old_slice 1 bit in length. old_slice should be set to zero before starting one frame. num_ref_idx_l0_active_minus1 4-bit in length to indicate the number of the active reference frame. chroma_qp_index_offset 5-bit in length to indicate qp-offset of chroma. with all fields shown above, around 21 of 32 bytes are used. the rest will be used as hardware intermediate data buffer between slice switching. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 938 of 1535 index0 04 37 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 index11 index12 index13 index14 index15 3&'@'3".&@*/%&9@-*45 -4#cju .4#cju fig. 1. refernce frame index list ref_frame_ind ex_list[31:0] ref_frame_ind ex_list[63:32] 04 3 slice_length 78 11 slice_start_ad dr 12 15 16 {filteroffseta[1:0], slice_start_bit_cnt[5:0]} 17 {filteroffsetb[4:0], filteroffseta[4:2]} 18 19 init_slice_qp[7:0] 20 {1'd0, curr_qp_from_mc[5:0], mb_skip_run[11:0], chroma_qp_index_offset[4:0], num_ref_idx_l0_active_minus1[3:0], old_slice[0], slice_type[0], disable_deblk_filter_idc[1:0]} 23 24 27 28 31 interme_dma_start_addr[31:0] {26'd0, interme_dma_start_bitcnt[5:0]} {3'd0, valid, rec_list_idx[3:0]} fig. 2. structure of slice configuration 5.15.2.2 dma h264+0020h h264 decoder dma limit register h264_dec_dm a_limit bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_limit[16:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register is used to describe the buffer size of each vlc dma buffer. after dma consume 4 bytes bit- streams, dma_limit will decrease one. whenever the limit is reached (decrease as resuming the bitstream) and dma_pause interrupt mask is off, and dma_pause interrupt will be generated. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 939 of 1535 5.15.2.3 mc h264+0030h h264 reference frame address register ? all slice groups h264_ref_fra me_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ref_pic_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ref_pic_addr[15:6] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro this register specifies an address where the actual locations in sram of 16 reference frames are stored. the base address must be 64-bytes aligned . the real locations of 16 reference frames are implied as follow: address of reference frame with reference frame index equal to 0x0 is ref_pic_addr[31:0]. address of reference frame with reference frame index equal to 0x1 is (ref_pic_addr+4)[31:0]. address of reference frame with reference frame index equal to 0x2 is (ref_pic_addr+8)[31:0]. address of reference frame with reference frame index equal to 0x3 is (ref_pic_addr+12)[31:0]. address of reference frame with reference frame index equal to 0x4 is (ref_pic_addr+16)[31:0]. address of reference frame with reference frame index equal to 0x5 is (ref_pic_addr+20)[31:0]. address of reference frame with reference frame index equal to 0x6 is (ref_pic_addr+24)[31:0]. address of reference frame with reference frame index equal to 0x7 is (ref_pic_addr+28)[31:0]. address of reference frame with reference frame index equal to 0x8 is (ref_pic_addr+32)[31:0]. address of reference frame with reference frame index equal to 0x9 is (ref_pic_addr+36)[31:0]. address of reference frame with reference frame index equal to 0xa is (ref_pic_addr+40)[31:0]. address of reference frame with reference frame index equal to 0xb is (ref_pic_addr+44)[31:0]. address of reference frame with reference frame index equal to 0xc is (ref_pic_addr+48)[31:0]. address of reference frame with reference frame index equal to 0xd is (ref_pic_addr+52)[31:0]. address of reference frame with reference frame index equal to 0xe is (ref_pic_addr+56)[31:0]. address of reference frame with reference frame index equal to 0xf is (ref_pic_addr+60)[31:0]. ref_pic_addr base address storing the location of 16 reference frames, and the base address of every reference frame must be 32-bit aligned. h264+0034h h264 mc line buffer address register h264_mc_line_b uf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mc_line_buf_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mc_line_buf_addr[15:4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro mc_line_buf_addr base address for mc pre-fetch line buffer and 16-bytes aligned . the pre-fetch buffer size for mc is width_in_mb*16 * 48 *1.5 bytes . (46080bytes for vga) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 940 of 1535 h264+0038h h264 mc line buffer offset register h264_mc_line_bu f_offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mc_p fhen type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name uvbuf_offset ybuf_offset type r/w r/w r/w r/w r/w r/w mc_pfh_en enable mc pre-fetch pixel data mode if mc_pfh_en = 1?b1. note : this prefetch mode can only be enabled under the case that width_in_mb>=3 && height_in_mb>=4 uvbuf_offset number of mc pre-fetch line buffer for chroma. this number must be 2. ybuf_offset number of mc pre-fetch line buffer for luma. this number must be 4. h264+003ch h264 mc line buffer size register h264_mc_line_buf_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mc_line_uvbuf_size[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mc_line_ybuf_size[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mc_line_uvbuf_size chroma buffer byte size for mc pre-fetch line buffer. the pre-fetch uvbuffer size for mc is width_in_mb* (8+8*mc_line_uvbuf_offset) bytes and must be multiples of 4 bytes . (30720 bytes for vga as mc_line_buf_offset =2) mc_line_ybuf_size luma buffer byte size for mc pre-fetch line buffer. the pre-fetch ybuffer size for mc is width_in_mb* (16+8*mc_line_ybuf_offset) bytes and must be multiples of 4 bytes . (30720 bytes for vga as mc_line_buf_offset =4) h264+0040h h264 mc motion vect or buffer address register h264_mc_mv_bu ffer_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mc_mv_buf_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mc_mv _buf_addr[15:4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro mc_mv_buf_addr base address for mc motion vector buffer and must be 16-byte aligned . total memory is fixed to 3328 bytes. 5.15.2.4 deblocking filter h264+0044h h264 reconstructi on address register h264_dec_re c_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 941 of 1535 name rec_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rec_addr [15:4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro rec_addr reconstruction address. the address must be 16-bytes aligned . the memory size needs width_in_mb *16* height_in_mb*16 *1.5 bytes (460800 bytes for vga) h264+0048h h264 deblk buffer address register h264_dec_deb_ buf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name deb_buf_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name deb_buf_addr[15: 13] type r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro deb_buf_addr deblocking filter buffer working buffer. the address must be 16-bytes aligned. the memory size needs (width_in_mb *8 +8)*16 bytes (5248 bytes for vga) h264+004ch h264 reconstruction luma size register h264_dec_re c_y_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rec_y_size[19:16] type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rec_y_size[15:4] type r/w r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro rec_y_size size of reconstruction memory for luma and the supported size must be multiples of 16- bytes . the size is (width_in_mb *16* heigh _in_mb*16) bytes (307200 bytes for vga) h264+0050h h264 deblk data buffer0 address register h264_dec_deb_dat _buf0_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name deblk_dat_buf0_addr[16:15] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name deblk_dat_buf0_addr[15:4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro deblk_dat_buf0_addr deblocking filter/mc hand-shaking buffer0 address and must be 16-bytes aligned . the size is 384 bytes . if deblk_data_buf0_addr was assigned different internal memory bank address from deblk_data_buf1_addr , decoding performance could be better. note: if video sequence supports ipcm, the address must be 512-bytes aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 942 of 1535 h264+0054h h264 deblk data buffer1 address register h264_dec_deb_dat _buf1_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name deblk_data_buf0_addr[16:15] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name deblk_data_buf0_addr[15:4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro deblk_dat_buf1_addr deblocking filter/mc hand-shaking buffer0 address and must be 16-bytes aligned . the size is 384 bytes . if deblk_data_buf1_addr was assigned different internal memory bank address from deblk_data_buf0_addr , decoding performance could be better. note: if video sequence supports ipcm, the address must be 512-bytes aligned. 5.15.2.5 cavlc h264+0060h h264 cavlc base address register h264_cavlc_ba se_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cavlc_base_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cavlc_base_addr[ [15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cavlc_base_addr cavlc working buffer base address and must be 32-bit aligned . total size is 520 bytes. 5.15.2.6 interrupts h264+0070h h264 decoder interrupt status register h264_dec_irq _sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mb_p os_ir q mb_ty pe_er over flow vld- erro r dma_ paus e dec_ done type r/w r/w r/w r/w r/w r/w dec_done decode complete interrupt. goes high when decoder operation is done. dma_pause dma pause interrupt. goes high when dma access length reaches dma limit. dma access will resume when software program a new dma address into hardware.. vld_error vld error interrupt. goes high when cavlc decoder returns error as processing bit stream. this interrupt implies an error in bitstream. overflow overflow interrupt. goes high when decoder length counter reaches slice length and decoding operation is still not over. this interrupt implies an error in bitstream. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 943 of 1535 mb_type_err mb type error interrupt. goes high when decoded mb_type is an invalid type. mb_pos_irq mb position interrupt. goes high when current decoding macroblock matches the setting of h264_dec_mb_irq_pos. h264+0074h h264 decoder interrupt mask register h264_dec_irq _mask bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mb_p os_ir q mb_ty pe_er over flow vld_e rror dma_ paus e dec_ done type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 dec_done mask of decoder complete interrupt and interrupt status. dma_pause mask of dma pause interrupt and interrupt status. vld_error mask of vld error interrupt and interrupt status. overflow mask of overflow interrupt and interrupt status from idct. mb_type_err mask of overflow interrupt and interrupt status of mb_type_err. mb_pos_irq mask of overflow interrupt and interrupt status of mb_pos_irq. h264+0078h h264 decoder interrupt acknowledge register h264_dec_irq_ack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mb_p os_ir q mb_ty pe_er over flow vld_e rror dma_ paus e dec_ done type r/w r/w r/w r/w r/w r/w dec_done decoder complete interrupt acknowledge. dma_pause dma pause interrupt acknowledge. vld_error vld error interrupt acknowledge. overflow overflow interrupt acknowledge from idct. mb_type_err overflow interrupt acknowledge of mb_type_err. mb_pos_irq overflow interrupt acknowledge of mb_pos_irq. h264+007ch h264 decoder mb_ irq_pos setting h264_dec_mb_ir q_pos bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mb_irq_pos_y mb_irq_pos_x free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 944 of 1535 type r/w r/w mb_irq_pos_x, mb_irq_pos_y mb_pos_irq interrupt will generate when current decoding macroblocks is at the location of (mb_irq_pos_y,mb_irq_pos_x). 5.15.2.7 debug information h264+0100h h264 decoder dma status register h264_dec_dm a_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gaddr[15:3] type ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gaddr[2:0] wait_ glco md wait_ gdrd y- fifo_ full fifo_ empt y vld_r dy greq dma_state[4:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro dma_state dma fsm machine 0 idle 2 dma_addr 4 dma_rdata 8 dma_wait 16 dma_pend greq dma gmc request vld_rdy vld codeword ready for cavlc decoder fifo_empty dma fifo empty fifo_full dma fifo full wait_gdrdy wait for gmc data ready signal wait_glcomd wait for gmc command latch gaddr lsb-16 bit of dma?s requested memory address h264+0104h h264 decoder debug info0 register h264_dec_de bug_info0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name seq_i dle vld_e rr vld_r dy getbi t bitcnt[4:0] cavlc_blk_state[3:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cavlc_mb_state[3:0] cavlc_y_pos[5:0] cavlc_x_pos[5:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro cavlc_mb_x current macroblock x-position for cavlc cavlc_mb_y current macroblock y-position for cavlc cavlc_mb_state cavlc mb-level fsm state 0 mb_idle 1 rmem_en 2 rmem free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 945 of 1535 3 rmem_done 4 wait_blk_done 5 wmem_en 6 wmem 7 wmem_done 8 mb_done cavlc_blk_state cavlc 4x4 blk-level fsm state 0 blk_idle 1 rnc_wait 2 blk_str 3 total_coeff 4 trail1 5 level 6 total_zero 7 run 8 error 9 noncoded 10 blk_done 11 lelel_full 12 rest_coeff bitcnt consumed bit counts for the current vld-codeword getbit current vld-codeword is valid vld_rdy vld-codeword is ready for cavlc vld_err vld error for the current frame. seq_idle sequencer is in idle state h264+0108h h264 decoder debug info1 register h264_dec_de bug_info1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vld_codeword[31:16] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vld_codeword[15:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro vld_codeword current vld-codeword for cavlc h264+010ch h264 decoder debug info2 register h264_dec_de bug_info2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name idct_ over flow block_4x4_cnt_ip[4:0] busy[3:0] type ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trans[3:0] intra/mc_y_pos[5:0] intra/mc_x_pos[5:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 946 of 1535 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro intra/mc_mb_x current macroblock x-position for intra/mc intra/mc_mb_y current macroblock y-position for intra/mc trans[3:0] bit0 : is_intra4_trans , mc state machine1 state bit1 : is_intra16_trans mc state machine2 state bit2 : is_chroma_trans mc state machine2 state bit3 : is_pmb_trans mc state machine2 state busy[3:0] bit0 : iintra_busy bit1 : iintra_4x4_mode_busy bit2 : mc_busy bit3 : mv_busy block_4x4_cnt_ip idct_overflow idct overflow for the current frame h264+0110h h264 decoder debug info3 register h264_dec_de bug_info3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mvpred_counter[4:0] mvpred_state[3:0] type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ri_state[1: 0] fir_state_e xt[1:0] fir_state1[5:0] mf_state[4:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro mf_state intra state machine1 state fir_state1 intra state machine2 state ri_state load_ri_base_addr_state h264+0114h h264 decoder debug info4 register h264_dec_de bug_info4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mc_prefetch_mem_hit_cnt[17:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro mc_prefetch_mem_hit_cnt mc pre-fetch memory hit counts information of current frame. h264+0118h h264 decoder debug info5 register h264_dec_de bug_info5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 947 of 1535 name mc_prefetch_mem_miss_cnt[17:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro mc_prefetch_mem_miss_cnt mc pre-fetch memory miss counts information of current frame. h264+011ch h264 decoder debug info6 register h264_dec_de bug_info6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name intra_gmc_state[4:0] intra_state[5:0] type ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name acc0[14:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro intra_state intra state machine state h264+0120h h264 decoder de bug info7 register h264_dec_de bug_info7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name invtrans_st ate[1:0] qpy[5 ] type ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name qpy[4:0] invquant_state[2: 0] intra4x4_gmc_sta te[2:0] intra4x4_state[4:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro intra4x4_state intra4x4 state machine intra4x4_gmc_state intra4x4 gmc controller state machine h264+0124h h264 decoder debug info8 register h264_dec_de bug_info8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mem2 _rdy mem1 _rdy flr_r dy data_ buf deblk_flr_state[ 2:0] deblk_mem2_state[3:0] deblk_mem1_state[3:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name deblk_ seq_state[3:0] deblk_y_pos[5:0] deblk_x_pos[5:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro deblk_mb_x current macroblock x-position for deblocking filter deblk_mb_y current macroblock y-position for deblocking filter deblk_seq_state deblocking filter?s sequencer state machine state 0 idle 1 start 2 deblk_st0 3 deblk_st1 4 deblk_st2 5 deblk_st3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 948 of 1535 6 deblk_st4 7 deblk_st5 8 deblk_st6 9 deblk_st7 10 deblk_st8 deblk_mem1_state deblocking filter?s memory interface1 state machine state 0 idle 1 read_req_1 2 read_req_2 4 write_req_1 5 write_req_2 6 write_req_3 8 wait_dat_rdy1 9 wait_write_ok1 10 wait_write_ok2 11 wait_to_idle deblk_mem2_state deblocking filter?s memory interface2 state machine state 0 idle 1 wait_blk_done 4 write_req_1 6 write_req_2 9 wait_write_ok1 10 wait_to_idle deblk_flr_state deblocking filter core state machine4 state 0 idle 1 deblk_edge_0 2 deblk_edge_1 3 deblk_edge_2 4 deblk_edge_3 5 wait_dat1 6 wait_dat2 7 wait_empty_buff data_buf current deblk filter used data buffer. 0: data buffer0; 1: data buffer1 flr_rdy deblk filter core has finished in the current state mem1_rdy deblk memory interface1 has finished in the current state mem2_rdy deblk memory interface2 has finished in the current state h264+0128h h264 decoder debug info9 register h264_dec_de bug_info9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name h264_dec_cycle_cnt[31:16] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h264_dec_cycle_cnt[15:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 949 of 1535 type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro h264_dec_cycle_cnt total cycle counts from h264_dec start to h264_dec_done per frame. h264+012ch h264 decoder de bug info10 register h264_dec_debu g_info10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h264_seq_state [47:32] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro h264_dec_seq_state h264 decoder state machine h264+0130h h264 decoder debug info11 register h264_dec_debu g_info11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name h264_seq_state [31:16] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h264_seq_state[15:0] type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro h264_dec_seq_state h264 decoder state machine 5.16 image dma 5.16.1 general description image dma plays the role of moving image data between different image modules and memory. in MT6516, image dma has been divided into two modules, image dma 0 and image dma 1, and they are located in graphsys1 and graphsys2 respectively, as shown in figure 122 . in image dma 1, it mainly contains video and jpeg related sub-modules, and thus its major function is to provide services for video codec and jpeg encoder. besides, it contains two independent modules to support multiple outputs of ovl dma and irt0 dma. in image dma 0, it contains several modules to support image frame buffer read/write. it also contains two extra modules to support multiple outputs of ovl dma and irt0 dma. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 950 of 1535 image dma 1 image dma 0 post resizer jpeg encoder video frame buffer (yuv420) jpeg line buffer (yuv422) (yuv420) (yuv411) (gray) capture resizer drop resizer image post processing engine mp4 deblock engine lcd frame buffer (rgb565) (rgb888) (argb8888) tv out frame buffer (rgb565) image frame buffer (rgb565) (rgb888) (bgr888) lcd if figure 122 inter-connection of image dma 0 and image dma 1 5.16.1.1 image dma 0 image dma 0 contains 6 major modules. most of them work in rgb domain except that ovl dma works in yuv domain. they altogether support those functions listed below. z read rgb565/bgr888/rgb888 image frame and output by pixel. z overlay an image with a mask on-the-fly. z image clipping z image pitching z image rotation and flipping. z hardware triggering and direct couple interface to lcd dma. the details of each sub-module are described in the following. 5.16.1.1.1 image buffer write 1 dma (ibw1 dma) ibw1 dma receives rgb888 pixel data from y2r1 (yuv to rgv engine 1), and either write data into memory or output pixel data to lcd. when writing to memory, it supports three formats, rgb565, rgb888 or argb8888, as shown in figure 123 . it plays the role of saving the backup image. whenever jpeg dma, video dma, or irt1 dma is dumping images, ibw1 dma can be enabled to dump a backup image simultaneously. besides, ibw1 dma also plays the role of writing local display under videophone scenario. it has the following functions. z auto-restart and triple buffers supported z direct couple to lcd dma (dc mode) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 951 of 1535 z hardware trigger to lcd dma z image clipping z image pitching detail descriptions of those functions are described as below. auto-restart ibw1 dma can restart itself to receive next frame, and switch base address at every restart. it has three base addresses to support double or triple frame buffers under auto-restart mode. direct couple to lcd dma (dc mode) ibw1 dma can move data to lcd dma through direct couple interface. the interface consists of request, acknowledge, and 32-bit data bus. under dc mode, frame data will skip the frame buffer, as indicated in figure 123 . lcd updates the data on the fly under this mode. however this mode cannot work in camera preview. this is because lcd update could halt for a long time, and therefore the next pixel data from the camera may not be captured in time. hardware trigger to lcd dma ibw1 dma can issue a hardware trigger signal along with the current base address of the lcd frame buffer to acknowledge lcd dma starting to move data. the signal would be either asserted at the start of a frame under dc mode or at the end of frame when non-dc mode, as shown in figure 124 . image clipping ibw1 dma can grab a part of the input image frame as a new image, as illustrated in figure 125 . the advantage of image clipping is that the system does not need to prepare a large piece of memory to store the entire image frame just to show a small portion of it. this can save memory usage, especially for large images. image pitching ibw1 dma can write the received image onto a background image existed in the memory already, as shown in figure 126 . in order to make the function work, two information must be provides for ibw1 dma. the first is the base address where ibw1 would write the first pixel of the input image. the second is the horizontal size of the background image so that ibw1 dma can get the starting address of the next line when it finishes a line. the pitching function can save memory usage when writing a rectangular area of a lcd layer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 952 of 1535 ibw1 dma y2r1 frame buffer ( 3(# 3(# "3(# ) lcd dma 3(# qjyfm
"3(# qjyfm
%$.pef /po%$ .pef figure 123 inter-connection of ibw1 dma frame %$npef opo%$npef figure 124 hardware trigger signal of ibw1 dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 953 of 1535 *#8%." *oqvujnbhf $-*1@5 $-*1@# $-*1@- $-*1@3 0vuqvujnbhf $-*1@5upqcpvoebszpgqboojohxjoepx $-*1@#cpuupncpvoebszpgqboojohxjoepx $-*1@-mfgucpvoebszpgqboojohxjoepx $-*1@3sjhiucpvoebszpgqboojohxjoepx fjuifsupnfnpszpsup-$%%."
figure 125 image clipping of ibw1 dma *#8%." #bdlhspvoejnbhffyjtufejo uifnfnpsz *oqvujnbhf #fgpsf*#8%."tubsufe "gufs*#8%."gjojtife 'sbnfjouifnfnpsz figure 126 image pitching of ibw1 dma 5.16.1.1.2 image buffer write 2 dma (ibw2 dma) ibw2 dma receives rgb888 pixel data from ipp2 (image post processor 2) and then output pixel data to lcd dma, irt1 dma, or r2y0 (rgb to yuv engine 0). it is a pixel-in / pixel-out engine. note that the three output paths could be enabled at the same time. its functions are listed below. z auto-restart free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 954 of 1535 z direct couple to lcd dma (dc mode) z hardware trigger to lcd dma z image clipping z multiple outputs these first four functions are similar to those of ibw1 dma except hardware trigger of ibw2 dma. because direct couple is the only way that ibw2 dma handshakes with lcd dma, ibw2 dma issues a hardware trigger signal to lcd dma only when the starting of the input image. for more details, please refer to the section image buffer write 1 dma . here only the multiple output function is described. multiple outputs ibw2 dma supports multiple output function that it can output pixel data to irt1 dma, r2y0, and lcd dma simultaneously. this makes idp paths more flexible. 5.16.1.1.3 image buffer read 1 dma (ibr1 dma) the main function of ibr1 dma is to move rgb data from memory to r2y0 (rbg to yuv engine). the data format to r2y0 is rgb888 and the data formats from memory can be rgb565, rgb888 and bgr888 (which support bmp data format). the data placement in memory is illustrated in figure 127 . figure 127 rgb data in memory for ibr1 dma 5.16.1.1.4 overlay dma (ovl dma) and ovl multiple output (ovl mo) ovl dma services several output engines, such as jpeg dma, vdoenc dma, prz (post resizer), drz (drop resizer), and y2r0 (yuv to rgb engine 0). the first three modules are located in graphsys2. in order to make parallel service for those engines possible, two multiple output engines are located in graphsys1 and graphsys2 respectively to achieve the goal, as shown in figure 128 . the main function of ovl dma is to read a photo frame from memory, magnify it to the capturing image size, look-up palette table and overlay it onto the capturing image, as shown in figure 129 . the photo frame mask data format can be 1, 2, 4, 8-bpp color index modes. a 256-entry in 24-bit yuv format palette lookup table is used to convert a color index to yuv color value. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 955 of 1535 it is noted that the size of the input image should be multiple of the size of the mask. and although a 8-bits index is provided to select 256 colors, one value among 0~255 is used to be transparent color, i.e., if the value of the index is equal to color key, then it will output a pixel of the input image rather than of the mask. 07-%." 07-.0 07-.0 +1&(%." 7%0&/$%." 13; %3; :3 hsbqitzt hsbqitzt figure 128 multiple outputs of ovl dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 956 of 1535 07-%." nbtljouifnfnpsz y joqvujnbhfgspn*11ps$3; y pvuqvujnbhfup07-.0 y figure 129 overlay function of ovl dma 5.16.1.1.5 image rotator 1 / image rotator 3 dma (irt1 / irt3 dma) irt1 and irt3 dma provide the same functions. they all received pixel data from the input image and write them into memory with rgb565, rgb888, or argb8888 format. the major functions of irt1 / irt3 dma are listed below. z auto-restart and triple buffers supported z hardware trigger to lcd dma (only irt1 dma) z image pitching z image rotation and flipping the first three functions are similar to those of ibw1 dma except hardware trigger of irt1 dma. because irt1 dma has no direct couple to lcd dma, the hardware trigger signal issued by irt1 dma always at the ending of the written image. for more details, please refer to the section image buffer write 1 dma , and here only the last function is described. image rotation and flipping the definition of image rotation and flipping of irt1 / irt3 dma is shown in figure 130 . when rotation function and flipping function are both enabled, the total effect is to rotate image first and then horizontally flip the rotated image, as indicated in the figure. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 957 of 1535 figure 130 definition of image rotation and flipping of irt1 / irt3 dma 5.16.1.2 image dma 1 image dma 1 contains 4 major modules, and all of them work in yuv domain. they altogether support those functions listed below. z data stream flow control on jpeg encoder dma. z color format conversion (yuv444 yuv420, yuv444 yuv422, yuv444 yuv411) z data sequence conversion (scan-line based block based) z video rotation and flipping the details of each sub-module are described in the following. 5.16.1.2.1 jpeg encoder dma (jpeg dma) the main function of jpeg dma is to receive yuv444 data from ovl dma by pixels and transmit yuv422/ yuv420/yuv411/gray data to jpeg encoder by 8x8 blocks. its main functions are described below. z auto-restart z color format conversion (yuv444 yuv420, yuv444 yuv422, yuv444 yuv411) z image padding z data format conversion z flow control free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 958 of 1535 detail descriptions of those functions are described as below. auto-restart to overlap the codec processing time with that of file system manipulations, an auto-restart mode is designed. jpeg encoder dma automatically restarts itself to receive next frame without being re-configured and re-enabled by mcu. jpeg dma will not stop transfer until it is disabled by mcu. note that associated settings must be programmed in other related engines as well. color format conversion jpeg dma receives packed yuv444 data (pixel) from ovl dma, and converts them into one of the four kinds of formats, i.e., yuv422, yuv420, yuv422, or gray data. the differences of these four formats are shortly described in table 105 . u / v y horizontal vertical yuv422 no sub-sampled sub-sampled by 2 no sub-sampled yuv420 no sub-sampled sub-sampled by 2 sub-sampled by 2 yuv411 no sub-sampled sub-sampled by 4 no sub-sampled gray no sub-sampled abandoned abandoned table 105 format supported by jpeg dma image padding jpeg encoder processes 8x8-block y/u/v data, and jpeg dma is responsible for transmitting these blocks. in order to ensure an image can be divided into 8x8 blocks in y/u/v component respectively, jpeg dma will pad the input image if needed. referred to table 105 , if yuv422 format is selected, the u/v component of the input image will be horizontally sub-sampled by 2. to keep the sub-sampled component able to be divided into 8x8 blocks completely, the input image must be padded to be horizontally multiple of 16 and vertically multiple of 8 so that the size of u/v component after sub-sampled would be multiple of 8 in both horizontal and vertical. with the same consideration, the input image must be padded to multiple of 16 in both horizontal and vertical under yuv420 mode, multiple of 32 in horizontal and multiple of 8 under yuv411 mode, and multiple of 8 in both horizontal and vertical under gray mode. an example of yuv422 mode is illustrated in figure 131 . in this case, the original frame size is (16n+13) x (8n+6), which is not multiple of 16 x 8. therefore, three additional pixels are padded to the end of each line to make the pixel count multiple of 16. in the vertical direction, two more lines are padded with last line to make line count to multiple of 8. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 959 of 1535 16n+13 8n+6 original frame padded frame figure 131 image padding under yuv422 mode data format conversion since the jpeg encoder needs data of signed 2?s complement format. the jpeg encoder dma takes the responsibility to handle the data format conversion. each of y, u, or v component values of input data is of 8- bit unsigned format, which represents a value ranging from 0 to 255. the component value of the data is converted into 8-bit 2?s complement format, which represents a value ranging from ?128 to 127. flow control when converting scan-line data into 8x8-block data, jpeg dma uses line buffers to temporarily store the input pixel data. when working under yuv422, yuv411, and gray mode, jpeg dma must store 8-line data and then it can transmit 8x8 blocks to jpeg encoder. when working under yuv420 mode, because u/v component are vertically sub-sampled by 2, jpeg dma must store 16-line data to make u/v component be divided into 8x8 blocks completely. after jpeg dma collects enough line data, it transmits blocks inside a macro block to jpeg encoder. after a macro-block finishes, it continue to transmit blocks inside the next macro block. the blocks inside a macro-block is determined by its format, as shown in figure 132 . note that the number inside each macro block in figure 132 represents the sequence of y blocks. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 960 of 1535 yuv422 yuv420 16 8 16 16 8 32 yuv411 gray 8 8 y y0 y1 y2 y3 u v macro block size blocks inside a macro block y0 y1 y2 y3 u v y0 y1 u v 01 01 23 01 23 figure 132 sequence of blocks transmitted to jpeg encoder 5.16.1.2.2 video encode dma (vdoenc dma) the main functions of vdoenc dma are listed below. z auto-restart z color format conversion (packed yuv444 data planar yuv 420 data) z co-work with irt0 dma to support video frame rotation and flipping vdoenc dma has a frame buffer write engine (vdoenc w dma) and a frame buffer read engine (vdoenc r dma) to handle frame buffers, as shown in figure 133 . vdoenc dma is responsible for converting packed yuv444 data (pixel) to planar yuv420 data, and vdoenc w dma writes those planar data into three contiguous component buffers (y/u/v buffer) for mpeg4 encoder. for some design consideration, the data sequece of each component is 4x4 block now, and thus vdoenc dma needs line buffers to convert the scan-line data into 4x4 block data. by the way, for video preview, vdoenc r dma can be triggered by vdoenc w dma to reads the planar yuv420 data buffers written by vdoenc w dma, and then output to image rotator 0 dma (irt0 dma). if vdoenc r dma is not idle when vdoenc w dma issues a trigger signal, it will ignore the signal and continue its current transmission. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 961 of 1535 packed yuv444 (pixel) y u v vdoenc wdma v buffer vdoenc rdma planar yuv420 scan-line based block based block based mp4 encoder u buffer y buffer irt0 dma packed yuv444 (pixel) y u v figure 133 overview of vdoenc dma figure 134 scan-line mode vs. block mode auto-restart vdoecn w dma automatically restarts itself to receive next frame without being re-configured and re- enabled by mcu. this can save a lot of mcu time since the mcu no longer needs to handle vdoenc dma at each frame boundary, which also makes the data stream smoother. usually, double buffer scheme is employed to smooth video encoding. therefore, the second set of base addresses register are provided in vdoenc dma to contain the second frame buffer. vdoenc w dma automatically switches the base address free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 962 of 1535 between the two addresses at every restart. by the way, as mentioned above, vdoenc r dma is triggered by vdoenc w dma, so it can be restarted by vdoenc w dma when it is idle. the base address of vdoenc r dma is sent by vdoenc w dma to ensure vdoenc r dma reads the frame buffer which vdoenc w dma just wrote. color format conversion as mentioned, vdoenc dma converts packed yuv444 data into planar yuv420 data. besides, it also converts the scan-line data into 4x4 block data. rotation and flipping vdoecn rdma must co-work with irt0 dma to execute the functions. the data forward to irt0 dma are 4x4 block data, and irt0 will convert them into packed yuv444 data. the definitions of rotation and flipping are the same to those of irt1 dma. please refer to figure 130 for more details. 5.16.1.2.3 video decode dma ( vdodec dma ) the main functions of vdodec dma are listed below. z both scan-line based buffer and block-based buffer supported z color format conversion (planar yuv 420 data packed yuv444 data) z co-work with irt0 dma to support video frame rotation and flipping scan-line mode vs. block mode vdodec can read 4x4 block based frame buffer and scan-line based frame buffer, as shown in figure 135 . when vdodec dma works under scan-line mode, it will output to irt0 multiple output engine directly, and thus unable to rotate or flip the frame. color format conversion when working under scan-line mode, vdodec will output packed yuv444 data to the succeeding module. thus conversion from planar yuv420 to pack yuv444 is done inside vdodec dma. co-work with irt0 dma when working under block mode, vdodec dma can co-work with irt0 dma to execute the rotation and flipping functions, just as vdoenc r dma does. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 963 of 1535 figure 135 overview of vdodec dma 5.16.1.2.4 image rotator 0 dma (irt0 dma) and irt0 multiple output (irt0 mo) irt0 dma has three main functions. z convert 4x4 block data to packed yuv444 data z co-work with video encode rdma or video decode dma to support video frame rotation and flipping z multiple outputs irt0 dma uses line buffers to complete the functions above. about the definition of rotation and flipping, please refer to figure 130 . here only the function of multiple outputs is described. multiple outputs of irt0 dma irt0 dma services several output engines, such as capture resize (crz), image post processor 1 (ipp1), mpeg4 de-blocking engine (mp4deblk), and post resizer (prz). the first three modules are located in graphsys1. in order to make parallel service for those engines possible, two multiple output engines are located in graphsys1 and graphsys2 respectively to achieve the goal, as shown in figure 136 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 964 of 1535 figure 136 multiple outputs of irt0 dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 965 of 1535 5.16.2 register definitions engine width/height bits minimum v a e maximum val ue src_xsize 16 1 65,535 src_ysize 16 1 65,535 bkgd_xsize0 16 1 65,535 bkgd_xsize1 16 1 65,535 ibw1 d m a bkgd_xsize2 16 1 65,535 xsize 16 1 65,535 ibw2 d m a ysize 16 1 65,535 ibr1 d m a pxlnum 32 1 4,294,967,295 xsize 16 1 65,535 ovl d m a ysize 16 1 65,535 src_xsize 16 1 65,535 src_ysize 16 1 65,535 bkgd_xsize0 16 1 65,535 bkgd_xsize1 16 1 65,535 irt1 d m a bkgd_xsize2 16 1 65,535 src_xsize 16 1 65,535 src_ysize 16 1 65,535 bkgd_xsize0 16 1 65,535 bkgd_xsize1 16 1 65,535 irt3 d m a bkgd_xsize2 16 1 65,535 xsize 16 1 65,535 jpeg d m a ysize 16 1 65,535 xsize 12 16 (16x) 4080 (16x) vdoenc d m a ysize 12 16 (16x) 4080 (16x) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 966 of 1535 xsize 10 16 (16x) 1008 (16x) vdodec d m a ysize 10 16 (16x) 1008 (16x) xsize 12 16 (16x) 4080 (16x) irt0 d m a ysize 12 16 (16x) 4080 (16x) 5.16.2.1 image dma 0 register address register function acronym imgdma0+0000h image dma 0 status register imgdma0_sta imgdma0+0004h image dma 0 interrupt acknowledge register imgdma0_ackint imgdma0+0010h image dma software reset imgdma0_sw_rstb imgdma0+0020h image dma 0 gmc interface status imgdma0_gmcif_sta imgdma0+0040h image dma 0 current frame information imgdma0_curr_frame imgdma0+0300h image buffer write 1 dma start register imgdma0_ibw1_str imgdma0+0304h image buffer write 1 dma control register imgdma0_ibw1_con imgdma0+0308h image buffer write 1 dma alpha register imgdma0_ibw1_alpha imgdma0+0310h image buffer write 1 dma horizontal size register of source image imgdma0_ibw1_src_xsize imgdma0+0314h image buffer write 1 dma vertical size register of source image imgdma0_ibw1_src_ysize imgdma0+0318h image buffer write 1 dma clip left/right coordinate register of source image imgdma0_ibw1_cliplr imgdma0+031ch image buffer write 1 dma clip top/bottom coordinate register of source image imgdma0_ibw1_cliptb imgdma0+0320h image buffer write 1 dma base address register of frame buffer 0 imgdma0_ibw1_base_addr0 imgdma0+0324h image buffer write 1 dma base address register of frame buffer 1 imgdma0_ibw1_base_addr1 imgdma0+0328h image buffer write 1 dma base imgdma0_ibw1_base_addr2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 967 of 1535 address register of frame buffer 2 imgdma0+0330h image buffer write 1 dma horizontal size register of background image 0 imgdma0_ibw1_bkgd_xsize0 imgdma0+0334h image buffer write 1 dma horizontal size register of background image 1 imgdma0_ibw1_bkgd_xsize1 imgdma0+0338h image buffer write 1 dma horizontal size register of background image 2 imgdma0_ibw1_bkgd_xsize2 imgdma0+0340h image buffer write 1 dma horizontal pixel count register of received image imgdma0_ibw1_rx_xcnt imgdma0+0344h image buffer write 1 dma vertical line count register of received image imgdma0_ibw1_rx_ycnt imgdma0+0350h image buffer write 1 dma horizontal byte count register of written image imgdma0_ibw1_hori_cnt imgdma0+0354h image buffer write 1 dma vertical line count register of written image imgdma0_ibw1_vert_cnt imgdma0+0400h image buffer write 2 dma start register imgdma0_ibw2_str imgdma0+0404h image buffer write 2 dma control register imgdma0_ibw2_con imgdma0+0408h image buffer write 2 dma alpha value register imgdma0_ibw2_alpha imgdma0+0410h image buffer write 2 dma horizontal size register of source image imgdma0_ibw2_xsize imgdma0+0414h image buffer write 2 dma vertical size register of source image imgdma0_ibw2_ysize imgdma0+0418h image buffer write 2 dma clip left/right coordinate register of source image imgdma0_ibw2_cliplr imgdma0+041ch image buffer write 2 dma clip top/bottom coordinate register of source image imgdma0_ibw2_cliptb imgdma0+0420h image buffer write 2 dma horizontal pixel count register of received image imgdma0_ibw2_xcnt imgdma0+0424h image buffer write 2 dma vertical line count register of received image imgdma0_ibw2_ycnt free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 968 of 1535 imgdma0+0500h image buffer read 1 dma start register imgdma0_ibr1_str imgdma0+0504h image buffer read 1 dma control register imgdma0_ibr1_con imgdma0+0508h image buffer read 1 dma base address register of source image imgdma0_ibr1_base imgdma0+050ch image buffer read 1 dma pixel number register of source image imgdma0_ibr1_pxlnum imgdma0+0510h image buffer read 1 dma pixel count register of source image imgdma0_ibr1_pxlcnt imgdma0+0700h overlay dma start register imgdma0_ovl_str imgdma0+0704h overlay dma control register imgdma0_ovl_con imgdma0+0708h overlay dma base address register of mask image imgdma0_ovl_base imgdma0+070ch overlay dma configuration register imgdma0_ovl_cfg imgdma0+0710h overlay dma horizontal size register of mask image imgdma0_ovl_xsize imgdma0+0714h overlay dma vertical size register of mask image imgdma0_ovl_ysize imgdma0+0718h overlay dma horizontal pixel count register of mask image imgdma0_ovl_xcnt imgdma0+071ch overlay dma vertical line count register of mask image imgdma0_ovl_ycnt imgdma0+0800h overlay dma palette register 00 imgdma0_ovl_pal_base imgdma0+0780h overlay dma multiple output engine 0 start register imgdma0_ovl_mo_0_str imgdma0+0784h overlay dma multiple output engine 0 control register imgdma0_ovl_mo_0_con imgdma0+0788h overlay dma multiple output engine 0 busy status imgdma0_ovl_mo_0_busy imgdma0+0c80h image rotator 0 dma multiple output engine 0 start register imgdma0_irt0_mo_0_str imgdma0+0c84h image rotator 0 dma multiple output engine 0 control register imgdma0_irt0_mo_0_con imgdma0+0c88h image rotator 0 dma multiple output engine 0 busy status imgdma0_irt0_mo_0_busy imgdma0+0d00h image rotator 1 dma start register imgdma0_irt1_str imgdma0+0d04h image rotator 1 dma control register imgdma0_irt1_con free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 969 of 1535 imgdma0+0d08h image rotator 1 dma alpha value register imgdma0_irt1_alpha imgdma0+0d10h image rotator 1 dma horizontal size register of source image imgdma0_irt1_src_xsize imgdma0+0d14h image rotator 1 dma vertical size register of source image imgdma0_irt1_src_ysize imgdma0+0d20h image rotator 1 dma base address of frame buffer 0 imgdma0_irt1_base_addr0 imgdma0+0d24h image rotator 1 dma base address of frame buffer 1 imgdma0_irt1_base_addr1 imgdma0+0d28h image rotator 1 dma base address of frame buffer 2 imgdma0_irt1_base_addr2 imgdma0+0d30h image rotator 1 dma horizontal size register of background image 0 imgdma0_irt1_bkgd_xsize0 imgdma0+0d34h image rotator 1 dma horizontal size register of background image 1 imgdma0_irt1_bkgd_xsize1 imgdma0+0d38h image rotator 1 dma horizontal size register of background image 2 imgdma0_irt1_bkgd_xsize2 imgdma0+0d40h image rotator 1 dma base address register of line buffer imgdma0_irt1_fifo_base imgdma0+0d50h image rotator 1 dma horizontal pixel count register of received image imgdma0_irt1_rx_xcnt imgdma0+0d54h image rotator 1 dma vertical line count register of received image imgdma0_irt1_rx_ycnt imgdma0+0d60h image rotator 1 dma horizontal byte count register of written image imgdma0_irt1_hori_cnt imgdma0+0d64h image rotator 1 dma vertical line count register of written image imgdma0_irt1_vert_cnt imgdma0+0f00h image rotator 3 dma start register imgdma0_irt3_str imgdma0+0f04h image rotator 3 dma control register imgdma0_irt3_con imgdma0+0f08h image rotator 3 dma alpha value register imgdma0_irt3_alpha imgdma0+0f10h image rotator 3 dma horizontal size register of source image imgdma0_irt3_src_xsize imgdma0+0f14h image rotator 3 dma vertical size register of source image imgdma0_irt3_src_ysize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 970 of 1535 imgdma0+0f20h image rotator 3 dma base address of frame buffer 0 imgdma0_irt3_base_addr0 imgdma0+0f24h image rotator 3 dma base address of frame buffer 1 imgdma0_irt3_base_addr1 imgdma0+0f28h image rotator 3 dma base address of frame buffer 2 imgdma0_irt3_base_addr2 imgdma0+0f30h image rotator 3 dma horizontal size register of background image 0 imgdma0_irt3_bkgd_xsize0 imgdma0+0f34h image rotator 3 dma horizontal size register of background image 1 imgdma0_irt3_bkgd_xsize1 imgdma0+0f38h image rotator 3 dma horizontal size register of background image 2 imgdma0_irt3_bkgd_xsize2 imgdma0+0f40h image rotator 3 dma base address register of line fifo imgdma0_irt3_fifo_base imgdma0+0f50h image rotator 3 dma horizontal pixel count register of received image imgdma0_irt3_rx_xcnt imgdma0+0f54h image rotator 3 dma vertical line count register of received image imgdma0_irt3_rx_ycnt imgdma0+0f60h image rotator 3 dma horizontal byte count register of written image imgdma0_irt3_hori_cnt imgdma0+0f64h image rotator 3 dma vertical line count register of written image imgdma0_irt3_vert_cnt table 106 image dma 0 register map imgdma0+000 0h image dma 0 status register imgdma0_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irt3 run irt1 run ovl run ibr1 run ibw2 run ibw1 run type ro ro ro ro ro ro reset 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irt3 it irt1 it ovl it ibr1 it ibw2 it ibw1 it type ro ro ro ro ro ro reset 0 0 0 0 0 0 this register helps software program being well aware of the global status of image dma 0 channels. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 971 of 1535 it: interrupt status for engines inner image dma 0 0 : no interrupt is generated by associated engine of image dma 0 1 : an interrupt is generated by associated engine of image dma 0 and waiting for service. it would be cleared after setting corresponding bit in imgdma0_ackint register. run: dma engine status 0 : dma engine is stopped or has completed the transfer already. 1 : dma engine is currently running. if the engine is set to be auto-restart, the related bits will be always 1 until the engine is turned off. imgdma0+000 4h image dma 0 interrupt acknowledge register imgdma0_acki nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irt3 ack irt1 ack ovl ack ibr1 ack ibw2 ack ibw1 ack type wo wo wo wo wo wo this register is used to acknowledge the current interrupt request associated with the completion event of a dma channel by software program. note that this is a write-only register, and any read to it will return a value of ?0?. ack: interrupt acknowledge for the dma channel 0 : no effect 1 : interrupt request of associated engine is acknowledged and interrupt status shown in imgdma0_sta should be relinquished. imgdma0+001 0h image dma software reset imgdma0_sw_ rstb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type rw reset 1 this register is used to reset all registers inner sub-engines except those which are setting through apb. the start bit of each engine should be set to 0 before setting this bit to 0. once image dma is reset, it should be restarted after at least 100us. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 972 of 1535 rstb: software reset bit. 0 : reset all registers inner sub-engines of image dma 0 and image dma 1 except those which are setting through apb. 1 : no effect. imgdma0+002 0h image dma 0 gmc interface status imgdma0_gmc if_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irt3 rint gmc busy irt1 rint gmc busy irt3 wint gmc busy irt1 wint gmc busy ovl gmc busy ibw1 gmc busy ibr1 gmc busy irt3 wext gmc busy irt1 wext gmc busy type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name if4 busy if3 busy if2 busy if1 busy if0 busy type ro ro ro ro ro there are 9 gmc related engines and five gmc ports in image dma 0. this register is used to figure out which engine or which set of gmc interface is busy. when the engine or gmc interface is busy, it means that there are data waiting to read from / write into memory. xxx gmc busy: engine busy signal. 0 : engine does not issue a command. 1 : engine issues a command and not completed yet. ifx busy: gmc interface busy signal. 0 : gmc interface is idle. no action occurs in this port. 1 : gmc interface is busy. a command is not completed yet. imgdma0+004 0h image dma current frame information imgdma0_cur r_frame bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irt1_cur_fr ame ibw1_cur_f rame type ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type ibw1_cur_frmae: to represent the current working frame of ibw1 dma. irt1_cur_frmae: to represent the current working frame of irt1 dma. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 973 of 1535 imgdma0+030 0h image buffer write 1 dma start register imgdma0_ibw1 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ibw1 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ibw1 dma. 0 : stop ibw1 dma 1 : activate ibw1 dma imgdma0+030 4h image buffer write 1 dma control register imgdma0_ibw1 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fmt dc lcd clip pitch tripl e auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 it: interrupt enabling 0 : disable 1 : enable auto rstr: automatic restart. ibw1 dma automatically restarts itself while current frame is finished. 0 : disable 1 : enable triple: when automatic restart function is enabled, it could enable this bit to support triple frame buffers; else, two frame buffers are supported under auto-restart mode. 0 : two frame buffer supported 1 : three frame buffer supported pitch: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 974 of 1535 destination pitching. please refer to figure 126 . 0 : disable 1 : enable clip: picture clipping. once this function is enabled, only the pixels in the region specified by clip_l, clip_r, clip_t, and clip_b are dumped. please refer to figure 125 . 0 : disable 1 : enable lcd: signaling lcd dma. frame ready signal is issued at the beginning of frames in direct couple mode, and is issued at the end of frames in write-buffer mode. note that in the case of direct couple mode, this function must be enabled to trigger lcd dma. please refer to figure 124 . 0 : disable 1 : enable dc: directly coupling to lcd dma. once this function is enabled, image data will output to lcd dma directly instead of writing to lcd frame buffer. 0 : disable 1 : enable fmt: output frame buffer format control 00 : rgb565 01 : rgb888 10 : argb8888, where a is from ibw1_alpha set by software. 11 : reserved imgdma0+030 8h image buffer write 1 dma alpha value register imgdma0_ibw 1_alpha bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name value type r/w value: alpha value for each pixel. imgdma0+031 0h image buffer write 1 dma horizontal size register of source image imgdma0_ibw 1_src_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 975 of 1535 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source frame. if the value is x, then it represents the source is an x-pixel wide image. imgdma0+031 4h image buffer write 1 dma vertical size register of source image imgdma0_ibw 1_src_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source frame. if the value is y, then it represents the source is a y-line high image. imgdma0+031 8h image buffer write 1 dma clip left/right coordinate register of source image imgdma0_ibw 1_cliplr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name right type r/w left: clipped left boundary of the source image. if the value is l, then it represents the clipping function starts from l th pixel of each line. it will be effective while ibw1_con clip bit is enabled. right: clipped right boundary of the source image. if the value is r, then it represents the clipping function finished at r th pixel of each line. it will be effective while ibw1_con clip bit is enabled. please refer to figure 125 to get a visual understanding of the two register fields. imgdma0+031 ch image buffer write 1 dma clip top/bottom coordinate register of source image imgdma0_ibw 1_cliptb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name top type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bottom type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 976 of 1535 top: clipped top boundary of the source image. if the value is t, then it represents the clipping function starts from t th line of the source image. it will be effective while ibw1_con clip bit is enabled. bottom: clipped bottom boundary of the source image. if the value is b, then it represents the clipping function finished at b th line of the source image. it will be effective while ibw1_con clip bit is enabled. please refer to figure 125 to get a visual understanding of the two register fields. imgdma0+032 0h image buffer write 1 dma base address register of frame buffer 0 imgdma0_ibw1 _base_addr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 0. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. imgdma0+032 4h image buffer write 1 dma base address register of frame buffer 1 imgdma0_ibw1 _base_addr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. by the way, this register is only effective when ibw1 dma is working under auto-restart mode . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 977 of 1535 imgdma0+032 8h image buffer write 1 dma base address register of frame buffer 2 imgdma0_ibw1 _base_addr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. by the way, this register is only effective when ibw1 dma is working under auto-restart and triple- buffer mode .. imgdma0+033 0h image buffer write 1 dma horizontal size register of background image 0 imgdma0_ibw 1_bkgd_xsize 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 0. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when ibw1 dma is working under pitching mode , i.e., there have existed an image in the memory, and ibw1 dma will replace some rectangular region of this image. imgdma0+033 4h image buffer write 1 dma horizontal size register of background image 1 imgdma0_ibw 1_bkgd_xsize 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 978 of 1535 horizontal size of the background image 1. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when ibw1 dma is working under pitching and auto-restart mode , i.e., there have existed a second image in the memory, and ibw1 dma will replace some rectangular region of the second image when the writing base address has switched to ibw1_base_addr1. imgdma0+033 8h image buffer write 1 dma horizontal size register of background image 2 imgdma0_ibw 1_bkgd_xsize 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 2. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when ibw1 dma is working under pitching, auto-restart, and triple-buffer mode , i.e., there have existed a third image in the memory, and ibw1 dma will replace some rectangular region of the third image when the writing base address has switched to ibw1_base_addr2. imgdma0+034 0h image buffer write 1 dma horizontal pixel count register of received image imgdma0_ibw 1_rx_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of input image. it is a 16-bit up counter. if the value is x, then it represents ibw1 dma now receives x th pixel of a line of the input image. besides, while it counts to ibw1_src_xsize, it will be reset to 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 979 of 1535 imgdma0+034 4h image buffer write 1 dma vertical line count register of received image imgdma0_ibw 1_rx_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of input image. it is a 16-bit up counter. if the value is y, then it represents ibw1 dma now at y th line of the input image. besides, it will increases 1 while ibw1_rx_xcnt counts to ibw1_src_xsize and ibw1 dma receives a pixel successfully. note: when ibw1 dma starts: (ibw1_rx_xcnt, ibw1_rx_ycnt) = (1, 1); when ibw1 dma finishes: (ibw1_rx_xcnt, ibw1_rx_ycnt) = (1, ibw1_src_ysize+1); imgdma0+035 0h image buffer write 1 dma horizontal byte count register of written image imgdma0_ibw 1_hori_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal byte count of written image. it is an 18-bit down counter. if its value is h, then it represents that there are h bytes of a line not be written to memory yet. besides, while the remaining bytes could be written by a single writing command, it will be reset to ibw1_src_xsize*bpp. imgdma0+035 4h image buffer write 1 dma vertical line count register of written image imgdma0_ibw 1_vert_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 980 of 1535 count: vertical line count of written image. it is an 16-bit up counter. if its value is v, then it represents that ibw1 dma now at (v+1) th line of the written image. besides, it will increases 1 while the last write command of a line has been issued. note: ibw1 dma starts: (ibw1_hori_cnt, ibw1_vert_cnt) = (ibw1_src_xsize*bpp, 0); ibw1 dma finishes: (ibw1_hori_cnt, ibw1_vert_cnt) = (ibw1_src_xsize*bpp, ibw1_src_ysize); imgdma0+040 0h image buffer write 2 dma start register imgdma0_ibw2 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ibw2 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ibw2 dma. 0 : stop ibw2 dma 1 : activate ibw2 dma imgdma0+040 4h image buffer write 2 dma control register imgdma0_ibw2 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r2y0 irt1 dc cam_ crz_v sync_ en irt1_ ultra _high _en clip auto rstr lcd it type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 it: interrupt enabling 0: disable 1: enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 981 of 1535 lcd: signaling lcd dma. frame ready signal is issued at the beginning of frames in direct couple mode, and is issued at the end of frames in dual buffer mode. note that in the case of automatic restart plus direct couple mode, this function must be enabled to trigger lcd dma. 0: disable 1: enable auto rstr: automatic restart. ibw1 dma automatically restarts itself while current frame is finished. 0: disable 1: enable clip: picture clipping. once this function is enabled, only the pixels in the region specified by clip_l, clip_r, clip_t, and clip_b are dumped. please refer to figure 125 . 0: disable 1: enable dc: one of multiple output options of ibw2 dma. directly coupling to lcd dma. once this function is enabled, pixel data will output to lcd dma directly. 0: disable path to lcd dma 1: enable path to lcd dma irt1: one of multiple output options of ibw2 dma. while the bit is set, ibw2 dma will output pixel data to irt1 dma as well as other multiple output destinations simultaneously. 0: disable path to irt1 dma 1: enable path to irt1 dma r2y0: one of multiple output options of ibw2 dma. while the bit is set, ibw2 dma will output pixel data to r2y0 (rgb2yuv module of image post process module) as well as other multiple output destinations simultaneously. 0: disable path to r2y0 1: enable path to r2y0 irt1_ultra_high_en: this control bit is an eco solution for enabling irt1 ultra high function. when this port is enabled, irt1 will get more bandwidth from external memory. 0: disable irt1 ultra high function 1: enable irt1 ultra high function free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 982 of 1535 cam_crz_vsync_en: this control bit is an eco solution for controlling the frame synchronous of ovl dma and ovl_mo_0 to camera and crz. notice it should be configured only when ovl_mo_1 output to vdoenc wdma (video preview / video capture scenario) . 0: disable frame synchronous to camera and crz 1: disable frame synchronous to camera and crz imgdma0+040 8h image buffer write 2 dma alpha value register imgdma0_ibw 2_alpha bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name value type r/w value: alpha value for each pixel. because the input pixels are 24-bits rgb data, but data interface between ibw2 dma to lcd / ibw2 dma to irt1 dma are 32-bit wide, therefore it will prefix this alpha value to construct a argb pixel. imgdma0+041 0h image buffer write 2 dma horizontal size register of source image imgdma0_ibw 2_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source frame. if the value is x, then it represents the source is an x-pixel wide image. imgdma0+041 4h image buffer write 2 dma vertical size register of source image imgdma0_ibw 2_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source frame. if the value is y, then it represents the source is a y-line high image. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 983 of 1535 imgdma0+041 8h image buffer write 2 dma clip left/right coordinate register of source image imgdma0_ibw 2_cliplr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name left type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name right type r/w left: clipped left boundary of the source image. if the value is l, then it represents the clipping function starts from l th pixel of each line. it will be effective while ibw2_con clip bit is enabled. right: clipped right boundary of the source image. if the value is r, then it represents the clipping function finished at r th pixel of each line. it will be effective while ibw2_con clip bit is enabled. please refer to figure 125 to get a visual understanding of the two register fields. imgdma0+041 ch image buffer write 2 dma clip top/bottom coordinate register of source image imgdma0_ibw 2_cliptb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name top type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bottom type r/w top: clipped top boundary of the source image. if the value is t, then it represents the clipping function starts from t th line of the source image. it will be effective while ibw2_con clip bit is enabled. bottom: clipped bottom boundary of the source image. if the value is b, then it represents the clipping function finished at b th line of the source image. it will be effective while ibw2_con clip bit is enabled. please refer to figure 125 to get a visual understanding of the two register fields. imgdma0+042 0h image buffer write 2 dma horizontal pixel count register of received image imgdma0_ibw 2_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 984 of 1535 count: horizontal pixel count of input image. it is a 16-bit up counter. if the value is x, then it represents ibw2 dma now receives x th pixel of a line of the input image. besides, while it counts to ibw2_xsize, it will be reset to 1. imgdma0+042 4h image buffer write 2 dma vertical line count register of received image imgdma0_ibw 2_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of input image. it is a 16-bit up counter. if the value is y, then it represents ibw2 dma now at y th line of the input image. besides, it will increases 1 while ibw2_xcnt counts to ibw2_xsize and ibw2 dma receives a pixel successfully. note: when ibw2 dma starts: (ibw2_xcnt, ibw2_ycnt) = (1, 1); when ibw2 dma finishes: (ibw2_xcnt, ibw2_ycnt) = (1, ibw2_ysize+1); imgdma0+050 0h image buffer read 1 dma start register imgdma0_ibr1 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ibr1 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ibr1 dma. 0: stop ibr1 dma 1: activate ibr1 dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 985 of 1535 imgdma0+050 4h image buffer read 1 dma control register imgdma0_ibr1 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name orde r fmt it type r/w r/w r/w reset 0 0 0 it: interrupt enabling 0: disable 1: enable fmt: data format of frame buffer. 0: the data is two bytes per pixel, i.e., the data format of frame buffer is rgb565. 1: the data is three bytes per pixel, i.e., the data format of frame buffer is either rgb888 or bgr888. order: data order of a 3-byte pixel data. it determines the data format is rgb888 or bgr888. 0: bgr888, from msb to lsb (r is at lower memory location). 1: rgb888, from msb to lsb (b is at lower memory location). please refer to figure 127 to realize the byte sequence determined by fmt and order. imgdma0+050 8h image buffer read 1 dma base address register of source image imgdma0_ibr1 _base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the source image buffer. it should align at 8x address , or ibr1 dma will read wrong data. imgdma0+050 ch image buffer read 1 dma pixel number register of source image imgdma0_ibr1 _pxlnum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name num type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name num type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 986 of 1535 num: number of pixels of the source image. if its value is n, then it represents the source is an n-pixel image. imgdma0+051 0h image buffer read 1 dma pixel count register of source image imgdma0_ibr1 _pxlcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: pixel counter. it is a up counter. if its value is c, then it represents ibr1 now transfers (c+1) th pixel to r2y0 module. note: when ibr1 starts: ibr1_pxlcnt = 0; when ibr1 finishes: ibr1_pxlcnt = ibr1_pxlnum; imgdma0+070 0h overlay dma start register imgdma0_ovl _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ovl dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ovl dma. 0: stop ovl dma 1: activate ovl dma note: ovl dma needs to be set only when the overlay function is enabled. if ovl dma just bypass the pixel data, the only register needs to be set is ?psel? bit of ovl_con to select pixel data source, either from ipp1 (image post free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 987 of 1535 processor) or crz (capture resizer). imgdma0+070 4h overlay dma control register imgdma0_ovl _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name psel palen mode 1 mode 0 it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 it: interrupt enabling. it is valid only when ovl dma is started. 0: disable 1: enable mode: mask data format. ovl dma will read mask data from memory, and then overlay the input pixel data according the mask data. when value of mask data is equal to color key of ovl_cfg, ovl dma will bypass input pixel data to output; else, a new color is used to replace the current input pixel to output. 00: 1-bit per pixel of mask data 01: 2-bit per pixel of mask data 10: 4-bit per pixel of mask data 11: 8-bit per pixel of mask data palen: photo frame palette enabling. please set this bit before any operation with the palette memory. the palette memory is read/write through apb bus. 0: palette read/write disable 1: palette read/write enable psel: pixel engine selection. 0: ipp1 1: crz note: there exists a memory power off control bit (ap_graph1_mem_pwr_off bit 7) to turn off the ovl dma palette. before using ovl dma palette, sw should make sure that the control bit is set to 0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 988 of 1535 imgdma0+070 8h overlay dma base address register of mask image imgdma0_ovl _base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the source image buffer. it should align at 8x address , or ovl dma will read wrong data. imgdma0+070 ch overlay dma configuration register imgdma0_ovl _cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name color key vratio hratio type r/w r/w r/w color key: transparent color key for overlay function. if value of mask data equal to the color key, then ovl dma will bypass input pixel data to output. vratio: vertical scaling ratio. it is used to scaling the vertical size of mask image to the vertical size of source image received from the pixel engine. due to vratio is 4-bits, the scaling ratio could only be 1 to 15. if the value is v, then ovl dma will scale vertical size of make image v-ple. hratio: horizontal scaling ratio. it is used to scaling the horizontal size of mask image to the horizontal size of source image received from the pixel engine. due to hratio is 4-bits, the scaling ratio could only be 1 to 15. if the value is h, then ovl dma will scale horizontal size of make image h-ple. imgdma0+071 0h overlay dma horizontal size register of mask image imgdma0_ovl _xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 989 of 1535 type r/w xsize: horizontal size of the make image. if the value is x, then it represents the mask is an x-pixel wide image. imgdma0+071 4h overlay dma vertical size register of mask image imgdma0_ovl _ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the mask image. if the value is y, then it represents the mask is a y-line high image. imgdma0+071 8h overlay dma horizontal pixel count register of mask image imgdma0_ovl _xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of the make image. it is a 16-bit up counter. if the value is x, then it represents ovl dma now transmits (x+1) th pixel of a line of the make image. besides, while it counts to (ovl_xsize ? 1), it will be reset to 0. and this counter is effective only when overlay function is enabled. imgdma0+071 ch ovl dma vertical line count register of mask image imgdma0_ovl _ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of the mask image. it is a 16-bit up counter. if the value is y, then it represents ovl dma now at (y+1) th line of the make image. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 990 of 1535 besides, it will increases 1 while ovl_xcnt counts to (ovl_xsize ? 1). and if ovl_ycnt counts to (ovl_ysize ? 1), it will be reset to 0. note: when ovl dma starts or finishes: (ovl_xcnt, ovl_ycnt) = (0, 0); imgdma0+080 0h ovl dma palette register 00 imgdma0_ovl _pal_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name color y type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name color u color v type r/w this register stores the colors of the first entry of the palette. note that the second entry is at imgdma0+0804h, the third entry is at imgdma0+0808h, and so on. the last entry (256 th ) is at imgdma0+0xbfch. color y: palette entry y color value. color u: palette entry u color value. color v: palette entry v color value. note: before read/write the palette memory, remember to set palen bit of ovl_con first. imgdma0+078 0h overlay dma multiple output engine 0 start register imgdma0_ovl _mo_0_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ovl multiple output 0. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ovl multiple output 0 0: stop ovl multiple output 0 1: activate ovl multiple output 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 991 of 1535 note: ovl multiple output module is used to transmit ovl dma output pixel data to multiple destinations simultaneously, including jpeg dma, vdoenc wdma, prz, drz, and y2r0. due to its destination located at graphsys1 and graphsys2 respectively, in order to transmit pixel data to different destinations located at different graphsys, ovl multiple output has been divided into ovl multiple output 0 and ovl multiple output 1 to support multiple output function. the starting sequence of ovl dma, ovl multiple output 0 and ovl multiple output 1 should be as followed . ovl multiple output 1 started ? ovl multiple output 0 started ? ovl dma if ovl dma is allowed to transmit pixel data before ovl multiple output 0/1 are started, it would lose some pixels. imgdma0+078 4h overlay dma multiple output engine 0 control register imgdma0_ovl _mo_0_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz y2r0 imgd ma1 type r/w r/w r/w reset 0 0 0 imgdma1: enable output to ovl multiple output 1 in image dma 1. then ovl multiple output 1 will output data to vdoenc wdma, jpeg dma, or prz. 0: disable 1: enable y2r0: enable output to y2r0. 0: disable 1: enable drz: enable output to drz. 0: disable 1: enable imgdma0+078 8h overlay dma multiple output engine 0 busy status imgdma0_ovl _mo_0_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 992 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drz busy y2r0 busy imgd ma1 busy type ro ro ro the busy bits are used to show if ovl multiple output 0 transmits data to destination or not. if there are two or more output path are enabled and only some busy bit stays at 1, then the ovl multiple output 0 may be stalled by the path. imgdma1 busy: 0: no data transmit to image dma 1 now. 1: data are transmitted to image dma 1 now. y2r0 busy: 0: no data transmit to y2r0 now. 1: data are transmitted to y2r0 now. drz busy: 0: no data transmit to drz now. 1: data are transmitted to drz now. imgdma0+0c 80h image rotator 0 dma multiple output engine 0 start register imgdma0_irt0 _mo_0_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of irt0 multiple output 0. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for irt0 multiple output 0 0: stop irt0 multiple output 0 1: activate irt0 multiple output 0 note: irt0 multiple output module is used to transmit output pixel of either irt0 dma or vdodec dma with scan-line mode to multiple destinations simultaneously, including mp4deblk, crz, prz, and ipp1. due to its destination located at graphsys1 and graphsys2 respectively, in order to transmit pixel data to different destinations free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 993 of 1535 located at different graphsys, irt0 multiple output has been divided into irt0 multiple output 0 and irt0 multiple output 1 to support multiple output function. the starting sequence of irt0 dma/vdodec dma with scan-line mode, irt0 multiple output 0 and irt0 multiple output 1 should be as followed . irt0 multiple output 0 started ? irt0 multiple output 1 started ? irt0 dma / vdodec dma with scan-line mode if irt0 dma / vdodec dma with scan-line mode is allowed to transmit pixel data before irt0 multiple output 0/1 are started, it would lose some pixels. imgdma0+0c 84h image rotator 0 dma multiple output engine 0 control register imgdma0_irt0 _mo_0_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ipp1 crz type r/w r/w reset 0 0 crz: enable output to crz. 0: disable 1: enable ipp1: enable output to ipp1. 0: disable 1: enable imgdma0+0c 88h image rotator 0 dma multiple output engine 0 busy status imgdma0_irt0 _mo_0_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ipp1 busy crz busy type ro ro the busy bits are used to show if irt0 multiple output 0 transmits data to destination or not. if there are two or more output path are enabled and only some busy bit stays at 1, then the irt0 multiple output 0 may be stalled by the path. crz busy: 0: no data transmit to crz now. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 994 of 1535 1: data are transmitted to crz now. ipp1 busy: 0: no data transmit to ipp1 now. 1: data are transmitted to ipp1 now. imgdma0+0d 00h image rotator 1 dma start register imgdma0_irt1 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of irt1 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for irt1 dma. 0: stop irt1 dma 1: activate irt1 dma imgdma0+0d 04h image rotator 1 dma control register imgdma0_irt1 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buffe r doub le fmt flip rot pitch lcd tripl e auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 it: interrupt enabling 0: disable 1: enable auto rstr: automatic restart. irt1 dma automatically restarts itself while current frame is finished. 0: disable 1: enable triple: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 995 of 1535 when automatic restart function is enable, it could enable this bit to support triple frame buffers; else, two frame buffers are supported under auto-restart mode. 0: two frame buffer supported 1: three frame buffer supported lcd: signaling lcd dma. frame ready signal is issued at the end of writing data to frame buffer. please refer to section image rotator 1 / image rotator 3 dma for more details. 0: disable 1: enable pitch: destination pitching. please refer to figure 126 to get a quick understanding. 0: disable 1: enable rot: rotation direction related to input image. please refer to figure 130 to get the definition of rotation. 00: no rotation 01: 90 rotation 10: 180 rotation 11: 270 rotation flip: flipping option related to the rotated image. please refer to figure 130 to get the definition of flipping. 0: no flip 1: flipped after rotation fmt: output frame buffer format control 00: rgb565 01: rgb888 10: argb8888, where a is from ibw2_dma. 11: argb8888, where a is from irt1_alpha set by software. buffer double: when rotation direction is 90 or 270 , it needs to allocate a piece of memory to serve as line buffer to achieve the two kinds of rotations. if one of the two rotations is enabled, it needs at least irt1_src_xsize * 32 bytes to serve as line buffer. and if the buffer double bit is enabled, it will use irt1_src_xsize * 64 bytes to serve as line buffer. 0: disable 1: enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 996 of 1535 imgdma0+0d 08h image rotator 1 dma alpha value register imgdma0_irt1 _alpha bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name value type r/w value: alpha value for each pixel. imgdma0+0d 10h image rotator 1 dma horizo ntal size register of source image imgdma0_irt1 _src_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source frame. if the value is x, then it represents the source is an x-pixel wide image. imgdma0+0d 14h image rotator 1 dma vertical size register of source image imgdma0_irt1 _src_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source frame. if the value is y, then it represents the source is a y-line high image. imgdma0+0d 20h image rotator 1 dma base address register of frame buffer 0 imgdma0_irt1 _base_addr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 0. when the output format is rgb565, it should align at 2x address; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 997 of 1535 when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. imgdma0+0d 24h image rotator 1 dma base address register of frame buffer 1 imgdma0_irt1 _base_addr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. by the way, this register is only effective when irt1 dma is working under auto-restart mode . imgdma0+0d 28h image rotator 1 dma base address register of frame buffer 2 imgdma0_irt1 _base_addr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. by the way, this register is only effective when irt1 dma is working under auto-restart and triple- buffer mode .. imgdma0+0d 30h image rotator 1 dma horizo ntal size register of background image 0 imgdma0_irt1 _bkgd_xsize0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 998 of 1535 xsize: horizontal size of the background image 0. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt1 dma is working under pitching mode , i.e., there have existed an image in the memory, and irt1 dma will replace some rectangular region of this image. imgdma0+0d 34h image rotator 1 dma horizo ntal size register of background image 1 imgdma0_irt1 _bkgd_xsize1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 1. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt1 dma is working under pitching and auto-restart mode , i.e., there have existed a second image in the memory, and irt1 dma will replace some rectangular region of the second image when the writing base address has switched to irt1_base_addr1. imgdma0+0d 38h image rotator 1 dma horizo ntal size register of background image 2 imgdma0_irt1 _bkgd_xsize2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 2. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt1 dma is working under pitching, auto-restart, and triple-buffer mode , i.e., there have existed a third image in the memory, and irt1 dma will replace some rectangular region of the third image when the writing base address has switched to irt1_base_addr2. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 999 of 1535 imgdma0+0d 40h image rotator 1 dma base address register of line buffer imgdma0_irt1 _fifo_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of line buffer which is used when rotation is 90 or 270 . it should align at 8x address , or irt1 dma will read wrong data. besides, it should be set in the internal memory to get better performance. note 1: notice that irt1 dma is inside graph1sys, so the internal memory address would be better ranging from 0x4000_0000 to 0x4001_7fff than from 0x4002_0000 to 0x4004_3fff. note 2: when rotation is 90 or 270 , irt1 dma will use either (irt1_src_xsize * 32) bytes or (irt1_src_xsize * 64) bytes to serve as line buffer according to the setting of buffer double bit of irt1_con. imgdma0+0d 50h image rotator 1 dma horizontal pixel count register of received image imgdma0_irt1 _rx_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of input image. it is a 16-bit up counter. if the value is x, then it represents irt1 dma now receives x th pixel of a line of the input image. besides, while it counts to irt1_src_xsize, it will be reset to 1. imgdma0+0d 54h image rotator 1 dma vertical line count register of received image imgdma0_irt1 _rx_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1000 of 1535 vertical line count of input image. it is a 16-bit up counter. if the value is y, then it represents irt1 dma now at y th line of the input image. besides, it will increases 1 while irt1_rx_xcnt counts to irt1_src_xsize and irt1 dma receives a pixel successfully. note: when irt1 dma starts: (irt1_rx_xcnt, irt1_rx_ycnt) = (1, 1); when irt1 dma finishes: (irt1_rx_xcnt, irt1_rx_ycnt) = (1, irt1_src_ysize+1); imgdma0+0d 60h image rotator 1 dma horizontal byte count register of written image imgdma0_irt1 _hori_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal byte count of written image. it is an signed 19-bit down counter. it works at two modes. when rotation is 90 or 270 : it could not tell how many bytes of a line are not written yet. it only tell if a line is finished or not. at irt1 dma starts, its value will be irt1_src_xsize*bpp ; at the end of a frame, it should be zero or negative. when rotation is 0 or 180 : if its value is h, then it represents that there are h bytes of a line not be written to memory yet. besides, while the remaining bytes could be written by a single writing command, it will be reset to irt1_src_xsize*bpp. imgdma0+0d 64h image rotation 1 dma vertical line count register of written image imgdma0_irt1 _vert_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1001 of 1535 count: vertical line count of written image. it is an 16-bit up counter. if its value is v, then it represents that irt1 dma now at (v+1) th line of the written image. it also works at two modes. when rotation is 90 or 270 : it increases 1 while irt1 dma issue a write command to process the data of current segment. sometimes there are no data needed to be processed, and the counter just increases 1 and no action is performed. and it will be reset to 0 while it counts to (irt1_src_ysize ? 1) and an increase signal is issued. when rotation is 0 or 180 : it will increases 1 while the last write command of a line has been issued. note: irt1 dma starts: (irt1_hori_cnt, irt1_vert_cnt) = (irt1_src_xsize*bpp, 0); irt1 dma finishes: when rotation is 90 or 270 : (irt1_hori_cnt, irt1_vert_cnt) = (0 or -1, 0); when rotation is 0 or 180 : (irt1_hori_cnt, irt1_vert_cnt) = (irt1_src_xsize*bpp, irt1_src_ysize); imgdma0+0f 00h image rotator 3 dma start register imgdma0_irt3 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of irt3 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for irt3 dma. 0: stop irt3 dma 1: activate irt3 dma imgdma0+0f 04h image rotator 3 dma control register imgdma0_irt3 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1002 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buffe r doub le fmt flip rot pitch tripl e auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 it: interrupt enabling 0: disable 1: enable auto rstr: automatic restart. irt3 dma automatically restarts itself while current frame is finished. 0: disable 1: enable triple: when automatic restart function is enable, it could enable this bit to support triple frame buffers; else, two frame buffers are supported under auto-restart mode. 0: two frame buffer supported 1: three frame buffer supported pitch: destination pitching. please refer to figure 126 to get a quick understanding. 0: disable 1: enable rot: rotation direction related to input image. please refer to figure 130 to get the definition of rotation. 00: no rotation 01: 90 rotation 10: 180 rotation 11: 270 rotation flip: flipping option related to the rotated image. please refer to figure 130 to get the definition of flipping. 0: no flip 1: flipped after rotation fmt: output frame buffer format control 00: rgb565 01: rgb888 10: argb8888, where a is from lcd. 11: argb8888, where a is from irt3_alpha set by software. buffer double: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1003 of 1535 when rotation direction is 90 or 270 , it needs to allocate a piece of memory to serve as line buffe r to achieve the two kinds of rotations. if one of the two rotations is enabled, it needs at least irt3_src_xsize * 32 bytes to serve as line buffer. and if the buffer double bit is enabled, it will use irt3_src_xsize * 64 bytes to serve as line buffer. 0: disable 1: enable imgdma0+0f 08h image rotator 3 dma alpha value register imgdma0_irt3 _alpha bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name value type r/w value: alpha value for each pixel. imgdma0+0f 10h image rotator 3 dma horizo ntal size register of source image imgdma0_irt3 _src_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source frame. if the value is x, then it represents the source is an x-pixel wide image. imgdma0+0f 14h image rotator 3 dma vertical size register of source image imgdma0_irt3 _src_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source frame. if the value is y, then it represents the source is a y-line high image. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1004 of 1535 imgdma0+0f 20h image rotator 3 dma base address register of frame buffer 0 imgdma0_irt3 _base_addr0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 0. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. imgdma0+0f 24h image rotator 3 dma base address register of frame buffer 1 imgdma0_irt3 _base_addr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there are no limits about the address setting. by the way, this register is only effective when irt3 dma is working under auto-restart mode . imgdma0+0f 28h image rotator 3 dma base address register of frame buffer 2 imgdma0_irt3 _base_addr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the destination frame buffer 1. when the output format is rgb565, it should align at 2x address; when the output format is argb8888, it should align at 4x address; else, when the output format is rgb888, there free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1005 of 1535 are no limits about the address setting. by the way, this register is only effective when irt3 dma is working under auto-restart and triple- buffer mode .. imgdma0+0f 30h image rotator 3 dma horizo ntal size register of background image 0 imgdma0_irt3 _bkgd_xsize0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 0. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt3 dma is working under pitching mode , i.e., there have existed an image in the memory, and irt3 dma will replace some rectangular region of this image. imgdma0+0f 34h image rotator 3 dma horizo ntal size register of background image 1 imgdma0_irt3 _bkgd_xsize1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the background image 1. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt3 dma is working under pitching and auto-restart mode , i.e., there have existed a second image in the memory, and irt3 dma will replace some rectangular region of the second image when the writing base address has switched to irt3_base_addr1. imgdma0+0f 38h image rotator 3 dma horizo ntal size register of background image 2 imgdma0_irt3 _bkgd_xsize2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1006 of 1535 type r/w xsize: horizontal size of the background image 2. if the value is x, then it represents the background image is an x-pixel wide image. the register is effective when irt3 dma is working under pitching, auto-restart, and triple-buffer mode , i.e., there have existed a third image in the memory, and irt3 dma will replace some rectangular region of the third image when the writing base address has switched to irt3_base_addr2. imgdma0+0f 40h image rotator 3 dma base address register of line buffer imgdma0_irt3 _fifo_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of line buffer which is used when rotation is 90 or 270 . it should align at 8x address , or irt3 dma will read wrong data. besides, it should be set in the internal memory to get better performance. note 1: notice that irt3 dma is inside graph1sys, so the internal memory address would be better ranging from 0x4000_0000 to 0x4001_7fff than from 0x4002_0000 to 0x4004_3fff. note 2: when rotation is 90 or 270 , irt3 dma will use either (irt3_src_xsize * 32) bytes or (irt3_src_xsize * 64) bytes to serve as line buffer according to the setting of buffer double bit of irt3_con. imgdma0+0f 50h image rotator 3 dma horizontal pixel count register of received image imgdma0_irt3 _rx_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of input image. it is a 16-bit up counter. if the value is x, then it represents irt3 dma now receives x th pixel of a line of the input image. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1007 of 1535 besides, while it counts to irt3_src_xsize, it will be reset to 1. imgdma0+0f 54h image rotator 3 dma vertical line count register of received image imgdma0_irt3 _rx_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of input image. it is a 16-bit up counter. if the value is y, then it represents irt3 dma now at y th line of the input image. besides, it will increases 1 while irt3_rx_xcnt counts to irt3_src_xsize and irt3 dma receives a pixel successfully. note: when irt3 dma starts: (irt3_rx_xcnt, irt3_rx_ycnt) = (1, 1); when irt3 dma finishes: (irt3_rx_xcnt, irt3_rx_ycnt) = (1, irt3_src_ysize+1); imgdma0+0f 60h image rotator 3 dma horizontal byte count register of written image imgdma0_irt3 _hori_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name count type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal byte count of written image. it is an signed 18-bit down counter. it works at two modes. when rotation is 90 or 270 : it could not tell how many bytes of a line are not written yet. it only tell if a line is finished or not. at irt3 dma starts, its value will be irt3_src_xsize*bpp ; at the end of a frame, it should be zero or negative. when rotation is 0 or 180 : if its value is h, then it represents that there are h bytes of a line not be written to memory yet. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1008 of 1535 besides, while the remaining bytes could be written by a single writing command, it will be reset to irt3_src_xsize*bpp. imgdma0+0f 64h image rotation 3 dma vertical line count register of written image imgdma0_irt3 _vert_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of written image. it is an 16-bit up counter. if its value is v, then it represents that irt3 dma now at (v+1) th line of the written image. it also works at two modes. when rotation is 90 or 270 : it increases 1 while irt3 dma issue a write command to process the data of current segment. sometimes there are no data needed to be processed, and the counter just increases 1 and no action is performed. and it will be reset to 0 while it counts to (irt3_src_ysize ? 1) and an increase signal is issued. when rotation is 0 or 180 : it will increases 1 while the last write command of a line has been issued. note: irt3 dma starts: (irt3_hori_cnt, irt3_vert_cnt) = (irt3_src_xsize*bpp, 0); irt3 dma finishes: when rotation is 90 or 270 : (irt3_hori_cnt, irt3_vert_cnt) = (0 or -1, 0); when rotation is 0 or 180 : (irt3_hori_cnt, irt3_vert_cnt) = (irt3_src_xsize*bpp, irt3_src_ysize); 5.16.2.2 image dma 1 register address register function acronym imgdma1+0000h image dma 1 status register imgdma1_sta imgdma1+0004h image dma 1 interrupt acknowledge register imgdma1_ackint imgdma1+0020h image dma 1 gmc interface status imgdma1_gmcif_sta imgdma1+0100h jpeg dma start register imgdma1_jpeg_str free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1009 of 1535 imgdma1+0104h jpeg dma control register imgdma1_jpeg_con imgdma1+0110h jpeg dma base address register of line fifo imgdma1_jpeg_fifo_base imgdma1+0114h jpeg dma fifo length register imgdma1_jpeg_fifolen imgdma1+0120h jpeg dma horizontal size register of source image imgdma1_jpeg_xsize imgdma1+0124h jpeg dma vertical size register of source image imgdma1_jpeg_ysize imgdma1+0130h jpeg dma write pointer register imgdma1_jpeg_wrptr imgdma1+0134h jpeg dma write horizontal pixel count register of received image imgdma1_jpeg_wrxcnt imgdma1+0138h jpeg dma write vertical line count register of received image imgdma1_jpeg_wrycnt imgdma1+0140h jpeg dma read pointer register imgdma1_jpeg_rdptr imgdma1+0144h jpeg dma read horizontal block count register of padded image imgdma1_jpeg_rdxblk_cnt imgdma1+0148h jpeg dma read vertical block count register of padded image imgdma1_jpeg_rdyblk_cnt imgdma1+0150h jpeg dma fifo line count register imgdma1_jpeg_ffcnt imgdma1+0154h jpeg dma fifo write line index register imgdma1_jpeg_ffwrlidx imgdma1+0158h jpeg dma fifo read line index register imgdma1_jpeg_ffrdlidx imgdma1+0200h video encode dma start register imgdma1_vdoenc_str imgdma1+0204h video encode dma control register imgdma1_vdoenc_con imgdma1+0210h video encode dma y base address 1 register imgdma1_vdoenc_y_base1 imgdma1+0214h video encode dma u base address 1 register imgdma1_vdoenc_u_base1 imgdma1+0218h video encode dma v base address 1 register imgdma1_vdoenc_v_base1 imgdma1+0220h video encode dma y base address 2 register imgdma1_vdoenc_y_base2 imgdma1+0224h video encode dma u base address 2 register imgdma1_vdoenc_u_base2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1010 of 1535 imgdma1+0228h video encode dma v base address 2 register imgdma1_vdoenc_v_base2 imgdma1+0230h video encode dma horizontal size register of source image imgdma1_vdoenc_xsize imgdma1+0234h video encode dma vertical size register of source image imgdma1_vdoenc_ysize imgdma1+0238h video encode dma pixel number register of source image imgdma1_vdoenc_pxlnum imgdma1+0240h video encode write dma horizontal pixel count register of written image imgdma1_vdoenc_wxcnt imgdma1+0244h video encode write dma vertical line count register of written image imgdma1_vdoenc_wycnt imgdma1+0250h video encode read dma y component horizontal pixel count register imgdma1_vdoenc_y_xcnt imgdma1+0254h video encode read dma y component vertical line count register imgdma1_vdoenc_y_ycnt imgdma1+0258h video encode read dma v component horizontal pixel count register imgdma1_vdoenc_v_xcnt imgdma1+025ch video encode read dma v component vertical line count register imgdma1_vdoenc_v_ycnt imgdma1+0260h video encode read dma dropped frame count register imgdma1_vdoenc_drop_fcnt imgdma1+0270h video encode dma line buffer base address register imgdma1_vdoenc_lb_base imgdma1+0274h video encode dma line buffer length register imgdma1_vdoenc_lb_ylen imgdma1+0278h video encode dma line buffer write engine horizontal pixel count register imgdma1_vdoenc_lb_wr_xcnt imgdma1+027ch video encode dma line buffer write engine vertical line count register imgdma1_vdoenc_lb_wr_ycnt imgdma1+0280h video decode dma start register imgdma1_vdodec_str imgdma1+0284h video decode dma control register imgdma1_vdodec_con imgdma1+0290h video decode dma y base address register of source image imgdma1_vdodec_y_base free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1011 of 1535 imgdma1+0294h video decode dma u base address register imgdma1_vdodec_u_base imgdma1+0298h video decode dma v base address register imgdma1_vdodec_v_base imgdma1+02a0h video decode dma horizontal size register imgdma1_vdodec_xsize imgdma1+02a4h video decode dma vertical size register of source image imgdma1_vdodec_ysize imgdma1+02a8h video decode dma pixel number register of source image imgdma1_vdodec_pxlnum imgdma1+02b0h video decode dma y component horizontal pixel count register imgdma1_vdodec_y_xcnt imgdma1+02b4h video decode dma y component vertical line count register imgdma1_vdodec_y_ycnt imgdma1+02b8h video decode dma v component horizontal pixel count register imgdma1_vdodec_v_xcnt imgdma1+02bch video decode dma v component vertical line count register imgdma1_vdodec_v_ycnt imgdma1+0780h overlay dma multiple output engine 1 start register imgdma1_ovl_mo_1_str imgdma1+0784h overlay dma multiple output engine 1 control register imgdma1_ovl_mo_1_con imgdma1+0788h overlay dma multiple output engine 1 busy status imgdma1_ovl_mo_1_busy imgdma1+0c00h image rotator 0 dma start register imgdma1_irt0_str imgdma1+0c04h image rotator 0 dma control register imgdma1_irt0_con imgdma1+0c10h image rotator 0 dma base address register of line buffer imgdma1_irt0_fifo_base imgdma1+0c14h image rotator 0 dma fifo length register imgdma1_irt0_fifoylen imgdma1+0c20h image rotator 0 dma horizontal size register of source image imgdma1_irt0_xsize imgdma1+0c24h image rotator 0 dma vertical size register of source image imgdma1_irt0_ysize imgdma1+0c30h image rotator 0 dma write pointer imgdma1_irt0_wrptr imgdma1+0c40h image rotator 0 dma read pointer imgdma1_irt0_rdptr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1012 of 1535 imgdma1+0c44h image rotator 0 dma read horizontal pixel count register of output image imgdma1_irt0_rdxcnt imgdma1+0c48h image rotator 0 dma read vertical line count register of output image imgdma1_irt0_rdycnt imgdma1+0c50h image rotator 0 dma fifo line count register imgdma1_irt0_fifocnt imgdma1+0c54h image rotator 0 dma fifo write line index register imgdma1_irt0_wryidx imgdma1+0c58h image rotator 0 dma fifo read line index register imgdma1_irt0_rdyidx imgdma1+0c80h image rotator 0 dma multiple output engine 1 start register imgdma1_irt0_mo_1_str imgdma1+0c84h image rotator 0 dma multiple output engine 1 control register imgdma1_irt0_mo_1_con imgdma1+0c88h image rotator 0 dma multiple output engine 1 busy status imgdma1_irt0_mo_1_busy table 107 image dma 1 register map imgdma1+000 0h image dma 1 status register imgdma1_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irt0 run vdod ec run vdoe ncr run vdoe ncw run jpeg run type ro ro ro ro ro reset 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irt0 it vdod ec it vdoe ncr it vdoe ncw it jpeg it type ro ro ro ro ro reset 0 0 0 0 0 this register helps software program being well aware of the global status of image dma 1 channels. it: interrupt status for engines inner image dma 1 0: no interrupt is generated by associated engine of image dma 1 1: an interrupt is generated by associated engine of image dma 1 and waiting for service. it would be cleared after setting corresponding bit in imgdma1_ackint register. run: dma engine status free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1013 of 1535 0: dma engine is stopped or has completed the transfer already. 1: dma engine is currently running. if the engine is set to be auto-restart, the related bits will be always 1 until the engine is turned off. imgdma1+000 4h image dma 1 interrupt acknowledge register imgdma1_acki nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irt0 ack vdod ec ack vdoe ncr ack vdoe ncw ack jpeg ack type wo wo wo wo wo this register is used to acknowledge the current interrupt request associated with the completion event of a dma channel by software program. note that this is a write-only register, and any read to it will return a value of ?0?. ack: interrupt acknowledge for the dma channel 0: no effect 1: interrupt request of associated engine is acknowledged and interrupt status shown in imgdma1_sta should be relinquished. imgdma1+002 0h image dma 1 gmc interface status imgdma1_gmc if_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vdoe nc rlb gmc busy jpeg r gmc busy irt0 r gmc busy vdoe nc wlb gmc busy jpeg w gmc busy irt0 w gmc busy vdoe nc rdma gmc busy vdod ec gmc busy vdoe nc wdma gmc busy type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name if3 busy if2 busy if1 busy if0 busy type ro ro ro ro there are 9 gmc related engines and four gmc ports in image dma 1. this register is used to figure out which engine or which set of gmc interface is busy. when the engine or gmc interface is busy, it means that there are data waiting to read from / write into memory. xxx gmc busy: engine busy signal. 0 : engine does not issue a command. 1 : engine issues a command and not completed yet. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1014 of 1535 ifx busy: gmc interface busy signal. 0: gmc interface is idle. no action occurs in this port. 1: gmc interface is busy. a command is not completed yet. imgdma1+010 0h jpeg dma start register imgdma1_jpe g_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of jpeg dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for jpeg dma. 0: stop jpeg dma 1: activate jpeg dma imgdma1+010 4h jpeg dma control register imgdma1_jpe g_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cam_ crz_v sync_ en auto rstr mode 1 mode 0 it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 it: interrupt enabling 0: disable 1: enable mode: jpeg dma working mode. jpeg dma receives yuv444 pixel and convert received pixel data into block-based data and then output to jpeg encoder according to mode setting here. 00: yuv422 mode. convert to yuv422 block data. 01: gray mode. only y component are converted to block data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1015 of 1535 10: yuv420 mode. convert to yuv420 block data. 11: yuv411 mode. convert to yuv411 block data. auto rstr: automatic restart. jpeg dma automatically restarts itself while current frame is finished. 0: disable 1: enable cam_crz_vsync_en: this control bit is an eco solution for controlling the frame synchronous of ovl_mo_1 and vdoenc wdma to camera and crz. notice it should be configured only when ovl_mo_1 output to vdoenc wdma (video preview / video capture scenario) . 0: disable frame synchronous to camera and crz 1: disable frame synchronous to camera and crz imgdma1+011 0h jpeg dma base address register of line fifo imgdma1_jpe g_fifo_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name adr[15:0] type r/w addr: base address of line fifo used by jpeg dma. it should align at 8x address , or jpeg dma will read wrong data. besides, it should be set in the internal memory to get better performance. note: notice that jpeg dma is inside graph2sys, so the internal memory address would be better ranging from 0x4002_0000 to 0x4004_3fff than from 0x4000_0000 to 0x4001_7fff. imgdma1+011 4h jpeg dma fifo length register imgdma1_jpe g_fifolen bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifolen type r/w fifolen: jpeg dma fifo length. fifolen must be the multiple of 8. recommended values are at least 16 to support double buffer. note: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1016 of 1535 the fifo size is determined by three parameter, jpeg_xsize, jpeg_fifolen, and mode set in jpeg_con. in gray mode : in gray mode, only y component needs to be transmitted to jpeg encoder. because jpeg encoder needs 8x8 block based data, jpeg dma will pad horizontal size of source image to 8x. therefore the realistic horizontal size used to calculate the fifo size is pad_xsize_gray = ((jp eg_xsize + 7) >> 3) << 3 the byte per pixel in this mode is bpp_gray = 1. and thus fifo_size = pad_xsize_gray * jpeg_fifolen * bpp_gray. in yuv422 mode : in yuv422 mode, u&v component both down-sampled 2x. because jpeg encoder needs 8x8 block based data of y, u, and v component, respectively, jpeg dma will pad horizontal size of source image to 16x to ensure u&v component transmitted to jpeg encoder could be 8x. therefore the realistic horizontal size used to calculate the fifo size is pad_xsize_422 = ((jpeg_xsize + 15) >> 4) << 4 the byte per pixel is bpp_422 = 2 and thus fifo_size = pad_xsize_422 * jpeg_fifolen * bpp_422 in yuv411 mode : in yuv411 mode, u&v component both down-sampled 4x. because jpeg encoder needs 8x8 block based data of y, u, and v component, respectively, jpeg dma will pad horizontal size of source image to 32x to ensure u&v component transmitted to jpeg encoder could be 8x. therefore the realistic horizontal size used to calculate the fifo size is pad_xsize_411 = ((jpeg_xsize + 31) >> 5) << 5 the byte per pixel is bpp_411 = 1.5 and thus fifo_size = pad_xsize_411 * jpeg_fifolen * bpp_411 in yuv420 mode : in yuv 420 mode, the vertical size of u/v component are also down-sampled 2x. in order to transmit free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1017 of 1535 8x8 block based data of u&v component to jpeg encoder, jpeg dma must collect 16 line data. so, if jpeg_fifolen is set to 8, it would use 16 lines to store y component data and thus 8 lines to store u&v component. besides, as in yuv422 mode, the realistic horizontal size used to calculated the fifo size is pad_xsize_420 = ((jpeg_xsize + 15) >> 4) << 4 the byte per pixel is bpp_420 = 1.5 and thus fifo_size = pad_xsize_420 * jpeg_fifolen * 2 * bpp_420 imgdma1+012 0h jpeg dma horizontal size register of source image imgdma1_jpe g_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source frame. if the value is x, then it represents the source is an x-pixel wide image . imgdma1+012 4h jpeg dma vertical size register of source image imgdma1_jpe g_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source frame. if the value is y, then it represents the source is a y-line high image. imgdma1+013 0h jpeg dma write pointer register imgdma1_jpe g_wrptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wrptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrptr[15:0] type ro wrptr: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1018 of 1535 write pointer to display current writing address. imgdma1+013 4h jpeg dma write horizontal pixel count register of received image imgdma1_jpe g_wrxcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of input image. it is a 16-bit up counter. if the value is x, then it represents jpeg dma now receives (x+1) th pixel of a line of the input image. besides, while it counts to (jpeg_xsize ? 1), it will be reset to 0. imgdma1+013 8h jpeg dma write vertical line count register of received image imgdma1_jpe g_wrycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of input image. it is a 16-bit up counter. if the value is y, then it represents ibw1 dma now at (y+1) th line of the input image. besides, it will increases 1 while jpeg_wrxcnt counts to (jpeg_xsize ? 1) and jpeg dma receives a pixel successfully. note: when jpeg dma starts: (jpeg_wrxcnt, jpeg_wrycnt) = (0, 0); when jpeg dma finishes: (jpeg_wrxcnt, jpeg_wrycnt) = (0, jpeg_ysize); imgdma1+014 0h jpeg dma read po inter register imgdma1_jpe g_rdptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rdptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rdptr[15:0] type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1019 of 1535 rdptr: read pointer to display current reading address. imgdma1+014 4h jpeg dma read horizontal block count register of padded image imgdma1_jpe g_rdxblk_cn t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display the yuv block count within a segment. the segment include 16 lines in yuv420 mode, and 8 lines in other mode. it is a 14-bits down counter. if its value is c, it represents that there are still (c+1) 8x8 block of current segment not read out of fifo completely, including current reading block. if all 8x8 blocks of current segment are read out of fifo, then it will be reset to its initial value. note: initial value of jpeg_rdxblk_cnt is as followed. in gray mode : the total y component block within a segment (8 lines) is y_block_num_gray = pad_xsize_gray/8 so the initial value of this register under this mode is jpeg_rdxblk_cnt = y_block_num_gray - 1 in yuv422 mode : the total y component block within a segment (8 lines) is y_block_num_422 = pad_xsize_422/8 and due to u&v component being horizontally down-sampled 2x, u_block_num_422 = v_block_num_422 = pad_xsize_422/16 so the initial value of this register under this mode is jpeg_rdxblk_cnt = (y_block_num_422+u_block_num_422+v_block_num_422) - 1 in yuv411 mode : the total y component block within a segment (8 lines) is y_block_num_411 = pad_xsize_411/8 and due to u&v component being horizontally down-sampled 4x, u_block_num_411 = v_block_num_411 = pad_xsize_411/32 so the initial value of this register under this mode is jpeg_rdxblk_cnt = (y_block_num_411+u_block_num_411+v_block_num_411) - 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1020 of 1535 in yuv420 mode : the total y component block within a segment (16 lines) is y_block_num_420 = (pad_xsize_420 / 8) * 2 and due to u&v component being horizontally down-sampled 2x, u_block_num_420 = v_block_num_420 = pad_xsize_420 / 16 so the initial value of this register under this mode is jpeg_rdxblk_cnt = (y_block_num_420+u_block_num_420+v_block_num_420) - 1 imgdma1+014 8h jpeg dma read vertical block count register of padded image imgdma1_jpe g_rdyblk_cn t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display the vertical segment count of padding image. the segment includes 16 lines in yuv420 mode and 8 lines in other mode. it is a 13-bits down counter. if its value is c, it represents that jpeg dma is current at (c+1) th segments counting from bottom of the padding image. it will be decreased by 1 each time jpeg dma reads all 8x8 blocks of current segment out of fifo, except jpeg dma is currently at the bottom segment of padding image, i.e., jpeg_rdblk_cnt is 0 now. note: the initial value of jpeg_rdyblk_cnt is as followed. in yuv420 mode : the vertical segment of padding image in the mode is pad_y_seg_420 = (jpeg_ysize + 15)>>4 so the initial value is jpeg_rdyblk_cnt = pad_y_seg_420 ? 1 in other mode : the vertical segment of padding image in the mode is pad_y_seg_non_420 = (jpeg_ysize + 7)>>3 so the initial value is jpeg_rdyblk_cnt = pad_y_seg_non_420 ? 1 note: when jpeg dma finishes, (jpeg_rdxblk_cnt, jpeg_rdyblk_cnt) are always equal to (0, 0) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1021 of 1535 imgdma1+015 0h jpeg dma fifo line count register imgdma1_jpe g_ffcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display how many lines are stored in fifo now. it could count up or count down. count up: in yuv420 mode, because u&v component are down-sampled 2x, the counter will increase 1 while 2 lines of source image are written into fifo completely; in other mode, the counter will increase 1 while 1 line of source image is writing into fifo completely. therefore, in yuv420 mode, if its value is c, it represents there are (c*2) lines of source image are stored in fifo now; in other mode, a value c represents there are c lines of source image is stored in fifo now. count down: while jpeg dma read all 8x8 blocks of a segment (16 lines in yuv420 mode, and 8 lines in other mode), it will decrease by 8. imgdma1+015 4h jpeg dma fifo write line index register imgdma1_jpe g_ffwrlidx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yidx type ro yidx: display which fifo line jpeg dma is now writing. if its value is y, then jpeg dma is now writing y th fifo line. in yuv420 mode, because u&v component are down-sampled 2x, the counter will increase 1 while 2 lines of source are written into fifo completely; in other mode, the counter will increase 1 while 1 line of source image is writing into fifo completely. when its value is equal to jpeg_fifolen (at the bottom of the fifo) and writing a fifo line is completed, it will free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1022 of 1535 be reset to 1 to acknowledge jpeg dma to write to top of the fifo again. . imgdma1+015 8h jpeg dma fifo read line index register imgdma1_jpe g_ffrdlidx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yidx type ro yidx: display which fifo segment (8 fifo line) jpeg dma is now reading. if its value is y, then jpeg dma is now reading y th fifo segment. when its value is equal to jpeg_fifolen>>3 (at the bottom of the fifo segment) and all 8x8 blocks of current fifo segment are read out, it will be reset to 1 to acknowledge jpeg dma to read from top of the fifo again. imgdma1+020 0h video encode dma start register imgdma1_vdo enc_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of vdoenc dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for vdoenc dma. 0: stop vdoenc dma 1: activate vdoenc dma imgdma1+020 4h video encode dma control register imgdma1_vdo enc_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1023 of 1535 name vdoe nc_ul tra_h igh_e n flip rot rd it auto rstr w2r wr it type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 wr it: wdma done interrupt enable. interrupt issues when all of the transfers are done. for auto-restart mode, interrupt issues at every restart. 0: disable 1: enable w2r: wdma triggers rdma. while this function is enabled, vdoenc wdma will write data to video buffer first, and then a start pulse will issue to vdoenc rdma. if vdoenc rdma is idle now, it will accept the start pulse to read back the same buffer; else, it will ignore the start pulse until its current job is completed. 0: disable 1: enable auto rstr: automatic restart. vdo dma automatically restarts while current frame is finished. base address will be automatically switched between vdoenc_y/u/v_base1 and vdoecn_y/u/v_base2. 0: disable 1: enable rd it: rdma done interrupt enable. interrupt issues when all of the transfers are done. 0: disable 1: enable rot: rotation direction related to source frame buffer. vdoenc rdma must co-work with irt0 dma to execute the function. 00: no rotation 01: 90 rotation 10: 180 rotation 11: 270 rotation flip: flipping option related to source frame buffer. vdoenc rdma must co-work with irt0 dma to execute the function. 0: no flip free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1024 of 1535 1: flipped after rotation vdoenc_ultra_high_en: this control bit is an eco solution for enabling vdoenc wdma ultra high function. when this port is enabled, vdoenc wdma will get more bandwidth from external memory. 0: disable vdoenc ultra high function 1: enable vdoenc ultra high function note: vdoenc rdma must co-work with irt0 to achieve rotation and/or flip function. therefore the rotation/flip setting of vdoenc dma & irt0 dma must be the same. imgdma1+021 0h video encode dma y base address 1 register imgdma1_vdo enc_y_base1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the y component of destination frame buffer 1. it should align at 8x address , or vdoenc dma will read/write wrong data. imgdma1+021 4h video encode dma u base address 1 register imgdma1_vdo enc_u_base1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the u component of destination frame buffer 1. it should align at 8x address , or vdoenc dma will read/write wrong data. imgdma1+021 8h video encode dma v base address 1 register imgdma1_vdo enc_v_base1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1025 of 1535 addr: base address of the v component of destination frame buffer 1. it should align at 8x address , or vdoenc dma will read/write wrong data. imgdma1+022 0h video encode dma y base address 2 register imgdma1_vdo enc_y_base2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the y component of destination frame buffer 2. it should align at 8x address , or vdoenc dma will read/write wrong data. by the way, this register is only effective when vdoenc dma is working under auto-restart mode . imgdma1+022 4h video encode dma u base address 2 register imgdma1_vdo enc_u_base2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the u component of destination frame buffer 2. it should align at 8x address , or vdoenc dma will read/write wrong data. by the way, this register is only effective when vdoenc dma is working under auto-restart mode . imgdma1+022 8h video encode dma v base address 2 register imgdma1_vdo enc_v_base2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the v component of destination frame buffer 2. it should align at 8x address , or vdoenc dma will read/write wrong data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1026 of 1535 by the way, this register is only effective when vdoenc dma is working under auto-restart mode . imgdma1+023 0h video encode dma horizontal size register of source image imgdma1_vdo enc_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source image. if the value is x, then it represents the source is an x-pixel wide image. note that the horizontal size of the source image must be 16x . imgdma1+023 4h video encode dma vertical size register of source image imgdma1_vdo enc_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source image. if the value is y, then it represents the source is a y-line high image. note that the vertical size of the source image must be 16x . imgdma1+023 8h video encode dma pixel number register of source image imgdma1_vdo enc_pxlnum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name num type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name num type r/w num: pixel number of the source image. if its value is n, then it represents the source is an n-pixel image. note pixel number of the frame is equal to vdoenc_xsize * vdoenc_ysize . imgdma1+024 0h video encode write dma horizontal pixel count register of written image imgdma1_vdo enc_wxcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1027 of 1535 name count cur_ fram e type ro ro count: after eco, we use (count*2) to show the currently horizontal pixel position of a segment (4 lines) of y frame buffer where vdoenc wdma is now at. if its value is c, then it represents vdoenc wdma now at (c-7) th ~ c th pixel of a segment of y frame buffer. it is a up-counter. if vdoenc wdma writes last 8 pixel data of a segment, it will be reset to 8 to show vdoenc wdma will be at first 8 pixel of next segment. cur_frame: to represent the current working frame of vdoenc wdma. imgdma1+024 4h video encode write dma vertical line count register of written image imgdma1_vdo enc_wycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently vertical line position of y frame buffer where vdoenc wdma is at. if its value is c, then it represents vdoenc wdma is now at (c-3) th ~ c th line (a segment) of y frame buffer. it is a up-counter. if vdoenc wdma writes out last 8 pixel data of a segment, it will be increased by 4 to show vdoenc wdma switches to next segment. note: when vdoenc dma starts: (vdoenc_wxcnt, vdoenc_wycnt) = (8, 4) when vdoenc dma finishes: (vdoenc_wxcnt, vdoenc_wycnt) = (8, vdoenc_ysize + 4) imgdma1+025 0h video encode read dma y component horizontal pixel count register imgdma1_vdo enc_y_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1028 of 1535 count: show the currently horizontal pixel position of a segment (4 lines) of y frame buffer where vdoenc rdma is now at. if its value is c, then it represents vdoenc rdma is now at (c-3) th ~ c th pixel data of a segment of y frame buffer. it is a up-counter, and it works at two modes. when rotation is 90 or 270 : it is increased by 4 when vdoenc_y_ycnt counts to vdoenc_ysize and 16 bytes data of current position are read out of y frame buffer. when rotation is 0 or 180 : it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdoenc_xsize and 16 bytes data are read out. note: the pixel index is counted from either left or right according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 left right 90 left left 180 right left 270 right right imgdma1+025 4h video encode read dma y component vertical line count register imgdma1_vdo enc_y_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently vertical line position of y frame buffer where vdoenc rdma is now at. if its value is c, then it represents vdoenc rdma is now at (c-3) th ~ c th line (a segment) of y frame buffer. it is a up-counter, and it works at two modes. when rotation is 90 or 270 : it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdoenc_ysize and 16 bytes data are read out. when rotation is 0 or 180 : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1029 of 1535 it is increased by 4 when vdoenc_y_xcnt counts to vdoenc_xsize and 16 bytes data of current position are read out of y frame buffer. note: the line index is counted from either top or bottom according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 top top 90 bottom top 180 bottom bottom 270 top bottom note: vdoenc rdma accept a start pulse from vdoenc wdma (vdoenc_y_xcnt, vdoenc_y_ycnt) = (4 , 4); vdoenc rdma finishes when rotation is 90 or 270 : (vdoenc_y_xcnt, vdoenc_y_ycnt) = (vdoenc_xsize + 4 , 4); when rotation is 0 or 180 : (vdoenc_y_xcnt, vdoenc_y_ycnt) = (4 , vdoenc_ysize + 4); imgdma1+025 8h video encode read dma v component horizontal pixel count register imgdma1_vdo enc_v_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently horizontal pixel position of a segment (4 lines) of v frame buffer where vdoenc rdma is now at. if its value is c, then it represents vdoenc rdma is now (c-3) th ~ c th pixel data of a segment of v frame buffer. it is a up-counter, and it works at two modes. when rotation is 90 or 270 : it is increased by 4 when vdoenc_v_ycnt counts to vdoenc_ysize[11:1] and 16 bytes data of current position are read out of v frame buffer. when rotation is 0 or 180 : it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdoenc_xsize and 16 bytes data are read out. note: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1030 of 1535 the pixel index is counted from either left or right according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 left right 90 left left 180 right left 270 right right imgdma1+025 ch video encode read dma v component vertical line count register imgdma1_vdo enc_v_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently vertical line position of v frame buffer where vdoenc rdma is at. if its value is c, then it represents vdoenc rdma is now at (c-3) th ~ c th line (a segment) of v frame buffer. it is a up-counter, and it works at two modes. when rotation is 90 or 270 : it is increased by 4 each time 16 bytes data of current position are read out of v frame buffer. and it will be reset to 4 while it counts to vdoenc_ysize[11:1] and 16 bytes data are read out. when rotation is 0 or 180 : it is increased by 4 when vdoenc_v_xcnt counts to vdoenc_xsize[11:1] and 16 bytes data of current position are read out of v frame buffer. note: the line index is counted from either top or bottom according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 top top 90 bottom top 180 bottom bottom 270 top bottom note: vdoenc rdma accept a start pulse from vdoenc wdma (vdoenc_v_xcnt, vdoenc_v_ycnt) = (4 , 4); vdoenc rdma finishes when rotation is 90 or 270 : (vdoenc_v_xcnt, vdoenc_v_ycnt) = (vdoenc_xsize[11:1] + 4 , 4); when rotation is 0 or 180 : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1031 of 1535 (vdoenc_v_xcnt, vdoenc_v_ycnt) = (4 , vdoenc_ysize[11:1] + 4); imgdma1+026 0h video encode read dma dropped frame count register imgdma1_vdo enc_drop_fc nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vdoenc rdma dropped frame drop counter. when vdoenc wdma finished writing a frame to memory and issued a start pulse to vdoenc rdma, vdoecn rdma would accept or ignore the pulse depending on it is busy or idle now. if it is busy, then vdoenc rdma will ignore the pulse and the dropped frame counter will be increased by 1. note: the counter will be reset when vdoenc_str is set to 0. imgdma+0270 h video encode dma line buffer base address register imgdma1_vdo enc_lb_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of line buffer of video frame. the purpose of using line buffers is to convert scan-line data into 4x4 block data before writing data into frame buffer. it should align at 8x address , or vdoenc dma will read wrong data. besides, it should be set in the internal memory to get better performance. note: notice that vdoenc dma is inside graph2sys, so the internal memory address would be better ranging from 0x4002_0000 to 0x4004_3fff than from 0x4000_0000 to 0x4001_7fff. imgdma+0274 h video encode dma line buffer length register imgdma1_vdo enc_lb_ylen bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1032 of 1535 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lb_ylen type r/w lb_ylen: line buffer length of vdoenc dma line buffer write engine. it must be 4x . the line buffer size is calculated as followed. line buffer size = vdoenc_xsize * lb_ylen * 2 bytes imgdma+0278 h video encode dma line buffer write engine horizontal pixel count register imgdma11_vd oenc_lb_wr_ xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: horizontal pixel count of input image. it is a 12-bit up counter. if the value is c, then it represents vdoenc dma now writes (c-3) th ~ c th pixel into line buffer. while it counts to vdoenc_xsize[11:2] and the write- line-buffer command is finished, it will be reset to 4. imgdma+027 ch video encode dma line buffer write engine vertical line count register imgdma1_vdo enc_lb_wr_y cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: vertical line count of input image. it is a 12-bit up counter. if the value is c, then it represents vdoenc dma is now at (c-3) th ~ c th line of input image. while vdoecn_lb_wr_xcnt will be reset to 4, this counter will increase 1 at the same time. note: vdoenc dma starts: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1033 of 1535 (vdoenc_lb_wr_xcnt, vdoenc_lb_wr_xcnt) = (4, 1) vdoenc dma finishes: (vdoenc_lb_wr_xcnt, vdoenc_lb_wr_xcnt) = (4, vdoenc_ysize + 1) imgdma1+028 0h video decode dma start register imgdma1_vdo dec_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of vdodec dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for vdodec dma. 0: stop vdodec dma 1: activate vdodec dma imgdma1+028 4h video decode dma control register imgdma1_vdo dec_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name scan mode flip rotation it type r/w r/w r/w r/w reset 0 0 0 0 it: interrupt enabling. interrupt of vdodec dma issues when all the data transmission of an mp4 frame are done. 0: disable 1: enable rot: rotation direction related to source frame buffer. vdodec dma must co-work with irt0 dma to execute the function. 00: no rotation 01: 90 rotation 10: 180 rotation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1034 of 1535 11: 270 rotation flip: flipping option related to source frame buffer. vdodec dma must co-work with irt0 dma to execute the function. 0: no flip 1: flipped after rotation scan mode: to indicate vdodec dma the frame buffer is scan-line based or 4x4 block based. if vdodec dma is in scan line mode, no rotation or flip function are valid. and it will transmit pixel data to irt0 multiple output 1 instead transmit 4x4 block data to irt0 dma. 0: 4x4 block based 1: scan-line based imgdma1+029 0h video decode dma y base address register imgdma1_vdo dec_y_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the y component of source frame buffer. it should align at 8x address , or vdodec dma will read vdodec dm a irt0 irt0 multiple output 1 4x4 block prz imgdma0 yuv444 yuv444 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1035 of 1535 wrong data. imgdma1+029 4h video decode dma u base address register imgdma1_vdo dec_u_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the u component of source frame buffer. it should align at 8x address , or vdodec dma will read wrong data. imgdma1+029 8h video decode dma v base address register imgdma1_vdo dec_v_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of the v component of source frame buffer. it should align at 8x address , or vdodec dma will read wrong data. imgdma1+02 a0h video decode dma horizontal size register of source image imgdma1_vdo dec_xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source image. if the value is x, then it represents the source is an x-pixel wide image. note that the horizontal size of the source image must be 16x . imgdma1+02 a4h video decode dma vertical size register of source image imgdma1_vdo dec_ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1036 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source image. if the value is y, then it represents the source is a y-line high image. note that the vertical size of the source image must be 16x . imgdma1+02 a8h video decode dma pixel number register of source image imgdma1_vdo dec_pxlnum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name num type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name num type r/w num: pixel number of the source image. if its value is n, then it represents the source is an n-pixel image. note pixel number of the frame is equal to vdodec_xsize * vdodec_ysize . imgdma1+02 b0h video decode dma y component horizontal pixel count register imgdma1_vdo dec_y_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently horizontal pixel position of a segment (4 lines) of y frame buffer where vdodec dma is now at. if its value is c, then it represents vdodec dma is now at (c-3) th ~ c th pixel data of a segment of y frame buffer. it is a up-counter, and it works at three modes. under scan-line mode: it is increased by 16 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 16 while it counts to vdodec_xsize and 16 bytes data are read out. under 4x4 block mode & rotation is 90 or 270 : it is increased by 4 when vdodec_y_ycnt counts to vdodec_ysize and 16 bytes data of current position are read out of y frame buffer. under 4x4 block mode & rotation is 0 or 180 : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1037 of 1535 it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdodec_xsize and 16 bytes data are read out. note: when under scan-line mode, the pixel index is always counted from left. when under 4x4 block mode, the pixel index is counted from either left or right according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 left right 90 left left 180 right left 270 right right imgdma1+02 b4h video decode dma y component vertical line count register imgdma1_vdo dec_y_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently vertical line position of y frame buffer where vdodec dma is now at. if its value is c, then it represents vdodec dma is now at (c-3) th ~ c th line (a segment) of y frame buffer. it is a up-counter, and it works at three modes. under scan-line mode it is increased by 1 each time vdodec_y_xcnt count to vdodec_xsize and 16 bytes data of current position are read out of y frame buffer. under 4x4 block mode & rotation is 90 or 270 : it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdodec_ysize and 16 bytes data are read out. under 4x4 block mode & rotation is 0 or 180 : it is increased by 4 when vdodec_y_xcnt counts to vdodec_xsize and 16 bytes data of current position are read out of y frame buffer. note: when under scan-line mode, the line index is always counted from top. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1038 of 1535 when under 4x4 block mode, the line index is counted from either top or bottom according to the setting of rotation and flip bits in vdoenc_con. flip rotation 0 1 0 top top 90 bottom top 180 bottom bottom 270 top bottom note: vdodec dma starts under scan-line mode (vdodec_y_xcnt, vdodec_y_ycnt) = (16 , 1); under 4x4 block mode (vdoenc_y_xcnt, vdoenc_y_ycnt) = (4 , 4); vdodec dma finishes under scan-line mode: (vdodec_y_xcnt, vdodec_y_ycnt) = (16 , vdodec_ysize + 1); under 4x4 block mode & rotation is 90 or 270 : (vdodec_y_xcnt, vdodec_y_ycnt) = (vdodec_xsize + 4 , 4); under 4x4 block mode & rotation is 0 or 180 : (vdodec_y_xcnt, vdodec_y_ycnt) = (4 , vdodec_ysize + 4); imgdma1+02 b8h video decode dma v component horizontal pixel count register imgdma1_vdo dec_v_xcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently horizontal pixel position of a segment (4 lines) of v frame buffer where vdodec dma is now at. if its value is c, then it represents vdodec dma is now (c-3) th ~ c th pixel data of a segment of v frame buffer. it is a up-counter, but it is always 0 under scan-line mode. under 4x4 block mode, it works at two modes. when rotation is 90 or 270 : it is increased by 4 when vdoenc_v_ycnt counts to vdoenc_ysize[11:1] and 16 bytes data of current position are read out of v frame buffer. when rotation is 0 or 180 : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1039 of 1535 it is increased by 4 each time 16 bytes data of current position are read out of y frame buffer. and it will be reset to 4 while it counts to vdoenc_xsize and 16 bytes data are read out. note: the pixel index is counted from either left or right according to the setting of rotation and flip bits in vdodec_con. flip rotation 0 1 0 left right 90 left left 180 right left 270 right right imgdma1+02 bch v ideo decode dma v component vertical line count register imgdma1_vdo dec_v_ycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: show the currently vertical line position of v frame buffer where vdodec dma is at. if its value is c, then it represents vdodec dma is now at (c-3) th ~ c th line (a segment) of v frame buffer. it is a up-counter, but it is always 0 under scan-line mode. under 4x4 block mode, it works at two modes. when rotation is 90 or 270 : it is increased by 4 each time 16 bytes data of current position are read out of v frame buffer. and it will be reset to 4 while it counts to vdodec_ysize[9:1] and 16 bytes data are read out. when rotation is 0 or 180 : it is increased by 4 when vdodec_v_xcnt counts to vdodec_xsize[9:1] and 16 bytes data of current position are read out of v frame buffer. note: the line index is counted from either top or bottom according to the setting of rotation and flip bits in vdodec_con. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1040 of 1535 flip rotation 0 1 0 top top 90 bottom top 180 bottom bottom 270 top bottom note: vdodec dma starts ( 4x4 block mode): (vdodec_v_xcnt, vdodec_v_ycnt) = (4 , 4); vdodec dma finishes (4x4 block mode) when rotation is 90 or 270 : (vdodec_v_xcnt, vdodec_v_ycnt) = (vdoenc_xsize[9:1] + 4 , 4); when rotation is 0 or 180 : (vdodec_v_xcnt, vdodec_v_ycnt) = (4 , vdoenc_ysize[9:1] + 4); imgdma1+078 0h overlay dma multiple output engine 1 start register imgdma1_ovl _mo_1_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of ovl multiple output 1. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for ovl multiple output 1 0: stop ovl multiple output 1 1: activate ovl multiple output 1 note: ovl multiple output module is used to transmit ovl dma output pixel data to multiple destinations simultaneously, including jpeg dma, vdoenc wdma, prz, drz, and y2r0. due to its destination located at graphsys1 and graphsys2 respectively, in order to transmit pixel data to different destinations located at different graphsys, ovl multiple output has been divided into ovl multiple output 0 and ovl multiple output 1 to support multiple output function. the starting sequence of ovl dma, ovl multiple output 0 and ovl multiple output 1 should be as followed . ovl multiple output 1 started ? ovl multiple output 0 started ? ovl dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1041 of 1535 if ovl dma is allowed to transmit pixel data before ovl multiple output 0/1 are started, it would lose some pixels. imgdma1+078 4h overlay dma multiple output engine 1 control register imgdma1_ovl _mo_1_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prz vdoe nc dma jpeg dma type r/w r/w r/w reset 0 0 0 jpeg dma: enable output to jpeg dma. 0: disable 1: enable vdoenc dma: enable output to vdoenc dma. 0: disable 1: enable prz: enable output to prz. 0: disable 1: enable imgdma1+078 8h overlay dma multiple output engine 1 busy status imgdma1_ovl _mo_1_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prz busy vdoe nc dma busy jpeg dma busy type ro ro ro the busy bits are used to show if ovl multiple output 1 transmits data to destination or not. if there are two or more output path are enabled and only some busy bit stays at 1, then the ovl multiple output 1 may be stalled by the path. jpeg dma busy: 0: no data transmit to jpeg dma now. 1: data are transmitted to jpeg dma 1 now. vdoenc dma busy: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1042 of 1535 0: no data transmit to vdoenc dma now. 1: data are transmitted to vdoenc dma now. prz busy: 0: no data transmit to prz now. 1: data are transmitted to prz now. imgdma1+0c 00h image rotator 0 dma start register imgdma1_irt0 _str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of irt0 dma. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for irt0 dma. 0: stop irt0 dma 1: activate irt0 dma imgdma1+0c 04h image rotator 0 dma control register imgdma1_irt0 _con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flip rot srcs el auto rstr it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 it: irt0 done interrupt enable. interrupt issues when all data are transmitted to irt0 multiple output 1. for auto-restart mode, interrupt issues at every restart. 0: disable 1: enable auto rstr: automatic restart. irt0 dma automatically restarts while current frame is finished. 0: disable 1: enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1043 of 1535 srcsel: select source of irt0 dma. 0: vdoenc rdma 1: vdodec dma. vdodec dma could transmit data to irt0 dma if and only if it works under 4x4 block mode. rot: rotation direction related to source frame buffer of vdoenc rdma or vdodec dma. 00: no rotation 01: 90 rotation 10: 180 rotation 11: 270 rotation flip: flip option related to source frame buffer of vdoenc rdma or vdodec dma. 0: no flip 1: flipped after rotation note: irt0 dma must co-work with vdoenc rdma or vdodec dma to achieve rotation and/or flip function. therefore the rotation/flip setting of irt0 dma & vdoenc rdma/vdodec dma must be the same. imgdma1+0c 10h image rotator 0 dma base address register of line buffer imgdma1_irt0 _fifo_base bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr: base address of irt0 line buffer. the purpose of using line buffers is to convert 4x4 block based data into scan-line data before writing data to irt0 multiple output 1. it should align at 8x address , or irt0 dma will read/write wrong data. besides, it should be set in the internal memory to get better performance. notice that irt0 dma is inside graph2sys, so the internal memory address would be better ranging from 0x4002_0000 to 0x4004_3fff than from 0x4000_0000 to 0x4001_7fff. imgdma1+0c 14h image rotator 0 dma fifo length register imgdma1_irt0 _fifoylen bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1044 of 1535 name fifolen type r/w fifolen: irt0 dma fifo length. fifolen must be the multiple of 8. recommended values are at least 16 to support double buffer. note: the fifo size is determined by four parameter, irt0_xsize, irt0_ysize, irt0_fifolen, and rotation set in irt0_con. when rotation is 90 or 270 : fifo size = irt0_ysize * irt0_fifolen * 1.5; when rotation is 0 or 180 : fifo size = irt0_xsize * irt0_fifolen * 1.5; imgdma1+0c 20h image rotator 0 dma horizo ntal size register of source image imgdma1_irt0 _xsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xsize type r/w xsize: horizontal size of the source image. if the value is x, then it represents the source is an x-pixel wide image. note that the horizontal size of the source image must be 16x . imgdma1+0c 24h image rotator 0 dma vertical size register of source image imgdma1_irt0 _ysize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ysize type r/w ysize: vertical size of the source image. if the value is y, then it represents the source is a y-line high image. note that the vertical size of the source image must be 16x . imgdma1+0c 30h image rotator 0 dma write pointer imgdma1_irt0 _wrptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wrptr[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1045 of 1535 type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrptr[15:0] type ro wrptr: write pointer to display current writing address. imgdma1+0c 40h image rotator 0 dma read pointer imgdma1_irt0 _rdptr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rdptr[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rdptr[15:0] type ro rdptr: read pointer to display current reading address. imgdma1+0c 44h image rotator 0 dma read horizontal pixel count register of output image imgdma1_irt0 _rdxcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display the currently horizontal position of a line of y component. it is a 12-bits up counter. if its value is c, it represents irt0 dma now reads (c-7) th ~ c th pixel data of a line of y component. if all pixel data of a line are read out, then the counter will be reset to its initial value. note: when rotation is 90 or 270 : it is increased by 8 each time 8 bytes data of current position are read out of y frame buffer. and it will be reset to 8 while it counts to irt0_ysize and 8 bytes data are read out. when rotation is 0 or 180 : it is increased by 8 each time 8 bytes data of current position are read out of y frame buffer. and it will be reset to 8 while it counts to irt0_xsize and 8 bytes data are read out. imgdma1+0c 48h image rotator 0 dma read vertical line count register of output image imgdma1_irt0 _rdycnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1046 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display the currently vertical position of y component. it is a 12-bits up counter. if its value is c, it represents irt0 dma is now at c th line of y component. if all pixel data of a line are read out, the counter will be increased by 1. note: irt0 dma starts (irt0_rdxcnt, irt0_rdycnt) = (8, 1) irt0 dma finishes when rotation is 90 or 270 , (irt0_rdxcnt, irt0_rdycnt) = (8, irt0_xsize + 1) when rotation is 0 or 180 , (irt0_rdxcnt, irt0_rdycnt) = (8, irt0_ysize + 1) imgdma1+0c 50h image rotator 0 dma fifo line count register imgdma1_irt0 _fifocnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name count type ro count: display how many lines are stored in fifo now. it could count up or count down. count up: because the data written into fifo are 4x4 block, irt0 dma will increase the counter 4 after it finishes writing 4 line y component. therefore if its value is c, it represents there are c lines data in the fifo now. count down: irt0 dma will decrease the counter 4 while it reads out 4 line y component. imgdma1+0c 54h image rotator 0 dma fifo write line index register imgdma1_irt0 _wryidx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yidx type ro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1047 of 1535 yidx: display which fifo line irt0 dma is now writing. because irt0 receives 4x4 block data, if its value is y, then irt0 dma is now writing (y-3) th ~ y th fifo line. it will increase 4 while 4 line y component are written into fifo completely. when its value is equal to irt0_fifoylen (at the bottom of the fifo) and current 4 line data are written into fifo completed, it will be reset to 4 to acknowledge irt0 dma to write to top of the fifo again. . imgdma1+0c 58h image rotator 0 dma fifo read line index register imgdma1_irt0 _rdyidx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yidx type ro yidx: display which fifo line irt0 dma is now reading. if its value is y, then irt0 dma is now reading y th fifo line. when its value is equal to irt0_fifoylen (at the bottom of the fifo segment) and current line data are read out, it will be reset to 1 to acknowledge irt0 dma to read from top of the fifo again. imgdma1+0c 80h image rotator 0 dma multiple output engine 1 start register imgdma1_irt0 _mo_1_str bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name str type r/w reset 0 this register controls the activity of irt0 multiple output 1. note that before setting str to ?1?, all the configurations should be done by giving proper value. after setting the register, it would generate a starting pulse to set all controlling registers to initial values. str: start control for irt0 multiple output 1 0: stop irt0 multiple output 1 1: activate irt0 multiple output 1 note: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1048 of 1535 irt0 multiple output module is used to transmit output pixel of either irt0 dma or vdodec dma with scan-line mode to multiple destinations simultaneously, including mp4deblk, crz, prz, and ipp1. due to its destination located at graphsys1 and graphsys2 respectively, in order to transmit pixel data to different destinations located at different graphsys, irt0 multiple output has been divided into irt0 multiple output 0 and irt0 multiple output 1 to support multiple output function. the starting sequence of irt0 dma/vdodec dma with scan-line mode, irt0 multiple output 0 and irt0 multiple output 1 should be as followed . irt0 multiple output 0 started ? irt0 multiple output 1 started ? irt0 dma / vdodec dma with scan-line mode if irt0 dma / vdodec dma with scan-line mode is allowed to transmit pixel data before irt0 multiple output 0/1 are started, it would lose some pixels. imgdma1+0c 84h image rotator 0 dma multiple output engine 1 control register imgdma1_irt0 _mo_1_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src mp4d eblk prz imgd ma0 type r/w r/w r/w r/w reset 0 0 0 0 imgdma0: enable output to image dma 0. 0: disable 1: enable prz: enable output to prz. 0: disable 1: enable mp4deblk: enable output to mp4deblk. 0: disable 1: enable src: select input source of irt0 multiple output 1. 0: irt0 dma free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1049 of 1535 1: vdodec scan-line engine imgdma1+0c 88h image rotator 0 dma multiple output engine 1 busy status imgdma1_irt0 _mo_1_busy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4d eblk busy prz busy imgd ma0 busy type ro ro ro the busy bits are used to show if irt0 multiple output 1 transmits data to destination or not. if there are two or more output path are enabled and only some busy bit stays at 1, then the irt0 multiple output 1 may be stalled by the path. imgdma0 busy: 0: no data transmit to image dma 0 now. 1: data are transmitted to image dma 0 now. prz busy: 0: no data transmit to prz now. 1: data are transmitted to prz now. mp4deblk busy: 0: no data transmit to mp4deblk now. 1: data are transmitted to mp4deblk now. 5.16.3 application notes for developing c code this section is for both hardware and software engineers when they develop their c codes. the codes in each following section can be copied into a c file if there are no other considerations. and the behavior of each module would be a little different if the values of #define are modified. 5.16.3.1 image buffer write 1 dma #define ibw1_int 0 // interrupt enabled #define ibw1_succ 1 // auto restart #define ibw1_triple 0 // triple buffers support under auto restart #define ibw1_pitch 0 // pitch function #define ibw1_clip 0 // clip function #define ibw1_lcd 1 // hardware trigger to lcd #define ibw1_dc 0 // direct couple to lcd #define ibw1_format 0 // frame buffer format, 0:rgb565, 1:rgb888, 2:argb8888 #define ibw1_alpha 128 // alpha value when writing argb8888 to memory #define ibw1_src_xsize 100 // horizontal size of source image #define ibw1_src_ysize 100 // vertical size of source image free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1050 of 1535 #define ibw1_clip_l 11 // clip function horizontal starting pixel #define ibw1_clip_r 90 // clip function horizontal ending pixel #define ibw1_clip_t 21 // clip function vertical starting line #define ibw1_clip_b 70 // clip function vertical ending line #define ibw1_base_addr0 0x10100000 // base address of frame buffer 0 #define ibw1_base_addr1 0x10200000 // base address of frame buffer 1 #define ibw1_base_addr2 0x10300000 // base address of frame buffer 2 #define ibw1_bkgd_xsize0 150 // horizontal size of background image 0 #define ibw1_bkgd_xsize1 200 // horizontal size of background image 1 #define ibw1_bkgd_xsize2 250 // horizontal size of background image 2 *imgdma0_ibw1_str = 0x0 ; // ibw1 dma halts *imgdma0_ibw1_con = (ibw1_format<<8) | (ibw1_dc<<7) | (ibw1_lcd<<6) | (ibw1_clip<<5) | (ibw1_pitch<<4) | (ibw1_triple<<2) | (ibw1_succ<<1) | ibw1_int; *imgdma0_ibw1_src_xsize = ibw1_src_xsize; *imgdma0_ibw1_src_ysize = ibw1_src_ysize; *imgdma0_ibw1_base_addr0 = ibw1_base_addr0; if (ibw1_format == 2) *imgdma0_ibw1_alpha = ibw1_alpha; if (ibw1_clip) { *imgdma0_ibw1_cliplr = (ibw1_clip_l<<16) + ibw1_clip_r; *imgdma0_ibw1_cliptb = (ibw1_clip_t<<16) + ibw1_clip_b; } if (ibw1_succ) { *imgdma0_ibw1_base_addr1 = ibw1_base_addr1; if (ibw1_triple) *imgdma0_ibw1_base_addr2 = ibw1_base_addr2; } if (ibw1_pitch) { *imgdma0_ibw1_bkgd_xsize0 = ibw1_bkgd_xsize0; if (ibw1_succ) { *imgdma0_ibw1_bkgd_xsize1 = ibw1_bkgd_xsize1; if (ibw1_triple) *imgdma0_ibw1_bkgd_xsize2 = ibw1_bkgd_xsize2; } } *imgdma0_ibw1_str = 0x1 ; // ibw1 dma starts free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1051 of 1535 5.16.3.2 image buffer write 2 dma #define ibw2_int 0 // interrupt enabled #define ibw2_lcd 0 // hardware trigger to lcd #define ibw2_succ 0 // auto restart #define ibw2_clip 0 // clip function #define ibw2_out_dc 0 // direct couple to lcd #define ibw2_out_irt1 1 // output to irt1 #define ibw2_out_r2y0 0 // output to r2y0 #define ibw2_alpha 128 // alpha value when direct couple to lcd #define ibw2_xsize 100 // horizontal size of source image #define ibw2_ysize 100 // vertical size of source image #define ibw2_clip_l 11 // clip function horizontal starting pixel #define ibw2_clip_r 90 // clip function horizontal ending pixel #define ibw2_clip_t 21 // clip function vertical starting line #define ibw2_clip_b 70 // clip function vertical ending line #define irt1_ultra_high_en 0 // irt1 ultra high enable control #define cam_crz_vsync_en 0 // camera frame synchronous reset signal enable control *imgdma0_ibw2_str = 0x0 ; // ibw2 dma halts *imgdma0_ibw2_con = (ibw2_out_r2y0<<8) | (ibw2_out_irt1<<7) | (ibw2_out_dc<<6) | (ibw2_clip<<3) | (ibw2_succ<<2) | (ibw2_lcd<<1) | ibw2_int | (cam_crz_vsync_en<<5) | (irt1_ultra_high_en<<4); if (ibw2_out_dc) *imgdma0_ibw2_alpha = ibw2_alpha; *imgdma0_ibw2_xsize = ibw2_xsize; *imgdma0_ibw2_ysize = ibw2_ysize; if (ibw2_clip) { *imgdma0_ibw2_cliplr = (ibw2_clip_l<<16) + ibw2_clip_r; *imgdma0_ibw2_cliptb = (ibw2_clip_t<<16) + ibw2_clip_b; } *imgdma0_ibw2_str = 0x1 ; // ibw2 dma starts 5.16.3.3 image buffer read 1 dma #define ibr1_int 0 // interrupt enabled #define ibr1_format 0 // pixel format of input frame buffer. 0:16-bits, 1: 24-bits #define ibr1_order 0 // pixel data order when pixel format is 24- bits. 0: brg, 1: rgb #define ibr1_base 0x10100000 // base address of input frame buffer free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1052 of 1535 #define ibr1_pxlnum 10000 // pixel number of input frame buffer *imgdma0_ibr1_str = 0x0 ; // ibr1 dma halts *imgdma0_ibr1_con = (ibr1_order<<2) | (ibr1_format<<1) | ibr1_int; *imgdma0_ibr1_base = ibr1_base; *imgdma0_ibr1_pxlnum = ibr1_pxlnum; *imgdma0_ibr1_str = 0x1 ; // ibr1 dma starts 5.16.3.4 overlay dma and ovl multiple output #define ovl_mo_1_jpeg_dma 1 // multiple output to jpeg dma #define ovl_mo_1_vdo_dma 1 // multiple output to vdoenc dma #define ovl_mo_1_prz 1 // multiple output to prz #define ovl_mo_0_imgdma1 1 // multiple output to image dma 1 #define ovl_mo_0_y2r0 1 // multiple output to y2r0 #define ovl_mo_0_drz 1 // multiple output to drz #define ovl_enable 0 // overlay function enabled #define ovl_int 0 // interrupt enabled #define ovl_mode 3 // mask data format #define ovl_palen 1 // palette read/write enable #define ovl_psel 1 // pixel engine selection #define ovl_base 0x10100000 // base address of mask #define ovl_color_key 0 // 8-bits color key #define ovl_vratio 2 // vertical scaling ratio #define ovl_hartio 2 // horizontal scaling ratio #define ovl_xsize 100 // vertical size of mask #define ovl_ysize 100 // horizontal size of mask *imgdma1_ovl_mo_1_str = 0x0 ; // ovl mo 1 halts *imgdma0_ovl_mo_0_str = 0x0 ; // ovl mo 0 halts *imgdma1_ovl_mo_1_con = (ovl_mo_1_prz<<2) | (ovl_mo_1_vdo_dma<<1) | ovl_mo_1_jpeg_dma; *imgdma0_ovl_mo_0_con = (ovl_mo_0_drz<<2) | (ovl_mo_0_y2r0<<1) | ovl_mo_0_imgdma1; *imgdma1_ovl_mo_1_str = 0x1 ; // ovl mo 1 starts *imgdma0_ovl_mo_0_str = 0x1 ; // ovl mo 0 starts *imgdma0_ovl_str = 0x0 ; // ovl dma overlay function disable *imgdma0_ovl_con = (ovl_psel<<5); if (ovl_enable) { *imgdma0_ovl_con = *imgdma0_ovl_con | (ovl_palen<<4) | (ovl_mode << 1) | ovl_int; for(int i=0; i<256; i++) // setting palette { *(imgdma0_ovl_pal_base + i) = (24-bits yuv color); free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1053 of 1535 } *imgdma0_ovl_base = ovl_base; *imgdma0_ovl_cfg = (ovl_color_key<<8) | (ovl_vratio<<4) | ovl_hratio; *imgdma0_ovl_xsize = ovl_xsize; *imgdma0_ovl_ysize = ovl_ysize; *imgdma0_ovl_str = 0x1 ; // ovl dma overlay function enable } 5.16.3.5 image rotator 1 / image rotator 3 dma // note the following code could be applied to irt3 dma by replace irt1 with irt3 #define irt1_int 1 // interrupt enabled #define irt1_succ 0 // auto restart #define irt1_triple 0 // triple buffers support under auto restart #define irt1_lcd 1 // hardware trigger to lcd #define irt1_pitch 0 // pitch function #define irt1_rot 0 // rotation, 0: no rotation, 1: 90, 2: 180, 3: 270 #define irt1_flip 0 // flip after rotation #define irt1_format 0 // frame buffer format, 0:rgb565, 1:rgb888, 2:argb8888 #define irt1_alpha 128 // alpha value when writing argb8888 to memory #define irt1_src_xsize 100 // horizontal size of source image #define irt1_src_ysize 100 // vertical size of source image #define irt1_base_addr0 0x10100000 // base address of frame buffer 0 #define irt1_base_addr1 0x10200000 // base address of frame buffer 1 #define irt1_base_addr2 0x10300000 // base address of frame buffer 2 #define irt1_bkgd_xsize0 150 // horizontal size of background image 0 #define irt1_bkgd_xsize1 200 // horizontal size of background image 1 #define irt1_bkgd_xsize2 250 // horizontal size of background image 2 #define irt1_fifo_base 0x40000000 // fifo base address when rotated 90 or 270 *imgdma0_irt1_str = 0x0 ; // irt1 dma halts *imgdma0_irt1_con = (irt1_format<<8) | (irt1_flip<<7) | (irt1_rot<<5) | (irt1_pitch<<4) | (irt1_lcd<<3) | (irt1_triple<<2) | (irt1_succ<<1) | irt1_int; *imgdma0_irt1_src_xsize = irt1_src_xsize; *imgdma0_irt1_src_ysize = irt1_src_ysize; *imgdma0_irt1_base_addr0 = irt1_base_addr0; if (irt1_rot == 1 || irt1_rot == 3) *imgdma0_irt1_fifo_base = irt1_fifo_base; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1054 of 1535 if (irt1_format == 2) *imgdma0_irt1_alpha = irt1_alpha; if (irt1_succ) { *imgdma0_irt1_base_addr1 = irt1_base_addr1; if (irt1_triple) *imgdma0_irt1_base_addr2 = irt1_base_addr2; } if (irt1_pitch) { *imgdma0_irt1_bkgd_xsize0 = irt1_bkgd_xsize0; if (irt1_succ) { *imgdma0_irt1_bkgd_xsize1 = irt1_bkgd_xsize1; if (irt1_triple) *imgdma0_irt1_bkgd_xsize2 = irt1_bkgd_xsize2; } } *imgdma0_irt1_str = 0x1 ; // irt1 dma starts 5.16.3.6 jpeg encoder dma #define jpeg_int 0 // interrupt enabled #define jpeg_mode 0 // working mode. 0: yuv422, 1: gray, 2: yuv420, 3: yuv411 #define jpeg_succ 0 // auto restart #define jpeg_fifo_base 0x40000000 // fifo base address #define jpeg_fifolen 16 // 16 for double buffers #define jpeg_xsize 800 // horizontal size of input image #define jpeg_ysize 640 // vertical size of input image #define cam_crz_vsync_en 0 // camera frame synchronous reset signal enable control *imgdma1_jpeg_str = 0x0 ; // jpeg dma halts *imgdma1_jpeg_con = (jpeg_succ<<3) | (jpeg_mode<<1) | jpeg_int | (cam_crz_vsync_en<<7); *imgdma1_jpeg_fifo_base = jpeg_fifo_base; *imgdma1_jpeg_fifolen = jpeg_fifolen; *imgdma1_jpeg_xsize = jpeg_xsize; *imgdma1_jpeg_ysize = jpeg_ysize; *imgdma1_jpeg_str = 0x1 ; // jpeg dma starts 5.16.3.7 video encode dma #define vdoenc_wr_int 1 // frame buffer write engine interrupt enabled #define vdoenc_w2r 1 // trigger of read engine from write engine free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1055 of 1535 #define vdoenc_succ 1 // auto restart #define vdoenc_rd_int 0 // frame buffer read engine interrupt enabled #define vdoenc_rot 0 // rotation of read engine, 0: no rotation, 1: 90, 2: 180, 3: 270 #define vdoenc_flip 0 // flip after rotation #define vdoenc_xsize 176 // horizontal size of input image #define vdoenc_ysize 144 // vertical size of input image #define vdoenc_pxlnum 25344 // pixel number of input image #define vdoenc_y_base1 0x10000000 // y base address of frame buffer 1 #define vdoenc_u_base1 0x10006300 // u base address of frame buffer 1 #define vdoenc_v_base1 0x10007bc0 // v base address of frame buffer 1 #define vdoenc_y_base2 0x10100000 // y base address of frame buffer 2 #define vdoenc_u_base2 0x10106300 // u base address of frame buffer 2 #define vdoenc_v_base2 0x10107bc0 // v base address of frame buffer 2 #define vdoenc_lb_base 0x40000000 // base address of line buffer #define vdoenc_lb_ylen 8 // 8 for double buffers #define vdoenc_ultra_high_en 0 // 8 for double buffers *imgdma1_vdoenc_str = 0x0 ; // vdoenc dma halts *imgdma1_vdoenc_con = (vdoenc_flip<<6) | (vdoenc_rot<<4) | (vdoenc_rd_int<<3) | (vdoenc_succ<<2) | (vdoenc_w2r<<1) | vdoenc_wr_int | (vdoenc_ultra_high_en<<7); *imgdma1_vdoenc_y_base1 = vdoenc_y_base1; *imgdma1_vdoenc_u_base1 = vdoenc_u_base1; *imgdma1_vdoenc_v_base1 = vdoenc_v_base1; if (vdoenc_succ) { *imgdma1_vdoenc_y_base2 = vdoenc_y_base2; *imgdma1_vdoenc_u_base2 = vdoenc_u_base2; *imgdma1_vdoenc_v_base2 = vdoenc_v_base2; } *imgdma1_vdoenc_xsize = vdoenc_xsize; *imgdma1_vdoenc_ysize = vdoenc_ysize; *imgdma1_vdoenc_pxlnum = vdoenc_pxlnum; *imgdma1_vdoenc_lb_base = vdoenc_lb_base; *imgdma1_vdoenc_lb_ylen = vdoenc_lb_ylen; *imgdma1_vdoenc_str = 0x1 ; // vdoenc dma starts 5.16.3.8 video decode dma #define vdodec_int 0 // interrupt enabled #define vdodec_rot 0 // rotation of read engine, 0: no rotation, 1: 90, 2: 180, 3: 270 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1056 of 1535 #define vdodec_flip 0 // flip after rotation #define vdodec_scan_mode 0 // frame buffer mode selection, 0: 4x4 block, 1: scan line #define vdodec_xsize 176 // horizontal size of input image #define vdodec_ysize 144 // vertical size of input image #define vdodec_pxlnum 25344 // pixel number of input image #define vdodec_y_base 0x10000000 // y base address of frame buffer #define vdodec_u_base 0x10006300 // u base address of frame buffer #define vdodec_v_base 0x10007bc0 // v base address of frame buffer *imgdma1_vdodec_str = 0x0 ; // vdodec dma halts *imgdma1_vdodec_con = (vdodec_scan_mode<<7) | (vdodec_flip<<6) | (vdodec_rot<<4) | vdodec_int; *imgdma1_vdodec_y_base = vdodec_y_base; *imgdma1_vdodec_u_base = vdodec_u_base; *imgdma1_vdodec_v_base = vdodec_v_base; *imgdma1_vdodec_xsize = vdodec_xsize; *imgdma1_vdodec_ysize = vdodec_ysize; *imgdma1_vdodec_pxlnum = vdodec_pxlnum; *imgdma1_vdodec_str = 0x1 ; // vdodec dma starts 5.16.3.9 image rotator 0 dma and irt0 multiple output #define irt0_mo_0_crz 0 // multiple output to crz #define irt0_mo_0_ipp1 0 // multiple output to ipp1 #define irt0_mo_1_src 0 // source selection, 0: irt0 dma, 1: vdodec scan engine #define irt0_mo_1_mp4deblk 0 // multiple output to mp4deblk #define irt0_mo_1_prz 1 // multiple output to prz #define irt0_mo_1_imgdma0 0 // multiple output to image dma 0 #define irt0_int 0 // interrupt enabled #define irt0_succ 0 // auto restart #define irt0_src 0 // source selection, 0: vdoenc rdma, 1: vdodec dma #define irt0_rot 0 // rotation of read engine, 0: no rotation, 1: 90, 2: 180, 3: 270 #define irt0_flip 0 // flip after rotation #define irt0_fifo_base 0x40000000 // fifo base address #define irt0_fifoylen 16 // 16 for double buffers #define irt0_xsize 176 // horizontal size of video frame buffer #define irt0_ysize 144 // vertical size of video frame buffer *imgdma0_irt0_mo_0_str = 0x0 ; // irt0 mo 0 halts *imgdma1_irt0_mo_1_str = 0x0 ; // irt0 mo 1 halts *imgdma0_irt0_mo_0_con = (irt0_mo_0_ipp1<<1) | irt0_mo_0_crz; *imgdma1_irt0_mo_1_con = (irt0_mo_1_src<<8) | (irt0_mo_1_mp4deblk<<2) | free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1057 of 1535 (irt0_mo_1_prz<<1) | irt0_mo_1_imgdma0; *imgdma0_irt0_mo_0_str = 0x1 ; // irt0 mo 0 starts *imgdma1_irt0_mo_1_str = 0x1 ; // irt0 mo 1 starts if (vdodec_scan_mode == 0) // definition of vdodec_scan_mode, refer to previous section { *imgdma1_irt0_str = 0x0 ; // irt0 dma halts *imgdma1_irt0_con = (irt0_flip<<6) | (irt0_rot<<4) | (irt0_src<<2) | (irt0_succ<<1) | irt0_int; *imgdma1_irt0_fifo_base = irt0_fifo_base; *imgdma1_irt0_fifoylen = irt0_fifoylen; *imgdma1_irt0_xsize = irt0_xsize; *imgdma1_irt0_ysize = irt0_ysize; *imgdma1_irt0_str = 0x1 ; // irt0 dma starts } 5.16.4 a quick guideline for driver developer from tk6516 to MT6516 in MT6516, most modules are inherited from tk6516. therefore, most register settings are same between the two version. here we point out the differences when immigrating driver from tk6516 to MT6516. 5.16.4.1 global view there are two extreme modifications when immigrating from tk6516 to MT6516. 1. the first is image dma is divided into image dma 0 and image dma 1 . in image dma 1, it contains video and jpeg related modules, including vdoenc dma, vdodec dma, irt0 dma, and jpeg dma. the remaining modules are placed in image dma 0. due to the modification, the prefix of each register has been modified from imgdma_ to either imgdma0_ or imgdma1_. 2. the second extreme modification is ibr2 and irt2 dma have been removed from image dma in MT6516 . all the settings to these two modules are invalid now. besides, the address setting of each sub-module should be changed from 4x to 8x address, except base address of irt1 and irt3 . the detail address limit could refer to register definitions in the previous section. 5.16.4.2 local view the modifications of registers of each sub-module are described as follows. 5.16.4.2.1 ibw1 dma register removed: imgdma_ibw1_dpitch1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1058 of 1535 imgdma_ibw1_dpitch2 register added: imgdma0_ibw1_base_addr2 ? base address of the third frame buffer imgdma0_ibw1_bkgd_xsize0 ? horizontal size of the first background image imgdma0_ibw1_bkgd_xsize1 ? horizontal size of the second background image imgdma0_ibw1_bkgd_xsize2 ? horizontal size of the third background image register modified: imgdma_ibw1_bsaddr1 ? imgdma0_ibw1_baes_addr0 imgdma_ibw1_bsaddr2 ? imgdma0_ibw1_baes_addr1 imgdma_ibw1_hsize (set n-1) ? imgdma0_ibw1_src_xsize (set n) imgdma_ibw1_vsize (set n-1) ? imgdma0_ibw1_src_ysize (set n) imgdma_ibw1_cliplr (set n-1) ? imgdma0_ibw1_clip_lr (set n) imgdma_ibw1_cliptb (set n-1) ? imgdma0_ibw1_clip_tb (set n) imgdma_ibw1_con ? imgmda0_ibw1_con MT6516 imgdma0_ibw1_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fmt dc lcd clip pitch tripl e auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 tk6516 imgdma_ibw1_con name fmt clip dc auto rstr lcd pitch it type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 5.16.4.2.2 ibw2 dma register modified: imgdma_ibw2_hsize (set n-1) ? imgdma0_ibw2_xsize (set n) imgdma_ibw2_vsize (set n-1) ? imgdma0_ibw2_ysize (set n) imgdma_ibw2_cliplr (set n-1) ? imgdma0_ibw2_clip_lr (set n) imgdma_ibw2_cliptb (set n-1) ? imgdma0_ibw2_clip_tb (set n) imgdma_ibw2_con ? imgdma0_ibw2_con MT6516 imgdma0_ibw2_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r2y0 irt1 dc cam_ crz_v sync_ en irt1_ ultra _high _en clip auto rstr lcd it type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 tk6516 imgdma_ibw2_con name irt1 dc clip auto rstr lcd it free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1059 of 1535 type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 5.16.4.2.3 image buffer read 1 dma register modified: imgdma_ibr1_pxlnum (set n-1) ? imgdma0_ibr1_pxlnum (set n) 5.16.4.2.4 ovl dma and ovl multiple output register added: imgdma0_ovl_mo_0_str imgdma0_ovl_mo_0_con imgdma1_ovl_mo_1_str imgdma1_ovl_mo_1_con register modified: imgdma_ovl_bsaddr ? imgdma0_olv_base imgdma_ovl_hsize ? imgdma0_ovl_xsize imgdma_ovl_vsize ? imgdma0_ovl_ysize imgdma_ovl_con ? imgdma0_ovl_con MT6516 imgdma0_ovl_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name psel palen mode 1 mode 0 it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 tk6516 imgdma_ovl_con name prz drz y2r0 jpeg vdoe nc psel palen auto rstr mode 1 mode 0 it type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 5.16.4.2.5 irt1 / irt3 dma register removed: imgdma_irt1_line_dpitch1 imgdma_irt1_line_dpitch2 imgdma_irt1_frm_dpitch1 im gdma_irt1_frm_dpitch2 imgdma_irt1_fifoylen register added: imgdma0_irt1_base_addr2 ? base address of the third frame buffer imgdma0_irt1_bkgd_xsize0 ? horizontal size of the first background image imgdma0_irt1_bkgd_xsize1 ? horizontal size of the second background image imgdma0_irt1_bkgd_xsize2 ? horizontal size of the third background image register modified: imgdma_irt1_bsaddr1 ? imgdma0_irt1_baes_addr0 imgdma_irt1_bsaddr2 ? imgdma0_irt1_baes_addr1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1060 of 1535 imgdma_irt1_hsize (set n-1) ? imgdma0_irt1_src_xsize (set n) imgdma_irt1_vsize (set n-1) ? imgdma0_irt1_src_ysize (set n) imgdma_irt1_con ? imgmda0_irt1_con MT6516 imgdma0_irt1_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buffe r doub le fmt flip rot pitch lcd tripl e auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 tk6516 imgdma_irt1_con name lcd pitch out fmt flip rot auto rstr it type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 5.16.4.2.6 jpeg dma register modified: imgdma_jpeg_bsaddr ? imgmda1_jpeg_fifo_base imgdma_jpeg_hsize (set n-1) ? imgdma1_jpeg_xsize (set n) imgmda_jpeg_vsize (set n-1) ? imgdma1_jpeg_ysize (set n) 5.16.4.2.7 vdoenc dma register added: imgdma1_vdoenc_lb_base imgdma1_vdoenc_lb_ylen register modified: imgdma_vdoenc_hsize ? imgdma1_vdoenc_xsize imgdma_vdoenc_vsize ? imgdma1_vdoenc_ysize imgdma_vdoenc_con ? imgdma1_vdoenc_con MT6516 imgdma1_vdoenc_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdon ec_ul tra_h igh_e n flip rot rd it auto rstr w2r wr it type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 tk6516 imgdma_vdoenc_con name byps flip rot rd it auto rstr w2r wr it type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1061 of 1535 5.16.4.2.8 vdodec dma register modified: imgdma_vdodec_hsize ? imgdma1_vdodec_xsize imgdma_vdodec_vsize ? imgdma1_vdodec_ysize imgdma_vdodec_con ? imgdma1_vdodec_con MT6516 imgdma1_vdodec_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name scan mode flip rotation it type r/w r/w r/w r/w reset 0 0 0 0 tk6516 imgdma_vdodec_con name byps flip rotation h264 done it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 5.16.4.2.9 irt0 dma and irt0 multiple output register removed: imgdma_irt0_pxlnum register added: imgdma0_irt0_mo_0_str imgdma0_irt0_mo_0_con imgdma1_irt0_mo_1_str imgdma1_irt0_mo_1_con register modified: imgdma_irt0_base ? imgdma1_irt0_fifo_base imgdma_irt0_hsize ? imgdma1_irt0_xsize imgdma_irt0_vsize ? imgdma1_irt0_ysize imgdma_irt0_con ? imgdma1_irt0_con MT6516 imgdma1_irt0_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flip rot srcs el auto rstr it type r/w r/w r/w r/w r/w reset 0 0 0 0 0 tk6516 imgdma_irt0_con name mp4d eblk ipp1 prz crz byps flip rot h264 psel auto rstr it type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1062 of 1535 5.17 image processor the image processing processor consists of the three functional blocks shown in figure 137. the first functional block consists of ipp1, y2r0, and ipp2. the second one consists of r2y0, and the last one consists of y2r1. for each functional block, only one input source can be active, and only one output destination can be active, too. the input of the ipp1 can be only in yuv format. the input of the r2y0, of course, can be only in rgb format. the input of the y2r1 can be only in yuv format. hue adj. input buffer bright/contrast adj. colorize/ saturation adj. yuv dithering yuv to rgb color adj. gamma correct rgb ditherin g color replace output buffer input buffer yuv dithering yuv to rgb rgb ditherin g color replace output buffer ipp_a ipp_b input buffer yuv to rgb output buffer ipp_c ipp registers apb interface crz prz mp4deblk irt0 ovl irt2 ibr1 crz prz drz y u/v ovl ibw2 crz prz ibw1 ibw2 ibr1 hue adj. input buffer bright/contrast adj. colorize/ saturation adj. yuv dithering yuv to rgb color adj. gamma correct rgb ditherin g color replace output buffer input buffer yuv dithering yuv to rgb rgb ditherin g color replace output buffer ipp_a ipp_b input buffer yuv to rgb output buffer ipp_c ipp registers apb interface crz prz mp4deblk irt0 ovl irt2 ibr1 crz prz drz y u/v ovl ibw2 crz prz ibw1 ibw2 ibr1 figure 137: image processing processor (ipp) block diagram. 5.17.1 register definitions register address register function acronym img+0000h imgproc ipp configuration register imgproc_ipp_cfg img+0004h imgproc r2y0 configuration register imgproc_r2y0_cfg img+0008h imgproc y2r1 configuration register imgproc_y2r1_cfg img+000ch ipp sdt control register imgproc_ipp_sdtcon img+0010h y2r1 sdt control register imgproc_y2r1_sdtcon img+0100h hue adjustment coefficient c11 imgproc_hue11 img+0104h hue adjustment coefficient c12 imgproc_hue12 img+0108h hue adjustment coefficient c21 imgproc_hue21 img+010ch hue adjustment coefficient c22 imgproc_hue22 img+0110h saturation adjustment coefficient imgproc_sat img+0120h brightness adjustment coefficient b1 imgproc_briadj1 img+0124h brightness adjustment coefficient b2 imgproc_briadj2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1063 of 1535 img+0128h contrast adjustment coefficient imgproc_conadj img+0130h colorize effect coefficient imgproc_colorizeu img+0134h colorize effect coefficient imgproc_colorizev img+0170h gamma correction offset for segment 0 imgproc_gamma_off0 img+0174h gamma correction offset for segment 1 imgproc_gamma_off1 img+0178h gamma correction offset for segment 2 imgproc_gamma_off2 img+017ch gamma correction offset for segment 3 imgproc_gamma_off3 img+0180h gamma correction offset for segment 4 imgproc_gamma_off4 img+0184h gamma correction offset for segment 5 imgproc_gamma_off5 img+0188h gamma correction offset for segment 6 imgproc_gamma_off6 img+018ch gamma correction offset for segment 7 imgproc_gamma_off7 img+0190h gamma correction slope for segment 0 imgproc_gamma_slp0 img+0194h gamma correction slope for segment 1 imgproc_gamma_slp1 img+0198h gamma correction slope for segment 2 imgproc_gamma_slp2 img+019ch gamma correction slope for segment 3 imgproc_gamma_slp3 img+01a0h gamma correction slope for segment 4 imgproc_gamma_slp4 img+01a4h gamma correction slope for segment 5 imgproc_gamma_slp5 img+01a8h gamma correction slope for segment 6 imgproc_gamma_slp6 img+01ach gamma correction slope for segment 7 imgproc_gamma_slp7 img+01b0h gamma correction control register imgproc_gamma_con img+0200h color adjustment offset x for red segment 1 imgproc_color1r_offx img+0204h color adjustment offset x for red segment 2 imgproc_color2r_offx img+0208h color adjustment offset x for green segment 1 imgproc_color1g_offx img+020ch color adjustment offset x for green segment 2 imgproc_color2g_offx img+0210h color adjustment offset x for blue segment 1 imgproc_color1b_offx img+0214h color adjustment offset x for blue segment 2 imgproc_color2b_offx img+0220h color adjustment offset y for red segment 1 imgproc_color1r_offy img+0224h color adjustment offset y for red segment 2 imgproc_color2r_offy img+0228h color adjustment offset y for green segment 1 imgproc_color1g_offy img+022ch color adjustment offset y for green segment 2 imgproc_color2g_offy img+0230h color adjustment offset y for blue segment 1 imgproc_color1b_offy img+0234h color adjustment offset y for blue segment 2 imgproc_color2b_offy img+0240h color adjustment slope for red segment 0 imgproc_color1g_slp img+0244h color adjustment slope for red segment 1 imgproc_color1g_slp img+0248h color adjustment slope for red segment 2 imgproc_color2g_slp img+0250h color adjustment slope for red segment 0 imgproc_color1g_slp img+0254h color adjustment slope for red segment 1 imgproc_color1g_slp img+0258h color adjustment slope for red segment 2 imgproc_color2g_slp free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1064 of 1535 img+0260h color adjustment slope for red segment 0 imgproc_color1g_slp img+0264h color adjustment slope for red segment 1 imgproc_color1g_slp img+0268h color adjustment slope for red segment 2 imgproc_color2g_slp img+0318h input source and output destination selection imgproc_io_mux img+0320h image engine process enable imgproc_en img+0324h ipp rgb value detect imgproc_ipp_rgb_detect img+0328h ipp rgb value replace imgproc_ipp_rgb_replace img+032ch y2r1 rgb value detect imgproc_y2r1_rgb_detect img+0330h y2r1 rgb value replace imgproc_y2r1_rgb_replace table 108 image engine registers img+0000h imgproc ipp configuration register imgproc_ipp_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ipp_rg b_det ect_e n sdt1_ en inv_en gamm a_en clradj _en roun d_y2 r0 y2r0_ en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sdt0_e n clriz e_en sat_e n hue_en cb_en type r/w r/w r/w r/w r/w reset 0 0 0 0 0 ipp_rgb_detect_en: the enable bit of the ?rgb detect and replace? process sdt1_en: the enable bit of spatial dithering process for sdt1 (rgb domain) inv_en : the enable bit of color inversion gamma_en : the enable bit of gamma correction clradj_en : the enable bit of color adjustment round_y2r0 : the rounding control bit of yuv2rgb process y2r0_en : the enable bit of yuv2rgb conversion sdt0_en: the enable bit of spatial dithering process for sdt0 (yuv domain) clrize_en : the enable bit of colorize sat_en : the enable bit of saturation adjustment hue_en : the enable bit of hue adjustment cb_en : the enable bit of contrast and brightness adjustment note: sdt0_en and sdt1_en can not be ?1? simultaneously. img+0004h imgproc r2y0 configurat ion register imgproc_r2y0_cfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name roun d_r2y 0 r2y0_ en type rw rw reset 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1065 of 1535 r2y0_en: the enable bit of rgb2yuv conversion in r2y0 round_r2y0 : the rounding control bit of conversion process img+0008h imgproc y2r1 configurat ion register imgproc_y2r1_cfg bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y2r1_ rgb_ detec t_en sdt3_ en sdt2_ en roun d_y2r 1 y2r1_ en type rw rw rw rw rw reset 0 0 0 0 0 y2r1_rgb_detect_en: the enable bit of ?rgb detect and replace? process sdt3_en: the enable bit of spatial dithering process in rgb domain sdt2_en: the enable bit of spatial dithering process in yuv domain round_y2r1 : the rounding control bit of conversion process y2r1_en: the enable bit of yuv2rgb conversion in y2r1 note: sdt2_en and sdt3_en can not be ?1? simultaneously. img+000ch ipp sdt control regi ster imgproc_ipp_sdtcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ipp_seed1 ipp_seed2 type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7654 3 2 1 0 name ipp_seed3 ipp_bd1 ipp_bd2 ipp_bd3 type r/w r/w r/w r/w reset 0 0 0 0 ipp_bd1-3: the registers are used to configure the bit number of dithering. (e.g. 888 to 565, bd1=3;bd2=2;bd3=3) ipp_seed1-3: the registers are used to configure the seeds (lsb 4-bit) of the three pseudo-random code generators. note: ipp_seed1-3 should be configured when the enable bit (+0x0320) is ?0?. img+0010h y2r1 sdt control re gister imgproc_y2r1_sdtcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y2r1_seed1 y2r1_seed2 type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7654 3 2 1 0 name y2r1_seed3 y2r1_bd1 y2r1_bd2 y2r1_bd3 type r/w r/w r/w r/w reset 0 0 0 0 ipp_bd1-3: the registers are used to configure the bit number of dithering. (e.g. 888 to 565, bd1=3;bd2=2;bd3=3) ipp_seed1-3: the registers are used to configure the seeds (lsb 4-bit) of the three pseudo-random code generators. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1066 of 1535 img+0100h hue adjustment coefficient c11 imgproc_hue 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name c11 type r/w reset 40h img+0104h hue adjustment coefficient c12 imgproc_hue 12 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name c12 type r/w reset 0 img+0108h hue adjustment coefficient c21 imgproc_hue 21 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name c21 type r/w reset 0 img+010ch hue adjustment coefficient c22 imgproc_hue 22 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name c22 type r/w reset 40h this registers control the parameters of hue adjustment for the image. the effect is performed on the u and v component in yuv color space. the user should specify the coefficients that form the transformation matrix. the formula is listed as follows: cos 64 22 , sin 64 21 , sin 64 12 , cos 64 11 22 21 12 11 0 = ? = = = ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? c c c c where v u c c c c v u i i o the coefficients are in 2?s complement format and range from c0h to 40h (from ?64 to 64 in decimal, while 64 is normalized to 1). any value beyond this range is invalid. for example, to rotate the color space counterclockwise by 30 degree, the coefficients should be 37h, 20h, e0h, and 37h. c11: c11 of the transformation matrix in 2?s complement format c12: c12 of the transformation matrix in 2?s complement format c21: c21 of the transformation matrix in 2?s complement format c22: c22 of the transformation matrix in 2?s complement format free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1067 of 1535 img+0110h saturation adjustment coefficient imgproc_sat adj bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sat type r/w reset 20h this register defines the parameter of saturation adjustment for the image. the basics of saturation tuning is to multiply the u and v component by a scaling factor, which could range from 0 to 127, to degrade or enhance the strength on color components. setting to 20h represents no scaling. sat: saturation coefficient. img+0120h brightness adjustment coefficient b1 imgproc_bria dj1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bri type r/w reset 0 this register defines the parameter of brightness adjustment for the image. the parameter is in unsigned format. setting the value to be greater than 0 adds to the intensity of the image pixel. in terms of transfer curve, it represents the offset in the y-axis. the valid value ranges from 0 to 255. bri: brightness adjustment coefficient. img+0124h brightness adjustment coefficient b2 imgproc_bria dj2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name drk type r/w reset 0 this register controls the parameter of brightness adjustment for the image. the parameter is in unsigned format. setting the value to be greater than 0 degrades the intensity of the image pixel. in terms of transfer curve, it represents the offset in the x-axis. the valid value ranges from 0 to 255. drk: brightness adjustment coefficient img+0128h contrast adjustment coefficient imgproc_con adj bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name con type r/w reset 20h this register defines the parameter of contrast adjustment for the image pixel. the parameter is in unsigned format with normalization factor 20h. setting the value to be greater than 20h enhances the contrast for the image; and setting the value to be less than 20h lowers the contrast for the image. the valid value ranges from 0 to 255. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1068 of 1535 con: contrast adjustment coefficient img+0130h colorize u component coefficient imgproc_col orizeu bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ucom type r/w reset 0 img+0134h colorize v component coefficient imgproc_col orizev bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vcom type r/w reset 0 these registers controls the parameters of colorize effect for the image. the valid value ranges from ?128 to 127 in 2?s complement format. if the values of both coefficients are zero, it implies the gray-scale effect. ucom: colorize effect u component coefficient. vcom: colorize effect v component coefficient. img+0170h gamma correction offset value for segment 0 imgproc_gam ma_off0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name off0 type r/w reset 0 this register stores the y-offset value of the segment 0 for gamma correction. off0: offset value for offset values of other segments, please refer to table 109 . img+0190h gamma correction slope value for segment 0 imgproc_gam ma_slp0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slp0 type r/w reset 0 this register stores the slope value of the segment 0 for gamma correction. slp0: slope value for slope values of other segments, please refer to table 109 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1069 of 1535 img+01b0h gamma correction control register imgproc_gam ma_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gto type r/w reset 0 this register is used to control the gamma correction mode. gto: indicator of gamma value 0 gamma value is not greater than one. 1 gamma value is greater than one. register address register function acronym img+0170h offset value for the 1 st segment imgproc_gamma_off0 img+0174h offset value for the 2 nd segment imgproc_gamma_off1 img+0178h offset value for the 3 rd segment imgproc_gamma_off2 img+017ch offset value for the 4 th segment imgproc_gamma_off3 img+0180h offset value for the 5 th segment imgproc_gamma_off4 img+0184h offset value for the 6 th segment imgproc_gamma_off5 img+0188h offset value for the 7 th segment imgproc_gamma_off6 img+018ch offset value for the 8 th segment imgproc_gamma_off7 img+0190h slope value for the 1 st segment imgproc_gamma_slp0 img+0194h slope value for the 2 nd segment imgproc_gamma_slp1 img+0198h slope value for the 3 rd segment imgproc_gamma_slp2 img+019ch slope value for the 4 th segment imgproc_gamma_slp3 img+01a0h slope value for the 5 th segment imgproc_gamma_slp4 img+01a4h slope value for the 6 th segment imgproc_gamma_slp5 img+01a8h slope value for the 7 th segment imgproc_gamma_slp6 img+01ach slope value for the 8 th segment imgproc_gamma_slp7 table 109 gamma correction offset and slope register list img+0200h color adjustment offset x for 2 nd segment, red imgproc_col or1r_offx bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offx type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1070 of 1535 img+0220h color adjustment offset y for 2 nd segment, red imgproc_col or1r_offy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offy type r/w reset 0 img+0240h color adjustment slope for 2 nd segment, red imgproc_col or1r_slp bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slp type r/w reset 0 the above lists part of the registers that define the color adjustment parameters. color adjustment in image engine is used to tune the red, green, and blue color dimension individually to exhibit required color tone as a whole. the image engine provides 3-segment piecewise linear transfer curve for the user to be configured. the x offset defines the separation point for input color value. the y offset defines the offset for each segment. the slope defines the contrast enhancement ratio for each segment. for the red and blue components, the bit-width of the offset value is 5. for green, the bit-width of the offset value is 6. for slope of 3 color components, the bit-width is 6. offx: the separation point of the input value offy: the offset of output value slp: the slope which is used to do contrast tuning ratio within the segment. for all the registers of color adjustment, please refer to table 6 for detail information. register address register function bit- width acronym img+0200h color adjustment offset x for 2 nd segment, red 8 imgproc_color1r_offx img+0204h color adjustment offset x for 3 rd segment, red 8 imgproc_color2r_offx img+0208h color adjustment offset x for 2 nd segment, green 8 imgproc_color1g_offx img+020ch color adjustment offset x for 3 rd segment, green 8 imgproc_color2g_offx img+0210h color adjustment offset x for 2 nd segment, blue 8 imgproc_color1r_offx img+0214h color adjustment offset x for 3 rd segment, blue 8 imgproc_color2r_offx img+0220h color adjustment offset y for 2 nd segment, red 8 imgproc_color1r_offy img+0224h color adjustment offset y for 3 rd 8 imgproc_color2r_offy free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1071 of 1535 segment, red img+0228h color adjustment offset y for 2 nd segment, green 8 imgproc_color1g_offy img+022ch color adjustment offset y for 3 rd segment, green 8 imgproc_color2g_offy img+0230h color adjustment offset y for 2 nd segment, blue 8 imgproc_color1r_offy img+0234h color adjustment offset y for 3 rd segment, blue 8 imgproc_color2r_offy img+0240h color adjustment slope for 1 st segment, red 6 imgproc_color0r_slope img+0244h color adjustment slope for 2 nd segment, red 6 imgproc_color1r_slope img+0248h color adjustment slope for 3 rd segment, red 6 imgproc_color1r_slope img+0250h color adjustment slope for 1 st segment, green 6 imgproc_color0g_slope img+0254h color adjustment slope for 2 nd segment, green 6 imgproc_color1g_slope img+0258h color adjustment slope for 3 rd segment, green 6 imgproc_color1g_slope img+0260h color adjustment slope for 1 st segment, blue 6 imgproc_color0b_slope img+0264h color adjustment slope for 2 nd segment, blue 6 imgproc_color1b_slope img+0268h color adjustment slope for 3 rd segment, blue 6 imgproc_color1b_slope table 110 color adjustment offset and slope register list img+0318h r2y source select imgproc_r2y_ src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r2y0_io_sel[4:0] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y2r1_io_sel[3:0] ipp_io_sel[6:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 img+0320h imgproc machine enable imgproc_e n bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1072 of 1535 nam e rst y2r1 _en r2y0 _en ipp_ en type r/w r/w r/w r/w rese t 1 0 0 0 this register defines the enable and reset signals of the image processor. rst: the reset bit of ipp module 0 reset all status excluding control registers 1 enable normal function. y2r1_en: the hardware enable bit of the y2r1 module r2y0_en: the hardware enable bit of the r2y0 module ipp_en: the hardware enable bit of the ipp module note: all of the enable bits are active high, i.e. 1 to enable. img+0324h ipp rgb value detection imgproc_ipp_ rgb_detect bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red[7:0] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green[7:0] blue[7:0] type r/w r/w this register defines the rgb value for color detection in ipp path. img+0328h ipp rgb value replacement imgproc_ipp_ rgb_replace bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red[7:0] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green[7:0] blue[7:0] type r/w r/w this register defines the rgb value for replacement when the detection is hit. (ipp path) img+032ch y2r1 rgb value detection imgproc_y2r 1_rgb_detec t bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red[7:0] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green[7:0] blue[7:0] type r/w r/w this register defines the rgb value for detection in y2r1 path. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1073 of 1535 img+0330h y2r1 rgb value replacement imgproc_y2r1 _rgb_replac e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red[7:0] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green[7:0] blue[7:0] type r/w r/w this register defines the rgb value for replacement when the detection is hit. (y2r1 path) 5.17.2 image effect application the image engine is the hardware coprocessor that performs image effects on video stream or stand-alone image. it provides the following effects: 1. hue adjustment. 2. saturation adjustment. 3. contrast and intensity adjustment. 4. grayscale and colorization. 5. gamma correction. 6. color adjustment. 7. spatial dithering the format of the coefficients is listed in table 111 . function parameter group range (normalized factor) format hue c11, c12, c21, c22 -64 ~ 64 (64) 2?s complement saturation sat 0~127 (32) unsigned contrast and brightness bri1 0~255 unsigned bri2 0~255 unsigned contrast 0~255 (32) unsigned colorize u, v -128~127 2?s complement gamma correction offset 0~63 unsigned slope 0~255 (16) unsigned color adjustment offset for red 0~31 unsigned slope for red 0~63 (16) unsigned offset for green 0~63 unsigned slope for green 0~63 (16) unsigned free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1074 of 1535 offset for blue 0~31 unsigned slope for blue 0~63 (16) unsigned table 111 coefficients format table 5.17.2.1 gamma correction and color adjustment gamma correction is a nonlinear technique. image engine uses linear-approximation scheme for it and the same curve is applied equally on red, green, and blue components. two approaches are provided. for the first one, the overall input value is equally divided into 8 segments. it?s suitable for the case when gamma is greater than 1. for the second one, the value is divided into 6 unsymmetrical segments. it?s suitable for the case when gamma is smaller then 1. color adjustment is used to adjust different colors with different curves. for each color, a 3 segment piece- wise linear curve is applied. the user has to decide the offsets and the slopes of these 3 segments. the coefficients should be positive. cool tone and warm tone filters are both popular applications for color adjustment. examples of gamma correction and color adjustment are as follows. 5.18 jpeg decoder 5.18.1 general descriptions now most images must be stored as jpeg format compressed files. in order to display this kind of file and boost image processing performance, the hardware jpeg decoder is developed. as a result, jpeg decoder is designed to decode all baseline and progressive jpeg images with all yuv sampling frequencies combinations. to gain the best speed performance, jpeg decoder will handle all portions of jpeg files except the 17- byte sof marker. the software program only needs to program related control registers based on the sof marker and wait for an interrupt coming from hardware. fig 1 shows the basic jpeg file structure and starting address that jpeg decoder needs. the information of dqt and dht table is included in the jpeg file but need to be parsed by the jpeg decoder and store in the memory. the software program must program 2k-byte-align address in the table starting address because we has fixed the locations of all kinds of tables, as shown in fig 2 . taking into consideration the limited size of memories, hardware also supports multiple runs of jpeg progressive images and breakpoints insertion in huge jpeg files. multiple runs can greatly reduce memory usage by 1/n where n is the number of runs. before starting the current decoding run, jpeg decoder must reload the control signals from table address, as shown in fig 2 , and then start the decoding. so the starting table address can?t be changed if the multiple-run of one progressive jpeg file is enabled. breakpoints insertion allows software to load partial jpeg file from external flash to internal memory if the jpeg file is too large to sit internally at one time. jpeg decoder can support to only decode the target range in one baseline jpeg file. if enable this function, the decoding operations in un-targeted range will be skipped, as shown in fig 3. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1075 of 1535 soi eoi frame misc table scan jpeg_file_addr fig 1 the basic structure of jpeg files. dqt_tbl0 dqt_tbl1 dqt_tbl2 dqt_tbl3 dht_dc_tbl0 dht_ac_tbl0 dht_dc_tbl1 dht_ac_tbl1 dht_dc_tbl2 dht_ac_tbl2 dht_dc_tbl3 dht_ac_tbl3 multiple_run ctrl 11'b000_0000_0000 11'b000_0100_0000 11'b000_1000_0000 11'b000_1100_0000 11'b001_0000_0000 11'b001_0001_0000 11'b010_0000_0000 11'b010_0001_0000 11'b011_0000_0000 11'b011_0001_0000 11'b100_0000_0000 11'b100_0001_0000 11'b101_0000_0000 11'b101_0000_1100 fig 2 the memory address arrangement of dqt, dht. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1076 of 1535 mcu_col = 9 idct_row_num_per_row = 12 start_idct_mcu_row_index = 26 end_idc_mcu_row_row_index = 88 idct_skp_mcu_idx2 = 10 idct_skip_mcu_idx1=2 fig 3 the range setting for the range decoding. 5.18.2 register definitions register address register function acronym jpeg + 0000h jpeg decoder file address register jpg_dec_file_addr jpeg + 0004h jpeg decoder table address register jpg_dec_tbl_addr jpeg + 0008h jpeg decoder sampling factor register jpg_dec_samp_factor jpeg + 000ch jpeg decoder component id register jpg_dec_comp_id jpeg + 0010h jpeg decoder total mcu number register jpg_dec_total_mcu_num jpeg + 0014h jpeg decoder interleave mcu number per mcu row register jpg_dec_mcu_num_per_ mcu_row jpeg + 0018h jpeg decoder 0 st component?s non- interleave data-unit number per mcu row register jpg_dec_comp0_nointv_ du_num_per_ mcu_row jpeg + 011ch jpeg decoder 1 st component?s non- interleave data-unit number per mcu row register jpg_dec_comp1_nointv_ du_num_per_ mcu_row jpeg + 0020h jpeg decoder 2 nd component?s non- interleave data-unit number per mcu row register jpg_dec_comp2_nointv_ du_num_per_ mcu_row jpeg + 0024h jpeg decoder 0 st component?s data- unit number register jpg_dec_comp0_du_num free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1077 of 1535 jpeg + 0028h jpeg decoder 1 st component?s data- unit number register jpg_dec_comp1_du_num jpeg + 002ch jpeg decoder 2 nd component?s data- unit number register jpg_dec_comp2_du_num jpeg + 0030h jpeg decoder 0 st component?s progressive coefficient register jpg_dec_comp0_prog_ coef_addr jpeg + 0034h jpeg decoder 1 st component?s progressive coefficient register jpg_dec_comp1_prog_ coef_addr jpeg + 0038h jpeg decoder 2 nd component?s progressive coefficient register jpg_dec_comp2_prog_ coef_addr jpeg + 003ch jpeg decoder control register jpg_dec_ctrl jpeg + 0040h jpeg decoder trigger register jpg_dec_trig jpeg + 0044h jpeg decoder reset register jpg_dec_rstb jpeg + 0048h jpeg decoder breakpoint address register jpg_dec_brp_addr jpeg + 004ch jpeg decoder file size register jpg_dec_file_size jpeg + 0050h jpeg decoder interleave first mcu index register jpg_dec_intlv_first_ mcu_ idx jpeg + 0054h jpeg decoder interleave last mcu index register jpg_dec_last_last_ mcu_ idx jpeg + 0058h jpeg decoder non-interleave 0 st compont?s first data unit index register jpg_dec_nointv _comp0_ first_du_ idx jpeg + 005ch jpeg decoder non-interleave 0 st compont?s last data unit index register jpg_dec_nointv _comp0_ last_du_ idx jpeg + 0060h jpeg decoder non-interleave 1 st compont?s first data unit index register jpg_dec_nointv _comp1_ first_du_ idx jpeg + 0064h jpeg decoder non-interleave 1 st compont?s last data unit index register jpg_dec_nointv _comp1_ last_du_ idx jpeg + 0068h jpeg decoder non-interleave 2 nd compont?s first data unit index register jpg_dec_nointv _comp2_ first_du_ idx jpeg + 006ch jpeg decoder non-interleave 2 nd compont?s last data unit index register jpg_dec_nointv _comp2_ last_du_ idx jpeg + 0070h jpeg decoder quantization table id register jpg_dec_qt_id jpeg + 0074h jpeg decoder interrupt status register jpg_dec_int_status jpeg + 0078h jpeg decoder fsm status register jpg_dec_fsm_status jpeg + 007ch jpeg decoder range decode register jpg_dec_range_en jpeg + 0080h jpeg decoder range decoding starting mcu row index register jpg_dec_range_start_ mcu_idx jpeg + 0084h jpeg decoder range decoding ending mcu row index register jpg_dec_range_end_ mcu_idx jpeg + 0088h jpeg decoder range decoding mcu number pre row register jpg_dec_range_mcu_ num_per_row free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1078 of 1535 jpeg + 008ch jpeg decoder range decoding skipping mcu index1 register jpg_dec_range_skip_ mcu_ idx1 jpeg + 0090h jpeg decoder range decoding skipping mcu index2 register jpg_dec_range_skip_ mcu_ idx2 jpeg + 0094h jpeg decoder mcu counts register jpg_dec_mcu_cnt jpeg + 0098h jpeg decoder idct counts register jpg_dec_idct_cnt table 112 jpeg decoder registers 5.18.3 register definitions jpeg+0000h jpeg decoder file address register jpg_dec_file_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name file_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name file_addr[15:2] 0 0 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro file_addr starting address of input jpeg file. the jpeg file starting address must be a 4-byte aligned. this register?s content will be changed by hardware if jpeg decoder has been started. the contents represent the address that has been read. suggest the starting address should be set to the location of dqt marker (0xffdb) in the beginning of decoding one jpeg file. some dummy data can be inserted before the jpeg file and this can help to meet the limitation of 4-bytes align. when enabling the function of breakpoint, one jpeg file can be divided into several sections and then load to memory for decoding individually. in the every ending of section, software need to re-programmed the file address to the starting the next file section. it?s not permitted that any dummy data is inserted in file content. not affected by global reset and jpeg decoder abort. jpeg+0004h jpeg decoder table address register jpg_dec_tbl_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tbl_addr[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tbl_addr[15:11] type r/w r/w r/w r/w r/w tbl_addr the starting address of the memory space for 4 quantization tables and 8 huffman tables. the memory address must be a multiple of 2k bytes . the table starting address must be a multiple of 2k. the jpeg decoder will parser the information of dqt and dht table and store in this memory location, as shown in fig 2 . not affected by global reset and jpeg decoder abort. need reprogramming and keep the same address in all runs of progressive images. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1079 of 1535 jpeg+0008h jpeg decoder sample factor register jpg_dec_samp_f actor bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name h_samp_0[1: 0] v_samp_0[1: 0] h_samp_1[1: 0] v_samp_1[1:0 ] h_samp_2[1: 0] v_samp_2[1: 0] type r/w r/w r/w r/w r/w r/w h_samp_0 horizontal sampling factor of the 1 st component, y. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 v_samp_0 vertical sampling factor of the 1 st component, y. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 h_samp_1 horizontal sampling factor of the 2 nd component, u. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 v_samp_1 vertical sampling factor of the 2 nd component, u. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 h_samp_2 horizontal sampling factor of the 3 rd component, v. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 v_samp_2 vertical sampling factor of the 3 rd component, v. 00 sf is 1 01 sf is 2 10 invalid 11 sf is 4 this register contains the sampling factor of yuv components. for the grayscale jpeg file, the sampling factor only has one kind of setting, (h0, v0)= (1, 1) . not affected by global reset and jpeg decoder abort. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1080 of 1535 jpeg+000ch jpeg decoder component id register jpg_dec_comp_i d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp0_id[7:0] comp1_id[7:0] type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp2_id[7:0] type r/w comp0_id the 1 st component (y) id extracted from sof marker. comp1_id the 2 nd component (u) id extracted from sof marker. comp2_id the 3 rd component (v) id extracted from sof marker. this register contains the ids of yuv components. not affected by global reset and jpeg decoder abort. jpeg+0010h jpeg decoder total mcu number register jpg_dec_total_ mcu_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name total_mcu_num[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name total_mcu_num[15:0] type r/w total_mcu_num total mcu number will be decoded. this register contains the total mcu number in interleaved scan. note that if the mcu number is n , program (n-1) into this register. not affected by global reset and jpeg decoder abort. jpeg+0014h jpeg decoder interleave mcu number per mcu row register jpg_dec_intlv_ mcu_num_per_m cu_row bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name intlv_mcu_num_per_mcu_row[9:0] type r/w intlv_mcu_num_per_row mcu number in the interleave scan of progressive jpeg files. only effective in progressive images. note that if the mcu number per row in interleaved scan is n , program n into this register. n affected by global reset and jpeg decoder abort. jpeg+0018h jpeg decoder non-interleave 0 st compont?s data number setting register jpg_dec_comp0_ nonintlv_du_nu m_per_mcu_row bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1081 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dummy_du comp0_nonintlv_mcu_num_per_mcu_row[9:0] type r/w r/w dummy_du dummy data unit number in non-interleaved scan of the 0 st component 00 no dummy data unit 01 one dummy data unit 10 two dummy data units 11 three dummy data units comp0_nonintlv_mcu_num_per_mcu_row the mcu number per row in non-interleaved scan of the 1 st component (y). only effective in progressive images. this register contains the mcu number per row in non-interleaved scan of the 0 st component (y). not affected by global reset and jpeg decoder abort. in progressive image, dummy data unit columns are inevitable if more than 8 redundant pixel columns are transmitted to fill up the last mcu in a mcu row. for example, in 420 formats, a mcu is composed of 16 x 16 pixels. if a given image size is 355 x 400, for jpeg encoder to compress, the image will grow to 368 x 400 first such that both width and height are multiples of 16. it can be seen that to be divisible by 16, there are 13 redundant y-component pixels in the horizontal (width) direction. these 13 y-component pixels will be compressed by encoders in interleaved scans because a complete mcu will need 16 x 16 pixels. it is different from non-interleaved scans, because in non-interleaved scans a complete mcu only needs 8 x 8 y- component pixels. therefore, among the 13 redundant pixels the first 5 will still be compressed as interleaved scans while the last 8 will be dropped. in this case, software must program the dummy_du field to 1 so the hardware will know one 8 x 8 data unit should be skipped at the last of a mcu row in non-interleaved scan. jpeg+001ch jpeg decoder non-interleave 1 st compont?s data number setting register jpg_dec_comp1_ nonintlv_du_nu m_per_mcu_row bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dummy_du comp1_nonintlv_mcu_ num_per_mcu_row[9:0] type r/w r/w dummy_du dummy data unit number in non-interleaved scan of the 2 nd component 00 no dummy data unit 01 one dummy data unit 10 two dummy data units 11 three dummy data units comp1_nonintlv_mcu_num_per_mcu_row the mcu number per row in non-interleaved scan of the 1 st component (u). only effective in progressive images. this register contains the mcu number per row in non-interleaved scan of the 1 st component (y).not affected by global reset and jpeg decoder abort. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1082 of 1535 jpeg+0020h jpeg decoder non-interleave compont2?s data number setting register jpg_dec_comp2_ nonintlv_du_nu m_per_mcu_row bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dummy_du comp2_nonintlv_mcu_ num_per_mcu_row[9:0] type r/w r/w dummy_du dummy data unit number in non-interleaved scan of the 2 nd component 00 no dummy data unit 01 one dummy data unit 10 two dummy data units 11 three dummy data units comp2_nonintlv_mcu_num_per_mcu_row the mcu number per row in non-interleaved scan of the 3 rd component (v). only effective in progressive images. this register contains the mcu number per row in non-interleaved scan of the 2 nd component (v). not affected by global reset and jpeg decoder abort. jpeg+0024h jpeg decoder compont0?s data number register jpg_dec_comp0_ du_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp0_data_unit_num[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp0_data_unit_num[15:0] type r/w comp0_data_unit_num data unit number of 0 st component in progressive jpeg file. number of 0 st component is: 1 ) _ _ * _ _ ( * ) _ _ * _ _ ( 0 0 ? ? ? col ydu dumm v col per mcu row ydu dumm h row per mcu only effective in progressive images or grayscale mode. this register contains the 8x8 data unit number of the 1st component in non-interleaved scans. note that if the data unit number is n , program (n-1) into this register. not affected by global reset and jpeg decoder abort. jpeg+0028h jpeg decoder compont1?s data number register jpg_dec_comp1_ du_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp1_data_unit_num[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp1_data_unit_num[15:0] type r/w comp1_data_unit_num data unit number of 1 st component in progressive jpeg file. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1083 of 1535 number of 1 st component is: 1 _ _ ? num mcu total only effective in progressive images. this register contains the 8x8 data unit number of the 1 st component in non-interleaved frame. note that if the data unit number is n , program (n-1) into this register. not affected by global reset and jpeg decoder abort. jpeg+002ch jpeg decoder compont2?s data number register jpg_dec_comp2_ du_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp2_data_unit_num[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp2_data_unit_num[15:0] type r/w comp2_data_unit_num data unit number of 2 nd component in progressive jpeg file. number of 2 nd component is: 1 _ _ ? num mcu total only effective in progressive images. this register contains the 8x8 data unit number of the 2 nd component in non-interleaved frame. note that if the data unit number is n , program (n-1) into this register. not affected by global reset and jpeg decoder abort. jpeg+0030h jpeg decoder compont0?s progressive coefficient address register jpg_dec_comp0_ prog_coeff_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp0_progr_coeff_ addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp0_progr_coeff_ addr[15:0] type r/w comp0_progr_coeff_addr destination address of 0 st component?s coefficient in progressive jpeg file only effective in progressive images. this register contains the starting address of the memory space storing the intermediate progressive 16-bit coefficients of the 1st component. the memory requirement of 1st component is 2 _ _ _ _ 64 runx this in block total , total block means the block number of 0 st component this value must be a multiple of 4. not affected by global reset and jpeg decoder abort. jpeg+0034h jpeg decoder compont1?s progressive coefficient address register jpg_dec_comp1_ prog_coeff_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1084 of 1535 name comp1_progr_coeff_ addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp1_progr_coeff_ addr[15:0] type r/w comp1_progr_coeff_addr destination address of 1 st component?s coefficient in progressive jpeg file only effective in progressive images. this register contains the starting address of the memory space storing the intermediate progressive 16-bit coefficients of the 2nd component. the memory requirement of 1 st component is 2 _ _ _ _ 64 runx this in block total , total block means the block number of 2nd component this value must be a multiple of 4. not affected by global reset and jpeg decoder abort. jpeg+0038h jpeg decoder compont2?s progressive coefficient address register jpg_dec_comp2_ prog_coeff_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp2_progr_coeff_ addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp2_progr_coeff_ addr[15:0] type r/w comp2_progr_coeff_addr destination address of 2 nd component?s coefficient in progressive jpeg file only effective in progressive images. this register contains the starting address of the memory space storing the intermediate progressive 16-bit coefficients of the 2 nd component. the memory requirement of 3rd component is 2 _ _ _ _ 64 runx this in block total , total block means the block number of 3rd component this value must be a multiple of 4. not affected by global reset and jpeg decoder abort. jpeg+003ch jpeg decoder control register jpg_dec_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gray jpeg_ mode du9[2:0] du8[2:0] du7[2:0] du6[2:0] du5[2:0] type r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name du4[2:0] du3[2:0] du2[2:0] du1[2:0] du0[2:0] type r/w r/w r/w r/w r/w this register contains 2 kinds of information: the operating mode of jpeg decoder and the order of 3 components in a mcu. affected by global reset and jpeg decoder abort. need reprogramming for multiple runs of progressive images. gray_mode set the grayscale mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1085 of 1535 0 no-grayscale mode 1 grayscale mode jpeg_mode the operating mode of jpeg decoder. 0 baseline mode 1 progressive mode du9 the 10 th data unit component category in a mcu 100 the 10 th data unit is the 1 st component (y) 101 the 10 th data unit is the 2 nd component (u) 110 the 10 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du8 the 9 th data unit component category in a mcu 100 the 9 th data unit is the 1 st component (y) 101 the 9 th data unit is the 2 nd component (u) 110 the 9 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du7 the 8 th data unit component category in a mcu 100 the 8 th data unit is the 1 st component (y) 101 the 8 th data unit is the 2 nd component (u) 110 the 8 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du6 the 7 th data unit component category in a mcu 100 the 7 th data unit is the 1 st component (y) 101 the 7 th data unit is the 2 nd component (u) 110 the 7 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du5 the 6 th data unit component category in a mcu 100 the 6 th data unit is the 1 st component (y) 101 the 6 th data unit is the 2 nd component (u) 110 the 6 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du4 the 5 th data unit component category in a mcu 100 the 5 th data unit is the 1 st component (y) 101 the 5 th data unit is the 2 nd component (u) 110 the 5 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du3 the 4 th data unit component category in a mcu 100 the 4 th data unit is the 1 st component (y) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1086 of 1535 101 the 4 th data unit is the 2 nd component (u) 110 the 4 th data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du2 the 3 rd data unit component category in a mcu 100 the 3 rd data unit is the 1 st component (y) 101 the 3 rd data unit is the 2 nd component (u) 110 the 3 rd data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du1 the 2 nd data unit component category in a mcu 100 the 2 nd data unit is the 1 st component (y) 101 the 2 nd data unit is the 2 nd component (u) 110 the 2 nd data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid du0 the 1 st data unit component category in a mcu 100 the 1 st data unit is the 1 st component (y) 101 the 1 st data unit is the 2 nd component (u) 110 the 1 st data unit is the 3 rd component (v) 111 not used in current frame 000-011 invalid jpeg+0040h jpeg decoder trigger register jpg_dec_trig bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trig type w/o trig set to 1 to start jpeg decoder. jpeg+0044h jpeg decoder reset register jpg_dec_rstb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type r/w rstb low active reset. set to 0 to reset the jpeg decoder and idct processor. and set to 1 to finish the reset process. jpeg decoder reset must be issued once after finishing jpeg decoding. if not, the shared designs with mp4 can?t work normally. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1087 of 1535 jpeg+0048h jpeg decoder breakpoint address register jpg_dec_ brp_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jpeg_file_brp_addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jpeg_file_brp_addr [15:2] 0 0 type r/w ro ro jpeg_file_brp_addr breakpoint address. this address should be the ending of every section of jpeg files. jpeg_dec_brp stands for a 32-bit byte breakpoint address that hardware will stall once the breakpoint address is encountered. the data in the current breakpoint address will not be read. this control register provides a solution for software to swap internal memory content with external memory in case the jpeg source file is too big for internal memory to store at one time. a breakpoint interrupt will fire when hardware dma address hits the breakpoint address. software can refill the residue bitstream and written again these two registers, jpg_dec_brp_addr and jpeg_dec_file_addr to re-start jpeg decoding. jpg_dec_brp_addr must be written before jpeg_dec_file_addr. jpeg decoder will be re- started as jpeg_dec_file_addr is written. note that the breakpoint address must be a multiple of 4 and 16-byte dummy size must be included in this run. not affected by global reset and jpeg decoder abort. jpeg+004ch jpeg decoder file size register jpg_dec_file_ size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jpeg_file_total_size[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jpeg_file_total_size[15:0] type r/w jpeg_file_total_size jpeg file bytes size. if jpeg file size =m, this register is should be programmed (m+64). jpeg_file_total_size represents the jpeg source file size in bytes. hardware will fire a file overflow interrupt and stall if the dma address equals to this address. note that the file total size must be a multiple of 4 and must include 16-byte dummy size. if the file total size is not divisible by 4, increment the size value until it is. not affected by global reset and jpeg decoder abort. jpeg+0050h jpeg decoder interleave first mcu index register jpg_dec_intlv_ first_mcu_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name intlv_first_mcu_index[ 19:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name intlv_first_mcu_index[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1088 of 1535 intlv_first_mcu_index first mcu index of multiple-run decoding in interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the first mcu index that hardware will process in the interleaved scans of the current image. the jpeg decoder is able to skip certain mcus by defining the first and last mcu index. not affected by global reset and jpeg decoder abort. jpeg+0054h jpeg decoder interleave last mcu index register jpg_dec_intlv_ last_mcu_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name intlv_last_mcu_index[ 19:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name intlv_last_mcu_index[15:0] type r/w intlv_last_mcu_index last mcu index of multiple-run decoding in interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the last mcu index that hardware will process in the interleaved scans of the current image. the jpeg decoder is able to skip certain mcus by defining the first and last mcu index. not affected by global reset and jpeg decoder abort. jpeg+0058h jpeg decoder non-interleave 0 st component first data unit index register jpg_dec_comp0 _first_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp0_first_du_index[ 19:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp0_first_du_index[15:0] type r/w comp0_first_du_index first data-unit index of multiple-run decoding 0 st component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the first data unit index that hardware will process in the non-interleaved scans containing y component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. jpeg+005ch jpeg decoder non-interleave 0 st component last data unit index register jpg_dec_comp0 _last_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp0_last_du_index[1 9:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp0_last_du_index[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1089 of 1535 comp0_last_du_index last data-unit index of multiple-run decoding 0 st component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the last data unit index that hardware will process in the non-interleaved scans containing y component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. jpeg+0060h jpeg decoder non-interleave 1 st component first data unit index register jpg_dec_comp1 _first_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp1_first_du_index[ 19:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp1_first_du_index[15:0] type r/w comp1_first_du_index first data-unit index of multiple-run decoding 1 st component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the first data unit index that hardware will process in the non-interleaved scans containing u component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. jpeg+0064h jpeg decoder non-interleave 1 st component last data unit index register jpg_dec_comp1 _last_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp1_last_du_index[1 9:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp1_last_du_index[15:0] type r/w comp1_last_du_index last data-unit index of multiple-run decoding 1 st component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the last data unit index that hardware will process in the non-interleaved scans containing u component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. jpeg+0068h jpeg decoder non-interleave 2 nd component first data unit index register jpg_dec_comp2 _first_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp2_first_mcu_inde x[19:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1090 of 1535 name comp2_first_du_index[15:0] type r/w comp2_first_du_index first data-unit index of multiple-run decoding 2 nd component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the first data unit index that hardware will process in the non-interleaved scans containing v component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. jpeg+006ch jpeg decoder non-interleave 2 nd component last data unit index register jpg_dec_comp2 _last_du_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name comp2_last_du_index[1 9:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp2_last_du_index[15:0] type r/w comp2_last_du_index last data-unit index of multiple-run decoding 2 nd component in non-interleave scan of the progressive jpeg file. only effective in progressive images. this control register specifies the last data unit index that hardware will process in the non-interleaved scans containing v component of the current image. the jpeg decoder is able to skip certain data units by defining the first and last data unit index. not affected by global reset and jpeg decoder abort. in progressive image, interleave and no-interleave scans can both exit in one image. if we want to enable the function of multiple run, the range of every run for interleave and no-interleave scans need to be programmed simultaneously. for example, in 420 format, a mcu is composed of 16 x 16 pixels. if a image is 162x128, if we set run range for interleave scan, (intlv_first_mcu_index, intlv_last_mcu_index)= (0, 20), the run range of non-interleave scan should be (comp0_first_du_index, comp0_last_du_index )= (0, 77) ; (comp1_first_du_index, comp1_last_du_index )= (0, 20) ; (comp2_first_du_index, comp2_last_du_index )= (0, 20) , and the dummy data unit should be ignored in the non-interleave scan. jpeg+0070h jpeg decoder quantization table id register jpg_dec_qt_id bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp0_qt_id[3:0] comp1_qt_id[3:0] comp2_qt_id[3:0] type r/w r/w r/w comp0_qt_id quantization table id of y component directly extracted from sof marker comp1_qt_id quantization table id of u component directly extracted from sof marker comp2_qt_id quantization table id of v component directly extracted from sof marker free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1091 of 1535 this register contains the quantization table ids for yuv components. not affected by global reset and jpeg decoder abort. jpeg+0074h jpeg decoder interrupt status register jpeg_dec_int_ status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq_t yp type 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name int3 int2 int1 int0 type r/wc r/wc r/wc r/wc the register reflects the interrupt status int3 set to 1 by range decoding interrupt, and write 1 to clear interrupt signal. int2 set to 1 by file overflow interrupt, and write 1 to clear interrupt signal. int1 set to 1 by breakpoint interrupt, and write 1 to clear interrupt signal. int0 set to 1 by end of file interrupt, and write 1 to clear interrupt signal. irq_typ irq type 0 read clear mode 1 write clear mode (if enable write clear mode, this bit must be always set to 1 ) jpeg+0078h jpeg decoder fsm status register jpg_dec_fsm_s tatus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fos brps eofs jpeg_dec_state huff_dec_state marker_parser_state type ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sos_parser_state dht_parser_state dqt_parser_state data_unit_state type ro ro ro ro the register reflects the fsm status fos set to 1 in overflow condition brps set to 1 in breakpoint condition eofs set to 1 in eoi condition jpeg_dec_state 0 idle 1 dma_load 2 marker_parser 3 huffman_decode 4 rst_srch 5 reload_progr_coeff 6 wait_for_idct huff_dec_state 0 idle 1 reload_scan_start_addr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1092 of 1535 2 reload_eob_run 3 bypass_data 4 reload_ctrl 5 read_coeff 6 huff_addr_logical 7 huff_addr_physical 8 eob_run_gen 9 amp_cal a wait_coeff b save_scan_start_addr c save_eob_run d save_crl e wait_for_idct marker_parser_state 1 srch_0xff 2 marker_type_iden 3 marker_len_high 4 marker_len_low 5 marker_misc_info_dec sos_parser_state 1 ns 2 comp_spec 3 ss_field 4 se_field 5 ah_al_field dht_parser_state 1 tc_th 2 huff_sym_length 3 huff_val_collect 4 write_huff_val dqt_parser_state 0 idle 1 pq_tq 2 read_coeff 3 progr_coeff 4 write_coeff huff_dec_state 0 du0 1 du1 2 du2 3 du3 4 du4 5 du5 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1093 of 1535 6 du6 7 du7 8 du8 9 du9 jpeg+007ch jpeg decoder range decode enable register jpg_dec_rang _dec_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name en type r/w en set to 1 is to enable partial decoding. the register is to enable the function of partial decoding. only support the baseline jpeg file. jpeg+0080h jpeg decoder range decode starting mcu index register jpg_dec_rang e_start_mcu_i dx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start_idct_mcu_row_index[15:0] type r/w start_idc_mcu_row_index mcu index of the starting row in range decoding. please see fig 3. the register is to set which mcu is the starting point. note that if the mcu number is n , the setting range is from 0 ~ (n-1) . jpeg+0084h jpeg decoder range decode ending mcu index register jpg_dec_rang e_end_mcu_idx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end_idct_mcu_row_index type r/w end_idc_mcu_row_index mcu index of the ending row in range decoding. please see fig 3. the register is to set which mcu index is the ending point. note that if the mcu number is n , the setting range is from 1 ~ (n) . jpeg+0088h jpeg decoder range decode mcu number pre row register jpg_dec_rang e_mcu_num_pe r_row bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1094 of 1535 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name idct_mcu_num_per_row type r/w idc_mcu_num_per_row mcu number per image?s row. please see fig 3. the register is to define the valid number per row in the image. note that if the mcu number per row is m , the setting range is from 0 ~ (m-1) . jpeg+008ch jpeg decoder range decode skip mcu index1 register jpg_dec_rang e_skip_mcu_idx 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name idct_skip_mcu_index1 type r/w idc_skip_mcu_index1 skip mcu index1 pre mcu row for range decoding. please see fig 3. the register is to define the starting muc index per row in the image. note that if the mcu number per row is m , the setting range is from 0 ~ ( m-2 ). jpeg+0090h jpeg decoder range decode skip mcu index2 register jpg_dec_rang e_skip_mcu_idx 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name idct_skip_mcu_index2 type r/w idc_skip_mcu_index2 skip mcu index2 pre mcu row for range decoding. please see fig 3. the register is to define the ending muc index per row in the image. note that if the mcu number per row is m , the setting range is from 1 ~ (m-1) . jpeg+0094h jpeg decoder mcu counts register jpg_dec_mcu_ cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jpg_mcu_cnt[19:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jpg_mcu_cnt[15:0] type ro jpg_mcu_cnt mcu counts that had been decoded. the register is to report the current mcu number that has been decoded by jpeg decoder. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1095 of 1535 jpeg+0098h jpeg decoder idct counts register jpg_dec_idct_ cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name idct_blk_cnt[15:0] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jpeg_blk_cnt[15:0] type ro the register is to report the current block number that has been decoded by jpeg decoder and idct. jpeg_blk_cnt block number that has been finished by jpeg decoder design. idct_blk_cnt block number that has been finished by idct design. 5.19 jpeg encoder 5.19.1 general descriptions the hardware jpeg encoder implements the baseline mode of standard iso/iec 10918-1. it supports yuv 422, 420 and 411 formats for color pictures and grayscale format. with the software assist and suitable destination memory address setting; jfif/exif jpeg format can also be supported. for hardware reduction, it uses standard dc and ac huffman tables for both the luminance and chrominance components. to adjust the picture compression ratio and picture quality, there are 14 levels of quantization that can be programmed. after initialization by software, the hardware jpeg encoder can generate the entire compressed file. fig. 16 shows the procedure of the jpeg encoder. the yuv pixel data that came from image dma are grouped into 8x8 blocks and then down-sampled to yuv 422, yuv420 and yuv411 format. for grayscale encoding, only y component is present. when encoding, the first thing to do is to turn the pixel data into the frequency domain using fdct. after the quantizer is done, the quantized dct coefficients are encoded by rle and vlc. yuv image data 8 x 8 blocks fdct quantizer rle/vlc compressed image data table specifications table specifications fig. 16 the procedure of jpeg encoder. 5.19.2 jfif/exif jpeg format the original jpeg file can contain the information of camera, the thumbnail image and some good and important information by following jfif/exif format. if enabling jfif/exif mode, the jpeg encoder does not generate soi marker and related thumbnail header and small image data. the jpeg encoder just outputs free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1096 of 1535 the bitstreams from dqt marker. the software programs need to provide the suitable destination address after estimating the size of soi marker, related thumbnail header and small image data. the soi marker and related thumbnail header need to be handled by software programs and the small image data can be output by imgdma. with the suitable destination address configuration, the jfif/exif jpeg format can be generated. fig 17 illustrates the data partition for jfif/exif support. before jpeg encoding, three suitable address configurations provides. the addr1 is provided to soi maker and the thumbnail header. this part is handled by software. the addr2 is provided to imgdma to write rgb small image data. the last address, addr3, provides to the jpeg encoder to write out remaining bitstreams. soi marker thumbnail header thumbnail (rgb) table misc frame header scan eoi marker "%%3 "%%3 "%%3 4pguxsfhfofsbuf *.(%."hfofsbuf +1&(fodpefshfofsbuf fig 17 the jfif/exif data structure. 5.19.3 register definitions register address register function acronym jpeg + 0100h jpeg encoder reset register jpg_enc_rst jpeg + 0104h jpeg encoder control register jpg_enc_ctl jpeg + 0108h jpeg encoder quality register jpg_enc_quality jpeg + 010ch jpeg encoder block number register jpg_enc_blk_num jpeg + 0110h jpeg encoder block count register jpg_enc_blk_cnt jpeg + 0114h jpeg encoder frame number register jpg_enc_frame_num jpeg + 0118h jpeg encoder frame count register jpg_enc_frame_cnt jpeg + 011ch jpeg encoder interrupt status register jpg_enc_intsts jpeg + 0120h jpeg encoder 1 st base address register jpg_enc_dest_addr1 jpeg + 0124h jpeg encoder 1 st dma address register jpg_enc_dma_addr1 jpeg + 0128h jpeg encoder 1 st stall address register jpg_enc_stall_addr1 jpeg + 012ch jpeg encoder 2 nd base address2 jpg_enc_dest_addr2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1097 of 1535 register jpeg + 0130h jpeg encoder 2 nd dma address2 register jpg_enc_dma_addr2 jpeg + 0134h jpeg encoder 2 nd stall address2 register jpg_enc_stall_addr2 jpeg + 0138h jpeg encoder offset address register jpg_enc_offset_addr table 113 jpeg encoder registers free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1098 of 1535 jpeg+0100h jpeg encoder reset register jpg_enc_rst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type r/w reset 1 rstb set to 0 to reset the jpeg encoder and fdct processor. and set to 1 to finish the reset process. jpeg+0104h jpeg encoder control register jpg_enc_ctl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ultra _en addr _sw cont jpg yuv it gray en type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 1 0 0 en enable the jpeg encoder. this bit is cleared by hardware after encoding is done. jpeg will write out the bitstream of jpeg header after this enable bit is set. after finish writing out the header stream, the yuv data request to jpeg dma will be issued. in order to avoid some abnormal conditions, we assume that jpeg dma must be enabled before set this enabling bit. gray do grayscale encode. remember that the image dma should be programmed as grayscale too. 0 color 1 grayscale it interrupt enabling 0 disable 1 enable yuv yuv format 0 yuv 422 1 yuv 420 2 reserved 3 yuv 411 jpg jpeg or other application format support 0 jpeg 1 jfif/exif if enabling jfif/exif format, jpeg encoder won?t write out soi marker and write out dqt maker. software program can fill the jfif/exif content above the dqt marker to finish one jfif/exif jpeg file. cont jpeg continuous shooting. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1099 of 1535 0 off 1 on jpeg continuous shooting mode can encode continuous yuv data until it reaches the target frame number. addr_sw jpeg destination address switch in continuous shooting mode 0 off, frame destination address will be accumulated until it reaches the target frame numbe. 1 on, frame destination address switches between jpg_enc_dest_addr and jpg_enc_dest_addr2. ultra_en jpeg encoder accessing gmc with ultra high priority enable 0 off, jpeg encoder accessing gmc with normal priority. 1 on, jpeg encoder accessing gmc with high priority if buffer reaches the threshold jpeg+0108h jpeg encoder quality register jpg_enc_qualit y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name qt quality type r/w r/w reset 00 00 quality quality level in quantization tables. 00 low, only for high and good quality quantization table. 01 fair. 10 good. 11 high. qt quantization table selection 00 high quality table, 2 ~ 4 time compression ratio. 01 good quality table, 3 ~ 6 time compression ratio. 10 fair quality table, 5 ~ 10 time compression ratio. 11 low quality table, 7 ~ 30 time compression ratio. table 114 details all kinds of quality levels that jpeg encoder can provide. larger quality factor means better compression quality. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1100 of 1535 qt quality quality factor 00 60 01 80 10 90 00 11 95 00 39 01 68 10 84 01 11 92 00 48 01 48 10 74 10 11 87 00 34 01 34 10 64 11 11 82 table 114 quality v.s. quantization table setting jpeg+010ch jpeg block number register jpg_enc_blk _num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name blk_num[21:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blk_num[15:0] type ro reset 0 blk_num 8x8 block number will be encoded. 1 ) ( ) / ( ) / ( _ ? + + = v v u u y y y y v h v h v h v heigh ceil h width ceil num blk , note: the dummy 8x8 block must be considered in blk_num . for example, a 162x128 yuv420 jpeg file, the block number setting should be 527. jpeg+0110h jpeg block count register jpg_enc_blk _cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name blk_cnt[21:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blk_cnt[15:0] type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1101 of 1535 blk_cnt 8x8b lock count has been encoded. cnt will increase 1 after finishing rle/vlc . jpeg+0114h jpeg encoder continuous shooting frame number jpg_enc_fra me_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name frame_num type r/w reset 0 frame_num frame number in continuous shooting will be encoded jpeg+0118h jpeg encoder continuous shooting current frame count jpg_enc_cur r_frame_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name frame_cnt type r/o reset 0 frame_cnt frame counts had been encoded. jpeg+011ch jpeg encoder interrupt status register jpg_enc_ints ts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name stall done type r/wc r/wc reset 0 0 done indicates that encoding operation is done. need to set to 0 after reading. stall indicates that encoding operation is in the stall condition. need to set to 0 after reading but the stall condition can' cleared by this bit. the stall condition will be clear if we do the following procedure. the destination address need to be re-programmed firstly and then reprogrammed the stall address to clear the stall condition. after the stall condition is cleared, the encoding process will be started automatically. jpeg+0120h jpeg encoder 1 st base address register jpg_enc_dest_a ddr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1102 of 1535 name bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bs_addr[15:0] type r/w reset 0 bs_addr base address1 of encoded data. in the single shooting mode and continuous shooting mode without automatic address, hardware will use this address setting. in continuous shooting mode with automatic address switching, frame0, 2, 4..etc will use this address setting. jpeg+0124h jpeg encoder 1 st dma address register jpg_enc_dma_a ddr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma_addr[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_addr[15:0] type ro reset 0 curr_addr the current dma address during encoding. in the single shooting mode, this dma address will represent the current encoded address. but this dma address will just represent the encoded address of fram0, 2, 4..etc in continuous shooting mode. jpeg+0128h jpeg encoder 1 st stall address register jpg_enc_stall_ addr1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name stall_addr[31:16] type r/w reset 32?hf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name stall_addr[15:0] type r/w reset 32?hf stall_addr this field is the upper bound of jpeg encoder?s write-address. note that the stall address must be word-aligned. whenever the stall address is reached, the jpeg encoder stalls and issues an interrupt to software. after, if the software programs the jpg_enc_stall_addr to another value, the jpeg encoder resumes the encoding procedure and automatically uses the jpg_enc_dest_addr as the new starting address. it means that before we change the value of jpg_enc_stall_addr, the jpg_enc_dest_addr has to be programmed to a corresponding starting address. however, if the software wants to discard the uncompleted file, it can simply reset the jpeg encoder to cancel the encode operation. also, it is important that the value of jpg_enc_stall_addr should be larger than jpg_enc_dest_addr by at least 608 bytes to guarantee that the header of the jpeg file can be completely written into memory. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1103 of 1535 jpeg+012ch jpeg encoder 2 nd base address register jpg_enc_dest_a ddr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bs_addr[15:0] type r/w reset 0 bs_addr base address of 2 nd encoded data. in the single shooting mode and continuous shooting mode without automatic address, hardware will not use this address setting. in continuous shooting mode with automatic address switching, frame1, 3, 5..etc will use this address setting. jpeg+0130h jpeg encoder 2 nd dma address register jpg_enc_dma_a ddr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dma_addr2[31:16] type ro reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_addr2[15:0] type ro reset 0 dma_addr2 the current dma address during 2 nd encoding. in the single shooting mode, this dma address will represent the current encoded address. but this dma address will just represent the encoded address of fram1, 3, 5..etc in continuous shooting mode. jpeg+0134h jpeg encoder 2 nd stall address register jpg_enc_stall_ addr2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name stall_addr2[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name stall_addr2[15:0] type r/w reset 0 stall_addr2 this field is the upper bound of jpeg encoder?s write-address2. note that the stall address2 only works in continuous shooting and memory auto-switch mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1104 of 1535 jpeg+0138h jpeg encoder offset address register jpg_enc_off set_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name offset_addr type r/w reset 0 offset_addr offset address from the ending of the last frame in the continuous shooting mode. this address must be 4-byte align. offset_addr should be set to 0 (before enabling jpeg encoder) if we don?t need this function. because the starting destination address always use the following equation to cacluate the new starting destination jpeg encoder uses. ) _ _ _ ( _ _ addr dest curr addr offset addr dest new + = 5.20 lcd interface 5.20.1 general description MT6516 contains a versatile lcd controller which is optimized for multimedia applications. this controller supports many types of lcd modules and contains a rich feature set to enhance the functionality. these features are: z up to 640 x 480 resolution z the internal frame buffer supports 8bpp indexed color, rgb 565, rgb 888 and argb 8888 format. z supports 8-bpp (rgb332), 12-bpp (rgb444), 16-bpp (rgb565), 18-bit (rgb666) and 24-bit (rgb888) lcd modules. z 6 layers overlay with individual color depth, window size, vertical and horizontal offset, source key, alpha value and display rotation control(90,180, 270, mirror and mirror then 90, 180 and 270) z one color look-up table z three gamma correction tables z 3x3 matrix for color management for parallel lcd modules, the lcd controller can reuse external memory interface or use dedicated 8/9/16/18-bit parallel interface to access them and 8080 type interface is supported. it can transfer the display data from the internal sram or external sram/flash memory to the off-chip lcd modules. for serial lcd modules, this interface performs parallel to serial conversion and both 8- and 9- bit serial interface is supported. the 8-bit serial interface uses four pins ? lsce#, lsda, lsck and lsa0 ? to enter commands and data. meanwhile, the 9-bit serial interface uses three pins ? lsce#, lsda and lsck ? for the same purpose. data read is not available with the serial interface and data entered must be 8 bits. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1105 of 1535 lpce0# lpce1# lrst# lrd# lpa0 lwr# nld[17:0] lsce0# lsce1# lsda lsa0 lsck layer 3 controller layer 1 controller parallel lcd channel controller serial lcd channel controller overlay lcd ahb master layer 0 controller layer 2 controller ahb bus lut layer 5 controller layer 4 controller figure 138 lcd interface block diagram figure 139 shows the timing diagram of this serial interface. when the block is idle, lsck is forced low and lsce# is forced high. once the data register contains data and the interface is enabled, lsce# is pulled low and remain low for the duration of the transmission. 8-bit serial interface lsck(sph=spo=0) lsda d7 d6 d5 d4 d3 d2 d1 d0 lsce# lsa0 9-bit serial interface lsck(sph=spo=0) lsda a0 d7 d6 d5 d4 d3 d2 d1 d0 lsce# lsa0 figure 139 lcd interface transfer timing diagram free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1106 of 1535 lcd = 0x8012_0000 address register function width acronym lcd + 0000h lcd interface status register 16 lcd_sta lcd + 0004h lcd interface interrupt enable register 16 lcd_inten lcd + 0008h lcd interface interrupt status register 16 lcd_intsta lcd + 000ch lcd interface frame transfer register 16 lcd_start lcd + 0010h lcd parallel/serial lcm reset register 16 lcd_rstb lcd + 0014h lcd serial interface configuration register 16 lcd_scnf lcd + 0018h lcd parallel interface 0 configuration register 32 lcd_pcnf0 lcd + 001ch lcd parallel interface 1 configuration register 32 lcd_pcnf1 lcd + 0020h lcd parallel interface 2 configuration register 32 lcd_pcnf2 lcd + 0024h lcd tearing control register 16 lcd_tecon lcd + 0028h lcd parallel interface data width configuration register 32 lcd_pcnfdw lcd + 0030h lcd roi window write to memory address register 0 32 lcd_wroi_w2madd0 lcd + 0034h lcd roi window write to memory address register 1 32 lcd_wroi_w2madd1 lcd + 0038h lcd roi window write to memory address register 2 32 lcd_wroi_w2madd2 lcd + 0040h lcd main window size register 32 lcd_mwinsize lcd + 0044h lcd roi window write to memory offset register 32 lcd_wroi_w2mofs lcd + 0048h lcd roi window write to memory control register 16 lcd_wroi_w2mcon lcd + 004ch region of interest window format register 16 lcd_wroifmt lcd + 0050h lcd roi window control register 32 lcd_wroicon lcd + 0054h lcd roi window offset register 32 lcd_wroiofs lcd + 0058h lcd roi window command start address register 16 lcd_wroicadd lcd + 005ch lcd roi window data start address register 16 lcd_wroidadd lcd + 0060h lcd roi window size register 32 lcd_wroisize lcd + 0064h lcd roi window hardware refresh register 32 lcd_wroi_hwref lcd + 0068h lcd roi direct couple register 32 lcd_wroi_dc lcd + 006ch lcd roi window background color register 32 lcd_wroi_bgclr lcd + 0070h lcd layer 0 window control register 32 lcd_l0wincon lcd + 0074h lcd layer 0 source color key register 32 lcd_l0winskey lcd + 0078h lcd layer 0 window display offset register 32 lcd_l0winofs lcd + 007ch lcd layer 0 window display start address register 32 lcd_l0winadd lcd + 0080h lcd layer 0 window size 32 lcd_l0winsize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1107 of 1535 lcd + 0084h lcd layer 0 scroll start offset 32 lcd_l0winscrl lcd + 0090h lcd layer 1 window control register 32 lcd_l1wincon lcd + 0094h lcd layer 1 source color key register 32 lcd_l1winskey lcd + 0098h lcd layer 1 window display offset register 32 lcd_l1winofs lcd + 009ch lcd layer 1 window display start address register 32 lcd_l1winadd lcd + 00a0h lcd layer 1 window size 32 lcd_l1winsize lcd + 00a4h lcd layer 1 scroll start offset 32 lcd_l1winscrl lcd + 00b0h lcd layer 2 window control register 32 lcd_l2wincon lcd + 00b4h lcd layer 2 source color key register 32 lcd_l2winskey lcd + 00b8h lcd layer 2 window display offset register 32 lcd_l2winofs lcd + 00bch lcd layer 2 window display start address register 32 lcd_l2winadd lcd + 00c0h lcd layer 2 window size 32 lcd_l2winsize lcd + 00c4h lcd layer 2 scroll start offset 32 lcd_l2winscrl lcd + 00d0h lcd layer 3 window control register 32 lcd_l3wincon lcd + 00d4h lcd layer 3 source color key register 32 lcd_l3winskey lcd + 00d8h lcd layer 3 window display offset register 32 lcd_l3winofs lcd + 00dch lcd layer 3 window display start address register 32 lcd_l3winadd lcd + 00e0h lcd layer 3 window size 32 lcd_l3winsize lcd + 00e4h lcd layer 3 scroll start offset 32 lcd_l3winscrl lcd + 00f0h lcd layer 4 window control register 32 lcd_l4wincon lcd + 00f4h lcd layer 4 source color key register 32 lcd_l4winskey lcd + 00f8h lcd layer 4 window display offset register 32 lcd_l4winofs lcd + 00fch lcd layer 4 window display start address register 32 lcd_l4winadd lcd + 0100h lcd layer 4 window size 32 lcd_l4winsize lcd + 0104h lcd layer 4 scroll start offset 32 lcd_l4winscrl lcd + 0110h lcd layer 5 window control register 32 lcd_l5wincon lcd + 0114h lcd layer 5 source color key register 32 lcd_l5winskey lcd + 0118h lcd layer 5 window display offset register 32 lcd_l5winofs lcd + 011ch lcd layer 5 window display start address register 32 lcd_l5winadd lcd + 0120h lcd layer 5 window size 32 lcd_l5winsize lcd + 0124h lcd layer 5 scroll start offset 32 lcd_l5winscrl lcd + 0130h lcd color management coefficient row 0 32 lcd_cm_coef_row0 lcd + 0134h lcd color management coefficient row 1 32 lcd_cm_coef_row1 lcd + 0138h lcd color management coefficient row 2 32 lcd_cm_coef_row2 lcd + 0140h lcd piece-wise linear gamma segment 0~20 32 lcd_gma0~20 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1108 of 1535 ~0193h lcd + 0200h frame buffer compression target rate 32 fbce_target_rate lcd + 0204h frame buffer compression input mode 2 fbce_input_mode lcd + 0208h frame buffer compression start 1 fbce_act_en lcd + 0210h frame buffer compression status 5 fbce_status lcd + 0220h frame buffer decompression control register fbcd_con lcd + 4000h lcd parallel interface 0 data 32 lcd_pdat0 lcd + 4100h lcd parallel interface 0 command 32 lcd_pcmd0 lcd + 5000h lcd parallel interface 1 data 32 lcd_pdat1 lcd + 5100h lcd parallel interface 1 command 32 lcd_pcmd1 lcd + 6000h lcd parallel interface 2 data 32 lcd_pdat2 lcd + 6100h lcd parallel interface 2 command 32 lcd_pcmd2 lcd + 8000h lcd serial interface 1 data 16 lcd_sdat1 lcd + 8100h lcd serial interface 1 command 16 lcd_scmd1 lcd + 9000h lcd serial interface 0 data 16 lcd_sdat0 lcd + 9100h lcd serial interface 0 command 16 lcd_scmd0 lcd + c000h ~ cffch lcd gamma correction lut register 32 lcd_gamma lcd + d000h ~ d3fch lcd color palette lut register 32 lcd_pal lcd + d400h ~ d47ch lcd interface command/parameter0 register 32 lcd_comd0 lcd + d480h ~ d4fch lcd interface command/parameter1 register 32 lcd_comd1 table 115 memory map of lcd interface 5.20.2 register definitions lcd +0000h lcd interface st atus register lcd_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name te_pe nd cmd_ cpen d data_ pend run type r r r r reset 0 0 0 0 run lcd interface running status data_pend data pending indicator in hardware trigger mode cmd_pend command pending indicator in hardware triggered refresh mode te_pend waiting tearing effect signal lcd +0004h lcd interface interrupt enable register lcd_inten bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1109 of 1535 name fbcd_ err te_de t cmd_ cpl data_ cpl cpl type r/w r/w r/w r/w r/w reset 0 0 0 0 0 cpl lcd frame transfer complete interrupt control data_cpl data transfer complete in hardware triggered refresh mode interrupt control cmd_cpl command transfer complete in hardware trigger refresh mode interrupt control te_det tearing effect signal detection interrupt control fbcd_err frame buffer decompression error interrupt control lcd +0008h lcd interface interrupt status register lcd_intsta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbcd_ err te_de t cmd_ cpl data_ cpl cpl type r/w r r r r reset 0 0 0 0 0 cpl lcd frame transfer complete interrupt data_cpl data transfer complete in hardware triggered refresh mode interrupt cmd_cpl command transfer complete in hardware triggered refresh mode interrupt te_det tearing effect signal detection interrupt fbcd_err frame buffer decompression error interrupt lcd +000ch lcd interface frame tr ansfer register lcd_start bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start type r/w reset 0 start start control of lcd frame transfer lcd +0010h lcd parallel/serial interface reset register lcd_rstb bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type r/w reset 1 rstb parallel/serial lcd module reset control lcd +0014h lcd serial interface configuration register lcd _scnf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 52m 26m gamma_id non_ dbi csp1 csp0 cmr cmg cmb 8/9 div sph spo type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 11 0 0 0 0 0 0 0 0 0 0 spo clock polarity control sph clock phase control div serial clock divide select bits free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1110 of 1535 0 reserved 1 engine clock/4 2 engine clock/8 3 engine clock/16 8/9 8-bit or 9-bit interface selection cmb color management for blue component. cmg color management for green component. cmr color management for red component. csp0 serial interface chip select 0 polarity control csp1 serial interface chip select 1 polarity control non_dbi non-dbi protocol serial interface 0 dbi type c serial interface, 8 or 9 bits per transaction 1 non-dbi type c serial interface, 8/9/16/18/24/32 bits per transaction if the transmission source is layer update or command queue, the bits per transaction is defined in lcd_fmt[8:6]. if the transmission source is from ahb bus write command, the bits per transaction is defined by the data width of this ahb write command. if ?8/9? bit is set, the first bit of transmission depends on the address of this write. if the write address is lcd_sdat1 or lcd_sdat0, the first bit is 0. if the write address is lcd_scmd1 or lcd_scmd0, the first bit is 1. gamma_id gamma correction lut id 00 table 0 01 table 1 10 table 2 11 no table selected 26m enable 26mhz clock gating. 52m enable 52mhz clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1111 of 1535 8bit (8/9=0, non_dbi=0) lsck (sph,sp0)=(1,1 ) lsck (sph,sp0)=(1,0 ) lsck (sph,sp0)=(0,1 ) lsck (sph,sp0)=(0,0 ) lsce# lsa0 lsda d7 d6 d5 d4 d3 d2 d1 d0 9bit (8/9=1, non_dbi=0) lsck lsce# lsda a0 d7 d6 d5 d4 d3 d2 d1 d0 16bit (8/9=0, non_dbi=1) lsck lsce# lsa0 lsda d15 d14 d13 d12 d11 d10 d9 d3 d2 d1 d0 16bit+a0 (8/9=1, non dbi=1 ) lsck lsce# lsa0 a0 d15 d14 d13 d12 d11 d10 d4 d3 d2 d1 d0 lsda lcd +0018h lcd parallel interface configuration register 0 lcd_pcnf0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name c2ws c2wh c2rs gamma_id_r gamma_id_g gamma_id_b dw type r/w r/w r/w r/w r/w r/w 0 0 0 11 11 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 52m 26m wst cmr cmg cmb rlt type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1112 of 1535 rlt read latency time cmb color management for blue component. cmg color management for green component. cmr color management for red component. wst write wait state time 26m enable 26mhz clock gating. 52m enable 52mhz clock gating. dw move to lcd_pcnfdw lcd+0028h gamma_id _r gamma correction lut id for red component 00 table 0 01 table 1 10 table 2 11 no table selected gamma_id_g gamma correction lut id for green component 00 table 0 01 table 1 10 table 2 11 no table selected gamma_id_b gamma correction lut id for blue component 00 table 0 01 table 1 10 table 2 11 no table selected c2rs chip select (lpce#) to read strobe (lrd#) setup time c2wh chip select (lpce#) to write strobe (lwr#) hold time c2ws chip select (lpce#) to write strobe (lwr#) setup time lcd +001ch lcd parallel interface c onfiguration register 1 lcd_pcnf1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name c2ws c2wh c2rs gamma_id dw type r/w r/w r/w r/w 0 0 0 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 52m 26m wst cmr cmg cmb rlt type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 rlt read latency time cmb color management for blue component. cmg color management for green component. cmr color management for red component. wst write wait state time 26m enable 26mhz clock gating. 52m enable 52mhz clock gating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1113 of 1535 dw move to lcd_pcnfdw lcd+0028h gamma_id gamma correction lut id 00 table 0 01 table 1 10 table 2 11 no table selected c2rs chip select (lpce#) to read strobe (lrd#) setup time c2wh chip select (lpce#) to write strobe (lwr#) hold time c2ws chip select (lpce#) to write strobe (lwr#) setup time lcd +0020h lcd parallel interface configuration register 2 lcd_pcnf2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name c2ws c2wh c2rs gamma_id dw type r/w r/w r/w r/w 0 0 0 11 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 52m 26m wst cmr cmg cmb rlt type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 rlt read latency time cmb color management for blue component. cmg color management for green component. cmr color management for red component. wst write wait state time 26m enable 26mhz clock gating. 52m enable 52mhz clock gating. dw move to lcd_pcnfdw lcd+0028h gamma_id gamma correction lut id 00 table 0 01 table 1 10 table 2 11 no table selected c2rs chip select (lpce#) to read strobe (lrd#) setup time c2wh chip select (lpce#) to write strobe (lwr#) hold time c2ws chip select (lpce#) to write strobe (lwr#) setup time free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1114 of 1535 paralle interface write timing c2ws=2, wst=3, c2wh=0, c2ws must <= wst lcd engine clk lpa0 lpce[0-2]b lwrb nld[xx:0] c2ws wst+1 c2wh+1 read timing c2rs=1, rlt=3 lcd engine clk lpa0 lpce[0-2]b lrdb nld[xx:0] c2rs rlt+2 lcd controller synchronization modes when te_en is enabled, lcd controller will synchronize its updating to lcm refresh timing. and it supports two synchronizing modes depending on te_mode. te_mode value synchronization mode 0 vertical synchronization mode. lcd controller starts to update lcm when it detects a te signal. 1 vertical and horizontal synchronization mode. lcd controller starts to update lcm when it detects a vertical te and following (te_hs_cnt_match_value+1) horizontal tes. table 116 lcd controller synchronization mode te signal polarity free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1115 of 1535 te_edge_sel can be used to select te polarity for te signal detection. te_edge_sel value te signal detection 0 detect a te signal at its rising edge. this setting is for active high te signal. 1 detect a te signal at its falling edge. this setting if for active low te signal. table 117 te signal polarity vertical synchronization mode in vertical synchronization mode, the lcd controller assumes te input is only a vertical synchronization signal. in this mode, lcd controller starts to update lcm after each rising edge of the te input (or falling edge, if te_edge_sel is set to 1) (see figure 3). in this mode, te_vs_width_limit, te_vs_width_cnt_div, te_hs_cnt_match_value are not used. figure 140 vertical synchronization mode vertical and horizontal synchronization mode in vertical and horizontal synchronization mode, the lcd controller assumes te input is an or of vertical and horizontal synchronization signal. te_vs_width_limit gives the minimum time that te input must stay active to be detected by the lcd controller as a vertical synchronization. this time is (te_vs_width_limit+1)*( divisor specified by te_vs_width_cnt_div) clock cycles. any pulse longer than this time is considered a vertical synchronization. any pulse shorter than this time is considered a horizontal synchronization. once a vertical synchronization has been detected, the lcd controller counts the active edges on the te input. when the number of active edges reaches te_hs_cnt_match_value, lcd controller starts to update lcm. if a new vertical synchronization is detected before hs_cnt_match_value horizontal synchro have been detected, the counter is reset and horizontal synchronization count begins once again (see figure 4). te input lcd updating vertical synchro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1116 of 1535 figure 141 vertical and horizontal synchronization mode lcd +0024h lcd tearing control register lcd_tecon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name te_vs_width_limit te_vs_wid th_cnt_di v type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name te_hs_cnt_match_value te_re peat te_m ode te_ed ge_se l te_en type r/w r/w r/w r/w r/w reset na 0 0 0 0 te_en enable tearing control. lcd controller will synchronize to lcm refresh timing. te_edge_sel select sync edge. 0 rising edge 1 falling edge te_mode tearing control mode. 0 start transmission to lcd after te edge. 1 wait (te_hs_cnt_match_value+1) lines after vertical te edge to start transmission to lcd. te_repeat repeat mode. 0 update lcm once every te signal coming. 1 repeat updating lcm after te signal coming. te_hs_cnt_match_value trigger lcd update after delaying (te_hs_cnt_match_value+1) lines after vertical te edge. te_vs_width_cnt_div engine clock divisor for vertical te detection. 00 divide engine clock by 8 01 divide engine clock by 16 te input lcd updating (te_hs_cnt_match_value=0) lcm vertical blank lcm horizontal lcd updating (te_hs_cnt_match_value=2) (te_vs_width_limit+1)*( divisor specified by te_vs_width_cnt_div) vertical synchro horizontal synchro free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1117 of 1535 10 divide engine clock by 32 11 divide engine clock by 64 te_vs_width_limit if the width of a te pulse is larger than (te_vs_width_limit+1)* (divisor specified by te_vs_width_cnt_div), it is a vertical te, otherwise it is a horizontal te. lcd +0028h lcd parallel interface data width configuration register lcd_pcnfdw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pcnf2_dw type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pcnf1_dw pcnf0_dw type r/w r/w pcnf0_dw data width of parallel interface 0 000 8 bit 001 9 bit 010 16 bit 011 18 bit 100 24 bit others reserved pcnf1_dw data width of parallel interface 1, bit encode is the same as pcnf0_dw pcnf2_dw data width of parallel interface 2, bit encode is the same as pcnf0_dw lcd +4000h lcd parallel 0 interface data lcd_pdat0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w data writing to lcd+4000 will drive lpa0 low when sending this data out in parallel bank0, while writing to lcd+4100 will drive lpa0 high. lcd +5000h lcd parallel 1 interface data lcd_pdat1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w data writing to lcd+5000 will drive lpa1 low when sending this data out in parallel bank1, while writing to lcd+5100 will drive lpa1 high free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1118 of 1535 lcd +6000h lcd parallel 2 interface data lcd_pdat2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data[15:0] type r/w data writing to lcd+6000 will drive lpa2 low when sending this data out in parallel bank2, while writing to lcd+6100 will drive lpa2 high lcd +8000/8100h lcd serial interface 1 data lcd_sdat1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data type w data writing to lcd+8000 will drive lsa0 low while sending this data out in serial bank1, while writing to lcd+8100 will drive lsa0 high lcd +9000/9100h lcd serial interface 0 data lcd_sdat0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data type w data writing to lcd+9000 will drive lsa0 low while sending this data out in serial bank0, while writing to lcd+9100 will drive lsa0 high lcd +0030h region of interest window write to memory address fb0 register lcd_wroi_w2 madd0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w2m_addr0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w2m_addr0 type r/w w2m_addr0 write to memory address for frame buffer 0. this address must be 8byte-aligned. lcd +0034h region of interest window write to memory address fb1 register lcd_wroi_w2 madd1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w2m_addr1 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w2m_addr1 type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1119 of 1535 w2m_addr1 write to memory address for frame buffer 1. this address must be 8byte-aligned. lcd +0038h region of interest window write to memory address fb2 register lcd_wroi_w2 madd2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w2m_addr2 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w2m_addr2 type r/w w2m_addr2 write to memory address for frame buffer 2. this address must be 8byte-aligned. lcd +0040h main window size register lcd_mwinsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w column 10-bit virtual image window column size row 10-bit virtual image window row size lcd +0044h region of interest window write to memory offset register lcd_wroi_w2 mofs bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w this control register is used to specify the offset of the roi window from the lcd_wroi_w2maddr when writing the roi window?s content to memory. x-offset the x offset of roi window in the destination memory. y-offset the y offset of roi window in the destination memory. lcd +0048h region of interest window write to memory control register lcd_wroi_w2 mcon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wb_di s dly_e n fbse q_rst fb2_e n fb1_e n type r/w r/w r/w r/w r/w reset 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name output_alpha dc_o ut_en addin c_dis able disco n w2m_forma t w2lc m type r/w r/w r/w r/w r/w r/w reset 0xff 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1120 of 1535 this control register is effective only when the w2m bit is set in lcd_wroicon register. w2lcm write to lcm simultaneously. w2m_format write to memory format. 00 rgb565 01 rgb888 10 argb8888 discon block write enable control. by setting both discon and w2m to 1, the lcd controller will write out the roi pixel data as a part of main window, using the width of main window to calculate the write- out address. if this bit is not set, the roi window will be written to memory in continuous addresses. addinc_disable disable address increase when writing to memory. dc_out_en enable direct couple to rotator 3. output_alpha output alpha value. fb1_en enable frame buffer 1, which starting address is lcd_wroi_w2madd1. fb2_en enable frame buffer 2, which starting address is lcd_wroi_w2madd2. dly_en enable that lcd overlay engine start to write to memory after dpi indication. wb_dis disable lcd dedicated write buffer. the write buffer is used to enhance the memory write efficiency. fbseq_rst reset the next update frame buffer to fb0. this bit will remain 1 after set until it takes effect. lcd +004ch region of interest wind ow format register lcd_wroifmt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dsi swp en_bl s wr2d si format type r/w r/w r/w r/w format lcd module data format bit 0 : in bgr sequence, otherwise in rgb sequence. bit 1 : lsb first, otherwise msb first. bit 2 : padding bits on msbs, otherwise on lsbs. bit 5-3 : 000 for rgb332, 001 for rgb444, 010 for rgb565, 011 for rgb666, 100 for rgb888. bit 8-6 : 000 for 8-bit interface, 001 for 16-bit interface, 010 for 9-bit interface, 011 for 18-bit interface, 100 for 24-bit interface, others for reserved. note: when the interface is configured as 9 bit or 18 bit, the field of bit5-2 is ignored. wr2dsi write to dsi. en_bls enable back light scaling. dsi_swp swap data order for dsi transmission. 1: low byte first, 0: high byte first 00000000 8bit 1cycle/1pixel rgb3.3.2 rrr ggg bb 00000001 1cycle/1pixel rgb3.3.2 bb ggg rrr 00001000 3cycle/2pixel rgb4.4.4 rrrrgggg bbbbrrrr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1121 of 1535 ggggbbbb 00001011 3cycle/2pixel rgb4.4.4 ggggrrrr rrrrbbbb bbbbgggg 00010000 2cycle/1pixel rgb5.6.5 rrrrrggg gggbbbbb 00010011 2cycle/1pixel rgb5.6.5 gggrrrrr bbbbbggg 00011000 3cycle/1pixel rgb6.6.6 rrrrrrxx ggggggxx bbbbbbxx 00011100 3cycle/1pixel rgb6.6.6 xxrrrrrr xxgggggg xxbbbbbb 00100000 3cycle/1pixel rgb8.8.8 rrrrrrrr gggggggg bbbbbbbb 10xxxx00 9bit 2cycle/1pixel rgb6.6.6 rrrrrrggg gggbbbbbb 10xxxx11 2cycle/1pixel rgb6.6.6 gggrrrrrr bbbbbbggg 01000000 16bit 1cycle/2pixel rgb3.3.2 rrrgggbbrrrgggbb 01000010 1cycle/2pixel rgb3.3.2 rrrgggbbrrrgggbb 01000001 1cycle/2pixel rgb3.3.2 bbgggrrrbbgggrrr 01000011 1cycle/2pixel rgb3.3.2 bbgggrrrbbgggrrr 01001100 1cycle/1pixel rgb4.4.4 xxxxrrrrggggbbbb 01001101 1cycle/1pixel rgb4.4.4 xxxxbbbbggggrrrr 01001000 1cycle/1pixel rgb4.4.4 rrrrggggbbbbxxxx 01001001 1cycle/1pixel rgb4.4.4 bbbbggggrrrrxxxx 01010000 1cycle/1pixel rgb5.6.5 rrrrrggggggbbbbb 01010001 1cycle/1pixel rgb5.6.5 bbbbbggggggrrrrr 01011100 3cycle/2pixel rgb6.6.6 xxxxrrrrrrgggggg xxxxbbbbbbrrrrrr xxxxggggggbbbbbb 01011111 3cycle/2pixel rgb6.6.6 xxxxggggggrrrrrr xxxxrrrrrrbbbbbb xxxxbbbbbbgggggg 01011000 3cycle/2pixel rgb6.6.6 rrrrrrggggggxxxx bbbbbbrrrrrrxxxx ggggggbbbbbbxxxx 01011011 3cycle/2pixel rgb6.6.6 ggggggrrrrrrxxxx rrrrrrbbbbbbxxxx free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1122 of 1535 bbbbbbggggggxxxx 01100000 3cycle/2pixel rgb8.8.8 rrrrrrrrgggggggg bbbbbbbbrrrrrrrr ggggggggbbbbbbbb 01100011 3cycle/2pixel rgb8.8.8 ggggggggrrrrrrrr rrrrrrrrbbbbbbbb bbbbbbbbrrrrrrrr 11xxxx00 18bit 1cycle/1pixel rgb6.6.6 rrrrrrggggggbbbbbb 11xxxx01 1cycle/1pixel rgb6.6.6 bbbbbbggggggrrrrrr 11100000 3cycle/2pixel rgb8.8.8 rrrrrrrrgggggggg bbbbbbbbrrrrrrrr ggggggggbbbbbbbb 11100011 3cycle/2pixel rgb8.8.8 ggggggggrrrrrrrr rrrrrrrrbbbbbbbb bbbbbbbbrrrrrrrr lcd +0050h region of interest wind ow control register lcd_wroicon bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en0 en1 en2 en3 en4 en5 period type r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enc w2m com_sel command format type r/w r/w r/w r/w format move to lcd_wroifmt lcd+004ch com_sel command queue id selection command number of commands to be sent to lcd module. maximum is 31. w2m enable write to memory enc command transfer enable control period waiting period between two consecutive transfers, effective for both data and command. enn layer window enable control lcd +0054h region of interest window offset register lcd_wroiofs bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w x-offset roi window column offset y-offset roi window row offset lcd +0058h region of interest window command start address register lcd_wroicad d bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1123 of 1535 type r/w addr roi window command address. only writing to lcd modules is allowed. lcd +005ch region of interest window data start address register lcd_wroidad d bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr roi window data address only writing to lcd modules is allowed. lcd +0060h region of interest window size register lcd_wroisize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w column roi window column size row roi window row size lcd +0064h region of interest window hardware refresh register lcd_wroi_hw ref bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en0 en1 en2 en3 en4 en5 hwref_sel type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hwen hwre f type r/w r/w reset 0 0 en n enable layer n source address from image_dma. hwen enable hardware triggered lcd fresh. hwref_sel select hardware triggered source. 00 triggered by irt1. 01 triggered by ibw1. 10 triggered by irt2 (without base address). 11 triggered by ibw2 (without base address). hwref starting the hardware triggered lcd frame transfer. lcd +0068h region of interest window direct couple register lcd_wroi_dc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en0 en1 en2 en3 en4 en5 type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1124 of 1535 name dc_sel0 dc_sel1 dc_sel2 dc_sel3 dc_sel4 dc_sel5 type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 en n enable layer n source data from image_dma. dc_seln select source layer n data. 00 reserved. 01 ibw1 10 irt2 11 ibw2 note : when direct couple is enabled on mulitple layers, the source data of each layer should be different. lcd +006ch region of interest background color register lcd_wroi_bg clr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name red[7:0] type r/w reset 1111_1111 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name green[7:0] blue[7:0] type r/w r/w reset 1111_1111 1111_1111 red red component of roi window?s background color green green component of roi window?s background color blue blue component of roi window?s background color lcd +0070h layer 0 window control register lcd_l0winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1125 of 1535 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +0074h layer 0 source color key register lcd_l0winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +0078h layer 0 window display offset register lcd_l0winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 0 window row offset x-offset layer 0 window column offset lcd+007ch layer 0 window display start address register lcd_l0winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 0 window data address. note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1126 of 1535 lcd +0080h layer 0 window size lcd_l0winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 0 window row size column layer 0 window column size lcd +0084h layer 0 scroll start offset lcd_l0winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 0 scroll start row offset, its value must satisfy y-offset < lcd_l0winsize.row x-offset layer 0 scroll start column offset, its value must satisfy x-offset < lcd_l0winsize.column lcd +0090h layer 1 window control register lcd_l1winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1127 of 1535 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +0094h layer 1 source color key register lcd_l1winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +0098h layer 1 window display offset register lcd_l1winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 1 window row offset x-offset layer 1 window column offset lcd+009ch layer 1 window display start address register lcd_l1winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 1 window data address. note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1128 of 1535 lcd +00a0h layer 1 window size lcd_l1winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 1 window row size column layer 1 window column size lcd +00a4h layer 1 scroll start offset lcd_l1winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 1 scroll start row offset, its value must satisfy y-offset < lcd_l1winsize.row x-offset layer 1 scroll start column offset, its value must satisfy x-offset < lcd_l1winsize.column lcd +00b0h layer 2 window control register lcd_l2winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1129 of 1535 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +00b4h layer 2 source color key register lcd_l2winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +00b8h layer 2 window display offset register lcd_l2winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 2 window row offset x-offset layer 2 window column offset lcd+00bch layer 2 window display start address register lcd_l2winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 1 window data address note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1130 of 1535 lcd +00c0h layer 2 window size lcd_l2winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 2 window row size column layer 2 window column size lcd +00c4h layer 2 scroll start offset lcd_l2winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 2 scroll start row offset, its value must satisfy y-offset < lcd_l2winsize.row x-offset layer 2 scroll start column offset, its value must satisfy x-offset < lcd_l2winsize.column lcd +00d0h layer 3 window control register lcd_l3winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1131 of 1535 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +00d4h layer 3 source color key register lcd_l3winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +00d8h layer 3 window display offset register lcd_l3winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 3 window row offset x-offset layer 3 window column offset lcd+00dch layer 3 window display start address register lcd_l3winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 3 window data address note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1132 of 1535 lcd +00e0h layer 3 window size lcd_l3winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 3 window row size column layer 3 window column size lcd +00e4h layer 3 scroll start offset lcd_l3winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 3 scroll start row offset, its value must satisfy y-offset < lcd_l3winsize.row x-offset layer 3 scroll start column offset, its value must satisfy x-offset < lcd_l3winsize.column lcd +00f0h layer 4 window control register lcd_l4winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1133 of 1535 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +00f4h layer 4 source color key register lcd_l4winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +00f8h layer 4 window display offset register lcd_l4winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 4 window row offset x-offset layer 4 window column offset lcd+00fch layer 4 window display start address register lcd_l4winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 4 window data address note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1134 of 1535 lcd +0100h layer 4 window size lcd_l4winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 4 window row size column layer 4 window column size lcd +0104h layer 4 scroll start offset lcd_l4winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 4 scroll start row offset, its value must satisfy y-offset < lcd_l4winsize.row x-offset layer 4 scroll start column offset, its value must satisfy x-offset < lcd_l4winsize.column lcd +0110h layer 5 window control register lcd_l5winco n bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name read_ cach e_dis gma_ en scrl_ en swp type r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src keye n rotate clrdpt opae n opa type r/w r/w r/w r/w r/w r/w opa opacity value, used as constant alpha value. opaen opacity enabled clrdpt color format 00 8bpp indexed color. 01 rgb 565 10 argb 8888 11 rgb 888 rotate rotation configuration 000 0 degree rotation 001 90 degree rotation counterclockwise 010 180 degree rotation counterclockwise free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1135 of 1535 011 270 degree rotation counterclockwise 100 horizontal flip 101 horizontal flip then 90 degree rotation counterclockwise 110 horizontal flip then 180 degree rotation counterclockwise 111 horizontal flip then 270 degree rotation counterclockwise keyen source key enable control src disable auto-increment of the source pixel address swp swap high byte and low byte of pixel data scrl_en enable scroll effect gma_en enable piece-wise linear gamma correction read_cache_dis disable cache for this layer lcd +0114h layer 5 source color key register lcd_l5winsk ey bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name srckey[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srckey[15:0] type r/w srckey transparent color key of the source image. lcd +0118h layer 5 window display offset register lcd_l5winof s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 5 window row offset x-offset layer 5 window column offset lcd+011ch layer 5 window display start address register lcd_l5winad d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type r/w addr layer 5 window data address note that the layer start address must be 8byte-aligned. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1136 of 1535 lcd +0120h layer 5 window size lcd_l5winsiz e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name row type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name column type r/w row layer 5 window row size column layer 5 window column size lcd +01284h layer 5 scroll start offset lcd_l5winsc rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y-offset type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x-offset type r/w y-offset layer 5 scroll start row offset, its value must satisfy y-offset < lcd_l5winsize.row x-offset layer 5 scroll start column offset, its value must satisfy x-offset < lcd_l5winsize.column lcd+0130h color management matrix coefficient row0 lcd_coef_ro w0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coef_row0[29:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coef_row0[15:0] type r/w coef_row0 matrix row 0 for color management. each coefficient is represented in signed 2.8 format (10bits). lcd+0134h color management matrix coefficient row1 lcd_coef_ro w1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coef_row1[29:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coef_row1[15:0] type r/w coef_row1 matrix row 1 for color management. each coefficient is represented as signed 2.8 format (10bits). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1137 of 1535 lcd+0138h color management matrix coefficient row2 lcd_coef_ro w2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coef_row2[29:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coef_row2[15:0] type r/w coef_row2 matrix row 2 for color management. each coefficient is represented as signed 2.8 format (10bits). lcd+0140h ~ 0193h lcd piece-wise linear gamma segment 0~19 lcd_gma0~20 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name slope0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yoff0 xoff0 type r/w r/w coef_row2 matrix row 2 for color management. each coefficient is represented as signed 2.8 format (10bits). lcd+0200h frame buffer compression target rate fbce_target _rate bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fbce_line_length type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbce_target_rate type r/w reset 0 fbce_target_rate range from 12~24 for rgb888 input mode, and range from 10~16 for rgb565 input mode. the compression rate is as fbce_target_rate/24 for rgb888 input mode, and as fbce_target_rate/16 for rgb565 input mode. this rate is that how many bytes will be encoded for a set (8 pixels). ex. for rgb888, ratio=50%, then target rate = 24*50% = 12. rgb565, ratio=62.5%, then target rate = 16*62.5% = 10. maxima compression rate is 50% for rgb888, and 62.5% for rgb565. fbce_line_length the bit stream length of a compressed line. its value is calculated by the following equation. ?? 2 _ _ * 8 / _ _ _ _ + = rate target fbce line per pixels length line fbce lcd+0204h frame buffer compression input mode fbce_input_ mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1138 of 1535 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbce_ parti al fbce_input _mode type r/w r/w reset 0 0 fbce_input_mode 0 rgb888 1 rgb565 others reserved fbce_partial fbce partial update mode. lcd+0208h frame buffer compression start fbce_act_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbce _act _en type r/w reset 0 fbce_act_en frame buffer compression enable, it will start to encode after lcd_start is set. lcd+0210h frame buffer compression status fbce_status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbcd_ err flag2 flag1 flag 0 type r r r r flag0 encode residual < 0. flag1 encode flush with qfifo or efifo not zero. flag2 frame buffer compression is running. fbcd_err frame buffer decompression decoding error. lcd+0220h frame buffer decompression target rate fbcd_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en0 en1 en2 en3 en4 en5 fbcd_input _mode type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fbcd_line_length type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1139 of 1535 fbcd_line_length the bit stream length of a compressed line. its value is calculated by the following equation. ?? 2 _ _ * 8 / _ _ _ _ + = rate target fbce line per pixels length line fbce fbcd_input_mode 0 rgb888 1 rgb565 others reserved enn enable layer n source data from frame buffer decompression. lcd +c000h~cffch lcd interface gamma correctio n lut registers lcd_gamma bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma_lut2 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gamm_lut1 gamma_lut0 type r/w r/w gamma_lut0 these bits set gamma lut 0. gamma_lut1 these bits set gamma lut 1. gamma_lut2 these bits set gamma lut 2. lcd +d000h~d3fch lcd interface color palette lut registers lcd_pal bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lut type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lut type r/w lut these bits set color palette in rgb888 format. lcd +d400h~d4fc lcd interface comm and/parameter registers lcd_comd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name c0 comm[17:16] type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comm[15:0] type r/w comm command data and parameter data for lcd module c0 write to roi command address if c0 = 1, otherwise write to roi data address free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1140 of 1535 5.21 m3d 5.21.1 general descriptions the 3d hardware engine in the MT6516 is designed for opengl es v1.1 common/common-lite profile specification and direct3d mobile specification. with this hardware accelerator, can produce the high quality 3d image with high efficiency. MT6516 3d hardware block diagram : m3d engine accesses internal memory or external memory through gmc. see figure 1.1. figure 1.1 MT6516 3d top architecture MT6516 3d key feature : ? opengl es v1.1 common/common-lite feature set with extensions ? direct 3d mobile feature set ? point / line / triangle ? specular color / color sum ? color material, local viewer and light range for lighting calculation ? flat / gouraud shading ? fill mode (point / line / solid) ? user-defined clipping plane ? advanced scan converter algorithm ? texture coordinate wrapping ? texture addressing mode : repeat / clamp to edge / mirror / clamp / border ? perspective bi- / tri-linear texture filter m3d engine gmc emi internal memory external memory free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1141 of 1535 ? multi-texture ? dot3 bump mapping ? flexible texture input formats ? advanced texture compression ? support three data formats of frame buffer : rgb565, rgb888, argb8888 ? maximum resolution : 1024 x 1024 the graphics pipeline provides the housepower to efficiently process and render opengl es scenes to a display, taking advantage of available hardware. this figure conceptually illustrates the building blocks of the pipeline : free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1142 of 1535 figure 1.2 MT6516 3d graphics pipeline 5.21.2 register definitions m3d_base = 0x register address register function acronym m3d_base+000h m3d trigger register m3d_trigger m3d_base+004h m3d reset register m3d_reset m3d_base+008h m3d status register m3d_status m3d_base+00ch m3d interrupt enable register m3d_inten m3d_base+010h m3d interrupt status register m3d_intsta m3d_base+014h m3d fragment cache enable register m3d_frag_cache_enable m3d_base+018h m3d fragment cache flush register m3d_frag_cache_flush m3d_base+01ch m3d fragment cache invalidate register m3d_frag_cache_inval m3d_base+020h m3d fragment cache reset register m3d_frag_cache_reset m3d_base+024h m3d texture cache clear register m3d_tex_cache_clear m3d_base+028h m3d primitive mode register m3d_primitive_mode m3d_base+02ch m3d draw mode register m3d_primitive_draw_mode m3d_base+030h m3d vertex count register m3d_primitive_count m3d_base+034h m3d draw-array first index register m3d_draw_array_first free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1143 of 1535 m3d_base+038h m3d draw-array end index egister m3d_draw_array_end m3d_base+03ch m3d draw-element index type register m3d_draw_element_type m3d_base+040h m3d draw-element pointer register m3d_draw_element_pointer m3d_base+044h m3d primitive anti-aliasing register m3d_primitive_aa m3d_base+048h m3d polygon offset enable/disable register m3d_polygon_offset_enable m3d_base+04ch|84ch m3d polygon offset type register m3d_polygon_offset_factor m3d_base+050h|850h m3d polygon offset unit register m3d_polygon_offset_units m3d_base+054h|854h m3d line width register m3d_line_width m3d_base+058h m3d point-sprite register m3d_point_sprite m3d_base+05ch m3d vertex array register m3d_vertex m3d_base+060h m3d vertex array stride register m3d_vertex_stride_b m3d_base+064h m3d vertex array pointer register m3d_vertex_pointer m3d_base+068h m3d vertex cache pointer register m3d_vertex_cache_pointer m3d_base+06ch m3d bounding box control register m3d_bbox_expand m3d_base+070h m3d normal array type register m3d_normal_type m3d_base+074h m3d normal array stride register m3d_normal_stride_b m3d_base+078h m3d normal array pointer register m3d_normal_pointer m3d_base+07ch m3d color array register m3d_color_0 m3d_base+080h m3d color array type/size/input register m3d_color_1 m3d_base+084h m3d color array stride register m3d_color_stride_b_0 m3d_base+088h m3d color array stride register m3d_color_stride_b_1 m3d_base+08ch m3d color array pointer register m3d_color_pointer_0 m3d_base+090h m3d color array pointer register m3d_color_pointer_1 m3d_base+094h m3d debug port 0 m3d_dbgrd_0 m3d_base+098h m3d debug port 1 m3d_dbgrd_1 m3d_base+09ch m3d debug port 2 m3d_dbgrd_2 m3d_base+0a0h m3d debug port 3 m3d_dbgrd_3 m3d_base+0a4h m3d debug port 4 m3d_dbgrd_4 m3d_base+0a8h m3d texture coordinate 0 register m3d_tex_coord_0 m3d_base+0ach m3d texture coordinate 1 register m3d_tex_coord_1 m3d_base+0b0h m3d texture coordinate 2 register m3d_tex_coord_2 m3d_base+0b4h m3d texture array 0 stride register m3d_tex_coord_stride_b_0 m3d_base+0b8h m3d texture array 1 stride register m3d_tex_coord_stride_b_1 m3d_base+0bch m3d texture array 2 stride register m3d_tex_coord_stride_b_2 m3d_base+0c0h m3d texture array 0 pointer register m3d_tex_coord_pointer_0 m3d_base+0c4h m3d texture array 1 pointer register m3d_tex_coord_pointer_1 m3d_base+0c8h m3d texture array 2 pointer register m3d_tex_coord_pointer_2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1144 of 1535 m3d_base+0cch m3d point array register m3d_pnt_size_input m3d_base+0d0h|8d0h m3d point array size register m3d_pnt_size m3d_base+0d4h m3d point array stride register m3d_pnt_size_stride_b m3d_base+0d8h m3d point array pointer register m3d_pnt_size_pointer m3d_base+0dch m3d projection matrix type register m3d_proj_matrix_type m3d_base+0e0h m3d user-defined clipping plane enable/disable register m3d_clip_plane_enable m3d_base+0e4h m3d normal scale enable/disable register m3d_normal_scale_enable m3d_base+0e8h m3d line last pixel m3d_line_last_pixel m3d_base+0ech m3d primitive culling register m3d_cull m3d_base+0f0h m3d shading model register m3d_shade_model m3d_base+0f4h m3d/d3dm lighting control register m3d_light_ctrl m3d_base+0f8h m3d texture image #0 height/width/type/format register m3d_tex_img_0 m3d_base+0fch m3d texture image #1 height/width/type/format register m3d_tex_img_1 m3d_base+100h m3d texture image #2 height/width/type/format register m3d_tex_img_2 m3d_base+104h m3d texture control register m3d_tex_ctrl m3d_base+108h m3d texture image #0 level #0 address m3d_tex_img_ptr_0_0 m3d_base+10ch m3d texture image #0 level #1 address m3d_tex_img_ptr_0_1 m3d_base+110h m3d texture image #0 level #2 address m3d_tex_img_ptr_0_2 m3d_base+114h m3d texture image #0 level #3 address m3d_tex_img_ptr_0_3 m3d_base+118h m3d texture image #0 level #4 address m3d_tex_img_ptr_0_4 m3d_base+11ch m3d texture image #0 level #5 address m3d_tex_img_ptr_0_5 m3d_base+120h m3d texture image #0 level #6 address m3d_tex_img_ptr_0_6 m3d_base+124h m3d texture image #0 level #7 address m3d_tex_img_ptr_0_7 m3d_base+128h m3d texture image #0 level #8 address m3d_tex_img_ptr_0_8 m3d_base+12ch m3d texture image #1 level #0 address m3d_tex_img_ptr_1_0 m3d_base+130h m3d texture image #1 level #1 address m3d_tex_img_ptr_1_1 m3d_base+134h m3d texture image #1 level #2 address m3d_tex_img_ptr_1_2 m3d_base+138h m3d texture image #1 level #3 address m3d_tex_img_ptr_1_3 m3d_base+13ch m3d texture image #1 level #4 address m3d_tex_img_ptr_1_4 m3d_base+140h m3d texture image #1 level #5 address m3d_tex_img_ptr_1_5 m3d_base+144h m3d texture image #1 level #6 address m3d_tex_img_ptr_1_6 m3d_base+148h m3d texture image #1 level #7 address m3d_tex_img_ptr_1_7 m3d_base+14ch m3d texture image #1 level #8 address m3d_tex_img_ptr_1_8 m3d_base+150h m3d texture image #2 level #0 address m3d_tex_img_ptr_2_0 m3d_base+154h m3d texture image #2 level #1 address m3d_tex_img_ptr_2_1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1145 of 1535 m3d_base+158h m3d texture image #2 level #2 address m3d_tex_img_ptr_2_2 m3d_base+15ch m3d texture image #2 level #3 address m3d_tex_img_ptr_2_3 m3d_base+160h m3d texture image #2 level #4 address m3d_tex_img_ptr_2_4 m3d_base+164h m3d texture image #2 level #5 address m3d_tex_img_ptr_2_5 m3d_base+168h m3d texture image #2 level #6 address m3d_tex_img_ptr_2_6 m3d_base+16ch m3d texture image #2 level #7 address m3d_tex_img_ptr_2_7 m3d_base+170h m3d texture image #2 level #8 address m3d_tex_img_ptr_2_8 m3d_base+174h|974h m3d color r register m3d_color_r_0 m3d_base+178h|978h m3d color g register m3d_color_g_0 m3d_base+17ch|97ch m3d color b register m3d_color_b_0 m3d_base+180h|980h m3d color a register m3d_color_a_0 m3d_base+184h|984h m3d color r register m3d_color_r_1 m3d_base+188h|988h m3d color g register m3d_color_g_1 m3d_base+18ch|98ch m3d color b register m3d_color_b_1 m3d_base+190h|990h m3d color a register m3d_color_a_1 m3d_base+194h m3d drawtex tex1 cropper region u coord m3d_drawtex_cru_1 m3d_base+198h m3d scissor test enable/disable register m3d_scissor_enable m3d_base+19ch m3d scissor test left boundary register m3d_scissor_left m3d_base+1a0h m3d scissor test bottom boundary register m3d_scissor_bottom m3d_base+1a4h m3d scissor test right boundary register m3d_scissor_right m3d_base+1a8h m3d scissor test top boundary register m3d_scissor_top m3d_base+1ach m3d alpha test register m3d_alpha_test m3d_base+1b0h m3d stencil test register m3d_stencil_test m3d_base+1b4h m3d depth test register m3d_depth_test m3d_base+1b8h m3d blending register m3d_blend m3d_base+1bch m3d logic operation register m3d_logic_op m3d_base+1c0h m3d frame buffer format register m3d_frame_buf_format m3d_base+1c4h m3d frame buffer address register m3d_frame_buf_addr m3d_base+1c8h m3d frame buffer width register m3d_frame_buf_width m3d_base+1cch m3d frame buffer height register m3d_frame_buf_height m3d_base+1d0h reserve for internal use reserved m3d_base+1d4h m3d depth buffer address m3d_depth_buf_addr m3d_base+1d8h m3d stencil buffer address m3d_stencil_buf_addr m3d_base+1dch m3d depth buffer clear value m3d_depth_clear_val m3d_base+1e0h reserve for internal use reserved m3d_base+1e4h reserve for internal use reserved m3d_base+1e8h m3d earlyz test enable/disable register m3d_early_z_enable free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1146 of 1535 m3d_base+1ech m3d earlyz buffer address register m3d_early_z_buf_addr m3d_base+1f0h m3d drawtex tex1 cropper region v coord m3d_drawtex_crv_1 m3d_base+1f4h m3d drawtex tex1 cropper region delta u coord m3d_drawtex_dcru_1 m3d_base+1f8h m3d drawtex tex1 cropper region delta v coord m3d_drawtex_dcrv_1 m3d_base+1fch m3d interrupt status write ack m3d_intsta_wtack m3d_base+200h|a00h m3d texture #0 environment red color m3d_tex_env_color_r_0 m3d_base+204h|a04h m3d texture #0 environment green color m3d_tex_env_color_g_0 m3d_base+208h|a08h m3d texture #0 environment blue color m3d_tex_env_color_b_0 m3d_base+20ch|a0ch m3d texture #0 environment alpha color m3d_tex_env_color_a_0 m3d_base+210h|a10h m3d texture #1 environment red color m3d_tex_env_color_r_1 m3d_base+214h|a14h m3d texture #1 environment green color m3d_tex_env_color_g_1 m3d_base+218h|a18h m3d texture #1 environment blue color m3d_tex_env_color_b_1 m3d_base+21ch|a1ch m3d texture #1 environment alpha color m3d_tex_env_color_a_1 m3d_base+220h|a20h m3d texture #2 environment red color m3d_tex_env_color_r_2 m3d_base+224h|a24h m3d texture #2 environment green color m3d_tex_env_color_g_2 m3d_base+228h|a28h m3d texture #2 environment blue color m3d_tex_env_color_b_2 m3d_base+22ch|a2ch m3d texture #2 environment alpha color m3d_tex_env_color_a_2 m3d_base+230h|a30h m3d texture #0 mipmap lod bias m3d_lod_bias_0 m3d_base+234h|a34h m3d texture #1 mipmap lod bias m3d_lod_bias_1 m3d_base+238h|a38h m3d texture #2 mipmap lod bias m3d_lod_bias_2 m3d_base+23ch m3d vertex cache hit counter m3d_vc_hit_cnt m3d_base+240h m3d texture #0 rgba scale and texture operation m3d_tex_op_0 m3d_base+244h m3d texture #1 rgba scale and texture operation m3d_tex_op_1 m3d_base+248h m3d texture #2 rgba scale and texture operation m3d_tex_op_2 m3d_base+24ch m3d vertex cache vertex counter m3d_vc_vtx_cnt m3d_base+250h m3d texture #0 rgba source/operand m3d_tex_src_opd_0 m3d_base+254h m3d texture #1 rgba source/operand m3d_tex_src_opd_1 m3d_base+258h m3d texture #2 rgba source/operand m3d_tex_src_opd_2 m3d_base+25ch m3d fill mode m3d_fill_mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1147 of 1535 m3d_base+260h|a60h m3d visible box lower-left x register m3d_vb_xllc m3d_base+264h|a64h m3d visible box lower-left y register m3d_vb_yllc m3d_base+268h|a68h m3d visible box upper-right x register m3d_vb_xurc m3d_base+26ch|a6ch m3d visible box upper-right y register m3d_vb_yurc m3d_base+270h|a70h m3d frustum near register m3d_frustum_near m3d_base+274h|a74h m3d frustum far register m3d_frustum_far m3d_base+278h|a78h m3d view port near register m3d_viewport_near m3d_base+27ch|a7ch m3d view port far register m3d_viewport_far m3d_base+280h|a80h m3d model view matrix register m3d_model_view_m_1 m3d_base+284h|a84h m3d model view matrix register m3d_model_view_m_2 m3d_base+288h|a88h m3d model view matrix register m3d_model_view_m_3 m3d_base+28ch|a8ch m3d model view matrix register m3d_model_view_m_4 m3d_base+290h|a90h m3d model view matrix register m3d_model_view_m_5 m3d_base+294h|a94h m3d model view matrix register m3d_model_view_m_6 m3d_base+298h|a98h m3d model view matrix register m3d_model_view_m_7 m3d_base+29ch|a9ch m3d model view matrix register m3d_model_view_m_8 m3d_base+2a0h|aa0h m3d model view matrix register m3d_model_view_m_9 m3d_base+2a4h|aa4h m3d model view matrix register m3d_model_view_m_10 m3d_base+2a8h|aa8h m3d model view matrix register m3d_model_view_m_11 m3d_base+2ach|aach m3d model view matrix register m3d_model_view_m_12 m3d_base+2b0h|ab0h m3d model view matrix register m3d_model_view_m_13 m3d_base+2b4h|ab4h m3d model view matrix register m3d_model_view_m_14 m3d_base+2b8h|ab8h m3d model view matrix register m3d_model_view_m_15 m3d_base+2bch|abch m3d model view matrix register m3d_model_view_m_16 m3d_base+2c0h|ac0h m3d vp matrix register m3d_pv_1 m3d_base+2c4h|ac4h m3d vp matrix register m3d_pv_2 m3d_base+2c8h|ac8h m3d vp matrix register m3d_pv_3 m3d_base+2cch|acch m3d vp matrix register m3d_pv_4 m3d_base+2d0h|ad0h m3d vp matrix register m3d_pv_5 m3d_base+2d4h|ad4h m3d vp matrix register m3d_pv_6 m3d_base+2d8h|ad8h m3d vp matrix register m3d_pv_7 m3d_base+2dch|adch m3d vp matrix register m3d_pv_8 m3d_base+2e0h|ae0h m3d vp matrix register m3d_pv_9 m3d_base+2e4h|ae4h m3d vp matrix register m3d_pv_10 m3d_base+2e8h|ae8h m3d vp matrix register m3d_pv_11 m3d_base+2ech|aech m3d vp matrix register m3d_pv_12 m3d_base+2f0h|af0h m3d vp matrix register m3d_pv_13 m3d_base+2f4h|af4h m3d vp matrix register m3d_pv_14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1148 of 1535 m3d_base+2f8h|af8h m3d vp matrix register m3d_pv_15 m3d_base+2fch|afch m3d vp matrix register m3d_pv_16 m3d_base+300h|b00h m3d user-defined clipping plane matrix register m3d_c_n_x m3d_base+304h|b04h m3d user-defined clipping plane matrix register m3d_c_n_y m3d_base+308h|b08h m3d user-defined clipping plane matrix register m3d_c_n_z m3d_base+30ch|b0ch m3d user-defined clipping plane matrix register m3d_c_n_w m3d_base+310h|b10h m3d texture #0 border color red m3d_tex_border_r_0 m3d_base+314h|b14h m3d texture #0 border color green m3d_tex_border_g_0 m3d_base+318h|b18h m3d texture #0 border color blue m3d_tex_border_b_0 m3d_base+31ch|b1ch m3d texture #0 border color alpha m3d_tex_border_a_0 m3d_base+320h|b20h m3d texture #1 border color red m3d_tex_border_r_1 m3d_base+324h|b24h m3d texture #1 border color green m3d_tex_border_g_1 m3d_base+328h|b28h m3d texture #1 border color blue m3d_tex_border_b_1 m3d_base+32ch|b2ch m3d texture #1 border color alpha m3d_tex_border_a_1 m3d_base+330h|b30h m3d texture #2 border color red m3d_tex_border_r_2 m3d_base+334h|b34h m3d texture #2 border color green m3d_tex_border_g_2 m3d_base+338h|b38h m3d texture #2 border color blue m3d_tex_border_b_2 m3d_base+33ch|b3ch m3d texture #2 border color alpha m3d_tex_border_a_2 m3d_base+340h|b40h m3d texture coordinate matrix register m3d_tex_m_0_1 m3d_base+344h|b44h m3d texture coordinate matrix register m3d_tex_m_0_2 m3d_base+348h|b48h m3d texture coordinate matrix register m3d_tex_m_0_3 m3d_base+34ch|b4ch m3d texture coordinate matrix register m3d_tex_m_0_4 m3d_base+350h|b50h m3d texture coordinate matrix register m3d_tex_m_0_5 m3d_base+354h|b54h m3d texture coordinate matrix register m3d_tex_m_0_6 m3d_base+358h|b58h m3d texture coordinate matrix register m3d_tex_m_0_7 m3d_base+35ch|b5ch m3d texture coordinate matrix register m3d_tex_m_0_8 m3d_base+360h|b60h m3d texture coordinate matrix register m3d_tex_m_0_9 m3d_base+364h|b64h m3d texture coordinate matrix register m3d_tex_m_0_10 m3d_base+368h|b68h m3d texture coordinate matrix register m3d_tex_m_0_11 m3d_base+36ch|b6ch m3d texture coordinate matrix register m3d_tex_m_0_12 m3d_base+370h|b70h m3d texture coordinate matrix register m3d_tex_m_1_1 m3d_base+374h|b74h m3d texture coordinate matrix register m3d_tex_m_1_2 m3d_base+378h|b78h m3d texture coordinate matrix register m3d_tex_m_1_3 m3d_base+37ch|b7ch m3d texture coordinate matrix register m3d_tex_m_1_4 m3d_base+380h|b80h m3d texture coordinate matrix register m3d_tex_m_1_5 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1149 of 1535 m3d_base+384h|b84h m3d texture coordinate matrix register m3d_tex_m_1_6 m3d_base+388h|b88h m3d texture coordinate matrix register m3d_tex_m_1_7 m3d_base+38ch|b8ch m3d texture coordinate matrix register m3d_tex_m_1_8 m3d_base+390h|b90h m3d texture coordinate matrix register m3d_tex_m_1_9 m3d_base+394h|b94h m3d texture coordinate matrix register m3d_tex_m_1_10 m3d_base+398h|b98h m3d texture coordinate matrix register m3d_tex_m_1_11 m3d_base+39ch|b9ch m3d texture coordinate matrix register m3d_tex_m_1_12 m3d_base+3a0h|ba0h m3d texture coordinate matrix register m3d_tex_m_2_1 m3d_base+3a4h|ba4h m3d texture coordinate matrix register m3d_tex_m_2_2 m3d_base+3a8h|ba8h m3d texture coordinate matrix register m3d_tex_m_2_3 m3d_base+3ach|bach m3d texture coordinate matrix register m3d_tex_m_2_4 m3d_base+3b0h|bb0h m3d texture coordinate matrix register m3d_tex_m_2_5 m3d_base+3b4h|bb4h m3d texture coordinate matrix register m3d_tex_m_2_6 m3d_base+3b8h|bb8h m3d texture coordinate matrix register m3d_tex_m_2_7 m3d_base+3bch|bbch m3d texture coordinate matrix register m3d_tex_m_2_8 m3d_base+3c0h|bc0h m3d texture coordinate matrix register m3d_tex_m_2_9 m3d_base+3c4h|bc4h m3d texture coordinate matrix register m3d_tex_m_2_10 m3d_base+3c8h|bc8h m3d texture coordinate matrix register m3d_tex_m_2_11 m3d_base+3cch|bcch m3d texture coordinate matrix register m3d_tex_m_2_12 m3d_base+3d0h|bd0h d3dm light range of light source 0 register m3d_light_range_0 m3d_base+3d4h|bd4h d3dm light range of light source 1 register m3d_light_range_1 m3d_base+3d8h|bd8h d3dm light range of light source 2 register m3d_light_range_2 m3d_base+3dch|bdch d3dm light range of light source 3 register m3d_light_range_3 m3d_base+3e0h|be0h d3dm light range of light source 4 register m3d_light_range_4 m3d_base+3e4h|be4h d3dm light range of light source 5 register m3d_light_range_5 m3d_base+3e8h|be8h d3dm light range of light source 6 register m3d_light_range_6 m3d_base+3ech|bech d3dm light range of light source 7 register m3d_light_range_7 m3d_base+3f0h m3d drawtex tex2 cropper region u coord m3d_drawtex_cru_2 m3d_base+3f4h m3d drawtex tex2 cropper region v coord m3d_drawtex_crv_2 m3d_base+3f8h m3d drawtex tex2 cropper region delta u coord m3d_drawtex_dcru_2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1150 of 1535 m3d_base+3fch m3d drawtex tex2 cropper region delta v coord m3d_drawtex_dcrv_2 m3d_base+400h|c00h m3d normal matrix register m3d_normal_n_1 m3d_base+404h|c04h m3d normal matrix register m3d_normal_n_2 m3d_base+408h|c08h m3d normal matrix register m3d_normal_n_3 m3d_base+40ch|c0ch m3d normal matrix register m3d_normal_n_4 m3d_base+410h|c10h m3d normal matrix register m3d_normal_n_5 m3d_base+414h|c14h m3d normal matrix register m3d_normal_n_6 m3d_base+418h|c18h m3d normal matrix register m3d_normal_n_7 m3d_base+41ch|c1ch m3d normal matrix register m3d_normal_n_8 m3d_base+420h|c20h m3d normal matrix register m3d_normal_n_9 m3d_base+424h|c24h m3d normal scale register m3d_normal_scale m3d_base+428h|c28h m3d fog color?s red component register m3d_fog_color_r m3d_base+42ch|c2ch m3d fog color?s green component register m3d_fog_color_g m3d_base+430h|c30h m3d fog color?s blue component register m3d_fog_color_b m3d_base+434h|c34h m3d fog color?s alpha component register m3d_fog_color_a m3d_base+438h|c38h reserve for internal use reserved m3d_base+43ch pixel counter m3d_pxl_cnt m3d_base+440h|c40h red component of ambient color of material register m3d_a_cm_r m3d_base+444h|c44h green component of ambient color of material register m3d_a_cm_g m3d_base+448h|c48h blue component of ambient color of material register m3d_a_cm_b m3d_base+44ch texture cache hit counter m3d_txcache_cnt m3d_base+450h|c50h red component of diffusion color of material register m3d_d_cm_r m3d_base+454h|c54h green component of diffusion color of material register m3d_d_cm_g m3d_base+458h|c58h blue component of diffusion color of material register m3d_d_cm_b m3d_base+45ch|c5ch alpha component of diffusion color of material register m3d_d_cm_a m3d_base+460h|c60h red component of specular color of material register m3d_s_cm_r m3d_base+464h|c64h green component of specular color of material register m3d_s_cm_g m3d_base+468h|c68h blue component of specular color of material register m3d_s_cm_b m3d_base+46ch|c6ch alpha component of specular color of m3d_s_cm_a free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1151 of 1535 material register m3d_base+470h|c70h red component of emission color of material register m3d_e_cm_r m3d_base+474h|c74h green component of emission color of material register m3d_e_cm_g m3d_base+478h|c78h blue component of emission color of material register m3d_e_cm_b m3d_base+47ch z cache hit counter m3d_zc_cnt m3d_base+480h|c80h red component of ambient intensity of light source 0 register m3d_a_cl_0_r m3d_base+484h|c84h green component of ambient intensity of light source 0 register m3d_a_cl_0_g m3d_base+488h|c88h blue component of ambient intensity of light source 0 register m3d_a_cl_0_b m3d_base+48ch|c8ch alpha component of ambient intensity of light source 0 register m3d_a_cl_0_a m3d_base+490h|c90h red component of ambient intensity of light source 1 register m3d_a_cl_1_r m3d_base+494h|c94h green component of ambient intensity of light source 1 register m3d_a_cl_1_g m3d_base+498h|c98h blue component of ambient intensity of light source 1 register m3d_a_cl_1_b m3d_base+49ch|c9ch alpha component of ambient intensity of light source 1 register m3d_a_cl_1_a m3d_base+4a0h|ca0h red component of ambient intensity of light source 2 register m3d_a_cl_2_r m3d_base+4a4h|ca4h green component of ambient intensity of light source 2 register m3d_a_cl_2_g m3d_base+4a8h|ca8h blue component of ambient intensity of light source 2 register m3d_a_cl_2_b m3d_base+4ach|cach alpha component of ambient intensity of light source 2 register m3d_a_cl_2_a m3d_base+4b0h|cb0h red component of ambient intensity of light source 3 register m3d_a_cl_3_r m3d_base+4b4h|cb4h green component of ambient intensity of light source 3 register m3d_a_cl_3_g m3d_base+4b8h|cb8h blue component of ambient intensity of light source 3 register m3d_a_cl_3_b m3d_base+4bch|cbch alpha component of ambient intensity of light source 3 register m3d_a_cl_3_a m3d_base+4c0h|cc0h red component of ambient intensity of light source 4 register m3d_a_cl_4_r m3d_base+4c4h|cc4h green component of ambient intensity of light source 4 register m3d_a_cl_4_g free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1152 of 1535 m3d_base+4c8h|cc8h blue component of ambient intensity of light source 4 register m3d_a_cl_4_b m3d_base+4cch|ccch alpha component of ambient intensity of light source 4 register m3d_a_cl_4_a m3d_base+4d0h|cd0h red component of ambient intensity of light source 5 register m3d_a_cl_5_r m3d_base+4d4h|cd4h green component of ambient intensity of light source 5 register m3d_a_cl_5_g m3d_base+4d8h|cd8h blue component of ambient intensity of light source 5 register m3d_a_cl_5_b m3d_base+4dch|cdch alpha component of ambient intensity of light source 5 register m3d_a_cl_5_a m3d_base+4e0h|ce0h red component of ambient intensity of light source 6 register m3d_a_cl_6_r m3d_base+4e4h|ce4h green component of ambient intensity of light source 6 register m3d_a_cl_6_g m3d_base+4e8h|ce8h blue component of ambient intensity of light source 6 register m3d_a_cl_6_b m3d_base+4ech|cech alpha component of ambient intensity of light source 6 register m3d_a_cl_6_a m3d_base+4f0h|cf0h red component of ambient intensity of light source 7 register m3d_a_cl_7_r m3d_base+4f4h|cf4h green component of ambient intensity of light source 7 register m3d_a_cl_7_g m3d_base+4f8h|cf8h blue component of ambient intensity of light source 7 register m3d_a_cl_7_b m3d_base+4fch|cfch alpha component of ambient intensity of light source 7 register m3d_a_cl_7_a m3d_base+500h|d00h red component of diffusion intensity of light source 0 register m3d_d_cl_0_r m3d_base+504h|d04h green component of diffusion intensity of light source 0 register m3d_d_cl_0_g m3d_base+508h|d08h blue component of diffusion intensity of light source 0 register m3d_d_cl_0_b m3d_base+50ch|d0ch alpha component of diffusion intensity of light source 0 register m3d_d_cl_0_a m3d_base+510h|d10h red component of diffusion intensity of light source 1 register m3d_d_cl_1_r m3d_base+514h|d14h green component of diffusion intensity of light source 1 register m3d_d_cl_1_g m3d_base+518h|d18h blue component of diffusion intensity of light source 1 register m3d_d_cl_1_b m3d_base+51ch|d1ch alpha component of diffusion intensity of light source 1 register m3d_d_cl_1_a free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1153 of 1535 m3d_base+520h|d20h red component of diffusion intensity of light source 2 register m3d_d_cl_2_r m3d_base+524h|d24h green component of diffusion intensity of light source 2 register m3d_d_cl_2_g m3d_base+528h|d28h blue component of diffusion intensity of light source 2 register m3d_d_cl_2_b m3d_base+52ch|d2ch alpha component of diffusion intensity of light source 2 register m3d_d_cl_2_a m3d_base+530h|d30h red component of diffusion intensity of light source 3 register m3d_d_cl_3_r m3d_base+534h|d34h green component of diffusion intensity of light source 3 register m3d_d_cl_3_g m3d_base+538h|d38h blue component of diffusion intensity of light source 3 register m3d_d_cl_3_b m3d_base+53ch|d3ch alpha component of diffusion intensity of light source 3 register m3d_d_cl_3_a m3d_base+540h|d40h red component of diffusion intensity of light source 4 register m3d_d_cl_4_r m3d_base+544h|d44h green component of diffusion intensity of light source 4 register m3d_d_cl_4_g m3d_base+548h|d48h blue component of diffusion intensity of light source 4 register m3d_d_cl_4_b m3d_base+54ch|d4ch alpha component of diffusion intensity of light source 4 register m3d_d_cl_4_a m3d_base+550h|d50h red component of diffusion intensity of light source 5 register m3d_d_cl_5_r m3d_base+554h|d54h green component of diffusion intensity of light source 5 register m3d_d_cl_5_g m3d_base+558h|d58h blue component of diffusion intensity of light source 5 register m3d_d_cl_5_b m3d_base+55ch|d5ch alpha component of diffusion intensity of light source 5 register m3d_d_cl_5_a m3d_base+560h|d60h red component of diffusion intensity of light source 6 register m3d_d_cl_6_r m3d_base+564h|d64h green component of diffusion intensity of light source 6 register m3d_d_cl_6_g m3d_base+568h|d68h blue component of diffusion intensity of light source 6 register m3d_d_cl_6_b m3d_base+56ch|d6ch alpha component of diffusion intensity of light source 6 register m3d_d_cl_6_a m3d_base+570h|d70h red component of diffusion intensity of light source 7 register m3d_d_cl_7_r m3d_base+574h|d74h green component of diffusion intensity of light source 7 register m3d_d_cl_7_g free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1154 of 1535 m3d_base+578h|d78h blue component of diffusion intensity of light source 7 register m3d_d_cl_7_b m3d_base+57ch|d7ch alpha component of diffusion intensity of light source 7 register m3d_d_cl_7_a m3d_base+580h|d80h red component of specular intensity of light source 0 register m3d_s_cl_0_r m3d_base+584h|d84h green component of specular intensity of light source 0 register m3d_s_cl_0_g m3d_base+588h|d88h blue component of specular intensity of light source 0 register m3d_s_cl_0_b m3d_base+58ch|d8ch alpha component of specular intensity of light source 0 register m3d_s_cl_0_a m3d_base+590h|d90h red component of specular intensity of light source 1 register m3d_s_cl_1_r m3d_base+594h|d94h green component of specular intensity of light source 1 register m3d_s_cl_1_g m3d_base+598h|d98h blue component of specular intensity of light source 1 register m3d_s_cl_1_b m3d_base+59ch|d9ch alpha component of specular intensity of light source 1 register m3d_s_cl_1_a m3d_base+5a0h|da0h red component of specular intensity of light source 2 register m3d_s_cl_2_r m3d_base+5a4h|da4h green component of specular intensity of light source 2 register m3d_s_cl_2_g m3d_base+5a8h|da8h blue component of specular intensity of light source 2 register m3d_s_cl_2_b m3d_base+5ach|dach alpha component of specular intensity of light source 2 register m3d_s_cl_2_a m3d_base+5b0h|db0h red component of specular intensity of light source 3 register m3d_s_cl_3_r m3d_base+5b4h|db4h green component of specular intensity of light source 3 register m3d_s_cl_3_g m3d_base+5b8h|db8h blue component of specular intensity of light source 3 register m3d_s_cl_3_b m3d_base+5bch|dbch alpha component of specular intensity of light source 3 register m3d_s_cl_3_a m3d_base+5c0h|dc0h red component of specular intensity of light source 4 register m3d_s_cl_4_r m3d_base+5c4h|dc4h green component of specular intensity of light source 4 register m3d_s_cl_4_g m3d_base+5c8h|dc8h blue component of specular intensity of light source 4 register m3d_s_cl_4_b m3d_base+5cch|dcch alpha component of specular intensity of light source 4 register m3d_s_cl_4_a free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1155 of 1535 m3d_base+5d0h|dd0h red component of specular intensity of light source 5 register m3d_s_cl_5_r m3d_base+5d4h|dd4h green component of specular intensity of light source 5 register m3d_s_cl_5_g m3d_base+5d8h|dd8h blue component of specular intensity of light source 5 register m3d_s_cl_5_b m3d_base+5dch|ddch alpha component of specular intensity of light source 5 register m3d_s_cl_5_a m3d_base+5e0h|de0h red component of specular intensity of light source 6 register m3d_s_cl_6_r m3d_base+5e4h|de4h green component of specular intensity of light source 6 register m3d_s_cl_6_g m3d_base+5e8h|de8h blue component of specular intensity of light source 6 register m3d_s_cl_6_b m3d_base+5ech|dech alpha component of specular intensity of light source 6 register m3d_s_cl_6_a m3d_base+5f0h|df0h red component of specular intensity of light source 7 register m3d_s_cl_7_r m3d_base+5f4h|df4h green component of specular intensity of light source 7 register m3d_s_cl_7_g m3d_base+5f8h|df8h blue component of specular intensity of light source 7 register m3d_s_cl_7_b m3d_base+5fch|dfch alpha component of specular intensity of light source 7 register m3d_s_cl_7_a m3d_base+600h|e00h x coordinate of position of light source 0 register m3d_p_pl_0_x m3d_base+604h|e04h y coordinate of position of light source 0 register m3d_p_pl_0_y m3d_base+608h|e08h z coordinate of position of light source 0 register m3d_p_pl_0_z m3d_base+60ch|e0ch w coordinate of position of light source 0 register m3d_p_pl_0_w m3d_base+610h|e10h x coordinate of position of light source 1 register m3d_p_pl_1_x m3d_base+614h|e14h y coordinate of position of light source 1 register m3d_p_pl_1_y m3d_base+618h|e18h z coordinate of position of light source 1 register m3d_p_pl_1_z m3d_base+61ch|e1ch w coordinate of position of light source 1 register m3d_p_pl_1_w m3d_base+620h|e20h x coordinate of position of light source 2 register m3d_p_pl_2_x m3d_base+624h|e24h y coordinate of position of light source 2 register m3d_p_pl_2_y free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1156 of 1535 m3d_base+628h|e28h z coordinate of position of light source 2 register m3d_p_pl_2_z m3d_base+62ch|e2ch w coordinate of position of light source 2 register m3d_p_pl_2_w m3d_base+630h|e30h x coordinate of position of light source 3 register m3d_p_pl_3_x m3d_base+634h|e34h y coordinate of position of light source 3 register m3d_p_pl_3_y m3d_base+638h|e38h z coordinate of position of light source 3 register m3d_p_pl_3_z m3d_base+63ch|e3ch w coordinate of position of light source 3 register m3d_p_pl_3_w m3d_base+640h|e40h x coordinate of position of light source 4 register m3d_p_pl_4_x m3d_base+644h|e44h y coordinate of position of light source 4 register m3d_p_pl_4_y m3d_base+648h|e48h z coordinate of position of light source 4 register m3d_p_pl_4_z m3d_base+64ch|e4ch w coordinate of position of light source 4 register m3d_p_pl_4_w m3d_base+650h|e50h x coordinate of position of light source 5 register m3d_p_pl_5_x m3d_base+654h|e54h y coordinate of position of light source 5 register m3d_p_pl_5_y m3d_base+658h|e58h z coordinate of position of light source 5 register m3d_p_pl_5_z m3d_base+65ch|e5ch w coordinate of position of light source 5 register m3d_p_pl_5_w m3d_base+660h|e60h x coordinate of position of light source 6 register m3d_p_pl_6_x m3d_base+664h|e64h y coordinate of position of light source 6 register m3d_p_pl_6_y m3d_base+668h|e68h z coordinate of position of light source 6 register m3d_p_pl_6_z m3d_base+66ch|e6ch w coordinate of position of light source 6 register m3d_p_pl_6_w m3d_base+670h|e70h x coordinate of position of light source 7 register m3d_p_pl_7_x m3d_base+674h|e74h y coordinate of position of light source 7 register m3d_p_pl_7_y m3d_base+678h|e78h z coordinate of position of light source 7 register m3d_p_pl_7_z m3d_base+67ch|e7ch w coordinate of position of light source 7 register m3d_p_pl_7_w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1157 of 1535 m3d_base+680h|e80h x direction of spotlight for light source 0 register m3d_s_dl_0_x m3d_base+684h|e84h y direction of spotlight for light source 0 register m3d_s_dl_0_y m3d_base+688h|e88h z direction of spotlight for light source 0 register m3d_s_dl_0_z m3d_base+68ch|e8ch spotlight exponent for light source 0 register m3d_s_rl_0 m3d_base+690h|e90h x direction of spotlight for light source 1 register m3d_s_dl_1_x m3d_base+694h|e94h y direction of spotlight for light source 1 register m3d_s_dl_1_y m3d_base+698h|e98h z direction of spotlight for light source 1 register m3d_s_dl_1_z m3d_base+69ch|e9ch spotlight exponent for light source 1 register m3d_s_rl_1 m3d_base+6a0h|ea0h x direction of spotlight for light source 2 register m3d_s_dl_2_x m3d_base+6a4h|ea4h y direction of spotlight for light source 2 register m3d_s_dl_2_y m3d_base+6a8h|ea8h z direction of spotlight for light source 2 register m3d_s_dl_2_z m3d_base+6ach|each spotlight exponent for light source 2 register m3d_s_rl_2 m3d_base+6b0h|eb0h x direction of spotlight for light source 3 register m3d_s_dl_3_x m3d_base+6b4h|eb4h y direction of spotlight for light source 3 register m3d_s_dl_3_y m3d_base+6b8h|eb8h z direction of spotlight for light source 3 register m3d_s_dl_3_z m3d_base+6bch|ebch spotlight exponent for light source 3 register m3d_s_rl_3 m3d_base+6c0h|ec0h x direction of spotlight for light source 4 register m3d_s_dl_4_x m3d_base+6c4h|ec4h y direction of spotlight for light source 4 register m3d_s_dl_4_y m3d_base+6c8h|ec8h z direction of spotlight for light source 4 register m3d_s_dl_4_z m3d_base+6cch|ecch spotlight exponent for light source 4 register m3d_s_rl_4 m3d_base+6d0h|ed0h x direction of spotlight for light source 5 register m3d_s_dl_5_x m3d_base+6d4h|ed4h y direction of spotlight for light source 5 register m3d_s_dl_5_y free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1158 of 1535 m3d_base+6d8h|ed8h z direction of spotlight for light source 5 register m3d_s_dl_5_z m3d_base+6dch|edch spotlight exponent for light source 5 register m3d_s_rl_5 m3d_base+6e0h|ee0h x direction of spotlight for light source 6 register m3d_s_dl_6_x m3d_base+6e4h|ee4h y direction of spotlight for light source 6 register m3d_s_dl_6_y m3d_base+6e8h|ee8h z direction of spotlight for light source 6 register m3d_s_dl_6_z m3d_base+6ech|eech spotlight exponent for light source 6 register m3d_s_rl_6 m3d_base+6f0h|ef0h x direction of spotlight for light source 7 register m3d_s_dl_7_x m3d_base+6f4h|ef4h y direction of spotlight for light source 7 register m3d_s_dl_7_y m3d_base+6f8h|ef8h z direction of spotlight for light source 7 register m3d_s_dl_7_z m3d_base+6fch|efch spotlight exponent for light source 7 register m3d_s_rl_7 m3d_base+700h|f00h spotlight cutoff angle for light source 0 register m3d_c_rl_0 m3d_base+704h|f04h constant attenuation factor for light source 0 register m3d_k_0_0 m3d_base+708h|f08h linear attenuation factor for light source 0 register m3d_k_1_0 m3d_base+70ch|f0ch quadratic attenuation factor for light source 0 register m3d_k_2_0 m3d_base+710h|f10h spotlight cutoff angle for light source 1 register m3d_c_rl_1 m3d_base+714h|f14h constant attenuation factor for light source 1 register m3d_k_0_1 m3d_base+718h|f18h linear attenuation factor for light source 1 register m3d_k_1_1 m3d_base+71ch|f1ch quadratic attenuation factor for light source 1 register m3d_k_2_1 m3d_base+720h|f20h spotlight cutoff angle for light source 2 register m3d_c_rl_2 m3d_base+724h|f24h constant attenuation factor for light source 2 register m3d_k_0_2 m3d_base+728h|f28h linear attenuation factor for light source 2 register m3d_k_1_2 m3d_base+72ch|f2ch quadratic attenuation factor for light source 2 register m3d_k_2_2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1159 of 1535 m3d_base+730h|f30h spotlight cutoff angle for light source 3 register m3d_c_rl_3 m3d_base+734h|f34h constant attenuation factor for light source 3 register m3d_k_0_3 m3d_base+738h|f38h linear attenuation factor for light source 3 register m3d_k_1_3 m3d_base+73ch|f3ch quadratic attenuation factor for light source 3 register m3d_k_2_3 m3d_base+740h|f40h spotlight cutoff angle for light source 4 register m3d_c_rl_4 m3d_base+744h|f44h constant attenuation factor for light source 4 register m3d_k_0_4 m3d_base+748h|f48h linear attenuation factor for light source 4 register m3d_k_1_4 m3d_base+74ch|f4ch quadratic attenuation factor for light source 4 register m3d_k_2_4 m3d_base+750h|f50h spotlight cutoff angle for light source 5 register m3d_c_rl_5 m3d_base+754h|f54h constant attenuation factor for light source 5 register m3d_k_0_5 m3d_base+758h|f58h linear attenuation factor for light source 5 register m3d_k_1_5 m3d_base+75ch|f5ch quadratic attenuation factor for light source 5 register m3d_k_2_5 m3d_base+760h|f60h spotlight cutoff angle for light source 6 register m3d_c_rl_6 m3d_base+764h|f64h constant attenuation factor for light source 6 register m3d_k_0_6 m3d_base+768h|f68h linear attenuation factor for light source 6 register m3d_k_1_6 m3d_base+76ch|f6ch quadratic attenuation factor for light source 6 register m3d_k_2_6 m3d_base+770h|f70h spotlight cutoff angle for light source 7 register m3d_c_rl_7 m3d_base+774h|f74h constant attenuation factor for light source 7 register m3d_k_0_7 m3d_base+778h|f78h linear attenuation factor for light source 7 register m3d_k_1_7 m3d_base+77ch|f7ch quadratic attenuation factor for light source 7 register m3d_k_2_7 m3d_base+780h|f80h red component of ambient color of scene register m3d_a_cs_r m3d_base+784h|f84h green component of ambient color of scene register m3d_a_cs_g free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1160 of 1535 m3d_base+788h|f88h blue component of ambient color of scene register m3d_a_cs_b m3d_base+78ch color cache hit counter m3d_cc_cnt m3d_base+790h|f90h specular exponent of material register m3d_s_rm m3d_base+794h|f94h fog density register m3d_fog_density m3d_base+798h|f98h fog start register m3d_fog_start m3d_base+79ch|f9ch fog end register m3d_fog_end m3d_base+7a0h|fa0h lower bound of point size register m3d_point_size_min m3d_base+7a4h|fa4h upper bound of point size register m3d_ponit_size_max m3d_base+7a8h|fa8h constant coefficient of distance attenaution fucntion for point size register m3d_point_attenuation_a m3d_base+7ach|fach linear coefficient of distance attenaution fucntion for point size register m3d_point_attenuation_b m3d_base+7b0h|fb0h quadratic coefficient of distance attenaution fucntion for point size register m3d_point_attenuation_c m3d_base+7b4h m3d texture #0 filter/wrap mode m3d_tex_para_0 m3d_base+7b8h m3d texture #1 filter/wrap mode m3d_tex_para_1 m3d_base+7bch m3d texture #2 filter/wrap mode m3d_tex_para_2 m3d_base+7c0h m3d cache performance counter control m3d_cache_perf_ctrl m3d_base+7c4h reserved reserved m3d_base+7c8h m3d drawtex tex0 cropper region u coord m3d_drawtex_cru_0 m3d_base+7cch m3d drawtex tex0 cropper region v coord m3d_drawtex_crv_0 m3d_base+7d0h m3d drawtex tex0 cropper region delta u coord m3d_drawtex_dcru_0 m3d_base+7d4h m3d drawtex tex0 cropper region delta v coord m3d_drawtex_dcrv_0 m3d_base+7d8h m3d drawtex cropper region xy coord m3d_drawtex_xy m3d_base+7dch m3d drawtex cropper region width/height m3d_drawtex_wh m3d_base+7e0h m3d drawtex cropper region z value m3d_drawtex_z m3d_base+7e4h m3d drawtex cropper region fog factor m3d_drawtex_fog m3d_base+7e8h m3d dummy register 0 m3d_dummy_0 m3d_base+7ech m3d dummy register 1 m3d_dummy_1 m3d_base+7f0h m3d dummy register 2 m3d_dummy_2 m3d_base+7f4h m3d debug port 5 m3d_dbgrd_5 m3d_base+7f8h m3d debug port 6 m3d_dbgrd_6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1161 of 1535 m3d_base+7fch m3d debug port 7 m3d_dbgrd_7 table 118 m3d registers m3d_base+0 00h m3d trigger register m3d_trigger bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_d rawt ex_en able rese rved rese rved rese rved m3d_t rigge r type r/w r/w reset 0 0 m3d_trigger trigger the m3d hardware pipeline. it cannot be enabled when buffer clear operation is running. m3d_drawtex_enable trigger drawtex function when hardware operation is done, the corresponding bit would be cleared by hardware automatically. m3d_base+00 4h m3d reset register m3d_reset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rese t type r/w reset 0 reset .reset m3d hardware pipeline. m3d_base+00 8h m3d status register m3d_status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo r_flu sh_b usy m3d_z _flus h_bu sy rese rved rese rved rese rved rese rved m3d_ busy type ro ro ro reset 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1162 of 1535 m3d_busy indicating that m3d hardware is busy. m3d_z__flush_busy indicating that m3d is busy in z cache flushing. m3d_color_flush_busy indicating that m3d is busy in color cache flushing. m3d_base+00 ch m3d interrupt enable register m3d_inten bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo r_flu sh_d one_i nten m3d_z _flus h_do ne_in ten rese rved rese rved rese rved rese rved m3d_ rend er_d one_i nten type r/w r/w r/w reset 0 0 0 m3d_render_done_inten enable interrupting when rendering is done. m3d_z_flush_done_inten enable interrupting when z cache flush is done. m3d_color_flush_done_inten enable interrupting when color cache flush is done. m3d_base+01 0h m3d interrupt status register m3d_intsta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo r_flu sh_d one_i ntsta m3d_z _flus h_do ne_in tsta rese rved rese rved rese rved rese rved m3d_ rend er_d one_i ntst a type wc wc wc reset 0 0 0 m3d_render_done_intsta interrupting status of rendering. m3d_z_flush_done_intsta interrupting status of z cache flush. m3d_color_flush_done_intsta interrupting status of color cache flush. m3d_base+01 4h m3d fragment cache enable register m3d_frag_ca che_enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1163 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_t ex_ca che_e nabl e m3d_ colo rl_ca che_e nabl e m3d_z _cac he_en able m3d_ sten cil_c ache _ena ble type r/w r/w r/w r/w reset 1 1 1 1 m3d_stencil_cache_enable enable m3d stencil cache. m3d_z_cache_enable enable m3d z cache. m3d_color_cache_enable enable m3d color cache. m3d_tex_cache_enable enable m3d tex cache. m3d_base+01 8h m3d fragment cache flush register m3d_frag_ca che_flush bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo rl_ca che_f lush m3d_z _cac he_fl ush m3d_ sten cil_c ache _flus h type r/w r/w r/w reset 0 0 0 m3d_stencil_cache_flush flush the content of m3d stencil cache. m3d_z_cache_flush flush the content of m3d z cache. m3d_color_cache_flush flush the content of m3d color cache. m3d_base+01 ch m3d fragment cache invalidate register m3d_frag_ca che_inval bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo rl_ca che_i nval m3d_z _cac he_in vla m3d_ sten cil_c ache _invl al type r/w r/w r/w reset 0 0 0 m3d_stencil_cache_inval invalidate all cache lines in m3d stencil cache. m3d_z_cache_inval invalidate all cache lines in m3d z cache. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1164 of 1535 m3d_color_cache_inval invalidate all cache lines in m3d color cache. m3d_base+02 0h m3d fragment cache reset register m3d_frag_ca che_reset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ colo r_ca che_ reset m3d_z _cac he_re set m3d_ steci l_ca che_ rese t type r/w r/w r/w reset 0 0 0 m3d_stencil_cache_reset reset the m3d stencil cache hardware state machine. m3d_z_cache_reset reset the m3d z cache hardware state machine. m3d_color_cache_reset reset m3d stencil cache hardware state machine m3d_base+02 4h m3d texture cache clear register m3d_tex_cac he_clear bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ tex_c ache _cle ar type r/w reset 0 m3d_tex_cache_clear clear texture cache's valid bits and counter state. m3d_base+02 8h m3d primitive mode register m3d_primitiv e _mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_primitive _mode type r/w reset 0 m3d_primitive_mode primitive mode. 0x0 represent points free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1165 of 1535 0x4 represent lines 0x6 represent line loop 0x7 represent line strip 0x8 represent triangles 0xa represent triangle strip 0 0xb represent triangle strip 1 0xc represent triangle fan 0 0xd represent triangle fan 1 primitive type opengl- es d3dm points 0x0 lines 0x4 line loop 0x6 - line strip 0x7 triangles 0x8 triangle strip 0xa 0xb triangle fan 0xc 0xd m3d_base+02ch m3d draw mode register m3d_primitive_draw_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_primitive_draw_mode type r/w m3d_primitive_draw_mode draw mode. (0 represent draw-array, 1 represent draw-element) m3d_base+03 0h m3d vertex count register m3d_primitiv e_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_primitive_count type r/w m3d_primitive_count specifies the number of vertices to be rendered. m3d_base+03 4h m3d draw-array first index register m3d_draw_a rray_first bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1166 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_draw_array_first type r/w m3d_draw_array_first specifies the starting index of draw-array. m3d_base+03 8h m3d draw-array end index register m3d_draw_a rray_end bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_draw_array_end type r/w m3d_draw_array_end specifies the end index of draw-array. m3d_base+03 ch m3d draw-element index type register m3d_draw_el ement_type bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_draw_element_typ e type r/w m3d_draw_element_type specifies the data type of each index in the array. (0x1 represent unsigned byte, 0x3 represent unsigned short) m3d_base+04 0h m3d draw-element pointer register m3d_draw_el ement_point er bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_draw_element_pointer[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_draw_element_pointer[15:0] type r/w m3d_draw_element_pointer specifies the memory address of the index array for deaw-element. 8 bytes alignment. m3d_base+04 4h m3d primitive anti-aliasing register m3d_primitiv e_aa bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1167 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_p oint_ smoo th m3d_l ine_s moot h type r/w r/w reset 0 0 m3d_line_smooth line smooth disable/enable. (0 represent disable, 1 represent enable) m3d_point_smooth point smooth disable/enable. (0 represent disable, 1 represent enable) driver should do some judgements before enable point smooth. ? point_smooth is enable ? no glenableclientstate(gl_point_size_array_oes) ? glpointsizex(fixed size), size <= 4 and point_distance_attenuation is (1, 0, 0) m3d_base+04 8h m3d polygon offset enable/disable register m3d_polygo n_offset_en able bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ poly gon_ offs et_en able type r/w reset 0 m3d_polygon_offset_enable polygon offset disable/enable. (0 represent disable, 1 represent enable) m3d_base+04 ch|84ch m3d polygon offset factor register m3d_polygo n_offset_fa ctor bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_polygon_offset_factor[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_polygon_offset_ factor [15:0] type r/w m3d_polygon_offset_factor specifies a scale factor that is used to create a variable depth offset for each polygon. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1168 of 1535 m3d_base+05 0h|850h m3d polygon offset unit register m3d_polygo n_offset_uni ts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_polygon_offset_units[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_polygon_offset_units[15:0] type r/w m3d_polygon_offset_units original units is multiplied by an implementation-specific value to create a constant depth offset. (r * units) m3d_base+05 4h|854h m3d line width register m3d_line_wid th bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_line_width[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_line_width[15:0] type r/w m3d_line_width specify the width of rasterized lines. m3d_base+05 8h m3d point-sprite register m3d_point_s prite bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_point_coord _replace m3d_ point _spri te_e nabl e type r/w r/w reset 0 0 m3d_point_sprite_enable point-sprite disable/enable. (0 represent disable, 1 represent enable) m3d_point_coord_replace replace original texture coordinate with new when point-sprite is enable. (0 represent disable, 1 represent enable) m3d_base+05 ch m3d vertex array register m3d_vertex bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1169 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_v ertex _scre en m3d_vertex_type m3d_vertex _size type r/w r/w r/w reset 0 0 0 m3d_vertex_size specifies the number of coordinates per vertex. (0 represent 2 elements, 1 represent 3 elements, 2 represent 4 elements) m3d_vertex_type specifies the data type of each vertex coordinate in the array. (0x0 represent byte, 0x2 represent short, 0x6 represent float, 0xc represent fixed) m3d_vertex_screen specifies the vertex coordinate is screnn space coordinate or not. (0 represent object space, 1 represent screen space : x, y, z, rhw) m3d_base+06 0h m3d vertex array stride register m3d_vertex_ stride_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vertex_stride_b[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vertex_stride_b[15:0] type r/w m3d_vertex_stride_b specifies the byte offset between consecutive vertices. m3d_base+06 4h m3d vertex array pointer register m3d_vertex_ pointer bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vertex_pointer[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vertex_pointer[15:0] type r/w m3d_vertex_pointer specifies a pointer to the first coordinate of the first vertex in the array. m3d_base+06 8h m3d vertex cache pointer register m3d_vertex_ cache_point er bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vertex_cache_pointer[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vertex_cache_pointer[15:0] type r/w m3d_vertex_cache_pointer vertex cache pointer. vertex cache must use internal memory (gmc2 : 0x4002_0000 ~ 0x4004_3fff). 8 bytes alignment. need total 2048 bytes (32 entries, each entry has 64 bytes). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1170 of 1535 m3d_base+06 ch m3d bounding box control register m3d_bbox_ex pand bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ bbox _expa nd_y_ en m3d_ bbox _exp and_ x_en type r/w r/w reset 1 1 m3d_bbox_expand_x_en expand bounding box in x direction. (0 represent disable, 1 represent enable) m3d_bbox_expand_y_en expand bounding box in y direction. (0 represent disable, 1 represent enable) default is enable this function. please disable this function when viewport isn?t equal to screen. m3d_base+07 0h m3d normal array type register m3d_normal_ type bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_type type r/w m3d_normal_type specifies the data type of each coordinate in the array. (0x0 represent byte, 0x2 represent short, 0x6 represent float, 0xc represent fixed) m3d_base+07 4h m3d normal array stride register m3d_normal_ stride_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_stride_b[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_stride_b[15:0] type r/w m3d_normal_stride_b specifies the byte offset between consecutive normals. m3d_base+07 8h m3d normal array pointer register m3d_normal_ pointer bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_pointer[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_pointer[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1171 of 1535 m3d_normal_pointer specifies a pointer to the first coordinate of the first normal in the array. m3d_base+07 ch m3d color array type/size/input register m3d_color_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_type_0 m3d_ colo r_siz e_0 m3d_ colo r_or der_0 m3d_ colo r_inp ut_0 m3d_ colo r_en able _0 type r/w r/w r/w r/w r/w reset 0 0 0 0 1 m3d_color_enable_0 specifies the color disable/enable. (0 represent disable, 1 represent enable) m3d_color_input_0 specifies the source of color input. (0 represent register, 1 represent array) m3d_color_order_0 specifies the color order. (0x0 represent abgr, 0x1 represent argb) m3d_color_size_0 specifies the number of coordinates per color. (0 represent 3 elements, 1 represent 4 elements) m3d_color_type _0 specifies the data type of each coordinate in the array. (0x1 represent ubyte, 0x6 represent float, 0xc represent fixed) m3d_base+08 0h m3d color array type/size/input register m3d_color_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_type_1 m3d_ colo r_siz e_1 m3d_ colo r_or der_1 _1m3d _col or_in put_1 m3d_ colo r_en able _1 type r/w r/w r/w r/w r/w reset 0 0 0 0 1 m3d_color_enable_1 specifies the color disable/enable. (0 represent disable, 1 represent enable) m3d_color_input_1 specifies the source of color input. (0 represent register, 1 represent array) m3d_color_order_1 specifies the color order. (0x0 represent abgr, 0x1 represent argb) m3d_color_size_1 specifies the number of coordinates per color. (0 represent 3 elements, 1 represent 4 elements) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1172 of 1535 m3d_color_type _1 specifies the data type of each coordinate in the array. (0x1 represent ubyte, 0x6 represent float, 0xc represent fixed) m3d_base+08 4h m3d color array stride register m3d_color_s tride_b_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_stride_b_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_stride_b_0[15:0] type r/w m3d_color_stride_b_0 specifies the byte offset between consecutive colors. m3d_base+08 8h m3d color array stride register m3d_color_s tride_b_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_stride_b_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_stride_b_1[15:0] type r/w m3d_color_stride_b_1 specifies the byte offset between consecutive colors. m3d_base+08 ch m3d color array pointer register m3d_color_p ointer_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_pointer_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_pointer_0[15:0] type r/w m3d_color_pointer_0 specifies a pointer to the first coordinate of the first color in the array. m3d_base+09 0h m3d color array pointer register m3d_color_p ointer_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_pointer_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_pointer_1[15:0] type r/w m3d_color_pointer_1 specifies a pointer to the first coordinate of the first color in the array. m3d_base+09 4h m3d debug port 0 m3d_dbgrd_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1173 of 1535 name m3d_dbgrd_0[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_0[15:0] type r m3d_dbgrd_0 m3d engine debug port #0 (read only). m3d_base+09 8h m3d debug port 1 m3d_dbgrd_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_1[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_1[15:0] type r m3d_dbgrd_1 m3d engine debug port #1 (read only). m3d_base+09 ch m3d debug port 2 m3d_dbgrd_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_2[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_2[15:0] type r m3d_dbgrd_2 m3d engine debug port #2 (read only). m3d_base+0a 0h m3d debug port 3 m3d_dbgrd_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_3[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_3[15:0] type r m3d_dbgrd_3 m3d engine debug port #3 (read only). m3d_base+0a 4h m3d debug port 4 m3d_dbgrd_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_4[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_4[15:0] type r m3d_dbgrd_4 m3d engine debug port #4 (read only). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1174 of 1535 m3d_base+0a 8h m3d texture coordinate 0 register m3d_tex_coo rd_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_type_0 m3d_tex_coord_si ze_0 m3d_t ex_c oord _xfro m_pr oj_0 m3d_t ex_c oord _xfor m_en able_ 0 m3d_t ex_c oord _wra p_t_0 m3d_t ex_c oord _wra p_s_0 m3d_t ex_c oord _2d_0 m3d_ tex_ coor d_en able _0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 1 0 m3d_tex_coord_enable_0 tetxure coordinate disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_2d_0 specifies the dimension of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_s_0 specifies the s wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_t_0 specifies the t wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_xform_enable_0 texture coordinate transform disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_xform_proj_0 texture coordinate transform projected disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_size_0 specifies the number of coordinates per array element. 0x0 represent 1 element. (s, 1, 0, 0) 0x2 represent 2 elements. (s, t, 0, 1) 0x3 represent 2 elements. (s, t, 1, 0) 0x4 represent 3 elements. (s, t, r, 1) 0x6 represent 4 elements. (s, t, r, q) size opengl-es d3dm 1 - 0x0 2 0x2 0x3 3 0x4 4 0x6 - m3d_tex_coord_type_0 specifies the type of each texture coordinate.(0x0 represent byte, 0x2 represent short, 0x6 represent float, 0xc represent fixed) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1175 of 1535 m3d_base+0a ch m3d texture coordinate 0 register m3d_tex_coo rd_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_type_1 m3d_tex_coord_si ze_1 m3d_t ex_c oord _xfro m_pr oj_1 m3d_t ex_c oord _xfor m_en able_ 1 m3d_t ex_c oord _wra p_t_1 m3d_t ex_c oord _wra p_s_1 m3d_t ex_c oord _2d_1 m3d_ tex_ coor d_en able _1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 1 0 m3d_tex_coord_enable_1 tetxure coordinate disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_2d_1 specifies the dimension of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_s_1 specifies the s wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_t_1 specifies the t wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_xform_enable_1 texture coordinate transform disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_xform_proj_1 texture coordinate transform projected disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_size_1 specifies the number of coordinates per array element. 0x0 represent 1 element. (s, 1, 0, 0) 0x2 represent 2 elements. (s, t, 0, 1) 0x3 represent 2 elements. (s, t, 1, 0) 0x4 represent 3 elements. (s, t, r, 1) 0x6 represent 4 elements. (s, t, r, q) size opengl-es d3dm 1 - 0x0 2 0x2 0x3 3 0x4 4 0x6 - m3d_tex_coord_type_1 specifies the type of each texture coordinate.(0x0 represent byte, 0x2 represent short, 0x6 represent float, 0xc represent fixed) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1176 of 1535 m3d_base+0b 0h m3d texture coordinate 0 register m3d_tex_coo rd_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_type_2 m3d_tex_coord_si ze_2 m3d_t ex_c oord _xfro m_pr oj_2 m3d_t ex_c oord _xfor m_en able_ 2 m3d_t ex_c oord _wra p_t_0 m3d_t ex_c oord _wra p_s_2 m3d_t ex_c oord _2d_2 m3d_ tex_ coor d_en able _2 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 1 0 m3d_tex_coord_enable_2 tetxure coordinate disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_2d_2 specifies the dimension of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_s_2 specifies the s wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_wrap_t_2 specifies the t wrapping of each tetxure coordinate. (0x0 represent 1d, 0x1 represent 2d) m3d_tex_coord_xform_enable_2 texture coordinate transform disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_xform_proj_2 texture coordinate transform projected disable/enable. (0 represent disable, 1 represent enable) m3d_tex_coord_size_2 specifies the number of coordinates per array element. 0x0 represent 1 element. (s, 1, 0, 0) 0x2 represent 2 elements. (s, t, 0, 1) 0x3 represent 2 elements. (s, t, 1, 0) 0x4 represent 3 elements. (s, t, r, 1) 0x6 represent 4 elements. (s, t, r, q) size opengl-es d3dm 1 - 0x0 2 0x2 0x3 3 0x4 4 0x6 - m3d_tex_coord_type_2 specifies the type of each texture coordinate.(0x0 represent byte, 0x2 represent short, 0x6 represent float, 0xc represent fixed) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1177 of 1535 m3d_base+0b 4h m3d texture array 0 stride register m3d_tex_coo rd_stride_b_ 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_stride_b_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_stride_b_0[15:0] type r/w m3d_tex_coord_stride_b_0 specifies the byte offset between consecutive elements. m3d_base+0b 8h m3d texture array 1 stride register m3d_tex_coo rd_stride_b_ 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_stride_b_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_stride_b_1[15:0] type r/w m3d_tex_coord_stride_b_1 specifies the byte offset between consecutive elements. m3d_base+0b ch m3d texture array 2 stride register m3d_tex_coo rd_stride_b_ 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_stride_b_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_stride_b_2[15:0] type r/w m3d_tex_coord_stride_b_2 specifies the byte offset between consecutive elements. m3d_base+0c 0h m3d texture array 0 pointer register m3d_tex_coo rd_pointer_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_pointer_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_pointer_0[15:0] type r/w m3d_tex_coord_pointer_0 specifies a pointer to the first coordinate of the first element in the array. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1178 of 1535 m3d_base+0c 4h m3d texture array 1 pointer register m3d_tex_coo rd_pointer_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_pointer_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_pointer_1 [15:0] type r/w m3d_ tex_coord_pointer_1 specifies a pointer to the first coordinate of the first element in the array. m3d_base+0c 8h m3d texture array 2 pointer register m3d_tex_coo rd_pointer_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_coord_pointer_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_coord_pointer_2[15:0] type r/w m3d_ tex_coord_pointer_2 specifies a pointer to the first coordinate of the first element in the array. m3d_base+0c ch m3d point array type/input register m3d_pnt_size _input bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pnt_size_type m3d_ pnt_ size_i nput type r/w r/w reset 0 0 m3d_pnt_size_input specifies the source of point size. (0 represent register, 1 represent array) m3d_pnt_size_type specifies the type of point size. (0x06 represent float , 0x0c represent fixed) m3d_base+0d 0h|8d0h m3d point array size register m3d_pnt_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pnt_size[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pnt_size[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1179 of 1535 m3d_pnt_size set the current point size. (00d0h : data format is s15.16, 20d0h : data format is s[8].23) m3d_base+0d 4h m3d point array stride register m3d_pnt_size _stride_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pnt_size_stride_b[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pnt_size_stride_b[15:0] type r/w m3d_pnt_size_stride_b specifies the byte offset between consecutive point size. m3d_base+0d 8h m3d point array pointer register m3d_pnt_size _pointer bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pnt_size_pointer[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pnt_size_pointer[15:0] type r/w m3d_pnt_size_pointer specifies a pointer to the first point size in the array. m3d_base+0d ch m3d projection matrix type register m3d_proj_ma trix_type bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_proj_ matrix_typ e type r/w reset 0 m3d_proj_matrix_type projection matrix type. (0 represent general, 1 represent frustum, 2 represent ortho) m3d_base+0e 0h m3d user-defined clipping plane enable/disable register m3d_clip_pla ne_enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1180 of 1535 name m3d_ clip_ plan e_en able type r/w reset 0 m3d_clip_plane_enable user-defined clipping plane disable/enable. (0 represent disable, 1 represent enable) m3d_base+0e 4h m3d normal scale enable/disable register m3d_normal_ scale_enabl e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ norm al_s cale _ena ble type r/w reset 0 m3d_normal_scale_enable normal scale disable/enable. (0 represent disable, 1 represent enable) m3d_base+0e 8h m3d line last pixel m3d_line_las t_pixel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ line_ last_ pixel type r/w reset 0 m3d_line_last_pixel line last pixel disable/enable. (0 represent disable, 1 represent enable) m3d_base+0e ch m3d primitive culling register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1181 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_f ront _face m3d_cull_f ace m3d_ cull_ clip_ plan e m3d_ cull_ z m3d_ cull_ zero_ area m3d_ cull_ all_o ut m3d_ cull _sma ll_t rian gle type r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 m3d_cull_small_triangle cull triangle that don?t enclose any pixel center. (0 represent disable, 1 represent enabl) m3d_cull_all_out trivial rejection when all vertices of a primitive is clipped. (0 represent disable, 1 represent enable) m3d_cull_zero_area trivial rejection when the area of a primitive is zero. (0 represent disable, 1 represent enable) m3d_cull_z z culling. (0 represent disable, 1 represent enable) m3d_cull_clip_plane_0 user-defined clipping plane culling. (0 represent disable, 1 represent enable) m3d_cull_face specifies whether front- or back-facing polygons are culled. (0 represent front, 1 represent back, 2 represent front and back, 3 represent none) m3d_front_face specifies the orientation of front-facing polygons. (0 represent cw, 1 represent ccw) m3d_base+0f 0h m3d shading model register m3d_shade_m odel bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_f lat_t ype m3d_ shad e_mo del type r/w r/w reset 0 1 m3d_shade_model shading model. (0 represent flat, 1 represent smooth) m3d_flat_type flat shading type. (0 represent the last vertex, 1 represent the first vertex) m3d_base+0f 4h m3d lighting control register m3d_light_ct rl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_li ght_in f_pos m3d_ ligh t_f_ enab le m3d_f og_c usto m m3d_l ight_ rang e_enb ale m3d_l ight_ lview _ena ble m3d_l ight_ spot_ enab le m3d_ colo r_su m_lig ht m3d_color_ material_s pecular m3d_color_ material_di ffuse m3d_color _material_ ambient type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1182 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_fog_m ode m3d_f og_e nabl e m3d_ norm alize m3d_l ight_ 7_ena ble m3d_l ight_ 6_ena ble m3d_l ight_ 5_ena ble m3d_l ight_ 4_ena ble m3d_l ight_ 3_ena ble m3d_l ight_ 2_ena ble m3d_l ight_ 1_ena ble m3d_l ight_ 0_ena ble m3d_ ligh ting_ enab le type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 m3d_lighting_enable enable global lighting and thus m3d_lightx_enable is valid. m3d_light_x_enable enable lightx, where x is 0 ~ 7, i.e., supporting 8 light sources at most. m3d_normalize enable normalization of vertex normal which is transformed in tnl stage. m3d_fog_enable enable fog. when it is enabled, the fog factor is calculated in lighting engine and passed to next stage. m3d_fog_mode fog mode. 00 exp. 01 exp2. 10 linear. 11 reserved. m3d_color_material_ambient enable color material for ambient item. in opengl-es, when color material is set, the two bits should be set to ?01? to select color from vertex color 1. 00 material color. 01 from color 1. 10 from color 2. 11 reserved. m3d_color_material_diffuse enable color material for diffuse item. in opengl-es, when color material is set, the two bits should be set to ?01? to select color from vertex color 1. 00 material color. 01 from color 1. 10 from color 2. 11 reserved. m3d_color_material_specular enable color material for specular item. 00 material color. 01 from color 1. 10 from color 2. 11 reserved. m3d_color_sum_light to indicate if the two colors of one vertex should be summed or not. in opengl-es, the diffuse color and specular color are summed in light engine, so it must be set to 1. in d3dm, it must be set to 0. 0 not summed. 1 summed. m3d_light_spot_enable to enable/disable spot light source. in d3dm, it does not support spot light source, so the bit must be set to 0. in opengl-es, it must be set to 1. 0 disable. 1 enable. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1183 of 1535 m3d_light_lview_enable to indicate if local view is supported or not. 0 disable. 1 enable. m3d_light_range_eanble if this bit is enabled, then the attenuation item is zero while the distance between the vertex and the light source exceeds light?s range. 0 disable. 1 enable. m3d_fog_cutom to determine the fog factor is calculated by fog factor equation or is assigned through alpha value of the second color. 0 calculated by fog factor equation. 1 assigned through alpha value of the second color. m3d_light_f_enable specular color?s f enable/disable 0 for d3dm 1 for opengl-es m3d_light_inf_pos to determine the infinite view vector. 0 set infinite view vector [0 0 1] 1 set infinite view vector [0 0 -1] m3d_base+0f 8h m3d texture image #0 height/width/type/format register m3d_tex_img _0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_img_height_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_width_0 rese rve m3d_t ex_by te_or der_0 m3d_tex_img_format_0 type r/w r/w r/w m3d_tex_img_format_0 specifies the format of texture image #0 0 r8g8b8 1 r5g6b5 2 a8r8g8b8 3 x8r8g8b8 4 a1r5g5b5 5 x1r5g5b5 6 l8 7 a8 8 a4r4g4b4 9 x4r5g4b4 10 l8a8 11 (reserved) 12 (reserved) 13 dxt1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1184 of 1535 14 dxt2 15 dxt3 m3d_tex_byte_order_0 specifies the byte order of texture image #0 0 opengl es 1 d3dm m3d_tex_img_width_0 specifies the width of texture image #0 m3d_tex_img_height_0 specifies the height of texture image #0 m3d_base+0f ch m3d texture image #1 height/width/type/format register m3d_tex_img _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_img_height_1 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_width_1 rese rve m3d_t ex_by te_or der_1 m3d_tex_img_format_1 type r/w r/w r/w m3d_tex_img_format_1 specifies the format of texture image #1 m3d_tex_byte_order_1 specifies the byte order of texture image #1 m3d_tex_img_width_1 specifies the width of texture image #1 m3d_tex_img_height_1 specifies the height of texture image #1 m3d_base+10 0h m3d texture image #2 height/width/type/format register m3d_tex_img_ 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_img_height_2 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_width_2 rese rve m3d_t ex_by te_or der_2 m3d_tex_img_format_2 type r/w r/w m3d_tex_img_format_2 specifies the format of texture image #2 m3d_tex_byte_order_2 specifies the byte order of texture image #2 m3d_tex_img_width_2 specifies the width of texture image #2 m3d_tex_img_height_2 specifies the height of texture image #2 m3d_base+10 4h m3d texture control register m3d_tex_ctr l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_t ex_lo d_hal f_en_ 2 m3d_t ex_lo d_hal f_en_ 1 m3d_t ex_lo d_hal f_en_ 0 m3d_t ex_th resh old_2 m3d_t ex_th resh old_e n_1 m3d_t ex_th resh old_e n_0 m3d_max_lod_2 m3d_ max _lod _1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1185 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_max_lod_1 m3d_max_lod_0 m3d_s pecu lar_e nabl e m3d_tex_stage_en m3d_tex_enable type r/w r/w r/w r/w r/w reset 0 0 0 0 0 m3d_tex_enable texture disable/enable. (0 represent disable, 1 represent enable) m3d_tex_stage_en texture stage disable/enable. (0 represent disable, 1 represent enable) m3d_specular_enable d3dm_specularenable m3d_max_lod_0 d3dmtss_maxmiplevel of texture #0 m3d_max_lod_1 d3dmtss_maxmiplevel of texture #1 m3d_max_lod_2 d3dmtss_maxmiplevel of texture #2 m3d_tex_threshold_en_0 magnification threshold 0.5 of texture #0 m3d_tex_threshold_en_1 magnification threshold 0.5 of texture #1 m3d_tex_threshold_en_2 magnification threshold 0.5 of texture #2 m3d_tex_lod_half_en_0 minification less than 0.5 of texture #0 m3d_tex_lod_half_en_1 minification less than 0.5 of texture #1 m3d_tex_lod_half_en_2 minification less than 0.5 of texture #2 m3d_base+10 8h m3d texture image #0 level #0 address m3d_tex_img _ptr_0_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_0[15:0] type r/w m3d_tex_img_ptr_0_0 specifies the address of texture image #0 level #0 m3d_base+10 ch m3d texture image #0 level #1 address m3d_tex_img _ptr_0_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_1[15:0] type r/w m3d_tex_img_ptr_0_1 specifies the address of texture image #0 level #1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1186 of 1535 m3d_base+11 0h m3d texture image #0 level #2 address m3d_tex_img_ ptr_0_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_2[15:0] type r/w m3d_tex_img_ptr_0_2 specifies the address of texture image #0 level #2 m3d_base+11 4h m3d texture image #0 level #3 address m3d_tex_img _ptr_0_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_3[15:0] type r/w m3d_tex_img_ptr_0_3 specifies the address of texture image #0 level #3 m3d_base+11 8h m3d texture image #0 level #4 address m3d_tex_img _ptr_0_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_4[15:0] type r/w m3d_tex_img_ptr_0_4 specifies the address of texture image #0 level #4 m3d_base+11 ch m3d texture image #0 level #5 address m3d_tex_img_ ptr_0_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_5[15:0] type r/w m3d_tex_img_ptr_0_5 specifies the address of texture image #0 level #5 m3d_base+12 0h m3d texture image #0 level #6 address m3d_tex_img _ptr_0_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_6[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1187 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_6[15:0] type r/w m3d_tex_img_ptr_0_6 specifies the address of texture image #0 level #6 m3d_base+12 4h m3d texture image #0 level #7 address m3d_tex_img _ptr_0_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_7[15:0] type r/w m3d_tex_img_ptr_0_7 specifies the address of texture image #0 level #7 m3d_base+12 8h m3d texture image #0 level #8 address m3d_tex_img _ptr_0_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_0_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_0_8[15:0] type r/w m3d_tex_img_ptr_0_8 specifies the address of texture image #0 level #8 m3d_base+12 ch m3d texture image #1 level #0 address m3d_tex_img _ptr_1_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_0[15:0] type r/w m3d_tex_img_ptr_1_0 specifies the address of texture image #1 level #0 m3d_base+13 0h m3d texture image #1 level #1 address m3d_tex_img _ptr_1_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_1[15:0] type r/w m3d_tex_img_ptr_1_1 specifies the address of texture image #1 level #1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1188 of 1535 m3d_base+13 4h m3d texture image #1 level #2 address m3d_tex_img_ ptr_1_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_2[15:0] type r/w m3d_tex_img_ptr_1_2 specifies the address of texture image #1 level #2 m3d_base+13 8h m3d texture image #1 level #3 address m3d_tex_img _ptr_1_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_3[15:0] type r/w m3d_tex_img_ptr_1_3 specifies the address of texture image #1 level #3 m3d_base+13 ch m3d texture image #1 level #4 address m3d_tex_img _ptr_1_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_4[15:0] type r/w m3d_tex_img_ptr_1_4 specifies the address of texture image #1 level #4 m3d_base+14 0h m3d texture image #1 level #5 address m3d_tex_img_ ptr_1_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_5[15:0] type r/w m3d_tex_img_ptr_1_5 specifies the address of texture image #1 level #5 m3d_base+14 4h m3d texture image #1 level #6 address m3d_tex_img _ptr_1_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_6[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1189 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_6[15:0] type r/w m3d_tex_img_ptr_1_6 specifies the address of texture image #1 level #6 m3d_base+14 8h m3d texture image #1 level #7 address m3d_tex_img _ptr_1_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_7[15:0] type r/w m3d_tex_img_ptr_1_7 specifies the address of texture image #1 level #7 m3d_base+14 ch m3d texture image #1 level #8 address m3d_tex_img _ptr_1_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_1_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_1_8[15:0] type r/w m3d_tex_img_ptr_1_8 specifies the address of texture image #1 level #8 m3d_base+15 0h m3d texture image #2 level #0 address m3d_tex_img _ptr_2_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_0[15:0] type r/w m3d_tex_img_ptr_2_0 specifies the address of texture image #2 level #0 m3d_base+15 4h m3d texture image #2 level #1 address m3d_tex_img _ptr_2_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_1[15:0] type r/w m3d_tex_img_ptr_2_1 specifies the address of texture image #2 level #1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1190 of 1535 m3d_base+15 8h m3d texture image #2 level #2 address m3d_tex_img_ ptr_2_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_2[15:0] type r/w m3d_tex_img_ptr_2_2 specifies the address of texture image #2 level #2 m3d_base+15 ch m3d texture image #2 level #3 address m3d_tex_img _ptr_2_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_3[15:0] type r/w m3d_tex_img_ptr_2_3 specifies the address of texture image #2 level #3 m3d_base+16 0h m3d texture image #2 level #4 address m3d_tex_img _ptr_2_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_4[15:0] type r/w m3d_tex_img_ptr_2_4 specifies the address of texture image #2 level #4 m3d_base+16 4h m3d texture image #2 level #5 address m3d_tex_img_ ptr_2_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_5[15:0] type r/w m3d_tex_img_ptr_2_5 specifies the address of texture image #2 level #5 m3d_base+16 8h m3d texture image #2 level #6 address m3d_tex_img _ptr_2_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_6[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1191 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_6[15:0] type r/w m3d_tex_img_ptr_2_6 specifies the address of texture image #2 level #6 m3d_base+16 ch m3d texture image #2 level #7 address m3d_tex_img _ptr_2_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_7[15:0] type r/w m3d_tex_img_ptr_2_7 specifies the address of texture image #2 level #7 m3d_base+17 0h m3d texture image #2 level #8 address m3d_tex_img _ptr_2_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_img_ptr_2_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_img_ptr_2_8[15:0] type r/w m3d_tex_img_ptr_2_8 specifies the address of texture image #2 level #8 m3d_base+17 4h|974h m3d color r register m3d_color_r _0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_r_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_r_0[15:0] type r/w m3d_color_r_0 set the current color r. (0088h : data format is s15.16, 2088h : data format is s[8].23) m3d_base+17 8h|978h m3d color g register m3d_color_g _0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_g_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_g_0[15:0] type r/w m3d_color_g_0 set the current color g. (008ch : data format is s15.16, 208ch : data format is s[8].23) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1192 of 1535 m3d_base+17 ch|97ch m3d color b register m3d_color_b _0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_b_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_b_0[15:0] type r/w m3d_color_b_0 set the current color b. (0090h : data format is s15.16, 2090h : data format is s[8].23) m3d_base+18 0h|980h m3d color a register m3d_color_a _0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_a_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_a_0[15:0] type r/w m3d_color_a_0 set the current color a. (0094h : data format is s15.16, 2094h : data format is s[8].23) m3d_base+18 4h|984h m3d color r register m3d_color_r _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_r_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_r_1[15:0] type r/w m3d_color_r_1 set the current color r. (0088h : data format is s15.16, 2088h : data format is s[8].23) m3d_base+18 8h|988h m3d color g register m3d_color_g _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_g_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_g_1[15:0] type r/w m3d_color_g_1 set the current color g. (008ch : data format is s15.16, 208ch : data format is s[8].23) m3d_base+18 ch|98ch m3d color b register m3d_color_b _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_b_1[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1193 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_b_1[15:0] type r/w m3d_color_b_1 set the current color b. (0090h : data format is s15.16, 2090h : data format is s[8].23) m3d_base+19 0h|990h m3d color a register m3d_color_a _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_color_a_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_color_a_1[15:0] type r/w m3d_color_a_1 set the current color a. (0094h : data format is s15.16, 2094h : data format is s[8].23) m3d_base+19 8h m3d scissor test enable/disable register m3d_scissor _enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_ sciss or_e nabl e type r/w reset 0 m3d_scissor_enable scissor test disable/enable. (0 represent disable, 1 represent enable) m3d_base+19 ch m3d scissor test left boundary register m3d_scissor _left bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_scissor_left[9:0] type r/w reset 0 m3d_scissor_left scissor box left boundary m3d_base+1a 0h m3d scissor test bottom boundary register m3d_scissor _bottom bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1194 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_scissor_bottom[9:0] type r/w reset 0 m3d_scissor_bottom scissor box bottom boundary m3d_base+1a 4h m3d scissor test right boundary register m3d_scissor _right bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_scissor_right[9:0] type r/w reset 0 m3d_scissor_right scissor box right boundary m3d_base+1a 8h m3d scissor test top boundary register m3d_scissor _top bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_scissor_top[9:0] type r/w reset 0 m3d_scissor_top scissor box top boundary m3d_base+1 ach m3d alpha test register m3d_alpha_t est bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_alpha_test_ref[7:0] m3d_alpha_func[2 :0] m3d_ alph a_tes t_ena ble type r/w r/w r/w reset 0 0 0 m3d_alpha_test_enable enable alpha test. m3d_alpha_test_func the alpha test function. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1195 of 1535 000 never 001 less 010 equal 011 lequal 100 greater 101 notequal 110 gequal 111 always m3d_alpha_test_ref the alpha test reference value. m3d_base+1 b0h m3d stencil test register m3d_stencil _test bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_s tenci l_tes t_fmt m3d_stencil_test_ dppass_op m3d_stencil_test_ dpfail_op m3d_stencil_test_ sfail_op m3d_stencil_test_mas k[7:4] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_stencil_test_mask[ 3:0] m3d_stencil_test_ref[7:0] m3d_stencil_test _func[2:0] m3d_ sten cilt est_ ena ble type r/w r/w r/w r/w reset 0 0 0 0 m3d_stencil_test_enable enable stencil test. m3d_stencil_test_func stencil test function 000 never 001 less 010 equal 011 lequal 100 greater 101 notequal 110 gequal 111 always m3d_stencil_test_ref stencil test reference value. m3d_stencil_test_mask stencil test mask. m3d_stencil_test_sfail_op the stencil operation when stencil test fails. 000 keep 001 replace 010 incr 011 decr 100 zero free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1196 of 1535 101 invert 110 incr_wrap 111 decr_wrap m3d_stencil_test_dpfail_op the stencil operation when depth test fails. 000 keep 001 replace 010 incr 011 decr 100 zero 101 invert 110 incr_wrap 111 decr_wrap m3d_stencil_test_dppass_op the stencil operation when depth test passes. 000 keep 001 replace 010 incr 011 decr 100 zero 101 invert 110 incr_wrap 111 decr_wrap m3d_stencil_test_fmt the stencil value format. 0 8-bits 1 1-bit. m3d_base+1 b4h m3d depth test register m3d_depth_t est bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_z _mas k m3d_depth_func[2: 0] m3d_ dept ha_t est_ enab le type r/w r/w r/w reset 0 0 0 m3d_depth_test_enable enable the depth test. m3d_depth_test_func select the depth function 000 never 001 less 010 equal free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1197 of 1535 011 lequal 100 greater 101 notequal 110 gequal 111 always m3d_z_test_mask z buffer mask. set this bit to 0 to disable z buffer output. m3d_base+1 b8h m3d blending register m3d_blend bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_blend_op m3d_r _mas k m3d_ g_ma sk m3d_b _mas k m3d_a _mas k m3d_blend_func_dest[3: 0] m3d_blend_func_src[3:0 ] m3d_ blen d_en able type r/w r/w r/w r/w r/w r/w r/w reset 0 1 1 1 1 0 0 m3d_blend_enable enable the blending function. m3d_blend_func_src select the blending function for source color. 0000 blend_src_color 0001 blend_one_minus_src_color 0010 blend_src_alpha 0011 blend_one_minus_src_alpha 0100 blend_dst_alpha 0101 blend_one_minus_dst_alpha 0110 blend_dst_color 0111 blend_one_minus_dst_color 1000 blend_src_alpha_saturate 1001 blend_zero 1010 blend_one m3d_blend_func_dest select the blending function for destination color. 0000 blend_src_color 0001 blend_one_minus_src_color 0010 blend_src_alpha 0011 blend_one_minus_src_alpha 0100 blend_dst_alpha 0101 blend_one_minus_dst_alpha 0110 blend_dst_color 0111 blend_one_minus_dst_color 1000 blend_src_alpha_saturate 1001 blend_zero 1010 blend_one free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1198 of 1535 m3d_a_mask the alpha color mask. set this bit to 0 will disable the alpha channel output to color buffer. m3d_b_mask the blue color mask. set this bit to 0 will disable the blue channel output to color buffer. m3d_g_mask the green color mask. set this bit to 0 will disable the green channel output to color buffer. m3d_r_mask the red color mask. set this bit to 0 will disable the red channel output to color buffer. m3d_blend_op select the blending operation 000 c = cs*s + cd*d 001 c = cs*s?cd*d 010 c = cd*d?cs*s 011 c = min(cs,cd) 100 c = max(cs,cd) m3d_base+1 bch m3d logic operation register m3d_logic_o p bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_logic_op_func[3:0] m3d_l ogic_ op_e nabl e type r/w r/w r/w reset 0 0 0 m3d_logic_op_enable enable the logic operation. m3d_logic_op_func select the logic operation function 0000 clear 0001 and 0010 and_reverse 0011 copy 0100 and_inverted 0101 noop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or_reverse 1100 copy_inverted 1101 or_inverted 1110 nand free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1199 of 1535 1111 set m3d_base+1 c0h m3d frame buffer format register m3d_frame_b uf_format bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frame_buf_f ormat type r/w reset 0 m3d_frame_buf_format select the format of color buffer 001 rgb_888 010 rgb565 100 argb8888 m3d_base+1 c4h m3d frame buffer address register m3d_frame_b uf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_frame_buf_addr[31:16] type r/w 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frame_buf_addr[15:0] type r/w reset 0 m3d_frame_buf_addr color buffer address. m3d_base+1 c8h m3d frame buffer width register m3d_frame_b uf_width bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frame_buf_widith[9:0] type r/w reset 0 m3d_frame_buf_width frame buffer width. m3d_base+1 cch m3d frame buffer height register m3d_frame_b uf_height bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1200 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frame_buf_height[9:0] type r/w reset 0 m3d_frame_buf_height frame buffer height. m3d_base+1d 0h m3d stencil buffer write mask register m3d_stencil_ wt_mask bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_stencil_wt_mask type r/w reset ff m3d_stencil_wt_mask stencil buffer write mask after stencil operation. m3d_base+1 d4h m3d depth buffer address register m3d_depth_b uf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_depth_buf_addr[31:16] type r/w 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_depth_buf_addr[15:0] type r/w reset 0 m3d_depth_buf_addr depth buffer address. m3d_base+1 d8h m3d stencil buffer address register m3d_stencil_ buf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_stencil_buf_addr[31:16] type r/w 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_stencil_buf_addr[15:0] type r/w reset 0 m3d_stencil_buf_addr stencil buffer address. m3d_base+1 dch m3d depth buffer clear value register m3d_depth_c lear_val bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1201 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_depth_clear_val[15:0] type r/w reset 0 m3d_depth_clear_val depth buffer clear value. m3d_base+1e 8h m3d earlyz test enable/disable register m3d_early_z _enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_e arlyz _mod e m3d_ earl y_z_e nabl e type r/w r/w reset 0 0 m3d_early_z_enable earlyz test disable/enable. (0 represent disable, 1 represent enable) earlyz must be disable when alpha test/stencil test/line/point is enable once earlyz is disable at some list, it must be disable until the frame buffer is flush m3d_earlyz_mode earlyz mode. (0 specifies each earlyz buffer unit contains 4 pix, 1 specifies each earlyz buffer unit contains 8 pix) set m3d_earlyz_mode=0, better performance but more sysram usage set m3d_earlyz_mode=1, worse performance but less sysram usage if sysram is big enough, set m3d_earlyz_mode 0 is recommended m3d_base+1e ch m3d earlyz buffer address register m3d_early_z _buf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_early_z_buf_addr[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_early_z_buf_addr[15:0] type r/w m3d_early_z_buf_addr specifies the memory address of the earlyz buffer for vga size, earlyz buffer is 76.8kb(earlyz mode 0) and 38.4kb(earlyz mode 1) for qvga size, earlyz buffer is 38.4kb(earlyz mode 0) and 19.2kb(earlyz mode 1) if earlyz is enable, clear depth buffer and earlyz buffer at the same time. the clear value of earlyz buffer is {1?b0,m3d_depth_clear_val[15:9]} free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1202 of 1535 m3d_base+1f ch m3d intsta_wack m3d_intsta_ wtack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserved type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserved m3d_ colo r_flu sh_d one_i ntst a_wt ack m3d_z _flus h_do ne_in tsta_ wtac k rese rved rese rved reser ved rese rved m3d_ rend er_d one_i ntst a_wt ack type w w w m3d_render_done_intsta mcu clear interrupting status of rendering. m3d_z_flush_done_intsta mcu clear interrupting status of z cache flush. m3d_color_flush_done_intsta mcu clear interrupting status of color cache flush. m3d_base+20 0h|a00h m3d texture image #0 environment red color m3d_tex_env _color_r_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_r_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_r_0[15:0] type r/w m3d_tex_env_color_r_0 specifies the environment red color of texture image #0 m3d_base+20 4h|a04h m3d texture image #0 environment green color m3d_tex_env _color_g_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_g_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_g_0[15:0] type r/w m3d_tex_env_color_g_0 specifies the environment green color of texture image #0 m3d_base+20 8h|a08h m3d texture image #0 environment blue color m3d_tex_env _color_b_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_b_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_b_0[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1203 of 1535 m3d_tex_env_color_b_0 specifies the environment blue color of texture image #0 m3d_base+20 ch|a0ch m3d texture image #0 environment alpha color m3d_tex_env _color_a_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_a_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_a_0[15:0] type r/w m3d_tex_env_color_a_0 specifies the environment alpha color of texture image #0 m3d_base+21 0h|a10h m3d texture image #1 environment red color m3d_tex_env _color_r_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_r_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_r_1[15:0] type r/w m3d_tex_env_color_r_1 specifies the environment red color of texture image #1 m3d_base+21 4h|a14h m3d texture image #1 environment green color m3d_tex_env _color_g_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_g_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_g_1[15:0] type r/w m3d_tex_env_color_g_1 specifies the environment green color of texture image #1 m3d_base+21 8h|a18h m3d texture image #1 environment blue color m3d_tex_env _color_b_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_b_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_b_1[15:0] type r/w m3d_tex_env_color_b_1 specifies the environment blue color of texture image #1 m3d_base+21 ch|a1ch m3d texture image #1 environment alpha color m3d_tex_env _color_a_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_a_1[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1204 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_a_1[15:0] type r/w m3d_tex_env_color_a_1 specifies the environment alpha color of texture image #1 m3d_base+22 0h|a20h m3d texture image #2 environment red color m3d_tex_env _color_r_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_r_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_r_2[15:0] type r/w m3d_tex_env_color_r_2 specifies the environment red color of texture image #2 m3d_base+22 4h|a24h m3d texture image #2 environment green color m3d_tex_env _color_g_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_g_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_g_2[15:0] type r/w m3d_tex_env_color_g_2 specifies the environment green color of texture image #2 m3d_base+22 8h|a28h m3d texture image #2 environment blue color m3d_tex_env _color_b_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_b_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_b_2[15:0] type r/w m3d_tex_env_color_b_2 specifies the environment blue color of texture image #2 m3d_base+22 ch|a2ch m3d texture image #2 environment alpha color m3d_tex_env _color_a_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_env_color_a_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_env_color_a_2[15:0] type r/w m3d_tex_env_color_a_2 specifies the environment alpha color of texture image #2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1205 of 1535 m3d_base+23 0h|a30h m3d texture #0 mipmap lod bias m3d_lod_bia s_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_lod_bias_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_lod_bias_0[15:0] type r/w m3d_lod_bias_0 specifies the mipmap lod bias of texture image #0 m3d_base+23 4h|a34h m3d texture #1 mipmap lod bias m3d_lod_bia s_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_lod_bias_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_lod_bias_1[15:0] type r/w m3d_lod_bias_1 specifies the mipmap lod bias of texture image #1 m3d_base+23 8h|a38h m3d texture #2 mipmap lod bias m3d_lod_bia s_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_lod_bias_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_lod_bias_2[15:0] type r/w m3d_lod_bias_2 specifies the mipmap lod bias of texture image #2 m3d_base+23 ch m3d vertex cache hit counter m3d_vc_hit_c nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vc_hit_cnt[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vc_hit_cnt[15:0] type r/w m3d_vc_hit_cnt vertex cache hit counter. m3d_base+240 h m3d texture image #0 scale and texture operation m3d_tex_op_ 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1206 of 1535 name reserve m3d _te x_o p_d st_ a_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_t ex_op _dst_ rgb_0 m3d_tex _dot3_r gba_0 m3d_tex_a_ scale_0 m3d_tex_rg b_scale_0 m3d_tex_op_a_0 m3d_tex_op_rgb_0 type r/w r/w r/w r/w r/w r/w m3d_tex_op_rgb_0 specifies rgb operation of texture image #0 0 selectarg1 1 selectarg2 2 modulate 3 add 4 addsigned 5 subtract 6 premodulate 7 dotproduct3 8 multiplyadd 9 lerp m3d_tex_op_a_0 specifies a operation of texture image #0 m3d_tex_ rgb_scale_0 specifies rgb scale of texture image #0 m3d_tex_ a_scale_0 specifies a scale of texture image #0 m3d_tex_ dot3_rgba_0 specifies dot3_rgba environment mode of texture image #0 m3d_tex_op_dst_rgb_0 specifies rgb output destination of texture image #0 0 default (current) 1 temp m3d_tex_op_dst_a_0 specifies a output destination of texture image #0 opengl es texture functions: // initialization m3d_tex_op_rgb_0 = m3d_tex_op_a_= m3d_tex_op_selectarg1; m3d_tex_src0_rgb_0 = m3d_tex_src1_rgb_0 = m3d_tex_src2_rgb_0 = m3d_tex_src0_a_0 = m3d_tex_src1_a_0 = m3d_tex_src2_a_0 = m3d_tex_src_primary; m3d_tex_opd0_rgb_0 = m3d_tex_opd1_rgb_1 = m3d_tex_opd2_rgb_2 = m3d_tex_opd_src_color; m3d_tex_opd0_a_0 = free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1207 of 1535 m3d_tex_opd1_a_0 = m3d_tex_opd2_a_0 = m3d_tex_opd_src_alpha; m3d_tex_rgb_scale_0 = 0; m3d_tex_a_scale_0 = 0; m3d_tex_dot3_rgba_0 = false; switch (texture function) { case replace : // rgb part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_previous; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_texture; break; default: assert(false); break; } } // a part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_op_src1_a_0 = m3d_tex_src_texture; break; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1208 of 1535 case m3d_tex_fmt_l8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_src1_a_0 = m3d_tex_src_previous; break; default: assert(false); break; } } case modulate : // rgb part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_previous; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_rgb_0 = m3d_tex_op_modulate; m3d_tex_src1_rgb_0 = m3d_tex_src_previous; m3d_tex_src2_rgb_0 = m3d_tex_src_texture; break; default: assert(false); break; } } // a part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_a8r8g8b8: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1209 of 1535 case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_a_0 = m3d_tex_op_modulate; m3d_tex_src1_a_0 = m3d_tex_src_previous; m3d_tex_src2_a_0 = m3d_tex_src_texture; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: m3d_tex_op_a_0 = m3d_tex_op_selectarg1 m3d_tex_src1_a_0 = m3d_tex_src_previous; break; default: assert(false); break; } } break; case decal : // rgb part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_texture; break; case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_rgb_0 = m3d_tex_op_lerp; m3d_tex_src0_rgb_0 = m3d_tex_src_texture; m3d_tex_src1_rgb_0 = m3d_tex_src_texture; m3d_tex_src2_rgb_0 = m3d_tex_src_previous; m3d_tex_opd0_rgb_0 = m3d_tex_opd_src_alpha; break; default: assert(false); break; } } // a part free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1210 of 1535 { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_src1_a_0 = m3d_tex_src_previous; break; default: assert(false); break; } } break; case blend : // rgb part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_previous; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_rgb_0 = m3d_tex_op_lerp; m3d_tex_src0_rgb_0 = m3d_tex_src_texture; m3d_tex_src1_rgb_0 = m3d_tex_src_constant; m3d_tex_src2_rgb_0 = m3d_tex_src_previous; break; default: assert(false); break; } } free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1211 of 1535 // a part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_a_0 = m3d_tex_op_modulate; m3d_tex_src1_a_0 = m3d_tex_src_previous; m3d_tex_src2_a_0 = m3d_tex_src_texture: break; case m3d_tex_fmt_l8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_src1_a_0 = m3d_tex_src1_previous; break; default: assert(false); break; } } break; case add : // rgb part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = m3d_tex_src_previous; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b5: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_rgb_0 = m3d_tex_op_add; m3d_tex_src1_rgb_0 = m3d_tex_src1_previous; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1212 of 1535 m3d_tex_src2_rgb_0 = m3d_tex_src2_texture; break; default: assert(false); break; } } // a part { switch (m3d_tex_img_0[3:0]) { case m3d_tex_fmt_a8: case m3d_tex_fmt_l8a8: case m3d_tex_fmt_a8r8g8b8: case m3d_tex_fmt_a1r5g5b5: case m3d_tex_fmt_a4r4g4b4: m3d_tex_op_a_0 = m3d_tex_op_modulate; m3d_tex_src1_a_0 = m3d_tex_src1_previous; m3d_tex_src2_a_0 = m3d_tex_src2_texture; break; case m3d_tex_fmt_l8: case m3d_tex_fmt_r8g8b8: case m3d_tex_fmt_r5g6b8: m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_src1_a_0 = m3d_tex_src_previous; break; default: assert(false); break; } } break; case combine : // rgb part { switch (combine_rgb) { case replace : m3d_tex_op_rgb_0 = m3d_tex_op_selectarg1; m3d_tex_src1_rgb_0 = src0_rgb_0; break; case modulate : m3d_tex_op_rgb_0 = m3d_tex_op_modulate; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1213 of 1535 m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case add : m3d_tex_op_rgb_0 = m3d_tex_op_add; m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case add_signed : m3d_tex_op_rgb_0 = m3d_tex_op_addsigned; m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case interpolate : m3d_tex_op_rgb_0 = m3d_tex_op_lerp; m3d_tex_src0_rgb_0 = src2_rgb_0 m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case subtract : m3d_tex_op_rgb_0 = m3d_tex_op_subtract; m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case dot3_rgb : m3d_tex_op_rgb_0 = m3d_tex_op_dotproduct3; m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; case dot3_rgba : m3d_tex_dot3_rgba = true; m3d_tex_op_rgb_0 = m3d_tex_op_dotproduct3; m3d_tex_src1_rgb_0 = src0_rgb_0; m3d_tex_src2_rgb_0 = src1_rgb_0; break; default: assert(false); break; } } // a part { switch (combine_a) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1214 of 1535 { case replace : m3d_tex_op_a_0 = m3d_tex_op_selectarg1; m3d_tex_src1_a_0 = src0_a_0; break; case modulate : m3d_tex_op_a_0 = m3d_tex_op_modulate; m3d_tex_src1_a_0 = src0_a_0; m3d_tex_src2_a_0 = src1_a_0; break; case add : m3d_tex_op_a_0 = m3d_tex_op_add; m3d_tex_src1_a_0 = src0_a_0; m3d_tex_src2_a_0 = src1_a_0; break; case add_signed : m3d_tex_op_a_0 = m3d_tex_op_addsigned; m3d_tex_src1_a_0 = src0_a_0; m3d_tex_src2_a_0 = src1_a_0; break; case interpolate : m3d_tex_op_a_0 = m3d_tex_op_lerp; m3d_tex_src0_a_0 = src2_a_0 m3d_tex_src1_a_0 = src0_a_0; m3d_tex_src2_a_0 = src1_a_0; break; case subtract : m3d_tex_op_a_0 = m3d_tex_op_subtract; m3d_tex_src1_a_0 = src0_a_0; m3d_tex_src2_a_0 = src1_a_0; break; default: assert(false); break; } } m3d_tex_opd0_rgb_0 = operand2_rgb_0; m3d_tex_opd1_rgb_0 = operand0_rgb_0; m3d_tex_opd2_rgb_0 = operand1_rgb_0; m3d_tex_opd0_a_0 = operand2_a_0; m3d_tex_opd1_a_0 = operand0_a_0; m3d_tex_opd2_a_0 = operand1_a_0; m3d_tex_rgb_scale_0 = scale_rgb_0; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1215 of 1535 m3d_tex_a_scale_0 = scale_a_0; break; default: assert(false); break; } m3d_base+244 h m3d texture image #1 scale and texture operation m3d_tex_op_ 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d _te x_o p_d st_ a_1 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_t ex_op _dst_ rgb_1 m3d_te s_dot3_ rgba_1 m3d_tex_a_ scale_1 m3d_tex_rg b_scale_1 m3d_tex_op_a_1 m3d_tex_op_rgb_1 type r/w r/w r/w r/w r/w r/w m3d_tex_op_rgb_1 specifies rgb operation of texture image #1 m3d_tex_op_a_1 specifies a operation of texture image #1 m3d_tex_ rgb_scale_1 specifies rgb scale of texture image #1 m3d_tex_ a_scale_1 specifies a scale of texture image #1 m3d_tex_ dot3_rgba_1 specifies dot3_rgba environment mode of texture image #1 m3d_tex_ op_dst_rgb_1 specifies rgb output destination of texture image #1 m3d_tex_ op_dst_a_1 specifies a output destination of texture image #1 m3d_base+248 h m3d texture image #2 scale and texture operation m3d_tex_op_ 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d _te x_o p_d st_ a_2 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_t ex_op _dst_ rgb_2 m3d_tex _dot3_r gba_2 m3d_tex_a_ scale_2 m3d_tex_rg b_scale_2 m3d_tex_op_a_2 m3d_tex_op_rgb_2 type r/w r/w r/w r/w r/w r/w m3d_tex_op_rgb_2 specifies the texture function of texture image #2 m3d_tex_op_a_2 specifies a combine function of texture image #2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1216 of 1535 m3d_tex_ rgb_scale_2 specifies rgb scale of texture image #2 m3d_tex_ a_scale_2 specifies a scale of texture image #2 m3d_tex_ dot3_rgba_2 specifies dot3_rgba environment mode of texture image #2 m3d_tex_ op_dst_rgb_2 specifies rgb output destination of texture image #2 m3d_tex_ op_dst_a_2 specifies a output destination of texture image #2 m3d_base+24 ch m3d vertex cache vertex counter m3d_vc_vtx_ cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vc_vtx_cnt[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vc_vtx_cnt[15:0] type r/w m3d_vc_vtx_cnt vertex cache vertex counter. m3d_base+250 h m3d texture image #0 rgba source m3d_tex_src _opd_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_opd_rgba_0 m3d_tex_s rc_rgba_ 0[17:16] type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_src_rgba_0[15:0] type r/w m3d_tex_src_rgba_0 specifies source of texture image #0 m3d_tex_src0_rgb[2:0] specifies rgb source #0 of texture image #0 m3d_tex_src1_rgb[5:3] specifies rgb source #1 of texture image #0 m3d_tex_src2_rgb[8:6] specifies rgb source #2 of texture image #0 m3d_tex_src0_a[11:9] specifies a source #0 of texture image #0 m3d_tex_src1_a[14:12] specifies a source #1 of texture image #0 m3d_tex_src2_a[17:15] specifies a source #2 of texture image #0 000 m3d_tex_src_texture 001 m3d_tex_src_constant 010 m3d_tex_src_primary 011 m3d_tex_src_previous (current) 100 m3d_tex_src_secondary 101 m3d_tex_src_temp 110 m3d_tex_src_zero m3d_tex_opd_rgba_0 specifies operand of texture image #0 m3d_tex_opd0_rgb[1:0] specifies rgb operand #0 of texture image #0 m3d_tex_opd1_rgb[3:2] specifies rgb operand #1 of texture image #0 m3d_tex_opd2_rgb[5:4] specifies rgb operand #2 of texture image #0 m3d_tex_opd0_a[7:6] specifies a operand #0 of texture image #0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1217 of 1535 m3d_tex_opd1_a[9:8] specifies a operand #1 of texture image #0 m3d_tex_opd2_a[11:10] specifies a operand #2 of texture image #0 00 m3d_tex_opd_src_color 01 m3d_tex_one_minus_src_color 10 m3d_tex_src_alpha 11 m3d_tex_one_minus_src_alpha m3d_base+254 h m3d texture image #1 rgba source/operand m3d_tex_src _opd_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_opd_rgba_1 m3d_tex_s rc_rgba_ 1[17:16] type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_src_rgba_1[15:0] type r/w m3d_tex_src_rgba_1 specifies source of texture image #1 m3d_tex_opd_rgba_1 specifies operand of texture image #1 m3d_base+258 h m3d texture image #2 rgba source/operand m3d_tex_src _op_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve m3d_tex_operand_rgba_2 m3d_tex_s rc_rgba_ 2[17:16] type r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_src_rgba_2[11:0] type r/w m3d_tex_src_rgba_2 specifies source of texture image #2 m3d_tex_opd_rgba_2 specifies operand of texture image #2 m3d_base+25 ch m3d fill mode m3d_fill_mo de bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_fill_m ode type r/w reset 2 m3d_fill_mode fill mode. (0 represent point, 1 represent wireframe, 2 represent solid) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1218 of 1535 m3d_base+26 0h|a60h m3d x of visible box lower-left register m3d_vb_xllc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vb_xllc[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vb_xllc [15:0] type r/w m3d_vb_xllc x of visible box lower-left. (0260h : data format is s15.16, 2260h : data format is s[8].23) m3d_base+26 4h|a64h m3d y of visible box lower-left register m3d_vb_yllc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vb_yllc[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vb_yllc [15:0] type r/w m3d_vb_yllc y of visible box lower-left. (0264h : data format is s15.16, 2264h : data format is s[8].23) m3d_base+26 8h|a68h m3d y of visible box upper-right register m3d_vb_xurc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vb_xurc[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vb_xurc [15:0] type r/w m3d_vb_xurc x of visible box upper-right. (0268h : data format is s15.16, 2268h : data format is s[8].23) m3d_base+26 ch|a6ch m3d y of visible box upper-right register m3d_vb_yurc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_vb_yurc[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_vb_yurc [15:0] type r/w m3d_vb_yurc y of visible box upper-right. (026ch : data format is s15.16, 226ch : data format is s[8].23) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1219 of 1535 m3d_base+27 0h|a70h m3d frustum near register m3d_frustum _near bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_frustum_near[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frustum_near [15:0] type r/w m3d_frustum_near n in glfrustum. (0270h : data format is s15.16, 2270h : data format is s[8].23) m3d_base+27 4h|a74h m3d frustum far register m3d_frustum _far bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_frustum_far[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_frustum_far [15:0] type r/w m3d_frustum_far f in glfrustum. (0274h : data format is s15.16, 2274h : data format is s[8].23) m3d_base+27 8h|a78h m3d view port near register m3d_viewpor t_near bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_viewport_near[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_viewport_near [15:0] type r/w m3d_viewport_near n in gldepthrange. (0278h : data format is s15.16, 2278h : data format is s[8].23) m3d_base+27 ch|a7ch m3d view port far register m3d_viewpor t_far bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_viewport_far[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_viewport_far [15:0] type r/w m3d_viewport_far f in gldepthrange. (027ch : data format is s15.16, 227ch : data format is s[8].23) m3d_base+28 0h|a80h m3d model view matrix register m3d_model_v iew_m_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_1[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1220 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_1 [15:0] type r/w m3d_model_view_1 model view matrix. (0280h : data format is s15.16, 2280h : data format is s[8].23) m3d_base+28 4h|a84h m3d model view matrix register m3d_model_v iew_m_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_2 [15:0] type r/w m3d_model_view_2 model view matrix. m3d_base+28 8h|a88h m3d model view matrix register m3d_model_v iew_m_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_3 [15:0] type r/w m3d_model_view_3 model view matrix. m3d_base+28 ch|a8ch m3d model view matrix register m3d_model_v iew_m_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_4 [15:0] type r/w m3d_model_view_4 model view matrix. m3d_base+29 0h|a90h m3d model view matrix register m3d_model_v iew_m_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_5 [15:0] type r/w m3d_model_view_5 model view matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1221 of 1535 m3d_base+29 4h|a94h m3d model view matrix register m3d_model_v iew_m_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_6 [15:0] type r/w m3d_model_view_6 model view matrix. m3d_base+29 8h|a98h m3d model view matrix register m3d_model_v iew_m_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_7 [15:0] type r/w m3d_model_view_7 model view matrix. m3d_base+29 ch|a9ch m3d model view matrix register m3d_model_v iew_m_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_8 [15:0] type r/w m3d_model_view_8 model view matrix. m3d_base+2a 0h|aa0h m3d model view matrix register m3d_model_v iew_m_9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_9 [15:0] type r/w m3d_model_view_9 model view matrix. m3d_base+2a 4h|aa4h m3d model view matrix register m3d_model_v iew_m_10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_10[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1222 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_10 [15:0] type r/w m3d_model_view_10 model view matrix. m3d_base+2a 8h|aa8h m3d model view matrix register m3d_model_v iew_m_11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_11[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_11 [15:0] type r/w m3d_model_view_11 model view matrix. m3d_base+2a ch|aach m3d model view matrix register m3d_model_v iew_m_12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_12[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_12 [15:0] type r/w m3d_model_view_12 model view matrix. m3d_base+2b 0h|ab0h m3d model view matrix register m3d_model_v iew_m_13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_13[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_13 [15:0] type r/w m3d_model_view_13 model view matrix. m3d_base+2b 4h|ab4h m3d model view matrix register m3d_model_v iew_m_14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_14[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_14 [15:0] type r/w m3d_model_view_14 model view matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1223 of 1535 m3d_base+2b 8h|ab8h m3d model view matrix register m3d_model_v iew_m_15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_15[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_15 [15:0] type r/w m3d_model_view_15 model view matrix. m3d_base+2b ch|abch m3d model view matrix register m3d_model_v iew_m_16 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_model_view_16[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_model_view_16 [15:0] type r/w m3d_model_view_16 model view matrix. m3d_base+2c 0h|ac0h m3d vp matrix register m3d_pv_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_1 [15:0] type r/w m3d_pv_1 vp matrix. (02c0h : data format is s15.16, 22c0h : data format is s[8].23) m3d_base+2c 4h|ac4h m3d vp matrix register m3d_pv_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_2 [15:0] type r/w m3d_pv_2 vp matrix. m3d_base+2c 8h|ac8h m3d vp matrix register m3d_pv_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_3[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1224 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_3 [15:0] type r/w m3d_pv_3 vp matrix. m3d_base+2c ch|acch m3d vp matrix register m3d_pv_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_4 [15:0] type r/w m3d_pv_4 vp matrix. m3d_base+2d 0h|ad0h m3d vp matrix register m3d_pv_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_5 [15:0] type r/w m3d_pv_5 vp matrix. m3d_base+2d 4h|ad4h m3d vp matrix register m3d_pv_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_6 [15:0] type r/w m3d_pv_6 vp matrix. m3d_base+2d 8h|ad8h m3d vp matrix register m3d_pv_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_7 [15:0] type r/w m3d_pv_7 vp matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1225 of 1535 m3d_base+2d ch|adch m3d vp matrix register m3d_pv_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_8 [15:0] type r/w m3d_pv_8 vp matrix. m3d_base+2e 0h|ae0h m3d vp matrix register m3d_pv_9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_9 [15:0] type r/w m3d_pv_9 vp matrix. m3d_base+2e 4h|ae4h m3d vp matrix register m3d_pv_10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_10[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_10 [15:0] type r/w m3d_pv_10 vp matrix. m3d_base+2e 8h|ae8h m3d vp matrix register m3d_pv_11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_11[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_11 [15:0] type r/w m3d_pv_11 vp matrix. m3d_base+2e ch|aech m3d vp matrix register m3d_pv_12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_12[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1226 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_12 [15:0] type r/w m3d_pv_12 vp matrix. m3d_base+2f 0h|af0h m3d vp matrix register m3d_pv_13 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_13[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_13 [15:0] type r/w m3d_pv_13 vp matrix. m3d_base+2f 4h|af4h m3d vp matrix register m3d_pv_14 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_14[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_14 [15:0] type r/w m3d_pv_14 vp matrix. m3d_base+2f 8h|af8h m3d vp matrix register m3d_pv_15 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_15[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_15 [15:0] type r/w m3d_pv_15 vp matrix. m3d_base+2f ch|afch m3d vp matrix register m3d_pv_16 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pv_16[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pv_16 [15:0] type r/w m3d_pv_16 vp matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1227 of 1535 m3d_base+30 0h|b00h m3d user-defined clipping plane matrix register m3d_c_n_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_c_n_x[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_c_n_x [15:0] type r/w m3d_c_n_x user-defined clipping plane matrix. (0300h : data format is s15.16, 2300h : data format is s[8].23) m3d_base+30 4h|b04h m3d user-defined clipping plane matrix register m3d_c_n_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_c_n_y[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_c_n_y [15:0] type r/w m3d_c_n_y user-defined clipping plane matrix. m3d_base+30 8h|b08h m3d user-defined clipping plane matrix register m3d_c_n_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_c_n_z[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_c_n_z [15:0] type r/w m3d_c_n_z user-defined clipping plane matrix. m3d_base+30 ch|b0ch m3d user-defined clipping plane matrix register m3d_c_n_w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_c_n_w[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_c_n_w [15:0] type r/w m3d_c_n_w user-defined clipping plane matrix. m3d_base+31 0h|b10h m3d texture image #0 border red color m3d_tex_bor der_r_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_r_0[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1228 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_r_0[15:0] type r/w m3d_tex_border_r_0 specifies the border red color of texture image #0 m3d_base+31 4h|b14h m3d texture image #0 border green color m3d_tex_bor der_g_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_g_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_g_0[15:0] type r/w m3d_tex_border_g_0 specifies the border green color of texture image #0 m3d_base+31 8h|b18h m3d texture image #0 border blue color m3d_tex_bor der_b_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_b_0[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_b_0[15:0] type r/w m3d_tex_border_b_0 specifies the border blue color of texture image #0 m3d_base+31 ch|b1ch m3d texture image #0 border alpha color m3d_tex_bor der_a_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_a_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_a_1[15:0] type r/w m3d_tex_border_a_1 specifies the border alpha color of texture image #1 m3d_base+32 0h|b20h m3d texture image #1 border red color m3d_tex_bor der_r_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_r_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_r_1[15:0] type r/w m3d_tex_border_r_1 specifies the border red color of texture image #1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1229 of 1535 m3d_base+32 4h|b24h m3d texture image #1 border green color m3d_tex_bor der_g_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_g_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_g_1[15:0] type r/w m3d_tex_border_g_1 specifies the border green color of texture image #1 m3d_base+32 8h|b28h m3d texture image #1 border blue color m3d_tex_bor der_b_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_b_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_b_1[15:0] type r/w m3d_tex_border_b_1 specifies the border blue color of texture image #1 m3d_base+32 ch|b2ch m3d texture image #1 border alpha color m3d_tex_bor der_a_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_a_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_a_1[15:0] type r/w m3d_tex_border_a_1 specifies the border alpha color of texture image #1 m3d_base+33 0h|b30h m3d texture image #2 border red color m3d_tex_bor der_r_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_r_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_r_2[15:0] type r/w m3d_tex_border_r_2 specifies the border red color of texture image #2 m3d_base+33 4h|b34h m3d texture image #2 border green color m3d_tex_bor der_g_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_g_2[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1230 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_g_2[15:0] type r/w m3d_tex_border_g_2 specifies the border green color of texture image #2 m3d_base+33 8h|b38h m3d texture image #2 border blue color m3d_tex_bor der_b_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_b_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_b_2[15:0] type r/w m3d_tex_border_b_2 specifies the border blue color of texture image #2 m3d_base+33 ch|b3ch m3d texture image #2 border alpha color m3d_tex_bor der_a_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_border_a_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_border_a_2[15:0] type r/w m3d_tex_border_a_2 specifies the border alpha color of texture image #2 m3d_base+34 0h|b40h m3d texture coordinate matrix register m3d_tex_m_0 _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_1 [15:0] type r/w m3d_tex_m_0_1 texture coordinate matrix. (0340h : data format is s15.16, 2340h : data format is s[8].23) m3d_base+34 4h|b44h m3d texture coordinate matrix register m3d_tex_m_0 _2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_2 [15:0] type r/w m3d_tex_m_0_2 texture coordinate matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1231 of 1535 m3d_base+34 8h|b48h m3d texture coordinate matrix register m3d_tex_m_0 _3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_3 [15:0] type r/w m3d_tex_m_0_3 texture coordinate matrix. m3d_base+34 ch|b4ch m3d texture coordinate matrix register m3d_tex_m_0 _4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_4 [15:0] type r/w m3d_tex_m_0_4 texture coordinate matrix. m3d_base+35 0h|b50h m3d texture coordinate matrix register m3d_tex_m_0 _5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_5 [15:0] type r/w m3d_tex_m_0_5 texture coordinate matrix. m3d_base+35 4h|b54h m3d texture coordinate matrix register m3d_tex_m_0 _6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_6 [15:0] type r/w m3d_tex_m_0_6 texture coordinate matrix. m3d_base+35 8h|b58h m3d texture coordinate matrix register m3d_tex_m_0 _7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_7[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1232 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_7 [15:0] type r/w m3d_tex_m_0_7 texture coordinate matrix. m3d_base+35 ch|b5ch m3d texture coordinate matrix register m3d_tex_m_0 _8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_8 [15:0] type r/w m3d_tex_m_0_8 texture coordinate matrix. m3d_base+36 0h|b60h m3d texture coordinate matrix register m3d_tex_m_0 _9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_9 [15:0] type r/w m3d_tex_m_0_9 texture coordinate matrix. m3d_base+36 4h|b64h m3d texture coordinate matrix register m3d_tex_m_0 _10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_10[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_10 [15:0] type r/w m3d_tex_m_0_10 texture coordinate matrix. m3d_base+36 8h|b68h m3d texture coordinate matrix register m3d_tex_m_0 _11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_11[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_11 [15:0] type r/w m3d_tex_m_0_11 texture coordinate matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1233 of 1535 m3d_base+36 ch|b6ch m3d texture coordinate matrix register m3d_tex_m_0 _12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_0_12[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_0_12 [15:0] type r/w m3d_tex_m_0_12 texture coordinate matrix. m3d_base+37 0h|b70h m3d texture coordinate matrix register m3d_tex_m_1 _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_1 [15:0] type r/w m3d_tex_m_1_1 texture coordinate matrix. (0370h : data format is s15.16, 2370h : data format is s[8].23) m3d_base+37 4h|b74h m3d texture coordinate matrix register m3d_tex_m_1 _2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_2 [15:0] type r/w m3d_tex_m_1_2 texture coordinate matrix. m3d_base+37 8h|b78h m3d texture coordinate matrix register m3d_tex_m_1 _3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_3 [15:0] type r/w m3d_tex_m_1_3 texture coordinate matrix. m3d_base+37 ch|b7ch m3d texture coordinate matrix register m3d_tex_m_1 _4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_4[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1234 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_4 [15:0] type r/w m3d_tex_m_1_4 texture coordinate matrix. m3d_base+38 0h|b80h m3d texture coordinate matrix register m3d_tex_m_1 _5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_5 [15:0] type r/w m3d_tex_m_1_5 texture coordinate matrix. m3d_base+38 4h|b84h m3d texture coordinate matrix register m3d_tex_m_1 _6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_6 [15:0] type r/w m3d_tex_m_1_6 texture coordinate matrix. m3d_base+38 8h|b88h m3d texture coordinate matrix register m3d_tex_m_1 _7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_7 [15:0] type r/w m3d_tex_m_1_7 texture coordinate matrix. m3d_base+38 ch|b8ch m3d texture coordinate matrix register m3d_tex_m_1 _8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_8 [15:0] type r/w m3d_tex_m_1_8 texture coordinate matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1235 of 1535 m3d_base+39 0h|b90h m3d texture coordinate matrix register m3d_tex_m_1 _9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_9 [15:0] type r/w m3d_tex_m_1_9 texture coordinate matrix. m3d_base+39 4h|b94h m3d texture coordinate matrix register m3d_tex_m_1 _10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_10[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_10 [15:0] type r/w m3d_tex_m_1_10 texture coordinate matrix. m3d_base+39 8h|b98h m3d texture coordinate matrix register m3d_tex_m_1 _11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_11[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_11 [15:0] type r/w m3d_tex_m_1_11 texture coordinate matrix. m3d_base+39 ch|b9ch m3d texture coordinate matrix register m3d_tex_m_1 _12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_1_12[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_1_12 [15:0] type r/w m3d_tex_m_1_12 texture coordinate matrix. m3d_base+3a 0h|ba0h m3d texture coordinate matrix register m3d_tex_m_2 _1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_1[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1236 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_1 [15:0] type r/w m3d_tex_m_2_1 texture coordinate matrix. (03a0h : data format is s15.16, 23a0h : data format is s[8].23) m3d_base+3a 4h|ba4h m3d texture coordinate matrix register m3d_tex_m_2 _2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_2[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_2 [15:0] type r/w m3d_tex_m_2_2 texture coordinate matrix. m3d_base+3a 8h|ba8h m3d texture coordinate matrix register m3d_tex_m_2 _3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_3 [15:0] type r/w m3d_tex_m_2_3 texture coordinate matrix. m3d_base+3a ch|bach m3d texture coordinate matrix register m3d_tex_m_2 _4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_4 [15:0] type r/w m3d_tex_m_2_4 texture coordinate matrix. m3d_base+3b 0h|bb0h m3d texture coordinate matrix register m3d_tex_m_2 _5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_5 [15:0] type r/w m3d_tex_m_2_5 texture coordinate matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1237 of 1535 m3d_base+3b 4h|bb4h m3d texture coordinate matrix register m3d_tex_m_2 _6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_6 [15:0] type r/w m3d_tex_m_2_6 texture coordinate matrix. m3d_base+3b 8h|bb8h m3d texture coordinate matrix register m3d_tex_m_2 _7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_7 [15:0] type r/w m3d_tex_m_2_7 texture coordinate matrix. m3d_base+3b ch|bbch m3d texture coordinate matrix register m3d_tex_m_2 _8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_8 [15:0] type r/w m3d_tex_m_2_8 texture coordinate matrix. m3d_base+3c 0h|bc0h m3d texture coordinate matrix register m3d_tex_m_2 _9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_9 [15:0] type r/w m3d_tex_m_2_9 texture coordinate matrix. m3d_base+3c 4h|bc4h m3d texture coordinate matrix register m3d_tex_m_2 _10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_10[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1238 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_10 [15:0] type r/w m3d_tex_m_2_10 texture coordinate matrix. m3d_base+3c 8h|bc8h m3d texture coordinate matrix register m3d_tex_m_2 _11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_11[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_11 [15:0] type r/w m3d_tex_m_2_11 texture coordinate matrix. m3d_base+3c ch|bcch m3d texture coordinate matrix register m3d_tex_m_2 _12 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_tex_m_2_12[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_tex_m_2_12 [15:0] type r/w m3d_tex_m_2_12 texture coordinate matrix. m3d_base+3d 0h|bd0 d3dm light range of light source 0 m3d_light_r ange_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 0. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3d 4h|bd4 d3dm light range of light source 1 m3d_light_r ange_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1239 of 1535 range to set the range of light source 1. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3d 8h|bd8 d3dm light range of light source 2 m3d_light_r ange_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 2. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3d ch|bdc d3dm light range of light source 3 m3d_light_r ange_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 3. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3e 0h|be0 d3dm light range of light source 4 m3d_light_r ange_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 4. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3e 4h|be4 d3dm light range of light source 5 m3d_light_r ange_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1240 of 1535 name range type r/w range to set the range of light source 5. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3e 8h|be8 d3dm light range of light source 6 m3d_light_r ange_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 6. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+3e ch|bec d3dm light range of light source 7 m3d_light_r ange_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name range type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name range type r/w range to set the range of light source 7. when m3d_light_range_enable is enabled, the attenuation item would be zero if the distance between the vertex and the light source exceeds the range value. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+40 0h|c00h m3d normal scale register m3d_normal_ n_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_1[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_1[15:0] type r/w m3d_normal_n_1 normal matrix. (0400h : data format is s15.16, 2400h : data format is s[8].23) m3d_base+40 4h|c04h m3d normal scale register m3d_normal_ n_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_2[31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1241 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_2[15:0] type r/w m3d_normal_n_2 normal matrix. m3d_base+40 8h|c08h m3d normal scale register m3d_normal_ n_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_3[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_3[15:0] type r/w m3d_normal_n_3 normal matrix. m3d_base+40 ch|c0ch m3d normal scale register m3d_normal_ n_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_4[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_4[15:0] type r/w m3d_normal_n_4 normal matrix. m3d_base+41 0h|c10h m3d normal scale register m3d_normal_ n_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_5[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_5[15:0] type r/w m3d_normal_n_5 normal matrix. m3d_base+41 4h|c14h m3d normal scale register m3d_normal_ n_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_6[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_6[15:0] type r/w m3d_normal_n_6 normal matrix. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1242 of 1535 m3d_base+41 8h|c18h m3d normal scale register m3d_normal_ n_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_7[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_7[15:0] type r/w m3d_normal_n_7 normal matrix. m3d_base+41 ch|c1ch m3d normal scale register m3d_normal_ n_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_8[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_8[15:0] type r/w m3d_normal_n_8 normal matrix. m3d_base+42 0h|c20h m3d normal scale register m3d_normal_ n_9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_n_9[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_n_9[15:0] type r/w m3d_normal_n_9 normal matrix. m3d_base+42 4h|c24h m3d normal scale register m3d_normal_ scale bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_normal_scale[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_normal_scale[15:0] type r/w m3d_normal_scale normal will be scaled by this scale factor. (0424h : data format is s15.16, 2424h : data format is s[8].23) m3d_base+42 8h|c28h red component of fog color register m3d_fog_col or_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_fog_color_r[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1243 of 1535 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_fog_color_r[15:0] type r/w m3d_fog_color_r red component of fog color. (0428h : data format is s15.16, 2428h : data format is s[8].23) m3d_base+42 ch|c2ch green component of fog color register m3d_fog_col or_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_fog_color_g[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_fog_color_g[15:0] type r/w m3d_fog_color_g green component of fog color. (042ch : data format is s15.16, 242ch : data format is s[8].23) m3d_base+43 0h|c30h blue component of fog color register m3d_fog_col or_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_fog_color_b[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_fog_color_b[15:0] type r/w m3d_fog_color_b blue component of fog color. (0430h : data format is s15.16, 2430h : data format is s[8].23) m3d_base+43 ch pixel counter m3d_pxl_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_pxl_cnt type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_pxl_cnt type r m3d_pxl_cnt pixel counter m3d_base+44 0h|c40h red component of ambient color of material register m3d_a_cm_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1244 of 1535 type r/w r_color red componet of a cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+44 4h|c44h green component of ambient color of material register m3d_a_cm_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+44 8h|c48h blue component of ambient color of material register m3d_a_cm_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+44 ch texture cache hit counter m3d_txcache _cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_txcache_cnt type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_txcache_cnt type r m3d_txcache_cnt texture cache hit counter m3d_base+45 0h|c50h red component of diffusion color of material register m3d_d_cm_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cm . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1245 of 1535 m3d_base+45 4h|c54h green component of diffusion color of material register m3d_d_cm_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+45 8h|c58h blue component of diffusion color of material register m3d_d_cm_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+45 ch|c5ch alpha component of diffusion color of material register m3d_d_cm_a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+46 0h|c60h red component of specular color of material register m3d_s_cm_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+46 4h|c64h green component of specular color of material register m3d_s_cm_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1246 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+46 8h|c68h blue component of specular color of material register m3d_s_cm_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+46 ch|c6ch alpha component of specular color of material register m3d_s_cm_a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+47 0h|c70h red component of emission color of material register m3d_e_cm_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of e cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+47 4h|c74h green component of emission color of material register m3d_e_cm_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of e cm . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1247 of 1535 m3d_base+47 8h|c78h blue component of emission color of material register m3d_e_cm_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of e cm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+47 ch z cache hit counter m3d_zc_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_zc_cnt type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_zc_cnt type r m3d_zc_cnt z cache hit counter m3d_base+48 0h|c80h red component of ambient intensity of light source 0 register m3d_a_cl_0_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+48 4h|c84h green component of ambient intensity of light source 0 register m3d_a_cl_0_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+48 8h|c88h blue component of ambient intensity of light source 0 register m3d_a_cl_0_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1248 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+48 ch|c8ch alpha component of ambient intensity of light source 0 register m3d_a_cl_0_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+49 0h|c90h red component of ambient intensity of light source 1 register m3d_a_cl_1_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+49 4h|c94h green component of ambient intensity of light source 1 register m3d_a_cl_1_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+49 8h|c98h blue component of ambient intensity of light source 1 register m3d_a_cl_1_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1249 of 1535 m3d_base+49 ch|c9ch alpha component of ambient intensity of light source 1 register m3d_a_cl_1_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4a 0h|ca0h red component of ambient intensity of light source 2 register m3d_a_cl_2_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4a 4h|ca4h green component of ambient intensity of light source 2 register m3d_a_cl_2_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4a 8h|ca8h blue component of ambient intensity of light source 2 register m3d_a_cl_2_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4a ch|cach alpha component of ambient intensity of light source 2 register m3d_a_cl_2_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1250 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4b 0h|cb0h red component of ambient intensity of light source 3 register m3d_a_cl_3_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4b 4h|cb4h green component of ambient intensity of light source 3 register m3d_a_cl_3_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4b 8h|cb8h blue component of ambient intensity of light source 3 register m3d_a_cl_3_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4b ch|cbch alpha component of ambient intensity of light source 3 register m3d_a_cl_3_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1251 of 1535 m3d_base+4c 0h|cc0h red component of ambient intensity of light source 4 register m3d_a_cl_4_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4c 4h|cc4h green component of ambient intensity of light source 4 register m3d_a_cl_4_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4c 8h|cc8h blue component of ambient intensity of light source 4 register m3d_a_cl_4_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4c ch|ccch alpha component of ambient intensity of light source 4 register m3d_a_cl_4_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4d 0h|cd0h red component of ambient intensity of light source 5 register m3d_a_cl_5_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1252 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4d 4h|cd4h green component of ambient intensity of light source 5 register m3d_a_cl_5_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4d 8h|cd8h blue component of ambient intensity of light source 5 register m3d_a_cl_5_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4d ch|cdch alpha component of ambient intensity of light source 5 register m3d_a_cl_5_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4e 0h|ce0h red component of ambient intensity of light source 6 register m3d_a_cl_6_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1253 of 1535 m3d_base+4e 4h|ce4h green component of ambient intensity of light source 6 register m3d_a_cl_6_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4e 8h|ce8h blue component of ambient intensity of light source 6 register m3d_a_cl_6_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4e ch|cech alpha component of ambient intensity of light source 6 register m3d_a_cl_6_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4f 0h|cf0h red component of ambient intensity of light source 7 register m3d_a_cl_7_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4f 4h|cf4h green component of ambient intensity of light source 7 register m3d_a_cl_7_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1254 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4f 8h|cf8h blue component of ambient intensity of light source 7 register m3d_a_cl_7_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+4f ch|cfch alpha component of ambient intensity of light source 7 register m3d_a_cl_7_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of a cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+50 0h|d00h red component of diffusion intensity of light source 0 register m3d_d_cl_0_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+50 4h|d04h green component of diffusion intensity of light source 0 register m3d_d_cl_0_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1255 of 1535 m3d_base+50 8h|d08h blue component of diffusion intensity of light source 0 register m3d_d_cl_0_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+50 ch|d0ch alpha component of diffusion intensity of light source 0 register m3d_d_cl_0_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+51 0h|d10h red component of diffusion intensity of light source 1 register m3d_d_cl_1_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+51 4h|d14h green component of diffusion intensity of light source 1 register m3d_d_cl_1_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+51 8h|d18h blue component of diffusion intensity of light source 1 register m3d_d_cl_1_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1256 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+51 ch|d1ch alpha component of diffusion intensity of light source 1 register m3d_d_cl_1_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+52 0h|d20h red component of diffusion intensity of light source 2 register m3d_d_cl_2_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+52 4h|d24h green component of diffusion intensity of light source 2 register m3d_d_cl_2_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+52 8h|d28h blue component of diffusion intensity of light source 2 register m3d_d_cl_2_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1257 of 1535 m3d_base+52 ch|d2ch alpha component of diffusion intensity of light source 2 register m3d_d_cl_2_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+53 0h|d30h red component of diffusion intensity of light source 3 register m3d_d_cl_3_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+53 4h|d34h green component of diffusion intensity of light source 3 register m3d_d_cl_3_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+53 8h|d38h blue component of diffusion intensity of light source 3 register m3d_d_cl_3_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+53 ch|d3ch alpha component of diffusion intensity of light source 3 register m3d_d_cl_3_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1258 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+54 0h|d40h red component of diffusion intensity of light source 4 register m3d_d_cl_4_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+54 4h|d44h green component of diffusion intensity of light source 4 register m3d_d_cl_4_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+54 8h|d48h blue component of diffusion intensity of light source 4 register m3d_d_cl_4_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+54 ch|d4ch alpha component of diffusion intensity of light source 4 register m3d_d_cl_4_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1259 of 1535 m3d_base+55 0h|d50h red component of diffusion intensity of light source 5 register m3d_d_cl_5_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+55 4h|d54h green component of diffusion intensity of light source 5 register m3d_d_cl_5_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+55 8h|d58h blue component of diffusion intensity of light source 5 register m3d_d_cl_5_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+55 ch|d5ch alpha component of diffusion intensity of light source 5 register m3d_d_cl_5_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+56 0h|d60h red component of diffusion intensity of light source 6 register m3d_d_cl_6_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1260 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+56 4h|d64h green component of diffusion intensity of light source 6 register m3d_d_cl_6_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+56 8h|d68h blue component of diffusion intensity of light source 6 register m3d_d_cl_6_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+56 ch|d6ch alpha component of diffusion intensity of light source 6 register m3d_d_cl_6_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+57 0h|d70h red component of diffusion intensity of light source 7 register m3d_d_cl_7_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of d cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1261 of 1535 m3d_base+57 4h|d74h green component of diffusion intensity of light source 7 register m3d_d_cl_7_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of d cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+57 8h|d78h blue component of diffusion intensity of light source 7 register m3d_d_cl_7_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of d cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+57 ch|d7ch alpha component of diffusion intensity of light source 7 register m3d_d_cl_7_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of d cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+58 0h|d80h red component of specular intensity of light source 0 register m3d_s_cl_0_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+58 4h|d84h green component of specular intensity of light source 0 register m3d_s_cl_0_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1262 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+58 8h|d88h blue component of specular intensity of light source 0 register m3d_s_cl_0_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+58 ch|d8ch alpha component of specular intensity of light source 0 register m3d_s_cl_0_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+59 0h|d90h red component of specular intensity of light source 1 register m3d_s_cl_1_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+59 4h|d94h green component of specular intensity of light source 1 register m3d_s_cl_1_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1263 of 1535 m3d_base+59 8h|d98h blue component of specular intensity of light source 1 register m3d_s_cl_1_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+59 ch|d9ch alpha component of specular intensity of light source 1 register m3d_s_cl_1_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5a 0h|da0h red component of specular intensity of light source 2 register m3d_s_cl_2_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5a 4h|da4h green component of specular intensity of light source 2 register m3d_s_cl_2_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5a 8h|da8h blue component of specular intensity of light source 2 register m3d_s_cl_2_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1264 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5a ch|dach alpha component of specular intensity of light source 2 register m3d_s_cl_2_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5b 0h|db0h red component of specular intensity of light source 3 register m3d_s_cl_3_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5b 4h|db4h green component of specular intensity of light source 3 register m3d_s_cl_3_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5b 8h|db8h blue component of specular intensity of light source 3 register m3d_s_cl_3_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1265 of 1535 m3d_base+5b ch|dbch alpha component of specular intensity of light source 3 register m3d_s_cl_3_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5c 0h|dc0h red component of specular intensity of light source 4 register m3d_s_cl_4_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5c 4h|dc4h green component of specular intensity of light source 4 register m3d_s_cl_4_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5c 8h|dc8h blue component of specular intensity of light source 4 register m3d_s_cl_4_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5c ch|dcch alpha component of specular intensity of light source 4 register m3d_s_cl_4_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1266 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5d 0h|dd0h red component of specular intensity of light source 5 register m3d_s_cl_5_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5d 4h|dd4h green component of specular intensity of light source 5 register m3d_s_cl_5_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5d 8h|dd8h blue component of specular intensity of light source 5 register m3d_s_cl_5_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5d ch|ddch alpha component of specular intensity of light source 5 register m3d_s_cl_5_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl5 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1267 of 1535 m3d_base+5e 0h|de0h red component of specular intensity of light source 6 register m3d_s_cl_6_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5e 4h|de4h green component of specular intensity of light source 6 register m3d_s_cl_6_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5e 8h|de8h blue component of specular intensity of light source 6 register m3d_s_cl_6_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5e ch|dech alpha component of specular intensity of light source 6 register m3d_s_cl_6_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5f 0h|df0h red component of specular intensity of light source 7 register m3d_s_cl_7_ r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1268 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of s cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5f 4h|df4h green component of specular intensity of light source 7 register m3d_s_cl_7_ g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of s cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5f 8h|df8h blue component of specular intensity of light source 7 register m3d_s_cl_7_ b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of s cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+5f ch|dfch alpha component of specular intensity of light source 7 register m3d_s_cl_7_ a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name alpha type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alpha type r/w alpha alpha componet of s cl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+60 0h|e00h x coordinate of position of light source 0 register m3d_p_pl_0_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl0 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1269 of 1535 m3d_base+60 4h|e04h y coordinate of position of light source 0 register m3d_p_pl_0_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+60 8h|e08h z coordinate of position of light source 0 register m3d_p_pl_0_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+60 ch|e0ch w coordinate of position of light source 0 register m3d_p_pl_0_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+61 0h|e10h x coordinate of position of light source 1 register m3d_p_pl_1_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+61 4h|e14h y coordinate of position of light source 1 register m3d_p_pl_1_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1270 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+61 8h|e18h z coordinate of position of light source 1 register m3d_p_pl_1_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+61 ch|e1ch w coordinate of position of light source 1 register m3d_p_pl_1_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+62 0h|e20h x coordinate of position of light source 2 register m3d_p_pl_2_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+62 4h|e24h y coordinate of position of light source 2 register m3d_p_pl_2_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl2 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1271 of 1535 m3d_base+62 8h|e28h z coordinate of position of light source 2 register m3d_p_pl_2_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+62 ch|e2ch w coordinate of position of light source 2 register m3d_p_pl_2_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+63 0h|e30h x coordinate of position of light source 3 register m3d_p_pl_3_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+63 4h|e34h y coordinate of position of light source 3 register m3d_p_pl_3_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+63 8h|e38h z coordinate of position of light source 3 register m3d_p_pl_3_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1272 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+63 ch|e3ch w coordinate of position of light source 3 register m3d_p_pl_3_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+64 0h|e40h x coordinate of position of light source 4 register m3d_p_pl_4_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+64 4h|e44h y coordinate of position of light source 4 register m3d_p_pl_4_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+64 8h|e48h z coordinate of position of light source 4 register m3d_p_pl_4_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl4 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1273 of 1535 m3d_base+64 ch|e4ch w coordinate of position of light source 4 register m3d_p_pl_4_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+65 0h|e50h x coordinate of position of light source 5 register m3d_p_pl_5_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+65 4h|e54h y coordinate of position of light source 5 register m3d_p_pl_5_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+65 8h|e58h z coordinate of position of light source 5 register m3d_p_pl_5_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+65 ch|e5ch w coordinate of position of light source 5 register m3d_p_pl_5_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1274 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+66 0h|e60h x coordinate of position of light source 6 register m3d_p_pl_6_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+66 4h|e64h y coordinate of position of light source 6 register m3d_p_pl_6_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+66 8h|e68h z coordinate of position of light source 6 register m3d_p_pl_6_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+66 ch|e6ch w coordinate of position of light source 6 register m3d_p_pl_6_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl6 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1275 of 1535 m3d_base+67 0h|e70h x coordinate of position of light source 7 register m3d_p_pl_7_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_coord type r/w x_coord x coordinate of p pl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+67 4h|e74h y coordinate of position of light source 7 register m3d_p_pl_7_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_coord type r/w y_coord y coordinate of p pl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+67 8h|e78h z coordinate of position of light source 7 register m3d_p_pl_7_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_coord type r/w z_coord z coordinate of p pl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+67 ch|e7ch w coordinate of position of light source 7 register m3d_p_pl_7_ w bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name w_coord type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name w_coord type r/w w_coord w coordinate of p pl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+68 0h|e80h x direction of spotlight for light source 0 register m3d_s_dl_0_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1276 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+68 4h|e84h y direction of spotlight for light source 0 register m3d_s_dl_0_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+68 8h|e88h z direction of spotlight for light source 0 register m3d_s_dl_0_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+68 ch|e8ch spotlight exponent for light source 0 register m3d_s_rl_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+69 0h|e90h x direction of spotlight for light source 1 register m3d_s_dl_1_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl1 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1277 of 1535 m3d_base+69 4h|e94h y direction of spotlight for light source 1 register m3d_s_dl_1_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+69 8h|e98h z direction of spotlight for light source 1 register m3d_s_dl_1_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+69 ch|e9ch spotlight exponent for light source 1 register m3d_s_rl_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6a 0h|ea0h x direction of spotlight for light source 2 register m3d_s_dl_2_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6a 4h|ea4h y direction of spotlight for light source 2 register m3d_s_dl_2_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1278 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6a 8h|ea8h z direction of spotlight for light source 2 register m3d_s_dl_2_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6a ch|each spotlight exponent for light source 2 register m3d_s_rl_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6b 0h|eb0h x direction of spotlight for light source 3 register m3d_s_dl_3_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6b 4h|eb4h y direction of spotlight for light source 3 register m3d_s_dl_3_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl3 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1279 of 1535 m3d_base+6b 8h|eb8h z direction of spotlight for light source 3 register m3d_s_dl_3_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6b ch|ebch spotlight exponent for light source 3 register m3d_s_rl_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6c 0h|ec0h x direction of spotlight for light source 4 register m3d_s_dl_4_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6c 4h|ec4h y direction of spotlight for light source 4 register m3d_s_dl_4_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6c 8h|ec8h z direction of spotlight for light source 4 register m3d_s_dl_4_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1280 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6c ch|ecch spotlight exponent for light source 4 register m3d_s_rl_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6d 0h|ed0h x direction of spotlight for light source 5 register m3d_s_dl_5_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6d 4h|ed4h y direction of spotlight for light source 5 register m3d_s_dl_5_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6d 8h|ed8h z direction of spotlight for light source 5 register m3d_s_dl_5_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl5 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1281 of 1535 m3d_base+6d ch|edch spotlight exponent for light source 5 register m3d_s_rl_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6e 0h|ee0h x direction of spotlight for light source 6 register m3d_s_dl_6_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6e 4h|ee4h y direction of spotlight for light source 6 register m3d_s_dl_6_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6e 8h|ee8h z direction of spotlight for light source 6 register m3d_s_dl_6_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6e ch|eech spotlight exponent for light source 6 register m3d_s_rl_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1282 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6f 0h|ef0h x direction of spotlight for light source 7 register m3d_s_dl_7_x bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name x_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x_direc type r/w x_direc x direction of s dl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6f 4h|ef4h y direction of spotlight for light source 7 register m3d_s_dl_7_y bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name y_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y_direc type r/w y_direc y direction of s dl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6f 8h|ef8h z direction of spotlight for light source 7 register m3d_s_dl_7_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z_direc type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z_direc type r/w z_direc z direction of s dl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+6f ch|efch spotlight exponent for light source 7 register m3d_s_rl_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp spotlight exponent s rl7 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1283 of 1535 m3d_base+70 0h|f00h spotlight cutoff angle for light source 0 register m3d_c_rl_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl0 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+70 4h|f04h constant attenuation factor for light source 0 register m3d_k_0_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 00 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+70 8h|f08h linear attenuation fact or for light source 0 register m3d_k_1_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 10 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+70 ch|f0ch quadratic attenuation factor for light source 0 register m3d_k_2_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 20 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1284 of 1535 m3d_base+71 0h|f10h spotlight cutoff angle for light source 1 register m3d_c_rl_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl1 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+71 4h|f14h constant attenuation factor for light source 1 register m3d_k_0_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 01 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+71 8h|f18h linear attenuation fact or for light source 1 register m3d_k_1_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 11 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+71 ch|f1ch quadratic attenuation factor for light source 1 register m3d_k_2_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 21 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1285 of 1535 m3d_base+72 0h|f20h spotlight cutoff angle for light source 2 register m3d_c_rl_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl2 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+72 4h|f24h constant attenuation factor for light source 2 register m3d_k_0_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 02 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+72 8h|f28h linear attenuation fact or for light source 2 register m3d_k_1_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 12 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+72 ch|f2ch quadratic attenuation factor for light source 2 register m3d_k_2_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 22 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1286 of 1535 m3d_base+73 0h|f30h spotlight cutoff angle for light source 3 register m3d_c_rl_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl3 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+73 4h|f34h constant attenuation factor for light source 3 register m3d_k_0_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 03 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+73 8h|f38h linear attenuation fact or for light source 3 register m3d_k_1_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 13 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+73 ch|f3ch quadratic attenuation factor for light source 3 register m3d_k_2_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 23 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1287 of 1535 m3d_base+74 0h|f40h spotlight cutoff angle for light source 4 register m3d_c_rl_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl4 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+74 4h|f44h constant attenuation factor for light source 4 register m3d_k_0_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 04 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+74 8h|f48h linear attenuation fact or for light source 4 register m3d_k_1_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 14 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+74 ch|f4ch quadratic attenuation factor for light source 4 register m3d_k_2_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 24 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1288 of 1535 m3d_base+75 0h|f50h spotlight cutoff angle for light source 5 register m3d_c_rl_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl5 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+75 4h|f54h constant attenuation factor for light source 5 register m3d_k_0_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 05 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+75 8h|f58h linear attenuation factor for light source 5 register m3d_k_1_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 15 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+75 ch|f5ch quadratic attenuation factor for light source 5 register m3d_k_2_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 25 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1289 of 1535 m3d_base+76 0h|f60h spotlight cutoff angle for light source 6 register m3d_c_rl_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl6 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+76 4h|f64h constant attenuation factor for light source 6 register m3d_k_0_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 06 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+76 8h|f68h linear attenuation fact or for light source 6 register m3d_k_1_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 16 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+76 ch|f6ch quadratic attenuation factor for light source 6 register m3d_k_2_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 26 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1290 of 1535 m3d_base+77 0h|f70h spotlight cutoff angle for light source 7 register m3d_c_rl_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cosine type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cosine type r/w cosine cosine value of spotlight cutoff angle c rl7 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+77 4h|f74h constant attenuation factor for light source 7 register m3d_k_0_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light constant attenuation factor k 07 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+77 8h|f78h linear attenuation fact or for light source 7 register m3d_k_1_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light linear attenuation factor k 17 . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+77 ch|f7ch quadratic attenuation factor for light source 7 register m3d_k_2_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name factor type r/w factor non-directional light quadratic attenuation factor k 27 . the format is s15.16 fixed-point or s[8].23 floating-point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1291 of 1535 m3d_base+78 0h|f80h red component of ambient color of scene register m3d_a_cs_r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name r_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_color type r/w r_color red componet of a cs . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+78 4h|f84h green component of ambient color of scene register m3d_a_cs_g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name g_color type r/w g_color green componet of a cs . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+78 8h|f88h blue component of ambient color of scene register m3d_a_cs_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_color type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_color type r/w b_color blue componet of a cs . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+78 ch color cache hit counter m3d_cc_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_cc_cnt type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_cc_cnt type r m3d_cc_cnt color cache hit counter m3d_base+79 0h|f90h specular exponent of material register m3d_s_rm bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name exp type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1292 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name exp type r/w exp specular exponent of material s rm . the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+79 4h|f94h fog density register m3d_fog_den sity bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name density type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name density type r/w density fog density d. the format is s15.16 fixed-point or s[8].23 floating-point. used when fog mode is exp or exp2. m3d_base+79 8h|f98h fog start register m3d_fog_sta rt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name start type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start type r/w start fog start s. the format is s15.16 fixed-point or s[8].23 floating-point. used when fog mode is linear. m3d_base+79 ch|f9ch fog end register m3d_fog_end bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name end type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name end type r/w end fog end e. the format is s15.16 fixed-point or s[8].23 floating-point. used when fog mode is linear. m3d_base+7a 0h|fa0h lower bound of point size register m3d_point_si ze_min bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name min type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name min free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1293 of 1535 type r/w reset 0 min lower bound of point size. if derived point size is less than min, it will be clamped to min. m3d_base+7a 4h|fa4h upper bound of point size register m3d_ponit_si ze_max bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name max type r/w reset 0x00010000 (s15.16) or 0x3f800000 (s[8].23) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max type r/w reset 0x00010000 (s15.16) or 0x3f800000 (s[8].23) max upper bound of point size. if derived point size is greater than max, it will be clamped to max. m3d_base+7a 8h|fa8h constant coefficient of distance attenaution fucntion for point size register m3d_point_at tenuation_a bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coeff_a type r/w reset 0x00010000 (s15.16) or 0x3f800000 (s[8].23) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coeff_a type r/w reset 0x00010000 (s15.16) or 0x3f800000 (s[8].23) coeff_a constant coefficient of distance attenaution fucntion to calculate derived point size. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+7a ch|fach linear coefficient of distance attenaution fucntion for point size register m3d_point_at tenuation_b bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coeff_b type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coeff_b type r/w reset 0 coeff_b linear coefficient of distance attenaution fucntion to calculate derived point size. the format is s15.16 fixed-point or s[8].23 floating-point. m3d_base+7b 0h|fb0h quadratic coefficient of distance attenaution fucntion for point size register m3d_point_at tenuation_c bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coeff_c type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1294 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coeff_c type r/w reset 0 coeff_c quadratic coefficient of distance attenaution fucntion to calculate derived point size. the format is s15.16 fixed-point or s[8].23 floating-point m3d_base+7b 4h m3d texture image #0 filter/wrap mode m3d_tex_par a_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserve m3d_tex_wrap_t_0 m3d_tex_wrap_s_0 m3d_t ex_m ag_fi lter_ 0 m3d_tex_min_fil ter_0 type r/w r/w r/w r/w m3d_tex_min_filter_0 specifies minify filter mode of texture image #0 000 m3d_tex_nearest 001 m3d_tex_linear 010 m3d_tex_nearest_mipmap_nearest 011 m3d_tex_linear_mipmap_nearest 100 m3d_tex_nearest_mipmap_linear 101 m3d_tex_ linear _mipmap_ linear m3d_tex_mag_filter_0 specifies magnify filter mode of texture image #0 0 m3d_tex_nearest 1 m3d_tex_linear m3d_tex_wrap_s_0 specifies s-direction wrap mode of texture image #0 0 m3d_tex_wrap_s_repeat 1 m3d_tex_wrap_s_clamp_to_edge 2 m3d_tex_wrap_s_mirror 3 m3d_tex_wrap_s_clamp 4 m3d_tex_wrap_s_border m3d_tex_wrap_t_0 specifies t-direction wrap mode of texture image #0 m3d_base+7b 8h m3d texture image #1 filter/wrap mode m3d_tex_par a_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1295 of 1535 name reserve m3d_tex_wrap_t_ 1 m3d_tex_wrap_s_1 m3d_t ex_m ag_fi lter_ 1 m3d_tex_min_fil ter_1 type r/w r/w r/w r/w m3d_tex_min_filter_1 specifies minify filter mode of texture image #1 m3d_tex_mag_filter_1 specifies magnify filter mode of texture image #1 m3d_tex_wrap_s_1 specifies s-direction wrap mode of texture image #1 m3d_tex_wrap_t_1 specifies t-direction wrap mode of texture image #1 m3d_base+7b ch m3d texture image #2 filter/wrap mode m3d_tex_par a_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserve m3d_tex_wrap_t_ 2 m3d_tex_wrap_s_2 m3d_t ex_m ag_fi lter_ 2 m3d_tex_min_fil ter_2 type r/w r/w r/w r/w m3d_tex_min_filter_2 specifies minify filter mode of texture image #2 m3d_tex_mag_filter_2 specifies magnify filter mode of texture image #2 m3d_tex_wrap_s_2 specifies s-direction wrap mode of texture image #2 m3d_tex_wrap_t_2 specifies t-direction wrap mode of texture image #2 m3d_base+7c0 h m3d cache performance counter control m3d_cache_p erf_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reserve m3d_v c_cnt _rst m3d_v c_cnt _en m3d_c c_cnt _rst m3d_c c_cnt _en m3d_z c_cnt _rst m3d_z c_cnt _en m3d_t xcac he_c nt_rs t m3d_t xcac he_c nt_en m3d_p xlcnt _rst m3 d_ px lc nt _e n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/ w m3d_pxlcnt_en enable pixel counter m3d_pxlcnt_rst reset pixel counter m3d_txcache_cnt_en enable texture cache hit counter m3d_txcache_cnt_rst reset texture cache hit counter m3d_zc_cnt_en enable z cache hit counter free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1296 of 1535 m3d_zc_cnt_rst reset z cache hit counter m3d_cc_cnt_en enable color cache hit counter m3d_cc_cnt_rst reset color cache hit counter m3d_vc_cnt_en enable vertex cache hit counter m3d_vc_cnt_rst reset vertex cache hit counter m3d_base+7c 8h m3d drawtex cropper region u coord m3d_drawte x_cru_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cru_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cru_0 type r/w m3d_drawtex_cru_0 specifies drawtex cropper region u coord m3d_base+7c ch m3d drawtex cropper region v coord m3d_drawte x_crv_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crv_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name crv_0 type r/w m3d_drawtex_crv_0 specifies drawtex cropper region v coord m3d_base+7d 0h m3d drawtex cropper region delta u coord m3d_drawte x_dcru_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dcru_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dcru_0 type r/w m3d_drawtex_dcru_0 specifies drawtex cropper region delta u coord m3d_base+7d 4h m3d drawtex cropper region delta v coord m3d_drawte x_dcrv_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dcrv_0 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dcrv_0 type r/w m3d_drawtex_dcrv_0 specifies drawtex cropper region delta v coord free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1297 of 1535 m3d_base+7d 8h m3d drawtex cropper region xy coord m3d_drawte x_xy bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve y type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name y x type r/w m3d_drawtex_xy specifies drawtex cropper region xy coord m3d_base+7d ch m3d drawtex cropper region width/height m3d_drawte x_wh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name reserve height type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name height width type r/w m3d_drawtex_wh specifies drawtex cropper region width/height m3d_base+7e 0h|fe0 m3d drawtex cropper region z value m3d_drawte x_z bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name z type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name z type r/w m3d_drawtex_z specifies drawtex cropper region z value. the format is fix s11.16 or floating s[8]23 m3d_base+7e 4h|fe4 m3d drawtex cropper region fog factor m3d_drawte x_fog bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fog factor type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fog factor type r/w m3d_drawtex_fog specifies drawtex cropper region fog factor. the format is fix s11.16 or floating s[8]23 m3d_base+7e 8h m3d dummy register 0 m3d_dummy_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dummy_0[31:16] type w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1298 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dummy_0[15:0] type w m3d_dummy_0 m3d engine dummy register #0 m3d_base+7e ch m3d dummy register 1 m3d_dummy_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dummy_1[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dummy_1[15:0] type r m3d_dummy_1 m3d engine dummy register #1 m3d_base+7f 0h m3d dummy register 2 m3d_dummy_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dummy_2[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dummy_2[15:0] type r m3d_dummy_2 m3d engine dummy register #2 m3d_base+7f 4h m3d debug port 5 m3d_dbgrd_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_5[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_5[15:0] type r m3d_dbgrd_5 m3d engine debug port #5 (read only). m3d_base+7f 8h m3d debug port 6 m3d_dbgrd_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_6[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_6[15:0] type r m3d_dbgrd_6 m3d engine debug port #6 (read only). free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1299 of 1535 m3d_base+7f ch m3d debug port 7 m3d_dbgrd_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name m3d_dbgrd_7[31:16] type r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name m3d_dbgrd_7[15:0] type r m3d_dbgrd_7 m3d engine debug port #7 (read only). 5.21.3 application note 1 m3d_frame_buf_format there is no alpha buffer in rgb565 and rgb888 format. default value 0xff is used as destination alpha color for blending operation. if application prefers destination alpha for blending op, argb8888 mode is recommended. 2 m3d_early_z_enable earlyz must be disable when alpha test/stencil test/line/point is enable once earlyz is disable at some list, it must be disable until the frame buffer is flush 3 m3d_early_z_buf_addr for wvga size, earlyz buffer is 102.48kb(earlyz mode 0) or 51.24kb(earlyz mode 1), for vga size, earlyz buffer is 76.8kb(earlyz mode 0) or 38.4kb(earlyz mode 1). for qvga size, earlyz buffer is 19.2kb(earlyz mode 0) or 9.6kb(earlyz mode 1). if earlyz is enable, clear depth buffer and earlyz buffer at the same time. the clear value of earlyz buffer is {1?b0,m3d_depth_clear_val[15:9]} 4 m3d_earlyz_mode set m3d_earlyz_mode=0, better performance but more sysram usage set m3d_earlyz_mode=1, worse performance but less sysram usage if sysram is big enough, set m3d_earlyz_mode 0 is recommended 5 m3d_frame_buf_addr must be 8-byte alignment 6 m3d_depth_buf_addr must be 8-byte alignment 7 m3d_tex_img_ptr_n_n must be 8-byte alignment 5.22 mpeg-4 deblocking filters 5.22.1 general description the purpose of deblocking filter is to reduce blocking artifacts while keeping image edge intact. the filter operations are performed across 8 8 block edge boundaries of decoded frames. in our design, deblocking edge filter algorithm in annex j.3 of itu-t rec. h.263 is used. the filtering operations include an additional clipping to ensure that resulting pixel values stay in the range 0...255. no filtering is performed across a picture edge. chrominance as well as luminance data are filtered. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1300 of 1535 the deblocking filter operates using a set of four pixel values on a horizontal or vertical line of the reconstructed picture, denoted as a, b, c and d, of which a and b belong to one block called block1 and c and d belong to a neighbouring block called block2 which is to the right of or below block1. filtering across a horizontal edge shall not have been influenced by previous filtering across a vertical edge. in other words, before filtering across a vertical edge using pixels (a, b, c, d), all modifications of pixels (a, b, c, d) resulting from filtering across a horizontal edge shall have taken place. figure 1.1 shows examples for the position of these pixels. figure 1.1? examples of positions of filtered pixels mp4 debloking filters are post-processing of mp4 decoder and the design is in the image datapath. its inputs are from itr0 and multi-ouputs are to crz, prz and ipp1. itr0 inputs yuv4:4:4 pixel data to mp4_deblk. mp4_deblk supports output deblocking pixel data (yuv4:4:4) to three engines simultaneously. the interface of mp4_deblk is shown in figure 1.2. figure 1.2? interface of mp4_deblk the block diagram of mp4_deblk is shown in figure 1.3. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1301 of 1535 figure 1.3? block diagram of mp4_deblk free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1302 of 1535 1.1.2 register definitions register address register name acronym mp4_deblk+ 0000h mp4 deblk command register mp4_deblk_comd mp4_deblk + 0004h mp4 deblk configuration register mp4_deblk_conf mp4_deblk + 0008h mp4 deblk status register mp4_deblk_sts mp4_deblk + 000ch mp4 deblk interrupt status register mp4_deblk_irq_sts mp4_deblk + 0010h mp4 deblk interrupt acknowledge register mp4_deblk_irq_ack mp4_deblk + 0014h mp4 deblk line buffer address register mp4_deblk_lin_buf_addr mp4_deblk + 0018h mp4 deblk quantizer address register mp4_deblk_quant_addr 1.1.2.1 main control mp4_deblk+ 0000h mp4 deblk command register mp4_dblk_co md bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - dblk_ start apb_r st core _rst type wo wowo this register is the main command register for mp4 deblocking filters. core_rst software reset control. writing 1 to this bit will reset the hardware core excluding apb control register set. apb_rst software reset control. writing 1 to this bit will reset the apb control register set of deblocking. note that this bit won?t reset the hardware core. dblk_start start the deblocking operation if writing 1 to this bit and if dblk_en is set. 1.1.2.2 configuration mp4_deblk+ 0004h mp4 deblk configuration register mp4_dblk_co nf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - ipp1_e n prz_e n crz_e n mb_y_limit type r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mb_x_limit - - - flip rotate dblk_ en irq type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 this register is used to configure the operating conditions and modes of mp4 deblocking filters. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1303 of 1535 irq control for interrupt request 0 disable the interrupt reporting mechanism 1 enable the interrupt reporting mechanism dblk_en deblocking filters 0 disable deblocking filters operation 1 enable deblocking filters operation rotate control for video rotate angle. need irt0 dma to rotate the video for mp4_deblk. 00 0 01 clockwise 90 10 clockwise 180 11 clockwise 270 flip control for flip video. need irt0 dma to flip the video for mp4_deblk. 0 no flip 1 flip mb_x_limit video frame width (before rotate/flip). if mb_x_limit is not integer (the decoded frame width is not multiple of 16), round up to integer. mb_y_limit video frame height (before rotate/flip). if mb_y_limit is not integer (the decoded frame height is not multiple of 16), round up to integer. crz_en control of output to crz 0 disable 1 enable prz_en control of output to prz 0 disable 1 enable ipp1_en control of output to ipp1 0 disable 1 enable mp4_deblk +0008h mp4 deblk status register mp4_dblk _sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name state type ro ro ro ro ro this register provides the state information of deblocking sequencer for software program. it is a mirror of the hw deblocking sequencer state machine and can be used for debugging. mp4_deblk+ 000ch mp4 deblk interrupt status register mp4_dblk _irq_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1304 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - - debl k_do ne type ro this register allows software program to poll which interrupt source generates the interrupt request. a bit set to ?1? indicates a corresponding active interrupt source. note that irq control bit in mp4_dblk_conf should be enabled first in order to activate the interrupt reporting mechanism. deblk_done deblocking filter complete. mp4_deblk+ 0010h mp4 deblk interrupt acknowledge register mp4_ dblk _irq_ack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - - debl k_do ne type wc this register provides a mean for software program to acknowledge the interrupt source. writing a ?1? to the specific bit position will result in an acknowledgement to the corresponding interrupt source and clear the corresponding bit in mp4_dblk_irq_sts . deblk_done deblocking filters task complete mp4_deblk+ 0014h mp4 deblk line buffer address register mp4_dblk _lin_buf_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lin_buf_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lin_buf_addr - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register describes the starting address of internal line buffer. note that this base address should be 4- byte aligned. and the required internal line buffer size (yuv420 format) should be: 1.5 * number of pixels of frame_width * 8 = 12 * number of pixels of frame_width (bytes). mp4_deblk+ 0018h mp4 deblk quantize r address register mp4_dblk _quant_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name quant_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1305 of 1535 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name quant_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register describes the starting address of quantizer scales for flip/rotate frame. note that this base address should be byte-aligned. the base address is dependent on mb_x_limit , mb_y_limit , flip and rotate settings. base_quant_addr stores quantizer scales of top-left 4 macroblock in a decoded frame. the table below is the conclusion. ( mb_x = mb_x_limit round up to multiple of 4.) flip rotate quant_addr 0 00 base_quant_addr 0 01 base_quant_addr e mb_x *( mb_y_limit ? 1) 0 10 base_quant_addr e mb_x *( mb_y_limit ? 1) e ( mb_x_limit ? 1) 0 11 base_quant_addr e mb_x_limit ? 1 1 00 base_quant_addr e mb_x_limit ? 1 1 01 base_quant_addr 1 10 base_quant_addr e mb_x *( mb_y_limit ? 1) 1 11 base_quant_addr e mb_x *( mb_y_limit ? 1) e ( mb_x_limit ? 1) 5.23 mpeg-4/h.263 video codec 5.23.1 general description mpeg-4 is an emerging video coding standard defined in iso/iec 14496-2. it is designed to cover a wide range of bit-rates (typically, 5 kbps to 10mbps). mpeg-4 standard has become one of the enabling factors for mobile multimedia communications. h.263 is another video coding standard that is developed by itu-t/sg 15 for low-bit-rate applications below 64kbps. h.263 profile 0 level 10 is the mandatory video decoder in 3gpp specification. therefore, our goal is to design a video codec suited to both mpeg-4 and h.263 standard. there are two coding modes in mpeg-4 video compression: intra-frame coding and inter-frame coding. intra-frame coding refers to video coding techniques that achieve compression by exploiting the high spatial correlation between neighboring pels within a video frame. such techniques are also known as spatial free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1306 of 1535 redundancy reduction techniques or still-image coding techniques. inter-frame coding refers to video coding techniques that achieve compression by exploiting the high temporal correlation between the frames of a video sequence. such methods are also known as temporal redundancy reduction techniques. note that inter-frame coding may not be appropriate for some applications. for example, it would be necessary to decode the complete inter-frame coded sequence before being able to randomly access individual frames. thus, a combined approach is normally used in which a number of frames are intra-frame coded (i-frames) at specific intervals within the sequence and the other frames are inter-frame coded (predicted or p-frames) with reference to those key frames. moreover, intra-frame coding is allowed in p-frames. the iso/iec 14496 specification is intended to be generic in the sense that it serves a wide range of applications, bit-rates, resolutions, qualities and services. a number of coding tools are defined in the specification. considering the practicality of implementing the full syntax of this specification, a limited number of subsets of the syntax are also stipulated by means of ?profile? and ?level?. a ?profile? is a defined subset of the entire bitstream syntax that is defined by this specification. a ?level? is a defined set of constraints imposed on parameters in the bitstream. our application is focused on handset devices. due to restriction of limited resource, only simple profile is supported for most of handset devices. according to 3gpp ts 26.234 specification, h.263 profile 0 level 10 is the mandatory video decoder. mpeg-4 visual simple profile level 0 is an optional video decoder. the mpeg-4/h.263 codec supports both mpeg-4 simple profile and h.263 baseline profile. generally, the file extension of mpeg-4 video file is .mp4. the file extension of 3gpp video file is .3gp. the design implements both decoder and encoder. the decoder block diagram is shown in figure 142. the encoder block diagram is shown in figure 143 the decoder specification is as follows: 1. support iso/iec 14496-2 mpeg-4 simple profile @ level 0~3 2. support h.263 profile 0 level 10 (baseline profile) 3. the following visual tools are supported ? i-vop ? p-vop ? ac/dc prediction ? 4-mv ? unrestricted mv ? error resilience ? slice resynchronization ? data partitioning ? reversible vlc ? short header mode ? full and half pel accuracy ? fcode can be 1~7 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1307 of 1535 ? maximum horizontal luminance pixel resolution can be up to 720 ? maximum vertical luminance pixel resolution can be up to 480 ? error concealment ? single object the encoder specification is as follows: 1. support iso/iec 14496-2 mpeg-4 simple profile @ level 0, partially support mpeg-4 simple profile @ level 1 2. support h.263 profile 0 level 10 3. the following visual tools are supported ? i-vop ? p-vop ? dc prediction ? unrestricted mv ? short header mode ? full and half pel motion estimation ? decision making logic ? fcode can be 1~3 ? intra_dc_vlc_threshold shall be 0 ? maximum horizontal luminance pixel resolution can be up to 720 ? maximum vertical luminance pixel resolution can be up to 480 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1308 of 1535 motion coding motion compensation variable length decoding in ve r se quantization in v e r se dc & ac prediction inver se sca n idct reference vop reconstructed vop delay coded bitstream (motion) coded bitstream (texture) texture decoding figure 142 block diagram of decoder delay coded bitstream reference vop reconstructed vop current vop motion estimation q variable length encoding bitstream packing motion compensation fdct idct iq motion vector prediction variable length encoding figure 143 block diagram of encoder free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1309 of 1535 5.23.2 register definitions 5.23.2.1 register map register address register name synonym mp4 + 0000h video codec command register mp4_codec_comd mp4 + 0004h vlc dma command register mp4_vlc_dma_comd mp4 + 0100h encoder configuration register mp4_enc_codec_conf mp4 + 0104h encoder status register mp4_enc_sts mp4 + 0108h encoder interrupt mask register mp4_enc_irq_mask mp4 + 010ch encoder interrupt status register mp4_enc_irq_sts mp4 + 0110h encoder interrupt acknowledge register mp4_enc_irq_ack mp4 + 0114h encoder configuration register mp4_enc_conf mp4 + 0124h encoder current vop base address register mp4_enc_vop_addr mp4 + 0128h encoder reference vop base address register mp4_enc_ref_addr mp4 + 012ch encoder reconstructed vop base address register mp4_enc_rec_addr mp4 + 0130h vle data load-store lsb base address register mp4_enc_data_store_addr mp4 + 0134h dc/ac prediction storage lsb base address register mp4_enc_dacp_addr mp4 + 0138h motion vector storage lsb base address register mp4_enc_mvp_addr mp4 + 0140h encoder vop structure 0 register mp4_enc_vop_struct0 mp4 + 0144h encoder vop structure 1 register mp4_enc_vop_struct1 mp4 + 0148h encoder vop structure 2 register mp4_enc_vop_struct2 mp4 + 014ch vop structure 3 register mp4_vop_struct3 mp4 + 0150h mb structure 0 register mp4_enc_mb_struct0 mp4 + 0160h encoder vlc dma base address register mp4_enc_vlc_base_addr mp4 + 0164h encoder vlc dma base bit count register mp4_enc_vlc_base_bitcnt mp4 + 0168h encoder vlc dma buffer limit register mp4_enc_vlc_limit mp4 + 016ch encoder vlc dma current word register mp4_enc_vlc_word mp4 + 0170h encoder vlc dma current bit count register mp4_enc_vlc_bitcn mp4 + 0174h encoder vlc dma ring buffer ending address register mp4_enc_vlc_jump_from_a ddr mp4 + 0178h encoder vlc dma ring buffer starting address register mp4_enc_vlc_jump_to_add r mp4 + 0180h mpeg4 encoder resync marker configuration 0 register mp4_enc_resync_conf0 mp4 + 0184h mpeg4 encoder resync marker configuration 1 register mp4_enc_resync_conf1 mp4 + 0188h mpeg4 encoder local time base register mp4_enc_time_base mp4 + 018ch mpeg4 encoder pre-fetch mode internal ref base address mp4_enc_ref_int_addr mp4 + 0190h mpeg4 encoder pre-fetch mode internal cur base address mp4_enc_cur_int_addr free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1310 of 1535 mp4 + 0194h mpeg4 encoder cycle count mp4_enc_cycle_count mp4 + 0200h decoder configuration register mp4_dec_codec_conf mp4 + 0204h decoder status register mp4_dec_sts mp4 + 0208h decoder interrupt mask register mp4_dec_irq_mask mp4 + 020ch decoder interrupt status register mp4_dec_irq_sts mp4 + 0210h decoder interrupt acknowledge register mp4_dec_irq_ack mp4 + 0224h decoder reference vop base address register mp4_dec_ref_addr mp4 + 0228h decoder reconstructed vop base address register mp4_dec_rec_addr mp4 + 0230h decoder data load-store lsb base address register mp4_dec_data_store_addr mp4 + 0234h dc/ac prediction storage lsb base address register mp4_dec_dacp_addr mp4 + 0238h motion vector storage lsb base address register mp4_dec_mvp_addr mp4 + 0240h decoder vop structure 0 register mp4_dec_vop_struct0 mp4 + 0244h decoder vop structure 1 register mp4_dec_vop_struct1 mp4 + 0248h decoder vop structure 2 register mp4_dec_vop_struct2 mp4 + 014ch decoder mb structure 0 register mp4_dec_mb_struct0 mp4 + 0260h decoder vlc dma base address register mp4_dec_vlc_base_addr mp4 + 0264h decoder vlc dma base bit count register mp4_dec_vlc_base_bitcnt mp4 + 0268h decoder vlc dma buffer limit register mp4_dec_vlc_limit mp4 + 026ch decoder vlc dma current word register mp4_dec_vlc_word mp4 + 0270h decoder vlc dma current bit count register mp4_dec_vlc_bitcnt mp4 + 0274h decoder vlc dma ring buffer ending address register mp4_dec_vlc_jump_from_a ddr mp4 + 0278h decoder vlc dma ring buffer starting address register mp4_dec_vlc_jump_to_add r mp4 + 027ch decoder quantization scale information of current frame starting address mp4_dec_qs_addr mp4 + 0280h mpeg4 decoder cycle count mp4_dec_cycle_count mp4 + 0280h core configuration register mp4_core_conf mp4 + 0300h core encoder configuration register mp4_core_enc_conf mp4 + 0304h core duplex controller status register mp4_duplex_sts mp4 + 0314h current vop base address register mp4_core_vop_addr mp4 + 0318h core reference vop base address register mp4_core_ref_addr mp4 + 031ch core reconstructed vop base address register mp4_core_rec_addr mp4 + 0324h core vle data load-store lsb base address register mp4_core_data_store_add r mp4 + 0328h core dc/ac prediction storage lsb base address register mp4_core_dacp_addr mp4 + 032ch core motion vector storage lsb base address register mp4_core_mvp_addr mp4 + 0330h core vop structure 0 register mp4_core_vop_struct0 mp4 + 0334h core vop structure 1 register mp4_core_vop_struct1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1311 of 1535 mp4 + 0338h core vop structure 2 register mp4_core_vop_struct2 mp4 + 033ch core vop structure 3 register mp4_core_vop_struct3 mp4 + 0340h core mb structure 0 register mp4_core_mb_struct0 mp4 + 0344h core mb structure 1 register mp4_core_mb_struct1 mp4 + 0348h core mb structure 2 register mp4_core_mb_struct2 mp4 + 034ch core mb structure 3 register mp4_core_mb_struct3 mp4 + 0350h core mb structure 4 register mp4_core_mb_struct4 mp4 + 0354h core mb structure 5 register mp4_core_mb_struct5 mp4 + 0358h core mb structure 6 register mp4_core_mb_struct6 mp4 + 035ch core mb structure 7 register mp4_core_mb_struct7 mp4 + 0370h core vlc dma status register mp4_core_vlc_dma_sts mp4 + 0374h core vle status register mp4_core_vle_sts mp4 + 0378h core vlc dma base address register mp4_core_vlc_base_addr mp4 + 037ch core vlc dma base bit count register mp4_core_vlc_base_bitcnt mp4 + 0380h core vlc dma buffer limit register mp4_core_vlc_limit mp4 + 0384h core vlc dma current word register mp4_core_vlc_word mp4 + 0388h core vlc dma current bit count register mp4_core_vlc_bitcnt mp4 + 038ch core vlc dma ring buffer ending address register mp4_core_vlc_jump_from_ addr mp4 + 0390h core vlc dma ring buffer starting address register mp4_core_vlc_jump_to_ad dr 5.23.2.2 main control mp4+0000h video codec command register mp4_codec_com d bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - dec_s tart enc_s tart dec_r st enc_r st core _rst type wo wo wo wo wo this register is the main command register for video codec. core_rst software reset control. writing 1 to this bit will reset the hardware core excluding apb control register set of decoder and encoder. only do the reset after 1 frame done or when codec is idle. enc_rst software reset control. writing 1 to this bit will reset the apb control register set of encoder. note that this bit won?t reset the hardware core. only do the reset after 1 frame done or when codec is idle. dec_rst software reset control. writing 1 to this bit will reset the apb control register set of decoder. note that this bit won?t reset the hardware core. only do the reset after 1 frame done or when codec is idle. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1312 of 1535 enc_start start the encode operation if writing 1 to this bit. the encode operation will start only when no decode operation is running; otherwise the encode operation will queue until decode operation is done. dec_start start the decode operation if writing 1 to this bit. the decode operation will start only when no encode operation is running; otherwise the decode operation will queue until encode operation is done. mp4+0004h vlc dma command register mp4_vlc_dma_c omd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - - - resu me stop type wo wo this register is the main control of vlc dma. stop stop the vlc dma. stop vlc dma activities through sw rather than hw state machine. resume resume the vlc dma access. vlc dma state machine will go to a pending state if the maximum allowed write count to target memory is reached and then an interrupt has occurred. after re-allocating the target address, sw writes resume to unfreeze the encoding process. 5.23.2.3 encoder 5.23.2.3.1 control mp4+0100h encoder configuration register mp4_enc_codec _conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - prefe tch chec k_tv type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - pmv dqua n - half step_limit vpgo b dct irq enc type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used to configure the operating conditions and modes of video codec. enc video codec operation mode 0 decode mode 1 encode mode irq control for interrupt request 0 disable the interrupt reporting mechanism 2 enable the interrupt reporting mechanism dct dct control 0 enable jpeg codec operation free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1313 of 1535 2 enable mpeg-4 video codec operation vpgob control for decoding video packet header. (no use in codec encoding mode ) 0 disable: decoding in video packet level. it means the software will take the responsibility for decoding packet header of each video packet. 1 enable: decoding in video object plane level step_limit step limit for motion estimation. the total number of steps in a n-step search is step_limit+2. increasing step_limit can increase search range of motion vectors. half motion estimation uses half-pel resolution 0 disable. perform full pel motion estimation only 1 enable. perform full pel motion estimation first, then half pel motion estimation dquan control for automatic update quantizer_scale process. (no use in codec encoding mode ) 0 disable 1 enable pmv predictive motion vector search. this is a two-path search algorithm. the idea is to initially consider several highly likely predictors (starting points), perform motion estimation from these predictors, and choose the best result among these predictors. in our approach, the two predictors approach is adopted. the origin (0,0) is considered as the predictor of first path. the minimum bdm point found in first pass will be the predictor of the second path. after finishing two-path motion estimation, choose the best result between the two minimum bdm points. this algorithm can significantly improve psnr by about 0.8db. however, the search time will increase by about 60%. setting pmv to 1 or 0 is the trade-off between visual quality and search time. 0 disable 1 enable check_tv enable signal to check if tv codec is busy before starting encoding operation. 0 do not check tv codec 1 check tv codec prefetch in order to reduce external memory access times , fetch reference frame and current frame from external memory into internal memory before encoding. pre-fetch do not support frames which width less than 128- pixel or height less than 96-pixel. 0 disable 1 enable mp4+0104h encoder status register mp4_enc_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides the state information of encoding sequencer for software program. it is a mirror of the hw one-hot sequencer state machine and can be used for debugging or irq status judging. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1314 of 1535 mp4+0108h encoder interrupt mask register mp4_enc_irq_ma sk bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - dma pack enc_ done type r/w r/w r/w reset 1 1 1 this register contains mask bit for each interruption source in mpeg-4 video encoder. it allows each interrupt source to be disabled or masked out separately under software control. after system reset or software reset, all bit values will be set to ?0? to indicate that interrupt requests are enabled. enc_done mask of encode complete interruption. pack mask of video packet bit count expire interruption. dma mask of vle dma limit interruption. mp4+010ch encoder interrupt status register mp4_enc_irq_st s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - - dma pack enc_ done type ro ro ro this register allows software program to poll which interrupt source generates the interrupt request. a bit set to ?1? indicates a corresponding active interrupt source. note that irq control bit in mp4_enc_codec_conf should be enabled first in order to activate the interrupt reporting mechanism. enc_done encode complete. a normal condition when encoding procedure is done. pack video packet bit count exceed interrupt. if a video packet size is larger than defined the interrupt will happen. dma mask of vlc dma interruption. when decoder detects empty vld stream buffer, an interrupt will inform the driver sw to refill the vld stream buffer. mp4+0110h encoder interrupt acknowledge register mp4_enc_irq_ac k bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1315 of 1535 name - - - - - - - - - - - - dma pack enc_ done type wc wc wc this register provides a mean for software program to acknowledge the interrupt source. writing a ?1? to the specific bit position will result in an acknowledgement to the corresponding interrupt source and clear the corresponding bit in mp4_enc_irq_sts . enc_done encode task complete. pack video packet bit count expired dma vlc dma buffer limit reached. mp4+0114h encoder configurat ion register mp4_enc_conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - packcnt pack type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - intra - - skip type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used specially to configure the desired encode conditions and modes for video codec. skip threshold for deciding not_coded bit. the value of skip is programmed by software first. the first round of pattern code ( me_pattern_code is set to 6?h0 whenever (sad y + sda u + sad v ) <= skip_threshold*16 not_coded bit will be set if pattern_code = 6?h0 and motion vector = (0,0) intra threshold for deciding intra coding in p frame. the value of intra is programmed by software first. the 3-bits macro-block type ( mb_type ) is set to 3?h0 (inter mb) if sady < intra_threshold *1024. otherwise, mb_type is set to 3?h3 (intra_mb) pack use video packet mode 0 disable 1 enable packcnt desired bit counts for a video packet. used in encode mode to define the largest vle buffer size of a video packet. 5.23.2.3.2 base addresses mp4+0124h encoder current vop base address register mp4_enc_vop_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vop type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vop - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1316 of 1535 this register describes the starting address of current vop frame that is going to be encoded. note that this base address should be 8-byte aligned . and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). vop current vop base address mp4+0128h encoder reference vop base address register mp4_enc_ref_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ref type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ref - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reference vop frame. note that this base address should be 8-byte aligned . and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). ref reference vop base address mp4+012ch encoder reconstructed vop base address register mp4_enc_rec_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rec type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rec - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reconstructed vop frame. note that this base address should be 8-byte aligned . and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). rec reconstructed vop base address mp4+0130h vle data load-store lsb base address register mp4_enc_data_s tore_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name store type r/wr/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name store - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of vle data load-store buffer in data-partitioned mode. note that this base address should be 4-byte aligned. and the required buffer size for encoder and decoder should be: 3k bytes and (number of macroblock per frame * 32) bytes, respectively. store lsb address of vle data load-store buffer free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1317 of 1535 mp4+0134h dc/ac prediction storage lsb base address register mp4_enc_dacp_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dacp type r/wr/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dacp - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of dc/ac prediction storage buffer. note that this base address should be 4- byte aligned. and the required buffer size for encoder and decoder should be 2k bytes and 4k bytes, respectively. dacp lsb address of dc/ac prediction storage buffer mp4+0138h motion vector storage lsb base address register mp4_enc_mvp_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mvp_addr type r/wr/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mvp_addr - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of motion vector storage buffer. note that this base address should be 4-byte aligned. and the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 bytes for vga size. mvp_addr lsb address of motion vector storage buffer 5.23.2.3.3 data structure mp4+0140h encoder vop structure 0 register mp4_enc_vop_st ruct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - roun d type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlcthr quant fcode shor t - rvlc data type type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to describe the header information of a certain video object plane that is going to be processed by video codec. type vop_coding_type definition, for both decode and encode. 0 this is a p-vop frame (inter frame) 1 this is an i-vop frame (intra frame) data data_partitioned for decode only. (no use in codec encoding mode) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1318 of 1535 0 data stream is in non-data-partitioned mode 1 data stream is in data-partitioned mode rvlc resversible_vlc, for decode only. (no use in codec encoding mode) 0 data stream contains no reversible vlc information 1 data stream uses reversible vlc tables. short short_video_header; for both decode and encode 0 normal mpeg-4 format 1 h.263 compatible format fcode fcode setting for both decode and encode, ranges from 0 to 7. quant vop_quant for both decode and encode. quantizer scale of the current frame. for variable q in decode mode, quant is an initial setting of the current frame. vlcthr intra_dc_vlc_thr for decode only. according to vlcthr, the decoder has to switch from intra dc mode to inter dc mode when the quantizer_scale is larger than a pre-defined value. vlcthr ranges from 0 to 7. round rounding type of half-pel motion compensation. round==1 means truncation toward zero (the pixel value is always larger than 0); round==0 means rounding-off addition. round rounding type of half-pel motion compensati on. round== 1 means truncation toward zero (the pixel value is always larger than 0); round== 0 means rounding- off addition . mp4+0144h encoder vop structure 1 register mp4_enc_vop_st ruct1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - hecbit - - - - mblength type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - ylimit - - - xlimit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1319 of 1535 xlimit macroblock count in x direction of a frame. ylimit macroblock count in y direction of a frame. mblength bit count of macroblock number in video packet header. it is a value defined by the following formula: mbcnt = xlimit * ylimit. for larger mbcnt, we have larger mblength. mblength is ranged from 1 to 14. hecbit bit count of extension header code in video packet header mp4+0148h encoder vop structure 2 register mp4_enc_vop_st ruct2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - mbno type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - vp_ypos - - - vp_xpos type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. vp_xpos starting position of the current video packet in x coordinate. vp_ypos starting position of the current video packet in y coordinate. mbno macroblock count limit for a video packet or frame. for a cif frame the value will be 396. mp4+014ch vop structure 3 register mp4_vop_struct 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - mbno type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - ypos - - - xpos type ro ro ro ro ro ro ro ro ro ro this register provides the position and count information of a certain macroblock that is currently under process of video codec. xpos current macroblock position in x coordinate ypos current macroblock position in y coordinate mbno current macroblock count mp4+0150h mb structure 0 register mp4_enc_mb_str uct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - quantizer type r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name quantizer dcvl c ac dquant pattern type code d type ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1320 of 1535 this register is used to store the header information of current macroblock. this register is mostly used for debugging. also used to provide hardware certain header information if all header parsing is done by software instead of hardware. coded not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header. type mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in macroblck header. pattern pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in macroblock header. dquant dquant. it can be ?2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by hardware from macroblock header. ac ac_pred_flag. it decides whether ac prediction is needed; always 0 in encoder; ac_pred_flag can be decoded by hardware from macroblock header. dcvlc use_intra_dc_vlc. if this bit is 0, intra ac vlc decode is used (no intra dc exists in current macroblock). quantizer quantizer_scale, ranged from 1 to 31. it can be variable if we have dquant values. 5.23.2.3.4 vlc dma mp4+0160h encoder vlc dma base address register mp4_enc_vlc_ba se_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to describe the address of started code word for each vlc dma buffer. note that this base address should be 4-byte aligned. base vlc dma base address mp4+0164h encoder vlc dma base bit count register mp4_enc_vlc_ba se_bitcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - bit type r/w r/w r/w r/w r/w this register is used to describe the starting bit position of the 1 st code word in the 1 st vlc dma buffer. for the following vlc dma buffers, it is assumed that they are all 4-byte aligned and always start from bit position ?0?. bit start of bit at the 1 st code word of 1 st dma buffer free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1321 of 1535 mp4+0168h encoder vlc dma buffer limit register mp4_enc_vlc_li mit bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register is used to describe the buffer size of each vlc dma buffer. note that the value is counted in 4 words (4*32-bit) . whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated. limit dma buffer size, count in word (32-bit) limit dma buffer size , count in word (32- bit) mp4+016ch encoder vlc dma current word register mp4_enc_vlc_w ord bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides the address information of a certain code word that is under process of video codec. sw reads it back after encode of a frame is done. addr vlc dma current address mp4+0170h encoder vlc dma current bit count register mp4_enc_vlc_bi tcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - bitcnt type ro ro ro ro ro this register provides the bit position information of a certain code word that is under process of video codec. bitcnt current bit count free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1322 of 1535 mp4+0174h encoder vlc dma ring buffer ending address register mp4_enc_vlc_ju mp_from_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_from_addr the ending address of the current dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr . to disable the ring buffer feature, set this register to all ones; note that the address counter will not jump until done with the content in memory with address as jump_from_addr. so the memory content with address jump_from_addr will be executed by hardware. mp4+0178h encoder vlc dma ring buffer starting address register mp4_enc_vlc_ju mp_to_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_to_addr the starting address of the next dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr ; note that the address counter will not jump until done with the content in memory with address as jump_from_addr . so the memory content with address jump_from_addr will be executed by hardware. 5.23.2.3.5 resync marker mp4+0180h mpeg4 encoder resync marker configuration 0 register mp4_enc_resync _conf0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name en mode period_bits type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name period_bits free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1323 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 en resync marker insertion enable 0 disable resync marker insertion 1 enable resync marker insertion mode resync marker insertion mode selection 0 resync marker is inserted based on number of bits 1 resync marker is inserted based on number of macroblocks period_bits period in number of bits to insert resync marker; only effective when mode is set to 0; hardware will insert resync marker at the next macroblock boundary once the bit length of a video packet exceeds this value. mp4+0184h mpeg4 encoder resync marker configuration 1 register mp4_enc_resync _conf1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - hec type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name period_mb type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 hec header extension code; indicates the value of header_extension_code in mpeg4 standard (iso/iec 14496-2) 0 header_extension_code is 0. 1 header_extension_code is 1. period_mb period in number of macroblocks (mb) to insert resync marker; only effective when mode is set to 1; hardware will insert resync marker at the next macroblock boundary once the number of macroblock in current video packet exceeds this value. mp4+0188h mpeg4 encoder local time base register mp4_enc_time_b ase bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - modulo_time_base bw type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vop_time_increment type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 modulo_time_base represent the value of modulo_time_base; value ranges from 0 to 31. bw bit width of vop_time_increment. the real bit-width of vop_time_increment is (bw + 1), ranging from 1 to 16. vop_time_increment carries the value of vop_time_increment defined in mpeg4 standard (iso/iec 14496-2); the meaningful bit width of vop_time_increment is signaled by bw field. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1324 of 1535 mp4+018ch mpeg4 encoder pre-fetch mode internal ref base address mp4_enc_ref_in t_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mp4_enc_ref_int_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_enc_ref_int_addr - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mp4_enc_ref_int_addr represent the base address of reference frame in internal memory. it is 8-byte aligned , and need search range size. only work in encoder pre-fetch mode. fetch reference frame data to internal memory. minimum internal memory size = frame_width * (56+32) = frame_width * 88. mp4_enc_ref_int_addr can?t be the beginning address of internal memory, it must have 32 bytes shift. and also, the end of reference internal memory must have 16-byte room to the last address of internal memory. mp4+0190h mpeg4 encoder pre-fetch mode internal cur base address mp4_enc_cur_in t_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mp4_enc_cur_int_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mp4_enc_cur_int_addr - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mp4_enc_cur_int_addr represent the base address of current frame in internal memory. it is 8-byte aligned , and need 3-macroblock size. only work in encoder pre-fetch mode. fetch current frame data to internal memory. mp4+0194h mpeg4 encoder cycle count mp4_enc_cycle_ count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cycle_count type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cycle_count type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register is used to store the total cycle count of encoder in current frame from start to end. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1325 of 1535 5.23.2.4 decoder mp4+0200h decoder configuration register mp4_dec_codec _conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - pmv dqua n - half step_limit vpgo b dct irq enc type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used to configure the operating conditions and modes of video codec. enc video codec operation mode 0 decode mode 1 encode mode irq control for interrupt request 0 disable the interrupt reporting mechanism 1 enable the interrupt reporting mechanism dct dct control 0 enable jpeg codec operation 1 enable mpeg-4 video codec operation vpgob control for decoding video packet header. 0 disable: decoding in video packet level. it means the software will take the responsibility for decoding packet header of each video packet. 1 enable: decoding in video object plane level step_limit step limit for motion estimation, for encode only; keep this for legacy reason. the total number of steps in a n-step search is step_limit+2. increasing step_limit can increase search range of motion vectors. half motion estimation uses half-pel resolution, for encode only. (no use in codec decoding mode ) 0 disable. perform full pel motion estimation only 1 enable. perform full pel motion estimation first, then half pel motion estimation dquan control for automatic update quantizer_scale process. 0 disable 1 enable pmv predictive motion vector search, for encode only; keep this for legacy reason. this is a two pass search algorithm. this algorithm can co-operate with both four step search (fme=0) and mediatek proprietary search (fme=1). the idea is to initially consider several highly likely predictors (starting points), perform motion estimation from these predictors, and choose the best result among these predictors. in our approach, the two predictors approach is adopted. the origin (0,0) is considered as the predictor of first pass. the minimum bdm point found in first pass will be the predictor of the second pass. after finishing two-pass motion estimation, choose the best result between the two minimum bdm points. this algorithm can significantly improve psnr by about 0.8db. however, the search time will increase by about 60%. setting pmv to 1 or 0 is the trade-off between visual quality and search time. (no use in codec decoding mode ) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1326 of 1535 0 disable 1 enable mp4+0204h decoder status register mp4_dec_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides the state information of decoding sequencer for software program. it is a mirror of the hw one-hot sequencer state machine and can be used for debugging or irq status judging. mp4+0208h decoder interrupt mask register mp4_dec_irq_ma sk bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - mb_mi smat ch_er r dma dec_d one mark er rld vld type r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 this register contains mask bit for each interrupt sources in mpeg-4 video decoder. it allows each interrupt source to be disabled or masked out separately under software control. after system reset or software reset, all bit values will be set to ?0? to indicate that interrupt requests are enabled. mb_mismatch_err mask of mb_mismatch_err interrupt. dma mask of vlc dma interrupt. dec_done mask of decode complete interrupt. mark mask of marker error interrupt in decode. rld mask of run length coding error interrupt vld mask of vld error interrupt generated in decoding process. mp4+020ch decoder interrupt status register mp4_dec_irq_st s bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1327 of 1535 name - - - - - - - - - mb_mi smat ch_er r dma dec_d one mark rld vld type ro ro ro ro ro ro this register allows software program to poll which interrupt source generates the interrupt request. a bit set to ?1? indicates a corresponding active interrupt source. note that irq control bit in mp4_dec_codec_conf should be enabled first in order to activate the interrupt reporting mechanism. mb_mismatch_err mb_mismatch_err interrupt, when macroblock_number error occurs, and the error number exceeds the limitation of total macroblock counts. dma mask of vlc dma interrupt. when decoder detects empty vld stream buffer, an interrupt will inform the driver sw to refill the vld stream buffer. dec_done decode complete. a normal condition when decoding procedure is done. mark marker decode error occurred. rld run length coding error. generated when the accumulated run value is larger than 64 (the 8x8 block memory size). vld vld error of decoding process. generated when a code can not be correctly referenced in vld table mp4+0210h decoder interrupt acknowledge register mp4_dec_irq_ac k bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - mb_mi smat ch_er r - dma dec_d one mark rld vld type wc wc wc wc wc wc this register provides a mean for software program to acknowledge the interrupt source. writing a ?1? to the specific bit position will result in an acknowledgement to the corresponding interrupt source. vld variable length decoding error rld run length decoding error mark marker decoding error dec_done decode task complete dma vlc dma buffer limit reached mb_mismatch_err mb_mismatch_err interrupt, when macroblock_number error occurs, and the error number exceeds the limitation of total macroblock counts. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1328 of 1535 5.23.2.4.1 base address mp4+0224h decoder reference vop base address register mp4_dec_ref_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ref_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ref_addr - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reference vop frame. note that this base address should be 8-byte aligned. and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). ref reference vop base address. mp4+0228h decoder reconstructed vop base address register mp4_dec_rec_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rec_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rec_addr - - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reconstructed vop frame. note that this base address should be 8-byte aligned. and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). rec reconstructed vop base address. mp4+0230h decoder data load-store lsb base address register mp4_dec_data_s tore_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name store type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name store - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of memory buffer used to store the macroblock header, intra dc values and motion vectors as decoding data-partitioned mpeg4 files. note that this base address should be 4-byte aligned. and the required buffer size for encoder and decoder should be: 3k bytes and (number of macroblock per frame * 32) bytes, respectively. store lsb address of vle data load-store buffer free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1329 of 1535 mp4+0234h dc/ac prediction storage lsb base address register mp4_dec_dacp_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dacp type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dacp - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of dc/ac prediction storage buffer. note that this base address should be 4- byte aligned. and the required buffer size for encoder and decoder should be: 2k bytes and 4k bytes, respectively. dacp lsb address of dc/ac prediction storage buffer mp4+0238h motion vector storage lsb base address register mp4_dec_mvp_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mvp_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mvp_addr - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of motion vector storage buffer. note that this base address should be 4-byte aligned. and the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 bytes for vga size. mvp_addr lsb address of motion vector storage buffer 5.23.2.4.2 data structure mp4+0240h decoder vop structure 0 register mp4_dec_vop_st ruct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - roun d type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlcthr quant fcode shor t - rvlc data type type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to describe the header information of a certain video object plane that is going to be processed by video codec. type vop_coding_type definition, for both decode and encode. 0 this is a p-vop frame (inter frame) 1 this is an i-vop frame (intra frame) data data_partitioned, for decode only. 0 data stream is in non-data-partitioned mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1330 of 1535 1 data stream is in data-partitioned mode rvlc resversible_vlc, for decode only. 0 data stream contains no reversible vlc information 1 data stream uses reversible vlc tables. short short_video_header; for both decode and encode 0 normal mpeg-4 format 1 h.263 compatible format fcode fcode size setting for both decode and encode, ranges from 0 to 7. quant vop_quant. for both decode and encode. quantizer scale of the current frame. for variable q in decode mode, quant is an initial setting of the current frame. vlcthr intra_dc_vlc_thr. for decode only. according to vlcthr, the decoder has to switch from intra dc mode to inter dc mode when the quantizer_scale is larger than a pre-defined value. vlcthr ranges from 0 to 7. round rounding type of half-pel motion compensation. round==1 means truncation toward zero (the pixel value is always larger than 0); round==0 means rounding-off addition. mp4+0244h decoder vop structure 1 register mp4_dec_vop_st ruct1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - hecbit - - - - mblength type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - ylimit - - - xlimit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. xlimit macroblock count in x direction of a frame. ylimit macroblock count in y direction of a frame. mblength bit count of macroblock number in video packet header. it is a value defined by the following formula: mbcnt = xlimit * ylimit. for larger mbcnt, we have larger mblength. mblength is ranged from 1 to 14. hecbit bit count of header extension code in video packet header; this section includes modulo_time_base, vop_time_increment, vop_coding_type, intra_dc_vlc_thr and vop_fcode_forward(only in p-vop). mp4+0248h decoder vop structure 2 register mp4_dec_vop_st ruct2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - mbno type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - vp_ypos - - - vp_xpos type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1331 of 1535 vp_xpos starting position of the current video packet in x coordinate. vp_ypos starting position of the current video packet in y coordinate. mbno macroblock count limit for a video packet or frame. for a cif frame the value will be 396. mp4+024ch decoder mb structure 0 register mp4_dec_mb_str uct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - quantizer type r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name quantizer dcvl c ac dquant pattern type code d type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the header information of the current macroblock. this register is mostly used for debugging. also used to provide hardware certain header information if all header parsing is done by software instead of hardware. coded not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header. type mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in macroblck header. pattern pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in macroblock header. dquant dquant. it can be ?2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by hardware from macroblock header. ac ac_pred_flag. it decides whether ac prediction is needed; always 0 in encoder; ac_pred_flag can be decoded by hardware from macroblock header. dcvlc use_intra_dc_vlc. if this bit is 0, intra ac vlc decode is used (no intra dc exists in current macroblock). quantizer quantizer_scale, ranged from 1 to 31. it can be variable if we have dquant values. 5.23.2.4.3 vlc dma .mp4+0260h decoder vlc dma base address register mp4_dec_vlc_ba se_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to describe the address of started code word for each vlc dma buffer. note that this base address should be 4-byte aligned. base vlc dma base address free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1332 of 1535 mp4+0264h decoder vlc dma base bit count register mp4_dec_vlc_ba se_bitcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - bit type r/w r/w r/w r/w r/w this register is used to describe the starting bit position of the 1 st code word in the 1 st vlc dma buffer. for the following vlc dma buffers, it is assumed that they are all 4-byte aligned and always start from bit position ?0?. bit start of bit at the 1 st code word of 1 st dma buffer mp4+0268h decoder vlc dma buffer limit register mp4_dec_vlc_li mit bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register is used to describe the buffer size of each vlc dma buffer. note that the value is counted in word (32-bit). whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated. limit dma buffer size, count in word (32-bit) mp4+026ch decoder vlc dma current word register mp4_dec_vlc_w ord bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides the address information of a certain code word that is under process of video codec. sw reads it back after decode of a frame is done. addr vlc dma current address mp4+0270h decoder vlc dma current bit count register mp4_dec_vlc_bi tcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1333 of 1535 name - - - - - - - - - - - bitcnt type ro ro ro ro ro this register provides the bit position information of a certain code word that is under process of video codec. bitcnt current bit count mp4+0274h decoder vlc dma ring buffer ending address register mp4_dec_vlc_ju mp_from_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_from_addr the ending address of the current dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr . to disable the ring buffer feature, set this register to all ones; note that the address counter will not jump until done with the content in memory with address as jump_from_addr. so the memory content with address jump_from_addr will be executed by hardware. mp4+0278h decoder vlc dma ring buffer starting address register mp4_dec_vlc_ju mp_to_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_to_addr the starting address of the next dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr ; note that the address counter will not jump until done with the content in memory with address as jump_from_addr . so the memory content with address jump_from_addr will be executed by hardware. mp4+027ch decoder quantization scale in formation of current frame starting address mp4_dec_qs_add r bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name qs_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1334 of 1535 reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name qs_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 qs_addr the starting address of the quantization scale and not_coded information in current frame for deblocking filter. the buffer size for decoder is: (((mb_x_limit+3)/4) * 4 * mb_y_limit) bytes. mp4+0280h mpeg4 decoder cycle count mp4_dec_cycle_ count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cycle_count type r r r r r r r r r r r r r r r r bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cycle_count type r r r r r r r r r r r r r r r r this register is used to store the total cycle count of decoder in current frame from start to end. 5.23.2.5 core mp4+0300h core configuration register mp4_core_conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - prefe tch - type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - pmv dqua n - half step_limit vpgo b dct irq enc type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this register is used to configure the operating conditions and modes of video codec. enc video codec operation mode 0 decode mode 1 encode mode irq control for interrupt request 0 disable the interrupt reporting mechanism 1 enable the interrupt reporting mechanism dct dct control 0 enable jpeg codec operation 1 enable mpeg-4 codec operation vpgob control for decoding video packet header. 0 disable: decoding in video packet level. it means the software will take the responsibility for decoding packet header of each video packet. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1335 of 1535 1 enable: decoding in video object plane level step_limit step limit for motion estimation. the total number of steps in a n-step search is step_limit+2. increasing step_limit can increase search range of motion vectors. half motion estimation uses half-pel resolution 0 disable. perform full pel motion estimation only 1 enable. perform full pel motion estimation first, then half pel motion estimation dquan control for automatic update quantizer_scale process. 0 disable 1 enable pmv predictive motion vector search. this is a two pass search algorithm. this algorithm can co-operate with both four step search (fme=0) and mediatek proprietary search (fme=1). the idea is to initially consider several highly likely predictors (starting points), perform motion estimation from these predictors, and choose the best result among these predictors. in our approach, the two predictors approach is adopted. the origin (0,0) is considered as the predictor of first pass. the minimum bdm point found in first pass will be the predictor of the second pass. after finishing two-pass motion estimation, choose the best result between the two minimum bdm points. this algorithm can significantly improve psnr by about 0.8db. however, the search time will increase by about 60%. setting pmv to 1 or 0 is the trade-off between visual quality and search time. 0 disable 1 enable mp4+0304h core encoder configuration register mp4_core_enc_ conf bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - packcnt pack type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - intra - - skip type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 this register is used specially to configure the desired encode conditions and modes for video codec. skip threshold for deciding not_coded bit. the value of skip is programmed by software first. the first round of pattern code ( me_pattern_code is set to 6?h0 whenever (sad y + sda u + sad v ) <= skip_threshold*16 not_coded bit will be set if pattern_code = 6?h0 and motion vector = (0,0) intra threshold for deciding intra coding in p frame. the value of intra is programmed by software first. the 3-bits macro-block type ( mb_type ) is set to 3?h0 (inter mb) if sady < intra_threshold *1024. otherwise, mb_type is set to 3?h3 (intra_mb) pack use video packet mode 0 disable 1 enable packcnt desired bit counts for a video packet. used in encode mode to define the largest vle buffer size of a video packet free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1336 of 1535 mp4+0308h core duplex controller status register mp4_duplex_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - duplex_state type ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name duplex_state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register is used to read back the current state of duplex controller in mpeg4 codec. duplex_state current state of duplex controller. 5.23.2.5.1 base addresses codec mpeg-4/h.263 codec msb base address mp4+0314h current vop base address register mp4_core_vop_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vop type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vop - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of current vop frame that is going to be encoded. note that this base address should be 4-byte aligned. and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). vop current vop base address. mp4+0318h core reference vop base address register mp4_core_ref_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ref type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ref - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reference vop frame. note that this base address should be 4-byte aligned. and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). ref reference vop base address. mp4+031ch core reconstructed vop base address register mp4_core_rec_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rec type ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1337 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rec - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the starting address of reconstructed vop frame. note that this base address should be 4-byte aligned. and the required frame buffer size should be: numbers of pixel per frame * 1.5 bytes (yuv420 format). rec reconstructed vop base address. mp4+0324h core vle data load-store lsb base address register mp4_core_data_ store_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name store type r/wr/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name store - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of vle data load-store buffer in data-partitioned mode. note that this base address should be 4-byte aligned. and the required buffer size for encoder and decoder should be: 3k bytes and (number of macroblock per frame * 32) bytes, respectively. store lsb address of vle data load-store buffer mp4+0328h core dc/ac prediction storage lsb base address register mp4_core_dacp _addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dacp type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dacp - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of dc/ac prediction storage buffer. note that this base address should be 4- byte aligned. and the required buffer size for encoder and decoder should be: 2k bytes and 4k bytes, respectively. dacp lsb address of dc/ac prediction storage buffer mp4+032ch core motion vector storage lsb base address register mp4_core_mvp_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name mvd_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mvd_addr - - type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register describes the lsb address of motion vector storage buffer. note that this base address should be 4-byte aligned. and the required buffer size for encoder should be mb_x_limit * 2 * 4 bytes, which equals to 320 bytes for vga size. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1338 of 1535 mvd_addr lsb address of motion vector storage buffer 5.23.2.5.2 data structure mp4+0330h core vop structure 0 register mp4_core_vop_ struct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - roun d type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlcthr quant fcode shor t - rvlc data type type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to describe the header information of a certain video object plane that is going to be processed by video codec. type vop_coding_type definition, for both decode and encode. 0 this is a p-vop frame (inter frame) 1 this is an i-vop frame (intra frame) data data_partitioned, for decode only. 0 data stream is in non-data-partitioned mode 1 data stream is in data-partitioned mode rvlc resversible_vlc, for decode only. 0 data stream contains no reversible vlc information 1 data stream uses reversible vlc tables. short short_video_header; for both decode and encode 0 normal mpeg-4 format 1 h.263 compatible format fcode fcode size setting for both decode and encode, ranges from 0 to 7. quant vop_quant. for both decode and encode. quantizer scale of the current frame. for variable q in decode mode, quant is an initial setting of the current frame. vlcthr intra_dc_vlc_thr. for decode only. according to vlcthr, the decoder has to switch from intra dc mode to inter dc mode when the quantizer_scale is larger than a pre-defined value. vlcthr ranges from 0 to 7. round rounding type of half-pel motion compensation. round==1 means truncation toward zero (the pixel value is always larger than 0); round==0 means rounding-off addition. mp4+0334h core vop structure 1 register mp4_core_vop_ struct1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - hecbit - - - - mblength type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - ylimit - - - xlimit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1339 of 1535 this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. xlimit macroblock count in x direction of a frame. ylimit macroblock count in y direction of a frame. mblength bit count of macroblock number in video packet header. it is a value defined by the following formula: mbcnt = (xlimit+15)/16 * (ylimit+15)/16. for larger mbcnt, we have larger mblength. mblength is ranged from 1 to 14. hecbit bit count of extension header code in video packet header mp4+0338h core vop structure 2 register mp4_core_vop_ struct2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - mbno type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - vp_ypos - - - vp_xpos type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used by software program to control the start position and count limit of macroblock for a certain video packet or video object plane that is going to be processed by video codec. vp_xpos starting position of current video packet in x coordinate that the sw wants to update. vp_ypos starting position of current video packet in y coordinate that the sw wants to update. mbno macroblock count limit for a video packet or frame. for a cif frame the value will be 396. mp4+033ch core vop structure 3 register mp4_core_vop_ struct3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - mbno type ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - ypos - - - xpos type ro ro ro ro ro ro ro ro ro ro this register provides the position and count information of a certain macroblock that is currently under process of video codec. xpos current macroblock position in x coordinate ypos current macroblock position in y coordinate mbno current macroblock count mp4+0340h core mb structure 0 register mp4_core_mb_s truct0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - quantizer type r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1340 of 1535 name quantizer dcvl c ac dquant pattern type code d type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the header information of current macroblock. this register is mostly used for debugging. also used to provide hardware certain header information if all header parsing is done by software instead of hardware. coded not_coded flag of current macroblock; not_coded can be decoded by hardware from macroblock header. type mb_coding_type of current macroblock; mb_coding_type can be decoded by hardware from mcbpc in macroblck header. pattern pattern_code of current macroblock; pattern_code can be decoded by hardware from cbpc and cbpy in macroblock header. dquant dquant. it can be ?2, -1, +1 or +2; total 4 possible choices using 2 bits to represent; dquant can be decoded by hardware from macroblock header. ac ac_pred_flag. it decides whether ac prediction is needed; always 0 in encoder; ac_pred_flag can be decoded by hardware from macroblock header. dcvlc use_intra_dc_vlc. if this bit is 0, intra ac vlc decode is used (no intra dc exists in current macroblock). quantizer quantizer_scale, ranged from 1 to 31. it can be variable if we have dquant values. mp4+0344h core mb structure 1 register mp4_core_mb_s truct1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - dc[1] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - dc[0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the dc value set 0 and 1 of current macroblock. dc[0] dc value for luminance block 0 dc[1] dc value for luminance block 1 mp4+0348h core mb structure 2 register mp4_core_mb_s truct2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - dc[3] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - dc[2] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the dc value set 2 and 3 of current macroblock. for debug purpose or sw encode/decode procedure. dc[2] dc value for luminance block 2 dc[3] dc value for luminance block 3 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1341 of 1535 mp4+034ch core mb structure 3 register mp4_core_mb_s truct3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - dc[5] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - dc[4] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the dc value set 4 and 5 of current macroblock. for debug purpose or sw encode/decode procedure. dc[4] dc value for chrominance block 4 dc[5] dc value for chrominance block 5 mp4+0350h core mb structure 4 register mp4_core_mb_s truct4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - mvy[0] type r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - mvx[0] type r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the motion vector set 0 of current macroblock. for debug purpose or sw encode/decode procedure. mvx[0] x component of motion vector set 0 mvy[0] y component of motion vector set 0 mp4+0354h core mb structure 5 register mp4_core_mb_s truct5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - mvy[1] type r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - mvx[1] type r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the motion vector set 1 of current macroblock. for debug purpose or sw encode/decode procedure. mvx[1] x component of motion vector set 1 mvy[1] y component of motion vector set 1 mp4+0358h core mb structure 6 register mp4_core_mb_s truct6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - mvy[2] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1342 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - mvx[2] type r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the motion vector set 2 of current macroblock. for debug purpose or sw encode/decode procedure. mvx[2] x component of motion vector set 2 mvy[2] y component of motion vector set 2 mp4+035ch core mb structure 7 register mp4_core_mb_s truct7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - mvy[3] type r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - mvx[3] type r/w r/w r/w r/w r/w r/w r/w r/w this register is used to store the motion vector set 3 of current macroblock. for debug purpose or sw encode/decode procedure. mvx[3] x component of motion vector set 3 mvy[3] y component of motion vector set 3 5.23.2.6 vlc dma mp4+0370h core vlc dma status register mp4_core_vlc_d ma_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gaddr_lsb type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - glco md gdrd y full empt y vld vle pack greq state type ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides software program the information of current status of vld dma. state state of vlc dma engine. greq request for data read/write. 0 no request. 1 request for data read/write. pack vle buffer maximum size meet. vle vle stream ready 0 vle is not ready 1 vle is ready vld vld stream ready 0 vld is not ready free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1343 of 1535 1 vld is ready empty fifo empty 0 vlc dma fifo is not empty 1 vlc dma fifo is empty full fifo full 0 vlc dma fifo is not full 1 vlc dma fifo is full gdrdy waiting for gdrdy, a signal from gmc, to return. 0 gdrdy has been received. 1 waiting for gdrdy to return. glcomd waitinf for glcomd, a signal from gmc, to return. 0 glcomd has been received. 1 waiting for glcomd to return. gaddr_lsb lower 16 bit value of gaddr, a signal to gmc. mp4+0374h core vle status register mp4_core_vle_s ts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - reload_cnt done type ro ro ro ro ro ro ro ro ro ro this register shows the status of mpeg4 vle block and is used for hardware debugging. done dc/ac coefficient reload done. reload_cnt dc/ac coefficient reload count. mp4+0378h core vlc dma base address register mp4_core_vlc_b ase_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base type wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base - - type wo wo wo wo wo wo wo wo wo wo wo wo wo wo this register is used to describe the address of started code word for each vlc dma buffer. note that this base address should be 4-byte aligned. base vlc dma base address mp4+037ch core vlc dma base bit count register mp4_core_vlc_b ase_bitcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1344 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - bit type wo wo wo wo wo this register is used to describe the starting bit position of the 1 st code word in the 1 st vlc dma buffer. for the following vlc dma buffers, it is assumed that they are all 4-byte aligned and always start from bit position ?0?. bit start of bit at the 1 st code word of 1 st dma buffer mp4+0380h core vlc dma buffer limit register mp4_core_vlc_l imit bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name limit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 this register is used to describe the buffer size of each vlc dma buffer. note that the value is counted in word (32-bit). whenever the limit is reached and the corresponding interrupt control is enabled, an interrupt request will be generated. limit dma buffer size, count in word (32-bit) mp4+0384h core vlc dma current word register mp4_core_vlc_ word bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name addr type ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name addr - - type ro ro ro ro ro ro ro ro ro ro ro ro ro ro this register provides the address information of a certain code word that is under process of video codec. sw reads it back after encode of a frame is done. addr vlc dma current address mp4+0388h core vlc dma current bit count register mp4_core_vlc_b itcnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name - - - - - - - - - - - - - - - - type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name - - - - - - - - - - - bitcnt type ro ro ro ro ro this register provides the bit position information of a certain code word that is under process of video codec. bitcnt current bit count free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1345 of 1535 mp4+038ch core vlc dma ring buffer ending address register mp4_core_vlc_j ump_from_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_from_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_from_addr the ending address of the current dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr . to disable the ring buffer feature, set this register to all ones; note that the address counter will not jump until done with the content in memory with address as jump_from_addr. so the memory content with address jump_from_addr will be executed by hardware. mp4+0390h core vlc dma ring buffer starting address register mp4_core_vlc_j ump_to_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name jump_to_addr type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 jump_to_addr the starting address of the next dma buffer; when a jump takes place in vlc dma address counter, the address will jump from the ending address of the current dma buffer, which is jump_from_addr , to the starting address of the next dma buffer, which is jump_to_addr ; note that the address counter will not jump until done with the content in memory with address as jump_from_addr . so the memory content with address jump_from_addr will be executed by hardware. 5.23.3 png decoder overview the png (portable network graphics) images, is widely used in many applications like icons, picture, and so on. in order to display many true-color icons in our applications and boost image processing performance, the hardware png decoder is developed. as a result, png decoder is designed to decode all kinds of png images with all color-depths combinations. to gain the best speed performance, png decoder can handle the png file from the first start bits of idat-chunk till the end of this png file. the software program only needs to program related control registers free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1346 of 1535 based on the ihdr chunk or sometimes plte chunk (palette mode) and wait for an interrupt coming from hardware. fig 1 shows the basic png file structure and software/hardware division. fig 2 shows the ihdr header that sw needs to parse. the information of dqt and dht table is included in the jpeg file but need to be parsed by the jpeg decoder and store in the memory. the software program must program 2k-byte-align address in the table starting address because we has fixed the locations of all kinds of tables, as shown in fig 2 . fig 3 shows the hw decoding procedures. from the first bit of idct chunk, hw will first do the extracting of chunk data. hw then get the zlib compressed bitstream by attaching every idat data. after extracting lz77 data from the zlib bitstream, hw will do read block-by-block in this lz77 bitstream. in doing block decoding, hw support all types of lz77 block decoding including uncompressed, dynamic huffman, and fixed huffman coded block. the coding type and final block information can be found in the first 3 bits of the block header. to decode the dynamic huffman coded block, hw will first decode the hclen table, storing it into uncompressed memory (external memory), then a compression action is performed to compress the table in external memory (128k) into compressed memory (internal memory recommended) (60bytes). same as the hclen table, the compression is performed for the hlit and hdist table. because the compressed hdist table born only after the hclen table can be discarded, sw can only allocate single hdist compressed memory for both hclen and hdist table storage. the compressed hlit table needs 572 bytes, and the compressed hdist table needs 60 bytes. notes that if the png image has no dynamic huffman coded block, these 3 memory (uncompressed, hlit, hclen) are no need to be allocated. fig. 4 shows the block diagram of the png hw decoder. besides uncompressed, hlit, and hclen memory, the source file, lz77 buffer, upper filtered buffer, color table, transparency table, and output memories are needed to be allocated and assigned by sw. fig. 5 shows the overall view of the png decoder and png resizer. png decoder sends the decoded image pixel-by-pixel to the png resizer in decoding a png image. the png resizer then doing the resizing, clipping, alpha blending and so on, then writes the resized image to the output buffer. png decoder supports the pause/resume function. the pause/resume steps are described below: (1) setting first infile_start_addr & infile_start_bitcnt for the first bits of idat chunk (the first infile_start_addr don?t need to be 4-bytes aligned) (2) set infile_end_addr for the pause point. this infile_end_addr should be infile_end_addr = (true_segment_boundary-8) | 0x3; where true_segment_boundary is the boundary which contains the true part of the png bitstream. (3) set png decode start, then png decoder starts decoding png file (4) hw then sends an interrupt (flag2) when bitstream dma reaches infile_end_addr and paused (5) set new infile_start_addr for the resume. infile_start_addr_new = (infile_start_addr_old & 0xfffffffc) + ((infile_consumed_bits>>3) & (0xfffffffc)); notes that the new inflie_start_addr would be 4-bytes aligned address. (6) set infile_consumed_bits to 0 (7) clear irq status (flag2) (8) set png decode start, then png decoder resumes to decode. png decoder sends an error interrupt when sequencer parsing error (flag2), crc checker fail (flag3), error filter type (flag4), output file over out_file_end_addr (flag5), or adler checker fail (flag6) occurred. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1347 of 1535 fig. 18 the basic structure of png files. field name size description width 4 bytes image width in pixels height 4 bytes image height in pixels bit depth 1 byte 1,2,4,8 or 16 color type 1 byte 0:grayscale, 2:rgb triple, 3:palette, 4:grayscale+alpha, 6: rgb+alpha compression method 1 byte must be 0 filter method 1 byte must be 0 interlace method 1 byte 0: non-interlaced. 1: adam 7 interlacing fig. 19 ihdr header which sw needs to parse sw sw hw free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1348 of 1535 fig. 20 the hardware decoding flow. si g nature ihdr plte idat idat idat idat iend compressed data (lz77) adler - 32 cmf flg zlib bitstream chunk layer hw block 0 block 1 block 2 lz77 dynamic huffman uncompressed fixed huffman final block compression type ? decoded lz77 raw bytes filtering format transfermation a r g b p a r g b p a r g b p a r g b p a r g b p ? indexed color (depth=1,2,4,8) : depth=1 : 8 pixel / 1byte depth=8 : 1 pixel / 1byte grey scale (depth=1,2,4,8,16) : depth=1 : 8 pixel / 1 byte depth=16 : 1 pixel / 2 bytes grey scale with alpha (depth=8,16) : depth=8 : 1 pixel / 2 bytes depth=16 : 1 pixel / 4 bytes true color (depth=8,16) : depth=8 : 1 pixel / 3 bytes 4 bytes/pixel sending to png resizer png standard ? lz77 decoding free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1349 of 1535 fig. 21 hardware block diagram. fig. 22 the png decoder and png resizer. 5.23.4 destination working buffer the hardware will perform sizing and clipping function during storing output data to working buffer. the sizing algorithm is simply add-drop pixel. the hw will support arbitrary ratio of sizing. as shown below the output destination address is indicated by (dst_x,dst_y) and with a given size by dst_w and dst_h, in the mean term the source image is also given a size with src_w and src_h and the source image will be applied to sizing algorithm to enlarge or shorten the size to fit the destination image. we should note that the destination starting point may be negative. the output pixel in negative position won?t be displayed on lcd window so neither output to working buffer. the clipping window is used to specify which part of image the lcd wants to display. the pixel out of clipping window should not output to working buffer. the destination working buffer is always start from (0.0) and with a given width (lcd_w) and height (lcd_h), if the pixel of destination image is in the clip window and lcd window it should be output to working buffer, and the address should be calculated as dst_output_addr = output_file_start_address + lcd_w * dst_y_ing * bytes_per_pixel + dst_x_ing * bytes_per_pixel bytes_per_pixel will depend on output format and list as follow argb888 : 4 bytes/pixel rgb888 : 3 bytes/pixel rgb565 : 2 bytes/pixel unpacked index : 1 bytes/pixel png codec png resizer gmc pixel by pixel internal memory emi arm free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1350 of 1535 5.23.5 sizing 1. enlarge 4 3 1 4 7 = 3 1 2 3 7 = 2. narrow 4 3 3 1 for simply hardware design hw need sw to provide these five parameters h src h src h dst height ratio h src h src h dst height ratio h src h src h dst height ratio h src h src h dst height ratio w src w src w dst width ratio _ _ 8 * _ 8 * _ . 5 _ _ 4 * _ 4 * _ . 4 _ _ 2 * _ 2 * _ . 3 _ _ _ _ . 2 _ _ _ _ . 1 nvm@ sbujp@i@o@ nvm@ sbujp@i@r@ nvm@ sbujp@i@o@ nvm@ sbujp@i@r@ nvm@ sbujp@i@o@ nvm@ sbujp@i@r@ sbujp@i@o sbujp@i@r sbujp@x@o sbujp@x@r ? = = ? = = ? = = ? = = ? = = 5.23.6 limitation the maximum decodable image size is max_width=min( floor((16*1024-1)/bytes_per_pixel) , 8192); max_height = is_interlace ? 8192 : 4096; free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1351 of 1535 max_height * ( max_width * bytes_per_pixel + 1 ) < 2 23 where bytes_per_pixel=8 for argb-16, 3 for rgb-8, 0.25 for grey-4, 1 for palette, and etc. 5.23.7 register definitions register address register function acronym pngdec+0000h input file start address infile_start_addr pngdec+0004h input file count infile_count pngdec+0008h input file consumed bits infile_consumed_bit pngdec+000ch color table start address ct_start_addr pngdec+0010h uncompressed start address uncompressed_start_addr pngdec+0014h huffman hlit table start address hlit_start_addr pngdec+0018h huffman hdist table start address hdist_start_addr pngdec+001ch line buffer0 start address buff0_start_addr pngdec+0020h lz77 buffer start address lz77_start_addr pngdec+0024h color_type color_type pngdec+0028h decode control register decode_ctrl pngdec+002ch clear enable register clr_en pngdec+0030h adler adler pngdec+0034h color output format out_format pngdec+0038h interrupt enable register irq_en pngdec+003ch interrupt status irq_status pngdec+0040h transparency table start address trns_addr pngdec+0044h trns ctrl trns ctrl pngdec+0048h transparency key1 trns_key1 pngdec+004ch transparency key2 trns_key2 pngdec+0050h background color bg_color pngdec+0054h index number index_num pngdec+0058h outfile start address outfile_start_addr pngdec+05ch outfile end address outfile_end_addr pngdec+0060h source image size src_image_size pngdec+0064h source image pixel count src_image_pixel_cnt pngdec+0068h destination image position dst_image_position pngdec+006ch destination sizing ration w1 dst_sizing_ratio_w1 pngdec+0070h destination sizing ration w2 dst_sizing_ratio_w2 pngdec+0074h destination sizing ration w4 dst_sizing_ratio_w4 pngdec+0078h destination sizing ration w8 dst_sizing_ratio_w8 pngdec+007ch destination sizing ration h1 dst_sizing_ratio_h1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1352 of 1535 pngdec+0080h destination sizing ration h2 dst_sizing_ratio_h2 pngdec+0084h destination sizing ration h4 dst_sizing_ratio_h4 pngdec+0088h destination sizing ration h8 dst_sizing_ratio_h8 pngdec+008ch lcd window size lcd_window_size pngdec+0090h clip window position upper-left clip_window_position_ul pngdec+0094h clip window position down-right clip_window_position_dr pngdec+0098h interlace control interlace_ctrl pngdec+009ch replaced color replaced_color pngdec+00a0h replace as color replace_as_color pngdec+00a4h alpha blending alpha_blending pngdec+00a8h alpha value a_value pngdec+00ach b buffer start address b_start_addr pngdec+00b0h b buffer format b_format pngdec+0100h png debug information 1 png_debug1 pngdec+0104h png debug information 2 png_debug2 pngdec+0108h png debug information 3 png_debug3 pngdec+010ch png debug information 4 png_debug4 pngdec+0110h png debug information 5 png_debug5 pngdec+0114h png debug information 6 png_debug6 pngdec+0118h png debug information 7 png_debug7 pngdec+011ch png debug information 8 png_debug8 pngdec+0120h png debug information 9 png_debug9 pngdec+0124h png debug information 10 png_debug10 table 119 png decoder registers pngdec+0000h input file start address infile_start_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name infile_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name infile_start_addr[15:0] type r/w reset 0 infile_start_addr the input file starting address; png decoder would get decompression data from this address. the address can be any byte alignment. pngdec+0004h input file count infile_count bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name infile_end_addr[31:16] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1353 of 1535 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name infile_ end_addr [15:0] type r/w reset 0 infile_end_addr the end address of input file in bytes. if png decoder fetch data reach to this address, it will stop and turn off dec_en and notify sw by interrupt. if pause-resume mechanism is wanted, sw just needs to turn on the dec_en when re-programmed the infile_start_addr and infile_end_addr. gif decoder will continue to decode using last states. if sw want to start a new decode process, it should set the clr_en = 1 then re-set it to 0 to clear png decoder?s states. the clr_en is used to reset gif decoder?s internal states. pngdec+0008h input file consum ed bits infile_consumed_bit bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name infile_cousumed_bit[23:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name infile_cousumed_bit[15:0] type r/w reset 0 infile_consumed_bit the consumed bits by png hardware decoder and units in bit. this number is used to inform sw how many bits hw has been read from input file. sw should notice that when hw issue input file empty interrupt the infile_consumed_bit doesn?t need to equal to infile_count. in fact when input file empty interrupt has been raised it imply that the hw has been dma in the infile_count data but may not consume all of them so if sw don?t clear the internal states the next time when dec_en is turn on hw will start to decode from the residual bits last time left. pngdec+000ch color table st art address ct_start_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ct_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ct_start_addr [15:0] type r/w reset 0 ct_start_addr the color table starting address. it needs to be word aligned. and each palette entry is one word. each word with following format: word[31:0]={8?b0,r,g,b}. the maximum size needed is 256x4 bytes pngdec+0010h uncompressed start address uncompressed_st art_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1354 of 1535 name uncompressed_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name uncompressed _start_addr[15:0] type r/w reset 0 uncompressed _start_addr uncompressed start address it needs to be word aligned. this table has maximum size 128k bytes pngdec+0014h huffman hlit table start address hlit_start_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hlit_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hlit_start_addr[15:0] type r/w reset 0 hlit_start_adde huffman literal code table starting address. it needs to be word aligned. this table has maximum size 572 bytes pngdec+0018h huffman hdist table start address hdist_start_a ddr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hdist_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hdist_start_addr[15:0] type r/w reset 0 hdist_start_addr huffman distance code table starting address. it needs to be word aligned. this table has maximum size 60 bytes pngdec+001ch line buffer0 start address buff0_start_ad dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buff0_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buff0_start_addr[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1355 of 1535 reset 0 buff0_start_addr line buffer0 starting address (for de-filtering). it needs to be word aligned. this table has maximum size ( ( source_width * bytes_per_pixel + 4) & 0xfffffffc ) where bytes_per_pixel=8 for argb-16, 3 for rgb-8, 0.25 for grey-4, 1 for palette, and etc. pngdec+0020h lz77 buffer start address lz77_start_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lz77_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lz77_start_addr[15:0] type r/w reset 0 lz77_start_addr lz77 buffer starting address. it needs to be word aligned. the maximum size = max(32k+16 bytes, image size) pngdec+0024h color type color_type bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name color_depth[4:0] color_type [2:0] type r/w r/w reset 0 0 color_type indicate color type of png image. 0: grayscale 1: reserved 2: true color 3: palette 4: grayscale with alpha 5: reserved 6: true color with alpha 7: reserved color_depth indicate color bit depth of png image. 1, 2, 4, 8, 16 pngdec+0028h decode control register decode_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1356 of 1535 name dec_ en type r/w reset 0 dec_en decode enable signal. pngdec+002ch clear enable register clr_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clr_e n type r/w reset 0 clr_en clear enable signal. 1 = clear, 0 = no clear note: to reset the png decoder, the clr_en should be first set to 1 then set to 0. pngdec+0030h adler adler bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name adler[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name adler[15:0] type r/w reset 0 adler adler checksum data report. pngdec+0034h color output format out_format bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name out_form at[1:0] type r/w reset 0 out_format output color format 2?b00: index (not support) 2?b01: rgb565, 2?b10: rgb888, 2?b11: argb8888 pngdec+0038h interrupt enable register irq_en bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1357 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name int6_e n int5_e n int4_e n int3_e n int2_e n int1_e n int0_ en type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 int0_en flag0 interrupt enable int1_en flag1 interrupt enable int2_en flag2 interrupt enable int3_en flag3 interrupt enable int4_en flag4 interrupt enable int5_en flag5 interrupt enable int6_en flag6 interrupt enable pngdec+003ch interrupt status irq_status bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name flag6 flag5 flag4 flag3 flag2 flag1 flag0 type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 flag0 image decompressed complete decoded pixels exactly the same as image size flag1 image decompressed complete result from input file empty flag2 image decompressed incomplete result from sequencer error flag3 image decompressed incomplete result from crc error flag4 image decompressed incomplete result from decoder decode an error filter type flag5 image decompressed incomplete result from output address over out_end_addr flag6 image decompressed incomplete result from adler error pngdec+0040h transparency table start address trns_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name trns_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trns_addr[15:0] type r/w reset 0 tran_addr transparency table start address. pngdec+0044h trns ctrl trns ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1358 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name t_out _spec t_tab le t_out t_en type r/w r/w r/w r/w reset 0 0 0 0 t_en transparent enable t_out 0: output transparent color as background color 1: no output when transparent t_table transparent table exist t_out_spec transparent color key enable pngdec+0048h transparency key1 trns_key1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name grey_key[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name r_key[15:0] type r/w reset 0 grey_key transparent color key of grayscale image r_key transparent color key of red component pngdec+004ch transparency key2 trns_key2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name g_key[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_key[15:0] type r/w reset 0 g_key transparent color key of green component b_key transparent color key of blue component pngdec+0050h background color bg_color bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bg_grey[7:0] bg_r[7:0] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bg_g[7:0] bg_b[7:0] type r/w r/w reset 0 0 bg_grey background color of grayscale image bg_r background color of red component bg_g background color of green component free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1359 of 1535 bg_b background color of blue component pngdec+0054h index number index_num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name color_num[7:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name trans_num[7:0] type r/w reset 0 color_num color entry number trans_num transparency entry number pngdec+0058h outfile star t address outfile_start_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name outfile_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name outfile_start_addr[15:0] type r/w reset 0 outfile _ start_addr output working buffer address we can view this buffer as lcd display buffer. this address is viewed as the (0,0) address of lcd window. it needs word aligned. pngdec+05ch outfile end address outfile_end_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name outfile_end_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name outfile_end_addr[15:0] type r/w reset 0 outfile_end_addr output file end address. the end address is set to prevent gif decoder from writing the wrong memory sections. when this happens, png decoder will stop and generate an interrupt to inform sw. it needs word aligned. pngdec+0060h source image size src_image_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_w[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_h[15:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1360 of 1535 src_w the width of the source image specifies in pixel. this value is an un-signed 16 bits. this parameter is used when sizing function required. the usage is described in the above section. the range is from 1~2^16-1. 0 is not valid. src_h the height of the source image specifies in pixel. this value is an un-signed 16 bits. this parameter is used when sizing function required. the usage is described in the above section. the range is from 1~2^16-1. 0 is not valid. pngdec+0064h source image pixel count src_image_pixel_cnt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_image_pixel_cnt[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_image_pixel_cnt[15:0] type r/w reset 0 src_image_pixel_cnt the result of src_w * src_h, unit in pixel, using this register to save a multiplier. pngdec+0068h destination image position dst_image_position bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_x[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_y[15:0] type r/w reset 0 dst_x the x-position of the destination image specifies in pixel. this value is a signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. this value must be a 2?s complement number. its range is from -2^15 ~ 2^15-1 dst_y the y-position of the destination image specifies in pixel. this value is a signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. this value must be a 2?s complement number. its range is from -2^15 ~ 2^15-1 pngdec+006ch destination sizing ration w1 dst_sizing_ratio_w1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_w_q[7:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_w_n[15:0] type r/w reset 0 dst_w_q the quotient of dst_w/src_w. this value is an un-signed 8 bits. if dst_w_q = 0, it means the resizer should perform shrink otherwise it would be enlarge function. dst_w_n the remainder of dst_w/src_w. pngdec+0070h destination sizing ration w2 dst_sizing_ratio_w2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1361 of 1535 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_w_q_mul_2[8:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_w_n_mul_2[15:0] type r/w reset 0 dst_w_q_mul_2 the quotient of 2*dst_w/src_w. this value is an un-signed 9 bits. dst_w_n_mul_2 the remainder of 2*dst_w/src_w. this value is an un-signed 16 bits. pngdec+0074h destination sizing ration w4 dst_sizing_ratio_w4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_w_q_mul_4[9:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_w_n_mul_4[15:0] type r/w reset 0 dst_w_q_mul_4 the quotient of 4*dst_w/src_w. this value is an un-signed 10 bits. dst_w_n_mul_4 the remainder of 4*dst_w/src_w. this value is an un-signed 16 bits. pngdec+0078h destination sizing ration w8 dst_sizing_ratio_w8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_w_q_mul_8[10:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_w_n_mul_8[15:0] type r/w reset 0 dst_w_q_mul_8 the quotient of 8*dst_w/src_w. this value is an un-signed 11 bits. dst_w_n_mul_8 the remainder of 8*dst_w/src_w. this value is an un-signed 16 bits. pngdec+007ch destination sizing ra tion h1 dst_sizing_ratio_h1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_h_q[7:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_h_n[15:0] type r/w reset 0 dst_h_q the quotient of dst_h/src_h. this value is an un-signed 8 bits. if dst_w_q = 0, it means the resizer should perform shrink otherwise it would be enlarge function. dst_h_n the remainder of dst_h/src_h. pngdec+0080h destination sizing ration h2 dst_sizing_ratio_h2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_h_q_mul_2[8:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1362 of 1535 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_h_n_mul_2[15:0] type r/w reset 0 dst_h_q_mul_2 the quotient of 2*dst_h/src_h. this value is an un-signed 9 bits. dst_h_n_mul_2 the remainder of 2*dst_h/src_h. this value is an un-signed 16 bits. pngdec+0084h destination sizing ration h4 dst_sizing_ratio_h4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_h_q_mul_4[9:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_h_n_mul_4[15:0] type r/w reset 0 dst_h_q_mul_4 the quotient of 4*dst_h/src_h. this value is an un-signed 10 bits. dst_h_n_mul_4 the remainder of 4*dst_h/src_h. this value is an un-signed 16 bits. pngdec+0088h destination sizing ra tion h8 dst_sizing_ratio_h8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dst_h_q_mul_8[10:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_h_n_mul_8[15:0] type r/w reset 0 dst_h_q_mul_8 the quotient of 8*dst_h/src_h. this value is an un-signed 11 bits. dst_h_n_mul_8 the remainder of 8*dst_h/src_h. this value is an un-signed 16 bits. pngdec+008ch lcd window size lcd_window_size bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name lcd_w [15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lcd_h [15:0] type r/w reset 0 lcd_w the width of the lcd window specifies in pixel. this value is an un-signed 16 bits. this parameter is used when sizing function required. the usage is described in the above section. the range is from 1~2^16-1. 0 is not valid. lcd_h the height of the lcd window specifies in pixel. this value is an un-signed 16 bits. this parameter is used when sizing function required. the usage is described in the above section. the range is from 1~2^16-1. 0 is not valid. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1363 of 1535 pngdec+0090h clip window position upper-left clip_window_p osition_ul bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clip_ul_x[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_ul_y[15:0] type r/w reset 0 clip_ul_x the up-left x-position of the clip window specifies in pixel. this value is an un-signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. its range is from 0 ~ 2^16- 1 clip_ul_y the up-left y-position of the clip window specifies in pixel. this value is an un-signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. its range is from 0 ~ 2^16- 1 pngdec+0094h clip window position down-right clip_window_ position_dr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clip__dr_x[15:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_dr_y[15:0] type r/w reset 0 clip_dr_x the down-right x-position of the clip window specifies in pixel. this value is an un-signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. its range is from 0 ~ 2^16-1 clip_dr_y the down-right y-position of the clip window specifies in pixel. this value is an un-signed 16 bits. this parameter is used to speed up gif display and reduce memory usage. its range is from 0 ~ 2^16-1 pngdec+0098h interlace c ontrol interlace_ctrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name inter lace type r/w reset 0 interlace 0 - non-interlaced 1 ? interlaced pngdec+009ch replaced color replaced_color bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1364 of 1535 name repla ce_en replaced_color[23:16] type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name replaced_color[15:0] type r/w reset 0 replace_en enable for replace function (when out_format is argb it should not be turn on) replaced_color the valid bit length is depend on out_format rgb888, replace color is 24 bits with rgb, rgb565, replace color is 16 bits pngdec+00a0h replace as color replace_as_color bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name replace_as color[23:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name replace_as color[15:0] type r/w reset 0 replace_as_color the format is depend on out_format, rgb888, replace color is 24 bits with rgb. rgb565, replace color is 16 bits pngdec+00a4h alpha blending alpha_blending bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name alph a_sid e blending_mode[2: 0] type r/w r/w reset 0 0 alpha_side apply alpha in which side (a*r1_value+(1-a)*r2_value) 0: r1_value = png file, r2_value = b buffer 1: r1_value = b buffer , r2_value = png file blending_mode 3?b000: no blending (turn off blending) 3?b001: use png alpha value (only support when png format is rgb or grey with alpha) and blend with b buffer 3?b010: use b buffer alpha value (only support when b buffer is argb mode) 3?b011: use user defined src alpha value 3?b100: use png alpha value (only support when png format is rgb or grey with alpha) and blend with back ground color note: alpha blending should be turned on only when png file is rgb with alpha or grey with alpha, if it turn on when png file hasn?t alpha the transparent function may be failed. pngdec+00a8h alpha value a_value bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1365 of 1535 name a_en type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dst_a_value[7:0] src_a_value[7:0] type r/w r/w reset 0 0 a_en 0: using png file alpha value as output alpha value if output format is argb8888 (if our_format = argb888 only no blend act can turn off a_en) 1: using dst_a_value as output alpha value if output format is argb8888 dst_a_value software specified value for using when output format is argb8888 and following two situations happened blending acts png source file hasn?t alpha value src_a_value this value is used for alpha blending when blending_mode == 2?b11. pngdec+00ach b buffer start address b_start_addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name b_start_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_start_addr[15:0] type r/w reset 0 b_start_addr the b buffer start address and its coordination is (0,0) pngdec+00b0h b buff er format b_format bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b_format[1: 0] type r/w reset 0 b_format 2?b00: no deinfed 2?b01: rgb565 2?b10: rgb888 2?b11: argb8888 pngdec+0100h png debug in formation 1 png_debug1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name seq_state[5:0] type r reset 0 seq_state sequencer state machine free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1366 of 1535 pngdec+0104h png debug in formation 2 png_debug2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vld_codeword[14:0] type r reset 0 vld_codeword vld_codeword pngdec+0108h png debug in formation 3 png_debug3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name out_gmc_state[12:0] type r reset 0 out_gmc_state out state machine pngdec+010ch png debug in formation 4 png_debug4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pal_ wait_ gdrd y out_b uf_fu ll pixel _vali d type r r r reset 0 0 0 pixel_valid pixel_valid signal out_buf_full out_buf_full signal pal_wait_gdrdy pal gmc port wait gdrdy signal pngdec+0110h png debug in formation 5 png_debug5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name raw_data_x[14:0] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name raw_data_y[11:0] type r reset 0 raw_data_x lz77 decoding position, x raw _data_y lz77 decoding position, y pngdec+0114h png debug in formation 6 png_debug6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name irq_b filter_type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1367 of 1535 type r r reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name zlib_blockno[1:0] type r reset 0 zlib_blockno current zlib_block number filter_type filter_type irq_b irq pngdec+0118h png debug in formation 7 png_debug7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dma_state[4:0] type r reset 0 dma_state dma_state_machine pngdec+011ch png debug in formation 8 png_debug8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crc[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name crc[15:0] type r reset 0 crc current crc value pngdec+0120h png debug in formation 9 png_debug9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name crc_fifo_bytepos[4:0] type r reset 0 crc_fifo_bytepos crc_fifo byte position pngdec+0124h png debug in formation 10 png_debug10 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name crc_read_length[31:16] type r reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name crc_read_length[15:0] type r reset 0 crc_read_length crc read length free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1368 of 1535 5.24 post resize 5.24.1 general description figure 116 shows the block diagram of post resize. it receives image data from a block-based source such as jpeg decoder or from a scan line based source, and then performs image resizing. the capability of resizing in the block is divided into two portions, coarse pass and fine pass. the first pass is coarse resizing pass and it is able to shrink image by a factor of 1, 1/4, 1/16, or 1/64. the second pass is the fine resizing pass, which is composed of horizontal and vertical resizing, and it is able to shrink or enlarge image in fractional ratio. the maximum allowable image size for the fine resizing pass is 4095x4095. thus the maximum allowable image size for coarse resizing pass is 32760x32760 if the strip buffer is enough. figure 144 block diagram of the post resize the strip buffer of coarse resizing pass accumulates de-compressed 8x8 yuv blocks separately. these yuv data are packed into pixels and sent to the fine resizing pass. the fine resizing pass is composed of horizontal and vertical resizing blocks. it can scale up or down the input image by any ratio. however, the maximum sizes of input and output images are limited to 4095x4095. the horizontal resizing function is a combination of 2?s power average and bi-linear interpolation. the vertical resizing function is a bi-linear interpolation. the input and output format are both yuv444. but the internal working memory format is yuv422 to mitigate memory and bandwidth requirements. 5.24.2 working memories there are two working memories in post resize. one is the strip buffer, and the other is the vertical buffer. 5.24.2.1 strip buffer let?s denote sampling factor for y-component as (h y , v y ), u-component as (h u , v u ) and v-component as (h v , v v ) in a jpeg file. the minimum requirement of memory size for the strip buffer is (the image width of after the coarse resizing pass) * (v y * 8 + v u * 8 + v v * 8) bytes. it is (4064) * (4 * 8 + 2 * 8 + 2 * 8) = 260k bytes jpeg dec coarse resize horizontal resize vertical resize vertical buffer strip buffer capture resize mp4 deblocking ibw4 dma rgb2yuv 0 image rotator 0 image post processing free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1369 of 1535 for extreme cases. to enhance the throughput of jpeg decode process, software may use double buffer scheme. then it becomes 520k bytes. please note that the strip buffer is composed of the y buffer, u buffer, and v buffer. software can allocate separate memory for them. 5.24.2.2 vertical buffer the minimum requirement of memory for the vertical buffer is (the target image width) * (the line number for vertical interpolation) * 2 bytes. it is (4095) * (2) * 2 = 16k bytes for extreme cases. to enhance throughputs of overall data paths, software may use double buffer scheme. then it becomes 32k bytes. 5.24.3 source image for the coarse resizing pass, the width of the source image must be multiples of 8 * (maximum horizontal sampling factor) . similarly, the height of the source image must be multiples of 8 * (maximum vertical sampling factor) . the maximum size of target image is 4095x4095. for the fine resizing pass, the maximum size of source image and target image are both 4095x4095. 5.24.4 flow control for the coarse resizing pass, the coarse resizing will send pixel data to the fine resizing when they are ready with hand shake signal. if strip buffer is full, the coarse resizing will halt image data input until the strip buffer is available. for the fine resizing pass, the fine resizing will send pixel data to the image post processing or yuv2rgb1 when they are ready with hand shake signal. if vertical buffer is full, the fine resizing will halt image data input until the vertical is available. 5.24.5 register definitions register address register name synonym prz+ 0000h post resize configuration register prz_cfg prz + 0004h post resize control register prz_con prz + 0008h post resize status register prz_sta prz + 000ch post resize interrupt register prz_int prz + 0010h post resize source image size register 1 prz_srcsz1 prz + 0014h post resize target image size register 1 prz_tarsz1 prz + 0018h post resize horizontal ratio register 1 prz_hratio1 prz + 001ch post resize vertical ratio register 1 prz_vratio1 prz + 0020h post resize horizontal residual register 1 prz_hres1 prz + 0024h post resize vertical residual register 1 prz_vres1 prz + 0030h post resize block coarse shrinking configuration register prz_blkcscfg prz + 0034h post resize y-component line buffer memory base address prz_ylmbase prz + 0038h post resize u-component line buffer memory base address prz_ulmbase prz + 003ch post resize v-component line buffer memory base address prz_vlmbase prz + 0040h post resize fine resizing configuration register prz_frcfg prz + 0050h post resize y line buffer size register prz_ylbsize free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1370 of 1535 prz + 005ch post resize pixel-based resizing working memory base address prz_prwmbase 5.24.5.1 post resize configuration register prz+0000h post resize config uration register prz_cfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lbsel psel pcon pelsrc1 type r/w r/w r/w r/w reset 0 0 0 0000 the register is for global configuration of post resize. pelsrc1 the register field specifies which pixel-based image source is serviced. 1 image rotator 0 2 mpeg4 deblocking 3 ibw4 dma 5 r2y 0 6 jpeg decoder others reserved pcon the register bit specifies if pixel-based resizing continues whenever an image finishes processing. if immediate stop is desired, reset post resize directly. if the last image is desired, set the register bit to ?0? first. then wait till post resize is not busy again. finally reset post resize. 0 single run 1 continuous run psel the register field determines if block-based image sources are serviced. 0 pelsrc1 is jpeg decoder. 1 pelsrc1 is not jpeg decoder. lbsel line buffer selection. when crz_cfg.lb_sel is set to 1, this bit should not be set to 1. 0 use shared memory as temporary buffer. 1 use resz_lb (resizer dedicated line buffer) as temporary buffer. total 24kb. 5.24.5.2 post resize control register prz+0004h post resize co ntrol register prz_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pelvr rst pelhr rst blkc srst type r/w r/w r/w reset 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pelvr ena pelhr ena blkc sena type r/w r/w r/w reset 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1371 of 1535 the register is for global control of post resize. note that block-based and pixel-based resizing cannot execute parallel. furthermore, software reset will not reset all register setting. remember trigger post resize first before trigger image sources to post resize. blkcsena writing ?1? to the register bit will cause block coarse shrinking proceed to work. block coarse shrinking is designed to cooperate width jpeg decoder. it works on the fly. bu it needs to be restarted every time before working. pelhrena writing ?1? to the register bit will cause pixel-based fine horizontal resizing proceed to work. however, if horizontal resizing is not necessary, do not write ?1? to the register bit. pelvrena writing ?1? to the register bit will cause pixel-based fine vertical resizing proceed to work. however, if vertical resizing is not necessary, do not write ?1? to the register bit. blkcsrst writing ?1? to the register bit will force block coarse shrinking to stop immediately and have block coarse shrinking keep in reset state. in order to have block coarse shrinking go to normal state, writing ?0? to the register bit. pelhrrst writing ?1? to the register will cause pixel-based fine horizontal resizing to stop immediately and have pixel-based fine horizontal resizing keep in reset state. in order to have pixel-based fine horizontal resizing go to normal state, writing ?0? to the register bit. pelvrrst writing ?1? to the register will pixel-based fine vertical resizing to stop immediately and have pixel-based fine vertical resizing keep in reset state. in order to have pixel-based fine vertical resizing go to normal state, writing ?0? to the register bit. 5.24.5.3 post resize status register prz+0008h post resize status register prz_sta bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blkin trab sy pelvr busy pelhr busy blkc sbus y type ro ro ro ro reset 0 0 0 0 the register indicates global status of post resize. blkcsbusy block-based cs (coarse shrinking) busy status pelhrbusy pixel-based hr (horizontal resizing) busy status pelvrbusy pixel-based vr (vertical resizing) busy status blkintrabsy block-based cs (coarse shrinking) intra-block busy status 5.24.5.4 post resize interrupt register prz+000ch post resize inte rrupt register prz_int bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1372 of 1535 type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pelvr int pelhr int blkc sint type rc rc rc reset 0 0 0 the register shows up the interrupt status of resizer. blkcsint interrupt for blkcs (block-based coarse shrink). no matter if the register bit prz_blkcscfg.inten is enabled or not, the register bit will be active whenever blkcs completes. it could be used as software interrupt by polling the register bit. clear it by reading the register. pelhrint interrupt for pelhr (pixel-based horizontal resizing). no matter if the register bit prz_frcfg.hrinten is enabled or not, the register bit will be active whenever pelhr completes. it could be used as software interrupt by polling the register bit. clear it by reading the register. pelvrint interrupt for pelvr (pixel -based vertical resizing). no matter if the register bit prz_frcfg.vrinten is enabled or not, the register bit will be active whenever pelvr completes. it could be used as software interrupt by polling the register bit. clear it by reading the register. 5.24.5.5 post resize source image size register 1 prz+0010h post resize source im age size register 1 prz_srcsz1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hs type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ws type r/w the register specifies the size of source image after coarse shrink process. the maximum allowable size is 4095x4095 . note that for the width of source image must be multiples of 8xh max and the height of source image must be multiples of 8xv max when block coarse shrinking is involved. and even if prz is set to output to crz directly (prz_frcfg.o_crz = 1), ws and hs should be filled as block coarse shrinking result. ws the register field specifies the width of source image after coarse shrink process. 1 the width of source image after coarse shrink process is 1. 2 the width of source image is 2. ? hs the register field specifies the height of source image after coarse shrink process. 1 the height of source image after coarse shrink process is 1. 2 the height of source image after coarse shrink process is 2. ? free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1373 of 1535 5.24.5.6 post resize target image size register 1 prz+0014h post resize target image size register 1 prz_tarsz1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ht type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wt type r/w the register specifies the size of target image. the maximum allowable size is 4095x4095. wt the register field specifies the width of target image. 1 the width of target image is 1. 2 the width of target image is 2. ? ht the register field specifies the height of target image. 1 the height of target image is 1. 2 the height of target image is 2. ? 5.24.5.7 post resize horizontal ratio register 1 prz+0018h post resize horizontal ratio register prz_hratio1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ratio [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ratio [15:0] type r/w the register specifies horizontal resizing ratio. it is obtained by prz_srcsz.ws * 2 20 / prz_tarsz.wt. 5.24.5.8 post resize vertical ratio register 1 prz+001ch post resize vertical ratio register 1 prz_vratio1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ratio [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ratio [15:0] type r/w the register specifies vertical resizing ratio. it is obtained by prz_srcsz.hs * 2 20 / prz_tarsz.ht. 5.24.5.9 post resize horizontal residual register 1 prz+0020h post resize horizontal residual register 1 prz_hres1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1374 of 1535 type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name residual type r/w the register specifies horizontal residual. it is obtained by prz_srcsz.ws % prz_tarsz.wt. the maximum allowable value is 4094. 5.24.5.10 post resize vertical residual register 1 prz+0024h post resize vertical residual register 1 prz_vres1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name residual type r/w the register specifies vertical residual. it is obtained by prz_srcsz.hs % prz_tarsz.ht. the allowable maximum value is 4094. 5.24.5.11 post resize block coarse shrinking configuration register prz+0030h post resize block coarse shrinking configuration register prz_blkcscfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name inten type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vv hv vu hu vy hy csf type r/w r/w r/w r/w r/w r/w r/w reset 00 00 00 00 00 00 00 the register is for various configuration of block coarse shrinking in post resize. block coarse shrinking is dedicated for jpeg decoder. therefore all processes are based on blocks composed of 8x8 pixels. note that all parameters must be set before writing ?1? to the register bit prz_con.blkcsena . csf it stands for coarse shrink factor. the value specifies the scale factor in coarse shrink pass. 00 image size does not change after coarse shrink pass. 01 image size becomes 1/4 of original size after coarse shrink pass. 10 image size becomes 1/16 of original size after coarse shrink pass. 11 image size becomes 1/64 of original size after coarse shrink pass. hy horizontal sampling factor for y-component 00 horizontal sampling factor for y-component is 1. 01 horizontal sampling factor for y-component is 2. 10 horizontal sampling factor for y-component is 4. 11 no y-component. vy vertical sampling factor for y-component free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1375 of 1535 00 vertical sampling factor for y-component is 1. 01 vertical sampling factor for y-component is 2. 10 vertical sampling factor for y-component is 4. 11 no y-component. hu horizontal sampling factor for u-component 00 horizontal sampling factor for u-component is 1. 01 horizontal sampling factor for u-component is 2. 10 horizontal sampling factor for u-component is 4. 11 no u-component. vu vertical sampling factor for u-component 00 vertical sampling factor for u-component is 1. 01 vertical sampling factor for u-component is 2. 10 vertical sampling factor for u-component is 4. 11 no u-component. hv horizontal sampling factor for v-component 00 horizontal sampling factor for v-component is 1. 01 horizontal sampling factor for v-component is 2. 10 horizontal sampling factor for v-component is 4. 11 no v-component. vv vertical sampling factor for v-component 00 vertical sampling factor for v-component is 1. 01 vertical sampling factor for v-component is 2. 10 vertical sampling factor for v-component is 4. 11 no v-component. inten interrupt enable. when interrupt for blkcs is enabled, interrupt will arise whenever blkcs finishes. 0 interrupt for blkcs is disabled. 1 interrupt for blkcs is enabled. 5.24.5.12 post resize y-component line buffer memory b ase address register prz+0034h post resize y-component line buffer memory base address register prz_ylmbase bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ylmbase [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ylmbase [15:0] type r/w the register specifies the base address of line buffer for y-component. it must be 4 bytes-aligned. the valid address is 0x4002_0000 to 0x4004_3fff. it is only useful in block-based mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1376 of 1535 5.24.5.13 post resize u-component line buffer memory base address register prz+0038h post resize u-component line buffer memory base address register prz_ulmbase bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ulmbase [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ulmbase [15:0] type r/w the register specifies the base address of line buffer for u-component. the valid address is 0x4002_0000 to 0x4004_3fff. it is only useful in block-based mode. 5.24.5.14 post resize v-component line buffer memory b ase address register prz+003ch post resize v-component line buffer memory base address register prz_vlmbase bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vlmbase [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vlmbase [15:0] type r/w the register specifies the base address of line buffer for v-component. the valid address is 0x4002_0000 to 0x4004_3fff. it is only useful in block-based mode. 5.24.5.15 post resize fine resizing configuration register prz+0040h post resize fine resizing configuration register prz_frcfg bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wmsz type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name o_y2r 1 o_ipp 1 o_crz pcsf1 vrint en hrint en vrss type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 00 0 0 0 the register specifies various setting of control for fine resizing, including of horizontal and vertical resizing. note that all parameters must be set before horizontal and vertical resizing proceeds. vrss the register bit specifies whether subsampling for vertical resizing is enabled. for throughput issue, vertical resizing may be simplified by subsampling lines vertically. the register bit is only valid in pixel- based mode. 0 subsampling for vertical resizing is disabled. 1 subsampling for vertical resizing is enabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1377 of 1535 hrinten hr (horizontal resizing) interrupt enable. when interrupt for hr is enabled, interrupt will be issued whenever hr finishes. 0 interrupt for hr is disabled. 1 interrupt for hr is enabled. vrinten vr (vertical resizing) interrupt enable. when interrupt for vr is enabled, interrupt will be issued whenever vr finishes. 0 interrupt for vr is disabled. 1 interrupt for vr is enabled. pcsf1 coarse shrinking factor 1 for pixel-based resizing. only horizontal coarse shrinking is supported for pixel-based resizing . 00 no coarse shrinking. 01 image width becomes 1/2 of original size after coarse shrink pass. 10 image width becomes 1/4 of original size after coarse shrink pass. 11 image width becomes 1/8 of original size after coarse shrink pass. o_crz the register bit is used to select output modules. 0 disable output to crz 1 enable output to crz note: only for source 5 (jpegdec) o_ipp1 the register bit is used to select output modules. 0 disable output to ipp 1 1 enable output to ipp 1 o_y2r1 the register bit is used to select output modules. 0 disable output to y2r 1 1 enable output to y2r 1 note: if o_crz is 1, o_ipp1 and o_y2r1 are meaningless. if o_crz is 0, both could be 1. wmsz it stands for working memory size. the register specifies how many lines after horizontal resizing can be filled into working memory. its minimum value is 4. note: the total working memory used by prz = (prz_tarsz1.wt+ prz_tarsz1.wt%2) * 2 * wmsz. 5.24.5.16 post resize y line buffer size register prz+0050h post resize y line buffer size register prz_ylbsize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ylbsz type r/w the register specifies line buffer size for image data after coarse shrinking. it is only useful in block-based mode. ylbsz it stands for y-component line buffer size. the register field specifies how many lines of y- component can be filled into line buffer. line buffer size for u- and v-component can be determined free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1378 of 1535 according to the sampling factor. for example, if (v y , v u , v v )=(4,4,2) and line buffer size for y- component is 32, lines then the line buffer size for u-component is also 32 lines and v-component 16 lines. if line buffer has capacity for whole image after block coarse shrinking, then block coarse shrinking can be used for the application of scaling down by a factor of 2, or 4, or 8. if dual line buffer is used, block coarse shrinking and horizontal resizing can execute parallel. the maximum allowable value is 2048. 1 line buffer size for y-component is 1 line. 2 line buffer size for y-component is 2 lines. 3 line buffer size for y-component is 3 lines. ? 5.24.5.17 post resize pixel-based resizing working memory base address register prz+005ch post resize pixel-based resizing working memory base address register prz_prwmbase bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name prwmbase [31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prwmbase [15:0] type r/w the register specifies the base address of working memory in pixel-based resizing mode. it must be 4 bytes- aligned. the valid address is 0x4002_0000 to 0x4004_3fff when prz_cfg.lb_sel is set, this address should be set as 0x40050000. 5.24.5.18 post resize information register 0 prz+00b0h post resize inform ation register 0 prz_info0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name info[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name info[15:0] type ro the register shows progress of blkcs. but they are not real processed width/height. sampling factors must be taken into consideration. info[31:16] blkcs y info[15:00] blkcs x 5.24.5.19 post resize information register 1 prz+00b4 post resize inform ation register 1 prz_info1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name info[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1379 of 1535 name info[15:0] type ro the register shows progress of blk2pel. info[31:16] blk2pel y info[15:00] blk2pel x 5.24.5.20 post resize information register 2 prz+00b8 post resize inform ation register 2 prz_info2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name info[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name info[15:0] type ro the register shows progress of pixels received from blkcs in fine resizing stage. info[31:16] indicate the account of vertical lines received from blkcs in fine resizing stage. info[15:00] indicate the account of horizontal pixels received from blkcs in fine resizing stage. note that it will become zero when resizing completes. 5.24.5.21 post resize information register 3 prz+00bc post resize inform ation register 3 prz_info3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name info[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name info[15:0] type ro the register shows progress of horizontal resizing in fine resizing stage. info[31:16] indicate the account of horizontal resizing in fine resizing stage in horizontal direction. info[15:00] indicate the account of horizontal resizing in fine resizing stage in vertical direction. 5.24.5.22 post resize information register 4 prz+00c0 post resize inform ation register 4 prz_info4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name info[31:16] type ro bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name info[15:0] type ro the register shows progress of vertical resizing in fine resizing stage. info[31:16] indicate the account of vertical resizing in fine resizing stage in horizontal direction. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1380 of 1535 info[15:00] indicate the account of vertical resizing in fine resizing stage in vertical direction. 5.24.6 application notes z determine line buffer size by taking into consideration of csf and sampling factor. for example, if csf=3 and (vy, vu, vv)=(4,x,x) then minimum of line buffer could be 4 instead of 32. z working memory. maximum value is 16 and minimum 4. remember that each pixel occupies 2 bytes . thus minimum requirement for working memory in pixel-based resizing is (pixel number in a line) x2x4 bytes. z configuration procedure for block-based image sources prz_cfg.psel=0; prz_cfg.pelsrc = 5 ; prz_frcfg.o_crz = 1 or 0; prz_frcfg.o_ipp1 = 1 or 0; prz_frcfg.o_y2r1 = 1 or 0; prz_blkcscfg = select csf, sampling factor, interrupt enable; prz_ylbbase = memory base for y-component; prz_ulbbase = memory base for u-component; prz_vlbbase = memory base for v-component; prz_ylbsize = line buffer size for y-component; other same as that for pixel-based image sources prz_con = 0x7; // then wait interrupt or polling prz_int.blkcsint or prz_int.blkhrint or // prz_int.blkvrint z configuration procedure for pixel-based image sources prz_cfg.psel=1; prz_cfg.pelsrc = 1~4 ; prz_frcfg.o_ipp1 = 1 or 0; prz_frcfg.o_y2r1 = 1 or 0; prz_srcsz = source image size; prz_tarsz = target image size; prz_hratio = horizontal ratio; prz_vratio = vertical ratio; prz_hres = horizontal residual; prz_vres = vertical residual; prz_frcfg = working memory size, interrupt enable; prz_prwmbase = working memory base; prz_con = 0x6; // then wait interrupt or polling prz_int.pelhrint or prz_int.pelvrint free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1381 of 1535 5.25 spi interface controller 5.25.1 general description figure 145: the pin connection between spi master and spi slave. the spi interface is a bit-serial, four-pin transmission protocol. figure 145 gives an example of the connection between spi master and spi slave. in our chip, the spi interface controller is a master responsible of the data transmission with the slave. 5.25.1.1 pin description cs_n: the low active chip select signal. sck: the (bit) serial clock. mosi: the data signal from master output to slave input. miso: the data signal from slave output to master input. 5.25.1.2 transmission formats figure 146: the spi transmission formats. figure 146 gives the waveform during the spi transmission. the low active cs_n determines the start point and end point of one transaction. the cs_n setup time, hold time, and idle time are also depicted. the cpol defines the clock polarity in the transmission. two kinds of polarity can be adopted, i.e. polarity 0 and polarity 1. figure 146 gives both of the clock polarity (cpol) as examples. the cpha defines the legal timing to sample mosi and miso. two different ways can be adopted. 5.25.2 features of the spi interface controller the features of the spi controller (master) are summarized below: free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1382 of 1535 1. the configurable cs_n setup time, hold time, and idle time. 2. the programmable sck high time and low time. 3. the configurable transmitting and receiving bit order. 4. two modes of the source of the data being transmitted can be configured. in tx dma mode, the spi controller will automatically fetch the transmitted data (to be put on the mosi line) from memory. in tx fifo mode, the data to be transmitted on the mosi line shall be written to the fifo before start of the transaction. 5. two modes of the destination of the data being received can be configured. in rx dma mode, the spi controller will automatically store the receiving data (from miso line) to memory. in rx fifo mode, the receiving data will just keep in the rx fifo of the spi controller. the processor must read back these data by itself. 6. the programmable byte length of transmission. 7. un-limited length of transmission. this is achieved by the operation of the pause mode. in pause mode, the cs_n signal keeps active (low) after the transmission. at this time, the spi controller is in pause_idle state, ready to receive the resume command. the state transition is shown in figure 147. figure 147: the operation flow with or without pause mode. 5.25.3 the spi configuration register register address register function acronym spi + 0000h spi configuration 0 register spi_cfg0 spi + 0004h spi configuration 1 register spi_cfg1 spi + 0008h spi tx source address register spi_tx_src spi + 000ch spi rx destination address register spi_rx_dst spi + 0010h spi tx data fifo spi_tx_data spi + 0014h spi rx data fifo spi_rx_data spi + 0018h spi command register spi_cmd spi + 001ch spi status 0 register spi_status0 spi + 0020h spi status 1 register spi_status1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1383 of 1535 table 120 the spi registers 5.25.4 register definition spi+0000h spi configuration 0 register spi_cfg0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cs_setup_count[7:0] cs_hold_count[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name sck_low_count[7:0] sck_high_count[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cs_setup_count[7:0] the chip select setup time = (cs_setup_count+1) * clk_period, where clk_period is the cycle time of the clock the spi engine adopts. cs_hold_count[7:0] the chip select hold time = (cs_hold_count+1) * clk_period. sck_low_count[7:0] the sck clock low time = (sck_low_count+1) * clk_period. sck_high_count[7:0] the sck clock high time = (sck_high_count+1) * clk_period. spi+0004h spi configuration 1 register spi_cfg1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name packet_length[9:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name packet_loop_cnt[7:0] cs_idle_count[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 packet_length[9:0], packet_loop_cnt[7:0] the transmission on the spi bus consists up units bytes. hence, the packet_length[9:0] define number of bytes in one packet, and packet_loop_cnt[7:0] defines the number of packets within one transaction. the number of bytes in one packet = packet_length + 1. the number of packets in one transaction = packet_loop_cnt + 1. total bytes of one transaction = (packet_length + 1) * (packet_loop_cnt + 1). cs_idle_count[7:0] the chip select idle time between consecutive transaction = (cs_hold_count+1) * clk_period. spi+0008h spi tx source address register spi_tx_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name spi_tx_src[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name spi_tx_src[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1384 of 1535 spi_tx_src[31:0] if tx_dma_en is set, the data to be putted on the mosi line are kept in memory in advance, and the spi controller will automatically read the data from memory. the spi_tx_src define the memory address from which spi controller starts to read data. spi+000ch spi rx destination address register spi_rx_dst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name spi_rx_dst[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name spi_rx_dst[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spi_rx_dst[31:0] if rx_dma_en is set, the received data from the miso line will be move to memory automatically by the spi controller. the spi_rx_dst define the memory address to which the spi controller starts to store the data. spi+0010h spi tx data fifo spi_tx_data bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name spi_tx_data[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name spi_tx_data[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spi_tx_data[31:0] the depth of the tx fifo is 32-bytes. write to this register will write 4 bytes to the tx fifo. the tx fifo pointer will automatically move toward the next four bytes. read from this register will read 4 bytes from the fifo, and the tx fifo pointer automatically moves toward the next four bytes. spi+0014h spi rx data fifo spi_rx_data bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name spi_rx_data[31:16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name spi_rx_data[15:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spi_rx_data[31:0] the depth of the rx fifo is 32-bytes. read from this register will read 4 bytes from the rx fifo. the rx fifo pointer will automatically move toward the next four bytes. write to this register will write 4 bytes to the fifo, and the rx fifo pointer automatically moves toward the next four bytes. spi_0018h spi command register spi_cmd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name paus e_ie finish _ie type r/w r/w reset 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1385 of 1535 name rxms bf txms bf tx_dm a_en rx_d ma_e n cpol cpha paus e_en reset resu me cmd_ act type r/w r/w r/w r/w r/w r/w r/w wo wo wo reset 0 0 0 0 0 0 0 0 0 0 pause_ie the interrupt enable bit of pause flag in spi status register. finish_ie the interrupt enable bit of finish flag in spi status register. rxmsbf indicate the data received from miso line is msb first or not. set rxmsbf to 1 for msb first, otherwise set it to 0. txmsbf indicate the data sent on mosi line is msb first or not. set txmsbf to 1 for msb first, otherwise set it to 0. tx_dma_en this bit is the dma mode enable bit of the data to be transmitted. default (0) is not to enable. rx_dma_en this bit is the dma mode enable bit of the data being received. cpol this bit is the control bit of the sck polarity. 0 is cpol = 0, 1 is cpol = 1. cpha this bit defines the spi clock format 0 or spi clock format 1 during transmission. 0 is cpha = 0, 1 is cpha = 1. pause_en this bit is the enable bit of the pause mode. set 1 to enable this mode. reset the software reset bit. resume this bit is used when controller is in pause idle state. write 1 to this bit triggers the spi controller resume transfer from pause idle state. cmd_act the command activate bit. write 1 to this bit triggers the spi controller starts the transaction. spi_001ch spi status 0 register spi_status0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name paus e finish type rc rc reset 0 0 finish the interrupt status bit in non-pause mode. it will be set by the spi controller when it completes the transaction, entering the idle state. pause the interrupt status bit in pause mode. it will be set by the spi controller when it completes the transaction, entering the pause idle state. spi_0020h spi status 1 register spi_status1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name busy type ro reset free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1386 of 1535 busy this status flag reflects the spi controller is busy or not. this bit is low active, i.e. 0 represents the spi controller is busy now. 5.26 tv controller 5.26.1 general description the tv output design can support ntsc/pal interlaced tv format. the display function includes two components: a tv controller and a tv encoder. the main functions of the tv controller are as follows: 1. fetch the tv frame buffer. ? in video playback mode , the source is from the video codec buffer in yuv420 format. in this mode, the tv controller and mpeg4 or h.264 decoder can also communicate to achieve the best performance. see fig. 25. ? in image playback mode , the source is in rgb565 format. in this mode, still images can be displayed. the lcm controller can direct the image path to the tv controller. when the lcm controller sends frames to the frame buffer as it does for the lcd display, the tv controller retrieves the frames for display. see fig. 25. 2. scale the frame size to fit the tv size. this tv design adopts bilinear interpolation in both horizontal and vertical dimension to scale up the frame. the user can adjust both the location and the size to achieve a suitable appearance. in ntsc mode, the ideal display area is 720(w) x 480(h), but the actual display area depends on the tv set. some boundary area may be invisible. in pal mode, the ideal display area is 720(w) x 576(h); the actual display area also depends on the tv set. tv frame updates consume a lot of bandwidth. for interlaced system, one frame contains 2 fields. in ntsc mode, the field update rate is 59.94 frames per second (fps); the field update rate in pal mode is 50 fps. performance is bound by the size of the source image. the larger the image size, the higher the bandwidth required to support the tv display. the controller supports an arbitrary image size up to 640 pixels in height and 480 pixels in width. fig. 29 . depicts the block diagram of the tv controller. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1387 of 1535 video dma gmc bus video scaler tv encoder tv controller apb bus 10 bit video dac ycbcr422 ycbcr420 or rgb565 fig. 29 block diagram of the tv encoder 5.26.2 pre-fetch dma description the dedicated and specified pre-fetch dma for tv is implemented to improve the critical bandwidth problem of tv. with enabling pre-fetch dma, tv can use the shared internal memory as tv?s line buffer. the number of buffer can be programmed but must be the multiple of 4 lines. in order to meet 4-beat burst access, the additional 16 dummy bytes memory size must be kept for every component pr-fetch buffer for burst mode memory access and vertical interpolation must be enabled. the main functions of tv pre-fetch dma are as shown in fig. 30 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1388 of 1535 tvc_prefetch dma ext_mem int_mem rd/wr buf tvc_dmaif fifo_valid tvc tv_addr_src tv_pfh_dma_addr_src fig. 30 pre-fetch dma block diagram with tvc. fig. 25 (a) rgb565/yuv420 sequential format, (b) yuv420 4x4-block format. 5.26.3 special register setting in order to simplify the address generation of tv controller, some special setting for the address generation needed to be programmed before enabling tv design. the line offset defines the offset byte size from the starting point of every line. the tv design will base on this setting and starting address to decide how to jump to the staring address of the next line, as shown in fig. 32. the start/stop pint register can set the final display range in tv device. with the different range setting, the partial or complete video appearance will be displayed in tv device, as shown in fig. 33. 1 2 3 4 5 yuv420-4x4blk 1 2 3 4 5 rgb565/yuv420-pixel free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1389 of 1535 1. yuv420 mode line offset =(srcwidth) bytes 2. rgb565 mode line o ffset =2x(sr c w id th ) bytes rgb565 source data srcheight srcwidth y source data srcwidth srcheight u source data v source data srcheight/2 srcwidth/2 start_addr line offset fig. 32 the line offset setting in tv address generation. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1390 of 1535 tv field tv field width tv field height active display appearance 45"35@19- 4501@19- start_line stop_line video width (video height/2) fig. 33 display range setting. 5.26.4 register definitions register address register function acronym tvc + 0000h tvc enable register tvc_ena tvc + 0004h tvc reset control register tvc_rstb tvc + 0008h tvc control register tvc_con tvc + 000ch tvc y data source address register tvc_yadr_src tvc + 0010h tvc u data source address register tvc_uadr_src tvc + 0014h tvc v data source address register tvc_vadr_src tvc + 0018h tvc data source line offset register tvc_line_offset tvc + 001ch tvc horizontal scaling coefficient register tvc_hcoef tvc + 0020h tvc vertical scaling coefficient register tvc_vcoef tvc + 0024h tvc frame source width control register tvc_srcwidth tvc + 0028h tvc frame source height control register tvc_srcheight tvc + 002ch tvc frame target width control register tvc_tarwidth tvc + 0030h tvc frame target height control register tvc_tarheight tvc + 0034h tvc start point control register 0-3 register tvc_start_point tvc + 0038h tvc stop point control register tvc_stop_point free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1391 of 1535 tvc + 003ch tvc pre-fetch dma y data source address tvc_pfh_dma_yadr_src tvc + 0040h tvc pre-fetch dma u data source address tvc_pfh_dma_uadr_src tvc + 0044h tvc pre-fetch dma v data source address tvc_pfh_dma_vadr_src tvc + 0048h tvc pre-fetch dma data source line offset register tvc_pfh_dma_ line_offset tvc + 004ch tvc pre-fetch dma fifo length register tvc_pfh_dma _fifo_length tvc + 0050h tvc check line register register tvc_check_point tvc + 0054h tvc register update control register tvc_reg_rdy tvc + 0058h tvc vertical average coefficient register tvc_avg_coeff tvc + 005ch tvc background color register tvc_background_color tvc + 0060h tvc slow control register tvc_slow_ctrl tvc + 0070h tvc status register tvc_satus tvc + 0074h tvc over-run status register tvc_ovr_satus tvc + 0080h tvc current read data value register tvc_rd_data_sts tvc + 0084h tvc current read address register tvc_rd_addr_sts tvc + 0088h tvc dac accumulator value register tvc_dac_acc_value table 121 tv controller register tvc+0000h tvc enable register tvc_ena bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tven type r/w reset 0 the register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. tven tv controller enable. 0 disable the tv frame update and display. 1 enable the tv frame update and display. tvc+0004h tvc reset control register tvc_rstb bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type r/w reset 1 the register is used to reset both the tv controller and the tv encoder and needs to re-write to 1 if finishing reset . this control bit is read/write. rstb low-active reset control bit. tvc+0008h tvc control register tvc_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1392 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name chk_e n ovr_e n clip avg ab_w r ab_r d pfh tv_bu sy burs t high_ pri noip data_fmt type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 this register contains double buffer control, burst-mode control, buffer configuration, vertical interpolation control, and color-space control. chk_en check line interrupt enable. (when tv_line hit the check line setting, the interrupt is asserted.) cvr_en line buffer over run interrupt enable. (when tv line buffer is over-run, the interrupt is asserted.) clip clip mode enable for over-run condition. (in buffer-over-run condition, tv will read less data.) avg average mode enable. if no vertical resizing, enable this bit can improve flicker but need to suitable average coefficients. ab_wr double buffer access control. 0 write write-buffer. the active-buffer will be written at the specified time by hardware. 1 write both write-buffer and active-buffer. the active-buffer and the write-buffer will be written directly. ab_rd double buffer access control. 0 read write-buffer. 1 read active-buffer. pfh pre-fetch access mode enable. please reference fig. 30 . double buffer. 0 disable pfh dma mode. 1 enable pfh dma mode(vertical interpolation must be enabled). tv_busy enable frame sync handshaking between tv and video codec. 0 disable. 1 enable. burst burst mode for memory read access enable. in order to gain better performance, burst mode is necessary. 0 disable 1 enable. high_pri memory access high priority enable. 0 disable 1 enable. noip bypass vertical interpolation. enabling this bit reduces the average data access bandwidth by 2. double buffer. 0 enable vertical interpolation. 1 bypass vertical interpolation. data_fmt tv source data format. double buffer. 0 rgb565. for lcd frame buffer. 1 reserved. 2 yuv420 sequential mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1393 of 1535 3 yuv420 4x4-block mode. tvc+000ch tvc y data source address register tvc_yadr_sr c bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_y [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_y [15:2] type r/w ro ro reset 0 0 0 src_y address of rgb565 or y source data. this register is a double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the y source address and must be word-align address . in rgb mode, the register represents the rgb source address. tvc+0010h tvc u data source address register tvc_uadr_sr c bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_u [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_u [15:2] type r/w ro ro reset 0 0 0 src_u address of u source data. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the u source address and must be word-align address . in rgb565 mode, this register has no function. tvc+0014h tvc v data source address register tvc_vadr_sr c bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name src_v [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name src_v [15:2] type r/w ro ro reset 0 0 0 src_v address of v source data. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the v source address and must be word-align address . in rgb565 mode, this register has no function. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1394 of 1535 tvc+0018h tvc data source line offset register tvc_line_off set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tv_line_buf_limit [3:0] type r/w reset 4?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tvc_lineoffset[11:2] type r/w ro ro reset 0 0 0 tvc_lineoffset this register is double buffer. this register can define the byte size (but must be multiple of 4) of one source line in the memory without respecting to the source width of video. normally, the line offset is ) 2 ( h sourcewidt for rgb565 mode or ) ( h sourcewidt for yuv420 mode. in yuv420 mode, the u/v line offset will be half of the programmed line offset. in pre-fetch mode, it can limit the pre-fetch line buffer size. tv_line_buf_limit this register can define the bus priority condition. when the number of tv line buffer that had been filled is not larger than tv_line_buf_limit, the high-priority request will be send to bus and then the request of tv can set the top priority to avoid the buffer-under-run in tv( bus_pri need to be enable ). tvc+001ch tvc horizontal scaling coefficient register tvc_hcoef bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name hcoefy type r/w reset 10?d222 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hcoefx type r/w reset 10?d62 hcoeffx horizontal scaling factor (x) . hcoeffy residue value of horizontal scaling (y). this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. the scaling coefficients should follow the formula: (only support enlarging function) , 256 1 1 ) arg ( 1 ) ( ? + = ? ? wt y x width et t wt width source ws where x, y are positive integers, and 0 < y < w t ? 1. for example, if the user needs to scale the image width from 640 pixels to 720 pixels, the formula is: 256 719 371 227 719 639 + = , values x=227 and y=371 should be programmed. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1395 of 1535 tvc+0020h tvc vertical scaling coefficient register tvc_vcoef bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vcoefy type r/w reset 10?d204 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vcoefx type r/w reset 10?d76 vcoeffx vertical scaling factor (x) . vcoeffy residue value of vertical scaling (y). this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. the scaling coefficients should follow the formula: (only support enlarging function) teger in positive y x ht y x height etn t ht height source hs , , 256 1 1 ) arg ( 1 ) ( ? + = ? ? tvc+0024h tvc frame source width control register tvc_srcwidt h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srcwidth type r/w reset 10?d176 srcwidth image/video source width. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the source width must be the multiple of 16; in rgb565 mode, the source width must be a multiple of 2 and less than 720. tvc+0028 tvc frame source height control register tvc_srcheig ht bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name srcheight type r/w reset 10?d144 srcheight image/video source height. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in order to meet ntsc/pal interlaced tv system, the source height must be the multiple of 2 and less than 480(ntsc) or 576(pal). tvc+002c tvc frame target width control register tvc_tarwidt h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1396 of 1535 name tarwidth type r/w reset 10?d640 tarwidth image/video target width. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in order to meet ntsc/pal interlaced and ycbcr422 tv system, the target width must be the multiple of 2 and less than 720. tvc+0030 tvc frame target height control register tvc_tarheig ht bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tarheight type r/w reset 10?d480 tarheight image/video target height. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in order to meet ntsc/pal interlaced tv system, the target width must be less than 480(ntsc) or 576(pal). tvc+0034h tvc start point control register tvc_start_p oint bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name start_pxl type r/w reset 10?d0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name start_line type r/w reset 10?d21 this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. this register is used to control the position of frame displayed on tv. setting start_pxl to 0 and start_line to 21(ntsc) or 22(pal) aligns the frame to the top-left corner of display. please reference fig. 33 . start_pxl starting pixel position in a line. start_line starting line of display. tvc+0038h tvc stop point control register tvc_stop_poi nt bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name stop_pxl type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1397 of 1535 name stop_line type r/w reset 0 this register is to define the number of displayed pixels and lines every field in tv. at the start of each frame, the enable bit is latched into the active buffer and takes effect. please reference fig. 33 . this register is used to control the display range of field displayed on tv. setting stop_pxl to the value of (target width + start_pixel) and stop_line to the ((target_height/2) + start_line) can display the complete frame of video. stop_pxl starting pixel position in a line. stop_line starting line of display field. tvc+003ch tvc pre-fetch dma y data source address tvc_pfh_dma _yadr_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pfh_dma_src_y [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pfh_dma_src_y [15:2] type r/w ro ro reset 0 0 0 pfh_dma_src_y address of pre-fetch dma?s line buffer for rgb565/y data. this register is a double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the y source address and must be in internal memory and word-align address . in rgb mode, the register represents the rgb source address. please reference fig. 30. tvc+0040h tvc pre-fetch dma u data source address tvc_pfh_dma _uadr_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pfh_dma_src_u [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pfh_dma_src_u [15:2] type r/w ro ro reset 0 0 0 pfh_dma_src_u address of pre-fetch dma?s line buffer for u data. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the u source address and must be in internal memory and word-align address . in rgb mode, this register has no function. please reference fig. 30 . tvc+0044h tvc pre-fetch dma v data source address tvc_pfh_dma _vadr_src bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1398 of 1535 name pfh_dma_src_v [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pfh_dma_src_v [15:2] type r/w ro ro reset 0 0 0 pfh_dma_src_v address of pre-fetch dma?s line buffer for v data. this register is double buffer. at the start of each frame, the enable bit is latched into the active buffer and takes effect. in yuv mode, the register represents the v source address and must be in internal memory and word-align address . in rgb mode, this register has no function. please reference fig. 30 . tvc+0048h tvc pre-fetch dma data source line offset register tvc_pfh_dma _line_offset bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tvc_pfh_dma_line_offset[11:2] type r/w ro ro reset 0 0 0 tvc_pfh_dma_line_offset this register is double buffer. this register can define the byte size of one source image?s line (the setting must be multiple of 16. if not, extend the byte size setting to the multiple of 16.) in yuv mode, the u/v line offset will be half of the programmed offset address. tvc+004ch tvc pre-fetch dma fifo length register tvc_pfh_dma _fifo_length bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fifo_length[6:0] type r/w reset 0 fifo_length this register is double buffer. this register can define the fifo length in internal fast memory (define by tvc_y/u/vadr_src). the fifo length must be the multiple of 4 and minimum number is 8. that means we must define the multiple of 4 lines if we want to enable this function to speed up tv output design. tvc+0050h tvc check line register tvc_check_p oint bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tv_check_line2[9:0] type r/w reset 10?h480 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1399 of 1535 name tv_check_line1[9:0] type r/w reset 10?h160 this register is double buffer. this register can set one checking point. when tv line reaches this point, the interrupt of tvc will be asserted if int_en has been set to 1. tv_check_line1 tv check points for even field tv_check_line2 tv check points for odd field tvc+0054h tvc register update control register tvc_reg_rdy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name reg_ rdy type r/w reset 0 this register indicates that the double buffer register data is ready to be latched into active buffer. at the start of each frame, the hardware monitors the bit. if the bit is set to 1 by the software, the double buffer register is latched into active buffer synchronously, and the reg_rdy bit is automatically cleared. reg_rdy double buffer control bit. tvc+0058h tvc vertical average coefficient register tvc_avg_coe ff bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name coeff2[8:0] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name coeff1[8:0] type r/w reset 9?h100 this register can define the average coefficient if neighboring vertical line average is necessary to improve the flicker. coeff1 ratio for the current line(9?h100 is 100%). coeff2 ratio for the neighboring (last) line (9?h0 is 0%) tvc+005ch tvc background color register tvc_backgr ound_color bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name u_color[7:0] type r/w reset 8?h80 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name v_color[7:0] y_color[7:0] type r/w r/w reset 8?h80 8?h0 y_color this register defines the luminance(y) value of tv?s background. u_color this register defines the chrominance (u) value of tv?s background free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1400 of 1535 v_color this register defines the chrominance (v) value of tv?s background tvc+0060h tvc slow control register tvc_slow_c trl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clip_fetch_num[3:0] clip_buf_high_num[3:0] clip_buf_low_num[3:0] type r/w r/w r/w reset 4?h2 4?h5 4?h4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clip_srcwidth[9:0] type r/w reset 10?d176 clip_srcwidt this register defines the clipping source width when tvc?s buffer is over-run. clip_buf_low_num this register defines the trigged condition for clipping.(tv_buffer_cnt <= this setting) clip_buf_high_num this register defines the disabled condition for clipping.(tv_buffer_cnt > this setting) clip_fetch_line_num this register defines the trigged condition for clipping.(tv_fetch_line <= this setting) tvc+0070h tvc status register tvc_satus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name chk_ir q ovr_i rq clip h_pri tv_bu sy field tv_line type r/w r/w ro ro ro ro ro reset 1 1 0 0 0 0 10?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tvc_dmaif_state hs_buf_cnt tv_lb_cnt type ro ro ro reset 3?h0 3?h0 4?h0 tv_lb_cnt number of line buffer that has been fetch data in(max number is 8). hs_buf_cnt number of working buffer that has been fetch data in(max number is 4). tvc_dmaif_state tvc dma interface state machine 0 idle 1 odd_field_init 2 check_line_req 3 init_vsca_ptr 4 init_hs 5 wait_empty 6 wait_line_ok tv_line index of tv line that displays now. field index of tv field that displays now( 0:even field; 1: odd field). tv_busy tv busy has been asserted and stalls video decoding. h_pri high primary bus access request has been asserted. clip clip function is working. ovr_irq tvc over-run interrupt status report. if tvc?s interrupt has been asserted, the status will be set to 0. after reading this status, it must be set to 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1401 of 1535 chk_irq tvc check line interrupt status report. if tvc?s interrupt has been asserted, the status will be set to 0. after reading this status, it must be set to 1. tvc+0074h tvc over-run status register tvc_ovr_sat us bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ovr_line_cnt [9:0] type ro reset 10?h0 ovr_line_cnt number of line over-run in one field. tvc+0080h tvc current read data status register tvc_rd_data _sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rd_data [31:16] type ro reset 16?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rd_data [15:0] type ro reset 16?h0 rd_data value of tv read data from tv source buffer ( tvc_yadr_src, tvc_uadr_src, tvc_uadr_src ). tvc+0084h tvc current read address status register tvc_rd_addr _sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rd_addr [31:16] type ro reset 16?h0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rd_addr [15:0] type ro reset 16?h0 rd_addr current address that is read by tv ( tvc_yadr_src, tvc_uadr_src, tvc_uadr_src ). tvc+0088h tvc dac accumulator value register tvc_dac_acc _value bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tvc_dac_acc_value [31:16] type ro reset 16?h0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1402 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tvc_dac_acc_value [15:0] type ro reset 16?h0 tvc_dac_acc_value accumulated dac output value until tv line = check line 5.27 tv encoder 5.27.1 general description tv encoder receives a ycbcr stream from the video scaler and encodes the stream into ntsc/pal signal. fig. 34 shows the block diagram of the tv encoder. video dma gmc bus video scaler tv encoder tv controller apb bus 10 bit video dac ycbcr422 ycbcr420 or rgb565 fig. 34 block diagram of tv encoder 5.27.2 register definitions register address register function acronym tve + 0000h tv encoder encode mode control register tve_mode tve + 0004h tv encoder scale control register tve_cscale tve + 0008h tv encoder dac control register tve_dactrl tve + 000ch tv encoder burst level control register tve_burst tve + 0010h tv encoder color frequency control register tve_freq tve + 0014h tv encoder slew control register tve_slew tve + 0028h tv encoder luma low-pass filter coefficients 10-11 register tve_ylpf tve + 002ch tv encoder luma low-pass filter coefficients 12- 15 register tve_ylpfd tve + 0030h tv encoder luma low-pass filter coefficients 16- tve_ylpfe free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1403 of 1535 19 register tve + 0034h tv encoder chrominance low-pass filter coefficients 0-3 register tve_clpfa tve + 0038h tv encoder chrominance low-pass filter coefficients 4-7 register tve_clpfb tve + 003ch tv encoder chrominance low-pass filter coefficients 8-9 register tve_clpfc tve + 0040h tv encoder gamma correction coefficient 0 register tve_gammaa tve + 0044h tv encoder gamma correction coefficients 1-2 register tve_gammab tve + 0048h tv encoder gamma correction coefficients 3-4 register tve_gammac tve + 004ch tv encoder gamma correction coefficients 5-6 register tve_gammad tve + 0050h tv encoder gamma correction coefficients 7-8 register tve_gammae tve + 0054h tv encoder burst level control register tve_dactrl tve + 0060h tv encoder software reset control register tve_rstb tve + 0070h tv encoder plug-in/out control register tve_plug tve + 0074h tv encoder interrupt enable register tve_intren tve + 0078h tv encoder interrupt status register tve_intr_status tve + 007ch tv encoder plug detection value register tve_plug_value tve + 0080h tv encoder plug detection line timing register tve_plug_line tve + 0084h tv encoder plug detection pixel timing register tve_plug_pxl table 122 tv encoder register tve+0000h encoder mode control register tve_mode bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name tvtype type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name uvsw p blke r sloff sydel ydel cupo f ylpo n clpo n clpse l setup cbon enco n type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 tvtype tv type. 00 ntsc (525 lines, no phase alternation line) 01 pal-m (525 lines, with phase alternation line) 10 pal-c (625 lines, with phase alternation line) 11 pal (625 lines, with phase alternation line) uvswp u/v swap. blker blacker than black mode on. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1404 of 1535 sloff slew at the beginning and at the end of the horizontal active area off. sydel delay of y (half sample resolution). ydel delay of y (one sample resolution). (recommended setting is 2.) cupof chrominance (chroma) of component up-sample off. ylpon luminance (luma) low-pass filter on. (recommended setting is 1.) clpon chroma low-pass filter on. (recommended setting is 1.) clpsel chroma low-pass filter coefficient selection. setup 7.5ire setup enable. (m) ntsc and (m, n) pal have a blanking pedestal. cbon enable the color bar. encon enable the tv encoder. tve+0004h scale control register tve_cscale bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name blank type r/w reset 0x4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vscale uscale type r/w r/w reset 0x5a (90) 0x5a (90) uscale scale of u (uscale/128). uscale u u new ? = vscale scale of v (vscale/128). vscale v v new ? = blank luma data at this level (blankx4) is presented as blank. this blacker function must be enabled. tve+0008h dac control register tve_dactrl bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rg_c kb_en rg_c k_src test_ana[3:0] trim type r/w r/w r/w r/w reset 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name blac ker test_ comp _en vplugref plug_ det_e n pdn_h aibias pdn_d ac2 pdn_d ac1 pdn_d ac0 pdn_b gref dac_ en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 1 rg_ckb_en enable 27mhz inverse clock source 0 disable. 1 enable. rg_ck_src tvdac clock source select 0 tve clock used 1 tvpll generated clock test_ana . plug-in threshold level selection trim trimming code for bgvref. blacker blank luma data adjustment enable. 0 disable. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1405 of 1535 1 enable test_comp_en comparator test enable. 0 disable. 1 enable. vplugref plug-in detect threshold selection. plug_det_en plug-in/out detect enable. (must enable plug-in or plug-out interrupt) 0 disable. 1 enable. pdn_haibias half bias current power down mode. 0 power down. 1 power up. pdn_dac2 dac current is ref dac i i 8 7 = enable control. 0 power down. 1 power up. pdn_dac1 dac current is ref dac i i 4 3 = enable control. 0 power down. 1 power up. pdn_dac0 dac current is ref dac i i 2 1 = enable control. 0 power down. 1 power up. pdn_bgref bgvref power down control. 0 power down. 1 power up. dac_en dac enable. tve+000ch burst level control register tve_burst bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name upqini type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name brstlvl type r/w reset 0x3a (58) upqini phase offset of the color burst. brstlvl color burst level. tve+0010h color frequency control register tve_freq bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bfp2 type r/w reset 0xdd0 (3536) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1406 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bfp1 type r/w reset 0x10f (271) burst frequency control. 2048 4 625 2 1 7mhz 2 h x bfp bfp frequency burst + + = , where h is the pixel clock cycle number per line. use the following table to get bfp1 and bfp2 (in decimal). tv type h x bfp1 bfp2 ntsc 1716 0 271 3536 pal 1728 67 336 2061 bfp2 color burst frequency synthesis value 2. bfp1 color burst frequency synthesis value 1. tve+0014h slew control register tve_slew bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name slewup type r/w reset 0xc8 (200) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name slewdn type r/w reset 0x6a4 (1700) slewup begin cycle of valid pixel with slew rate control. slewdn end cycle of valid pixel with slew rate control. tve+0028h luma low-pass filter coe fficients 10-11 register tve_ylpfc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ylpf11 ylpf10 type r/w r/w reset 0x32 (-14) 0x2 (2) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type reset ylpf11 luma low-pass filter coefficient 11. signed integer. ylpf10 luma low-pass filter coefficient 10. signed integer. tve+002ch luma low-pass filter coe fficients 12-15 register tve_ylpfd bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ylpf15 ylpf14 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1407 of 1535 type r/w r/w reset 0x2 (2) 0x1e (30) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ylpf13 ylpf12 type r/w r/w reset 0x3d (-3) 0x25 (-27) ylpf15 luma low-pass filter coefficient 15. signed integer. ylpf14 luma low-pass filter coefficient 14. signed integer. ylpf13 luma low-pass filter coefficient 13. signed integer. ylpf12 luma low-pass filter coefficient 12. signed integer. tve+0030h luma low-pass filter coe fficients 16-19 register tve_ylpfe bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ylpf19 ylpf18 type r/w r/w reset 0x90 (144) 0xb4 (180) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ylpf17 ylpf16 type r/w r/w reset 0xff (-1) 0xc7 (-57) ylpf19 luma low-pass filter coefficient 19. must be unsigned. hardware extends to 9 bits. ylpf18 luma low-pass filter coefficient 18. must be unsigned. hardware extends to 9 bits. ylpf17 luma low-pass filter coefficient 17. signed integer. ylpf16 luma low-pass filter coefficient 16. signed integer. tve+0034h chrominance low-pass filter co efficients 0-3 register tve_clpfa bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clpf3 clpf2 type r/w r/w reset 0x18 0xd bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clpf1 clpf0 type r/w r/w reset 0x10 0x1 clpf3 chrominance low-pass filter coefficient 3. clpf2 chrominance low-pass filter coefficient 2. clpf1 chrominance low-pass filter coefficient 1. clpf0 chrominance low-pass filter coefficient 0. tve+0038h chrominance low-pass filter co efficients 4-7 register tve_clpfb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name clpf7 clpf6 type r/w r/w reset 0x25 0x34 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clpf5 clpf4 type r/w r/w reset 0x20 0x21 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1408 of 1535 clpf7 chrominance low-pass filter coefficient 7. clpf6 chrominance low-pass filter coefficient 6. clpf5 chrominance low-pass filter coefficient 5. clpf4 chrominance low-pass filter coefficient 4. tve+003ch chrominance low-pass filter co efficients 8-9 register tve_clpfc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clpf9 clpf8 type r/w r/w reset 0x27 0x3c clpf9 chrominance low-pass filter coefficient 9. clpf8 chrominance low-pass filter coefficient 8. tve+0040h gamma correction coeffi cient 0 register tve_gammaa bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma0 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type reset gamma0~gamma8 indicate the turning points of a piecewise linear approximation for a gamma curve. by default, the values form a perfect linear equation with no gamma correction. gamma correction is performed on luma only. gamma0 gamma1 gamma2 gamma3 gamma8 gamma4 gamma5 gamma6 gamma7 gamma0 gamma correction coefficient 0. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1409 of 1535 tve+0044h gamma correction coeffici ents 1-2 register tve_gammab bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma2 type r/w reset 0x314 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gamma1 type r/w reset 0x18a gamma2 gamma correction coefficient 2. gamma1 gamma correction coefficient 1. tve+0048h gamma correction coeffici ents 3-4 register tve_gammac bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma4 type r/w reset 0x629 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gamma3 type r/w reset 0x49e gamma4 gamma correction coefficient 4. gamma3 gamma correction coefficient 3. tve+004ch gamma correction coeffici ents 5-6 register tve_gammad bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma6 type r/w reset 0x93d bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gamma5 type r/w reset 0x7b3 gamma6 gamma correction coefficient 6. gamma5 gamma correction coefficient 5. tve+0050h gamma correction coefficients 7-8 register tve_gammae bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gamma8 type r/w reset 0xc52 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gamma7 type r/w reset 0xac8 gamma8 gamma correction coefficient 8. gamma7 gamma correction coefficient 7. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1410 of 1535 tve+0060h software reset control register tve_rstb bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rstb type r/w reset 1 rstb set to 0 to reset thetv encoder. and set to 1 to finish the reset process tve+0070h tv encoder dac plug-in/o ut status register tve_plug bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name comp ress type ro reset 0 compress tvdac sense plug-in or plug-out. this bit is valid in the plug-detection period. 0 plug-out 1 plug-in tve+0074h tv encoder interrupt enable register tve_intren bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name plug_ out_d et plug _in_d et type r/wr/w reset 0 0 plug_out_det set to 1 to enable plug-out detection process and enable plug-out interrupt. (plug-in detection must be disabled) plug_in_det set to 1 to enable plug-in detection process and enable plug-in interrupt. (plug-out detection must be disabled) tve+0078h tv encoder interrupt status register tve_intr_sts bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1411 of 1535 name plug_ out plug _ in type r/w r/w reset 0 0 plug_out 1 indicate tv cable is plug-out and will assert tve?s interrupt. after finishing plug-out detection status reading, write 0 in this bit to clear the old status. plug_in 1 indicate tv cable is plug-in and will assert tve?s interrupt. after finishing plug-in detection status reading, write 0 in this bit to clear the old status. tve+007ch tv encoder plug detection value register tve_plug_va lue bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name plug_value[11:0] type r/w reset 12?hfff plug_value digital code that tv encoder will send to tvdac in plug detection period. please see fig. 35 . tve+0080h tv encoder plug detection line timing register tve_plug_lin e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name plug_line[9:0] type r/w reset 10?d11 plug_line line count is used for plug detection. this line should be selected the dummy line in tv display and we suggest 10?d11. please see fig. 35 . tve+0084h tv encoder plug detection pixel timing register tve_plug_px l bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name plug_end_pxl[10:0] type r/w reset 11?d426 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name plug_start_pxl[10:0] type r/w reset 11?d326 plug_end_pxl in this ending pixel count, plug detection will finish. (should be >11?d230) plug_start_pxl in this starting pixel count, plug detection will start. (should be >11?d1700) please see fig. 35 . free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1412 of 1535 don't care (n-1) (n) (n+1) tv_line[9:0] 0 1 2 nn start pxl end pxl nnnn n 0 1 2 nn start pxl end pxl nnnn n 0 1 2 nn start pxl end pxl nnnn n tv_pxl[9:0] dac_in[11:0] plug_value = 12'hfff tve_irq compress don't care irq_clr cable plug-out fig. 35 plug detection setting. 5.28 wavetable synthesizer 5.28.1 general descriptions wavetable synthesizer is an mcu coprocessor which is designed specifically for the feature of fancy sound effects realized by wavetable synthesis. this wavetable synthesizer has several functions including data movement, decompression, interpolation and some mathematic operations, thus the loading of mcu can be released. in general, this wavetable synthesizer has following functions. z data pre-fetch: the wavetable synthesis method, which needs large amount of sample data as well as the data rate, needs an efficient data transfer scheme. a 512-bit data buffer is used as a cache of the fetched data. in this way, a 8-beat burst access in gmc bus can take the advantage of address continuity; some burst mode accesses in external storage device can be activated. moreover, the optional dynamic switch to 2-beat mode are supported. z rewind if needed: wavetable method for ring-tone generation take the advantage of repetition of wave samples. the data transfer unit of this wavetable synthesizer will calculate the sample indices and judge if rewind operation is needed. in brief, it is a ring-buffer scheme plus some additional requirements. z wavetable format decoder: pcm16, pcm8, a-law, u-law, 4-bit adpcm and 8-bit adpcm are supported. if the wave table samples are compressed in order to save storage size and average access count, this wavetable synthesizer has decoders to decompress the 4-bit or 8-bit codes into 16-bit wave samples. z interpolation: this wavetable synthesizer is capable of finding the correct phase and the wave samples relative to the current sample index. using these information, the interpolation unit can generate correct sample data. it reduces data processing time in mcu as well as the data transfer count to system memory. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1413 of 1535 z two pole low-pass filter: this wavetable synthesizer provides an iir filter with dynamic controlled (programmable) cutoff frequency and resonance. this filter is optional to turn on or off. z envelope multiplier: linearly piecewise envelope process is applied to each tone before synthesis. the envelope gain can be programmabled. z synthesis: wavetable synthesizer processes the foregoing operations note by note. the processing results are accumulated with other tones and stored in an accumulation memory. maximum 256 tones can be supported. z interrupt the mcu: wavetable synthesizer will interrupt the mcu when all tones are processed. the synthesized results are ready to be read by mcu through apb bus. a general description of the role played by the wavetable synthesizer can be pictured as in figure 148. the wavetable synthesizer is controlled by mcu (the registers are defined as in 0). after a trigger signal register is set, the wavetable synthesizer starts to read processing parameters (the working memory are defined as in 5.28.3) of the first note from internal ram through gmc bus. from the processing parameters, the wavetable synthesizer gets the location of the wavetable data and fetches it through gmc bus. after all the wave samples of the current note are processed, the wavetable synthesizer will write some processing parameter values back to the internal ram as the initial values of the next section of wavetable synthesis. then, the wavetable synthesizer goes on reading the processing parameters of the next note and processes the wave data of the next note. the wavetable synthesizer works until one of the following conditions is met: (1) the required note number has reached. (2) mcu sends a stop signal to freeze the transfer (send trigger signal again). condition (2) is an abnormal case. it could be happened when mcu resource management fail, including computing time or memory space. in this case, the mcu should abandon current process, lost the tone of moment, and rebuild the data path until the resource is o.k again. to sum up, it is a prevention mechanism for the hardware / mcu interface falls into a dead lock scene. figure 148 role played by the wavetable synthesizer. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1414 of 1535 5.28.2 register definitions the wavetable base address is 0x80090000. address 0x0 ~ 0xeff are used for 960 wavetable output data address. if the software read the address 0x80090000/0x800980efc, the hardware will output the first/second left channel sythesized sample. if the software read the address 4, the hardware will output the first right channel sythesized sample. table 123 register table address register name description 0x80090000 wave_data_l1 first left channel sythesized sample 0x80090004 wave_data_r1 first right channel sythesized sample ~ ~ ~ 0x80090ef8 wave_data_l480 480th left channel sythesized sample 0x80090efc wave_data_r480 480th right channel sythesized sample 0x80090f00 wave_trig wavetable trigger register 0x80090f04 wave_slow wavetable slow down control 0x80090f08 wave_par_base parameter working memory base address 0x80090f0c wave_polling wavetable status polling register 0x80090f10 wave_irq_ack wavetable interrupt ack register 0x80090f14 wave_max_val wave synthesizer maximum value register 0x80090f18 dbg_cur_note debug register ? current note status 0x80090f1c dbg_core_fsm debug register ? core state machine 0x80090f20 dbg_par_fsm debug register ? parameter memory interface state machine 0x80090f24 dbg_data_fsm debug register ? data memory interface state machine 0x80090f00 wavetable trigger register wave_trig bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name note_num type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 the wavetable synthesizer starts to work when this register is written and stops working when this register is written again before it is finished. note_num this field defines the maximum number of notes to be synthesized. 0x80090f04 wavetable slow down control wave_slow bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1415 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name beat_ dyn wt_sdcnt sd_di s type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1 sd_dis 0 enable wavetable slow down mode. 1 disable wavetable slow down mode. wt_sdcnt the wait cycles in slow down mode. by setting this field, the hardware will delay wt_sdcnt cycles to access the data bus. beat_dyn 0 no dynamic switch to 64bit, 2word burst emi access when step size is too large. 1 dynamic switch to 64bit, 2word burst emi access when step size is too large. 0x80090f08 parameter working memory base address wave_par_ba se bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name par_base_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name par_base_addr[15:0] type r/w reset 0 par_base_addr the base address of the parameter working memory. 0x80090f0c wavetable status polling register wave_pollin g bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave _bus y type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wave_busy read only. for software to poll the wave synthesizer hardware status. 0 wavetable synthesizer finish the task and in idle state. 1 wavetable synthesizer is busy. 0x80090f10 wavetable interrupt ack register wave_irq_ac k bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name irq_a ck free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1416 of 1535 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 irq_ack software has to write this field as 1 to clear wavetable interrupt source when mcu get the wavetable completed interrupt. please refer to ap side cirq document to get interrupt information. 0x80090f14 wave synthesizer maximum value register wave_max_v al bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name max_val[25:0] type r/w r/w r/w r/w r/w r/w ro reset 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max_val[15:0] type ro reset 0 max_val maximum value of 480 output samples 0x80090f18 debug register ? current note status dbg_cur_not e bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name curr_sample_count type r/w r/w r/w r/w r/w r/w r/w ro reset 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name filte r_en loop_ en curr_note type r/w r/w r/w r/w r/w r/w r0 ro ro reset 0 0 0 0 0 0 0 0 0 0x80090f1c debug register ? core state machine dbg_core_fs m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name core_fsm_1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro reset 0 0 0 0 0 0 0 0 0 0 0 01h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name core_fsm_0 type r/w r/w ro reset 0 0 0001h 0x80090f20 debug register ? parameter memory interface state machine dbg_par_fsm bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wpar_fsm[8:0] rpar_fsm[1 7:16] type r/w r/w r/w ro r/w r/w ro reset 0 0 0 001h 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1417 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rpar_fsm[15:0] type ro reset 0001h 0x80090f24 debug register ? data memory interface state machine dbg_data_fs m bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name data_fsm[17 :16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data_fsm[15:0] type ro reset 0001h 5.28.3 working memory definition the working memory is used to store the processing information of wavetable synthesizer and must be programmed by the software before triggering the hardware (wavetable synthesizer) to work. this working memory occupies a part of internal sysram of which the starting address is 0x40000000. the actual base address of this working memory (a part of) is defined by the software and written to the wavetable synthesizer as wave_par_base. table 124 working memory table note number base address memory name wave_par_base +0000h note 0 work_mem_0 ~ ~ wave_par_base +0034h note 0 work_mem_13 wave_par_base +0038h reverved note_0 wave_par_base +003ch reverved wave_par_base +0040h note 1 work_mem_0 ~ ~ wave_par_base +0074h note 1 work_mem_13 wave_par_base +0078h reverved note_1 wave_par_base +007ch reverved ~ ~ ~ note_x+0000h word 0 in the working memory work_mem_0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name total_len type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name max_out_count table_format stere o filte r_en loop_ en note _on type r/w r/w r/w r/w r/w r/w note_on 0 this note is disabled. skip to next note. 1 this note is enabled. keep on wave modulating. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1418 of 1535 loop_en 0 looping operation is disabled. 1 looping operation is enabled. filter_en 0 iir filter is turned off. 1 iir filter is turned on. stereo 0 wavetable is stored as mono format. 1 wavetable is stored as stereo format. table_format wavetable format 000 16-bit pcm 001 8-bit pcm 010 8-bit a-law 011 8-bit u-law 100 8-bit adpcm 101 4-bit adpcm max_out_count maximum wavetable output sample number (<=480) total_len in release mode, if the wavetable sample is larger than total_len , the value will be zero. note_x+0004h word 1 in the working memory work_mem_1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wave_base[31:16] type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_base[15:0] type r/w wave_base base address of the wavetable samples stored in the external memory. note_x+0008h word 2 in the working memory work_mem_2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rewind_val type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name d2b_lpstr type r/w d2b_lpstr distance from loop start point to the base address. rewind_val this field records the loop start point value. if the current sample must be interpolated by the rewind point and the loop start point, the hardware will use this register value instead of fetching the loop start point value in the table. note_x+000ch word 3 in the working memory work_mem_3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name rewind_len type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rewind_phase type r/w rewind_len the integer part of the distance from the loop start point to the rewind point. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1419 of 1535 rewind_phase the fractional part of the distance from the loop start point to the rewind point. it is a 6.10 format fractional number (6-bit integer and 10-bit fraction). the absolute address of the rewind point can be described as ( wave_base + d2b_lpstr + rewind_len + rewind_phase[15:10] ) . note_x+0010h word 4 in the working memory work_mem_4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name envelope type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name envelope_rate type r/w envelope current envelope multipier value. the register should be write back to the working memory after each note of wavetable synthesis is completed. the write-back value should be kept and read-out from memory at next section of the same wavetable syntehsis. it is an unsigned 0.16 format fractional number (0-bit integer and 16-bit fraction). envelope_rate envelope updated rate. (per output sample). it is a signed -10.25 format fractional number (msb bits are sign value and then 1/2 10 , 1/2 11 , 1/2 12 , etc). note_x+0014h word 5 in the working memory work_mem_5 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name wave_str_index type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_str_phase type r/w wave_str_phase the initial sample phase at each transfer block. the register should be write back to the working memory after each note of wavetable synthesis is completed. the write-back value should be kept and read-out from memory at next section of the same wavetable syntehsis, or phase jitter will occur between successive transfer blocks. wave_str_index the initial sample index at each transfer block. like wave_str_phase , content of this register should be write back to the working memory after each note of wavetable synthesis is completed. the actual starting sample index is derived by ( wave_str_phase + wave_str_index ). note: if ( wave_str_phase + wave_str_index ) exceeds the rewind address, it rewinds by ( rewind_len + rewind_phase ). note_x+0018h word 6 in the working memory work_mem_6 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name shift_step_rate type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name shift_step type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1420 of 1535 shift_step the shift step between each sample index. it is a fractional number in 6.10 format. the register should be write back to the working memory after each note of wavetable synthesis is completed. shift_step_rate the shift step changing rate between each sample index. it is a fractional number in signed -4.19 format (msb bits are sign value and then 1/2 4 , 1/2 5 , 1/2 6 , etc). ote_x+001ch word 7 in the working memory work_mem_7 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name adpcm_ini_index type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name adpcm_ini_val type r/w adpcm_ini_value the initial sample of the adpcm procedure. after one block of data processing is done, this register write back to working mempry for connection of the next section with the same wave sample. adpcm_ini_index the 7-bit adpcm initial index value. valid values ranged from 0 to 88. same as adpcm_ini_value , this register needs to be written back after one data block processing. note_x+0020h word 8 in the working memory work_mem_8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name adpcm_lp_index type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name adpcm_lp_val type r/w adpcm_lp_value the adpcm sample value of the loop start point. for looping in wavetable procedure, adpcm sequencer must be reset. adpcm_lp_index the 7-bit adpcm index value of loop start point. valid values ranged from 0 to 88. note_x+0024h word 9 in the working memory work_mem_9 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iir_pre_y1[17 :16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iir_pre_y1[15:0] type r/w iir_pre_y1 previous one filtered value y(n-1) used in iir filter note_x+0028h word 10 in the working memory work_mem_1 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1421 of 1535 name iir_pre_y2[17 :16] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iir_pre_y2[15:0] type r/w iir_pre_y1 previous two filtered value y(n-2) used in iir filter note_x+002ch word 11 in the working memory work_mem_11 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iir_a0 type r/w iir_a0 iir filter parameter a0. the filter formula is y(n) = a0*x(n) + 2b1*y(n-1) ? b2*y(n-2). note_x+0030h word 12 in the working memory work_mem_1 2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name iir_b1 type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name iir_b2 type r/w iir_b1 iir filter parameter b1. iir_b2 iir filter parameter b2. note_x+0034h word 13 in the working memory work_mem_1 3 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pan_par_l type r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pan_par_r type r/w pan_par_r right channel pan calculation parameter. it is a fractional number in unsigned 0.16 format. pan_par_l left channel pan calculation parameter. it is a fractional number in unsigned 0.16 format. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1422 of 1535 6 clock, mixed subsystem 6.1 analog front-end & analog blocks 6.1.1 general description to communicate with analog blocks, a common control interface for all analog blocks is implemented. in addition, there are some dedicated interfaces for data transfer. the common control interface translates apb bus write and read cycle for specific addresses related to analog front-end control. during writing or reading of any of these control registers, there is a latency associated with transferring of data to or from the analog front-end. dedicated data interface of each analog block is implemented in the corresponding digital block. the analog blocks includes the following analog function for complete gsm/gprs base-band signal processing: 1. base-band rx : for i/q channels base-band a/d conversion 2. base-band tx : for i/q channels base-band d/a conversion and smoothing filtering, dc level shifting 3. rf control : two dacs for automatic power control (apc) and automatic frequency control (afc) are included. their outputs are provided to external rf power amplifier and vcxo), respectively. 4. auxiliary adc : providing an adc for battery and other auxiliary analog function monitoring 5. audio mixed-signal blocks: it provides complete analog voice signal processing including microphone amplification, a/d conversion, d/a conversion, earphone driver, and etc. besides, dedicated stereo d/a conversion and amplification for audio signals are included). 6. clock generation : a clock squarer for shaping system clock, and six plls that provide clock signals to dsp, mcu, camera, tvout, memory card, ceva dsp and usb units are included 7. xosc32 : it is a 32-khz crystal oscillator circuit for rtc application analog block descriptions 6.1.1.1 bbrx 6.1.1.1.1 block descriptions the receiver (rx) performs base-band i/q channels downlink analog-to-digital conversion: 1. analog input multiplexer: for each channel, a 4-input multiplexer that supports offset and gain calibration is included. 2. a/d converter: two 14-bit sigma-delta adcs perform i/q digitization for further digital signal processing. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1423 of 1535 &%(&3'39@#1* &%(&3'39@#/* &%(&3'39@#12 &%(&3'39@#/2 1"%@#%-"*/ 1"%@#%-"21 7$. 1"%@#%-"21 1"%@#%-"*1 3(@&%(&3'39@*4&-<> 3(@&%(&3'39@$"-*<> 3(@&%(&3'39@("*/<> 3(@&%(&3'39@%*5)&3%*4 &%(&3'39@18%# &%(&3'39@-18%# &%(&3'39@.@$, 3(@&%(&3'39@24&-<> 1"%@#%-"*1 1"%@#%-"2/ 7$. 1"%@#%-"2/ 1"%@#%-"*/ 7$. 7$. ##39"%$*di ##39"%$2di .692di

.69*di ##39 3(@&%(&3'39@%*5)@56/&<> *cjbt@3bujp 99 9 3(@&%(&3'39@$"-*<> 9 9 999 9 9 9 999 y y y y y y y y y 7ejui 3(@&%(&3'39@%*5)@56/&<> "7%% "7%% "7%% "7%% .by 7jeqq 3(@&%(&3'39@("*/<> 7 7 7 7 %ftdsjqujpo 3(@&%(&3'39@%*5)&3%*4 &obcmf%juifs %jtbcmf%juifs figure 149 block diagram of bbrx 6.1.1.1.2 functional specifications the functional specifications of the base-band downlink receiver are listed in the following table. symbol parameter min typical max unit n resolution 14 bit code type 2?s complemen t fc clock rate 26 mhz fs output sampling rate 13/12 msps input swing 0.8*avdd vpk free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1424 of 1535 when gain =?00? when gain =?01? when gain =?10? when gain =?11? 0.4*avdd 0.57*avdd 0.33*avdd oe offset error +/- 10 mv fse full swing error +/- 30 mv i/q gain mismatch 0.5 db sinad signal to noise and distortion ratio - 45khz sine wave in [0:90] khz bandwidth - 145khz sine wave in [10:190] khz bandwidth 70 70 db db icn idle channel noise - [0:90] khz bandwidth - [10:190] khz bandwidth -74 -70 db db dr dynamic range - [0:90] khz bandwidth - [10:190] khz bandwidth 74 70 db db rin input resistance 75 k ? dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption power-up power-down 1 1 ma a table 125 base-band downlink specifications 6.1.1.2 bbtx 6.1.1.2.1 block descriptions the transmitter (tx) performs base-band i/q channels up-link digital-to-analog conversion. each channel includes: 1. 10-bits d/a converter: it converts digital modulated signals to analog domain. the input to the dac is sampled at 4.33-mhz rate with 10-bits resolution. 2. smoothing filter: the low-pass filter performs smoothing function for dac output signals with a 350-khz 3 rd -order butterworth frequency response for gsm/gprs.. 6.1.1.2.2 function specifications the functional specifications of the base-band uplink transmitter are listed in the following table. symbol parameter min typical max unit n resolution 10 bit free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1425 of 1535 code type 2?s complemen t fs sampling rate gsm/gprs mode 4.33 msps msps sinad signal to noise and distortion ratio 57 60 db output swing 0.21*avdd 0.52*avdd v vocm output cm voltage 0.3*avdd 0.5*avdd 0.7*avdd v output capacitance 20 pf output resistance 10 k ? dnl differential nonlinearity -0.5 +0.5 lsb inl integral nonlinearity -0.5 +0.5 lsb oe offset error +/- 15 mv fse full swing error +/- 30 mv fcut filter ?3db cutoff frequency gsm/gprs mode 300 350 400 khz att filter attenuation (gsm/gprs mode) at 100-khz 270-khz 4.33-mhz 0.0 0.84 65.72 db db db i/q gain mismatch +/- 0.5 db i/q gain mismatch correction range -0.96 +0.84 db dvdd digital power supply 1.08 1.2 1.32 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption power-up power-down 3 2 ma a table 126 base-band uplink transmitter specifications 6.1.1.3 afc-dac 6.1.1.3.1 block descriptions as shown in the following figure, afc-dac is designed to produce a single-ended output signal at afc pin. afc pin should be connected to an external 1 st -order r-c low pass filter to meet the 13-bits resolution (dnl) requirement 1 . 1 dnl performance depends on external output rc filter bandwidth: the narrower the bandwidth, the better the dnl. thus, there exists a tradeoff between output setting speed and dnl performance free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1426 of 1535 pwdb afc _ figure 2 block diagram of afc-dac 6.1.1.3.2 functional specifications the following table gives the electrical specification of afc-dac. symbol parameter min typical max unit n resolution 13 bit code type offset binary fs sampling rate 1083 khz dvdd digital power supply 1 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 60 125
current consumption power-up power-down 500 1 a a output range gainsel=0 gainsel=1 avdd/23/8 *avdd 0~avdd v output resistor (in afc output rc network) 100 ? dnl differential nonlinearity +1/-1 lsb inl integral nonlinearity +5/-5 lsb free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1427 of 1535 settling time 166 s maximum code difference 70 lsb psr power supply ripple rejection ratio -57 db table 127 functional specification of afc-dac 6.1.1.4 apc-dac 6.1.1.4.1 block descriptions the apc-dac is a 10-bits dac with output buffer aimed for automatic power control. here blow are its analog pin assignment and functional specification tables. 1.5v + - tvdac banggap 1.202v tvdac_pwdb afc_pwdb apc_pwdb vga_pwdb vbias_pwdb dac_buf afc dac vbias dac vga dac 10 bit dff decoder msb_sel<63:0> lsb_sel<15:0> msb_sel<63:0> lsb_sel<15:0> apc_pwdb pwdb apc _ apc_rst apc_tg apc_tg_wel apc_cali<3:0> apc_pwdb pad_afc 100 ? 220p + - apc dac apc_bus<9:0> 10k 20k figure 3 block diagram of apc-dac 6.1.1.4.2 function specifications symbol parameter min typical max unit n resolution 10 bit code type offset binary fs sampling rate 1.0833 msps sinad signal to noise and distortion ratio (10-khz sine with 1.0v swing & 100-khz bw) 50 db 99% settling time (full swing on maximal capacitance) 5 s free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1428 of 1535 output swing avdd-0.2 v output capacitance 200 pf output resistance 10 k ? dnl differential nonlinearity +/- 0.5 lsb inl integral nonlinearity +/- 1.0 lsb oe offset error +/- 10 mv fse full swing error +/- 10 mv dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 60 125
current consumption power-up power-down 200 1 a a table 128 apc-dac specifications 6.1.1.5 auxiliary adc 6.1.1.5.1 block descriptions the auxiliary adc includes the following functional blocks: 1. analog multiplexer: the analog multiplexer selects signal from one of the seven auxiliary input pins. real word message to be monitored, like temperature, should be transferred to the voltage domain. 2. 10 bits a/d converter: the adc converts the multiplexed input signal to 10-bit digital data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1429 of 1535 auxadc_xp_drivep auxadc_yp_drivep auxadc_xm_drivep auxadc_ym_drivep auxadc_xp_pass auxadc_yp_pass auxadc_xm_pass auxadc_ym_pass figure 4 block diagram of aux adc 6.1.1.5.2 function specifications the functional specifications of the auxiliary adc are listed in the following table. symbol parameter min typical max unit n resolution 10 bit code type offset binary fc clock rate 0.1 2.56 mhz fs sampling rate @ n-bit 2.56/(n+1) msps input swing 0.0 avdd v cin input capacitance unselected channel selected channel 50 1.2 ff pf rin input resistance free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1430 of 1535 unselected channel selected channel 10 1.8 m ? m ? clock latency 11 1/fc dnl differential nonlinearity +1.0/-1.0 lsb inl integral nonlinearity +1.0/-1.0 lsb oe offset error +/- 10 mv fse full swing error +/- 10 mv sinad signal to noise and distortion ratio (10-khz full swing input & 13-mhz clock rate) 50 db dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption power-up power-down 300 1 a a table 129 the functional specification of auxiliary adc 6.1.1.6 audio mixed-signal blocks 6.1.1.6.1 block descriptions audio mixed-signal blocks (amb) integrate complete voice uplink/downlink and audio playback functions. as shown in the following figure, it includes mainly three parts. the first consists of stereo audio dacs and speaker amplifiers for audio playback. the second is the voice downlink path, including voice-band dac and amplifier, which produces voice signal. amplifiers in audio blocks are equipped with multiplexers to accept signals from internal audio/voice or external radio sources. the last is the voice uplink path, which is the interface between microphone (or other auxiliary input device) input and MT6516 dsp. a set of bias voltage is provided for external electrical microphone. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1431 of 1535 "6@.065- "6@.0653 "6@065@1 "6@065@/ "6@'.*/- "6@'.*/3 .69 .69 4ufsfpup .pop '.". sbejp dijq 7pjdf 4jhobm "vejp 4jhobm 7pjdf "nq "vejp "nq3 "vejp "nq- "6@7*/@1 "6@7*/@/ "6@7*/@/ "6@7*/@1 .69 7pjdf 4jhobm "vejp -$)%"$ "vejp 3$)%"$ 7pjdf %"$ 7pjdf "%$ 1(" figure 5 block diagram of audio mixed-signal blocks. 6.1.1.6.2 functional specifications the following table gives functional specifications of voice-band uplink/downlink blocks. symbol parameter min typical max unit fs sampling rate 6500 khz cref decoupling cap between a u_vcm_po and au_vcm_no 1 uf dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1432 of 1535 t operating temperature -20 80
current consumption of uplink 2 ma idc current consumption of downlink 2.85 ma vmic microphone biasing voltage 1.9 2.2 v imic current draw from microphone bias pins 2 ma uplink path 2 sinad signal to noise and distortion ratio input level: -40 dbm0 input level: 0 dbm0 (200mvrms differential) 2 9 69 db db rin input impedance (differential) 13 20 27 k ? icn idle channel noise -67 dbm0 xt crosstalk level -66 dbm0 downlink path 3 sinad signal to noise and distortion ratio input level: -40 dbm0 input level: 0 dbm0 2 9 69 db db rload output resistor load (differential) 28 ? cload output capacitor load 200 pf icn idle channel noise of transmit path -67 dbm0 xt crosstalk level on transmit path -66 dbm0 table 130 functional specifications of analog voice blocks functional specifications of the audio blocks are described in the following. symbol parameter min typical max unit fck clock frequency 6500 khz fs sampling rate 32 44.1 48 khz avdd power supply 2.6 2.8 3.1 v t operating temperature -20 80
idc current consumption 5 ma 2 for uplink-path, not all gain setting of vupg meets the specification listed on table, especially for the several lowest gains. the minimum gain that meets the specification is to be determined. 3 for uplink-path, not all gain setting of vupg meets the specification listed on table, especially for the several lowesthighest gains. the maximum minimum gain that meets the specification is to be determined. 3 for downlink-path, not all gain setting of vdpg meets the specification listed on table, especially for the several lowest gains. the minimum gain that meets the specification is to be determined. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1433 of 1535 psnr peak signal to noise ratio 85 db idc current consumption 6 ma dr dynamic range 90 db vout output swing for 0dbfs input level 0.85 vrms thd total harmonic distortion 45mw at 16 ? load 22mw at 32 ? load -85 -85 db db rload output resistor load (single-ended) 16 ? cload output capacitor load 200 pf xt l-r channel cross talk tbd db table 131 functional specifications of the analog audio blocks 6.1.1.7 clock squarer 6.1.1.7.1 block descriptions for most vcxo, the output clock waveform is sinusoidal with too small amplitude (about several hundred mv) to make MT6516 digital circuits function well. clock squarer is designed to convert such a small signal to a rail-to-rail clock signal with excellent duty-cycle. it provides also a pull-down function when the circuit is powered- down. 6.1.1.7.2 function specifications the functional specification of clock squarer is shown in table 132. symbol parameter min typical max unit fin input clock frequency 13 26 mhz fout output clock frequency 13 26 mhz vin input signal amplitude 500 avdd mvpp dcycin input signal duty cycle 50 % dcycout output signal duty cycle dcycin-5 dcycin+5 % tr rise time on pin clksqout 5 ns/pf tf fall time on pin clksqout 5 ns/pf dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption 100 ua table 132 the functional specification of clock squarer 6.1.1.7.3 application notes here below in the figure is an equivalent circuit of the clock squarer. please be noted that the clock squarer is designed to accept a sinusoidal input signal. if the input signal free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1434 of 1535 is not sinusoidal, its harmonic distortion should be low enough to not produce a wrong clock output. as a reference, for a 13mhz sinusoidal signal input with amplitude of 0.2v the harmonic distortion should be smaller than 0.02v. figure 6 equivalent circuit of clock squarer. 6.1.1.8 phase locked loop 6.1.1.8.1 block descriptions MT6516 includes six plls: mcu pll, usb pll, ceva dsp pll, camera pll, memory card pll and tv pll. usb pll is designed to accept 13mhz input clock signal and provides 48mhz output clocks for usb and irda. mcu pll is designed to accept 13mhz input clock signal and provides both 416mhz output clock for mcu domain and 104mhz clock for dsp domain. at the same time, mcpll and tv pll are designed to accept 13mhz input clock signal and provides 91mhz and 27mhz output clock, respectively. camera pll are programmable to provide 104~208mhz output clock. likewise, ceva pll are programmable to provide 208~416mhz output clock. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1435 of 1535 figure 7 pll & clksq block diagram 6.1.1.8.2 function specifications the functional specification of mcu pll is shown in the following table. symbol parameter min typical max unit fin input clock frequency 13 mhz fout output clock frequency mcu: dsp: 416 104 mhz lock-in time 200 us free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1436 of 1535 output clock duty cycle 45 50 55 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption tbd ma table 133 the functional specification of mcu pll the functional specification of usb pll is shown below. symbol parameter min typical max unit fin input clock frequency 13 mhz fout 1 output clock frequency (for usb &irda) 48 mhz lock-in time 200 s output clock duty cycle 40 45 50 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption tbd a table 134 the functional specification of usb pll the functional specification of camera pll is shown in the following table. symbol parameter min typical max unit fin input clock frequency 6.5 mhz fout output clock frequency 104 208 mhz lock-in time 400 us output clock duty cycle 45 50 55 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption tbd ma table 135 the functional specification of camera pll the functional specification of tv pll is shown in the following table. symbol parameter min typical max unit fin input clock frequency 13 mhz free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1437 of 1535 fout output clock frequency 27 mhz lock-in time 200 us output clock duty cycle 40 45 50 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.6 2.8 3.0 v t operating temperature -20 80
current consumption tbd ma table 136 the functional specification of tv pll the functional specification of mc pll is shown in the following table. symbol parameter min typical max unit fin input clock frequency 13 mhz fout output clock frequency 91 mhz lock-in time 200 us output clock duty cycle 45 50 55 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption tbd ma table 137 the functional specification of mc pll the functional specification of ceva pll is shown in the following table. symbol parameter min typical max unit fin input clock frequency 13 mhz fout output clock frequency 208 312 416 mhz lock-in time 200 us output clock duty cycle 45 50 55 % output clock jitter -100 +100 ps dvdd digital power supply 1.0 1.2 1.4 v avdd analog power supply 2.5 2.8 3.1 v t operating temperature -20 80
current consumption tbd ma table 138 the functional specification of ceva pll free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1438 of 1535 6.1.1.9 32-khz crystal oscillator 6.1.1.9.1 block descriptions the low-power 32-khz crystal oscillator xosc32 is designed to work with an external piezoelectric 32.768khz crystal and a load composed of two functional capacitors, as shown in the following figure. figure 8 block diagram of xosc32 6.1.1.9.2 functional specifications the functional specification of xosc32 is shown in the following table. symbol parameter min typical max unit avddrtc analog power supply 0.9 2.8 3.0 v tosc start-up time 5 sec dcyc duty cycle 35 50 % tr rise time on xoscout tbd ns/pf tf fall time on xoscout tbd ns/pf current consumption 5 a leakage current 1 a t operating temperature -20 80
gm transconductance of osc32 15 a/v table 139 functional specification of xosc32 here below are a few recommendations for the crystal parameters for use with xosc32. symbol parameter min typical max unit f frequency range 32768 hz gl drive level 5 uw ? f/f frequency tolerance +/- 20 ppm esr series resistance 50 k ? c0 static capacitance 1.6 pf free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1439 of 1535 cl 4 load capacitance 27 pf table 140 recommended parameters of the 32khz crystal 6.1.1.10 sim card interface 6.1.1.10.1 block descriptions the sim card interface circuitry of MT6516 meets all etsi and imt-2000 sim interface requirements. it provides level shifting needs for low voltage gsm controller to commun icate with either 1.8v or 3v sim cards. all sim cards contain a clock input, a reset input, and a bi-directional data input/output. the clock and reset inputs to sim cards are level shifted from the supply of digital io (vio) of ba seband chipset to the sim supply (vsim). the bi-directional data bus is internal pull high with 10kohm resistor. all pins that connect to the sim card (vsim, srst, sclk, sio) withstand over ??(5kv) of human body mode esd. in order to ensure proper esd protection, careful board layout is required. 6.1.1.10.2 functional specifications symbol parameter min typical max unit interface to 3 v sim card volrst the lowest output level of the srst (i = 20 a) --- --- 0.4 v vohrst the highest output level of the srst (i = -200 a) 0.9*vsim --- --- v volclk the lowest output level of the sclk (i = 20 a) --- --- 0.4 v vohclk the highest output level of the sclk (i = -200 a) 0.9*vsim --- --- v vilsio the maximum input low level which the sio can accept r --- --- 0.4 v vihsio , vohsio the minimum input/output high level which sio can accept/ apply (i = 20 a) vsim-0.4 --- --- v iilsio the maximum current drawn out from the sio while the sio input voltage is low (vilsio = 0 v) --- --- -1 ma volsio the maximum output low level which sio can apply (iolsio = 1 ma, simio 0.23 v) --- --- 0.15*vsim v interface to 1.8 v sim card volrst srst the lowest output level (i = 20 a) 0.2*vsim v vohrst srst the highest output level 0.9*vsim v 4 cl is the parallel combination of c1 and c2 in the block diagram. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1440 of 1535 (i = -200 a) volclk sclk the lowest output level (i = 20 a) 0.2*vsim v vohclk sclk the highest output level (i = -200 a) 0.9*vsim v vilsio the maximum input level which sio can accept 0.15*vsim v vihsio , vohsio the minimum input/output high level which sio can accept/ apply (i = 20 a) vsim-0.4 v iilsio the maximum current drawn out from the sio while the sio input voltage is low (vilsio = 0 v) -1 ma volsio the maximum output low level which sio can apply (iolsio = 1 ma, simio 0.23 v) 0.15*vsim v sim card interface timing sio pull-up resistance to vsim 8 10 12 k ? srst, sio rise/fall times (vsim = 3, 1.8 v, load with 30 pf) 1 s sclk rise/fall times (vsim = 3 v, clk load with 30 pf) 18 ns (vsim = 1.8 v, clk load with 30 pf) 50 ns sclk frequency (clk load with 30 pf) 5 mhz sclk duty cycle (simclk duty = 50%, fsimclk = 5 mhz) 47 53 % sclk propagation delay 30 50 ns table 19 functional specification of sim card level-shift 6.1.2 mcu register definitions table20 list control registers and their address mapping to the mcu address space. the audio-related control register addresses starts from the base address 0x80060000. while other analog control register addresses starts from the base address 0x83010000. register address register function acronym 0x8301000c switch the register configuration path cci_wr_path 0x83010100 audio front end voice analog gain control register afe_vag_con 0x83010104 audio front end voice analog circuit control register afe_vac_con 0x83010108 audio front end voice analog circuit control register 1 afe_vac_con1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1441 of 1535 0x8301010c audio front end voice analog power down control register afe_vapdn_con 0x83010110 audio front end voice analog circuit control register 2 afe_vac_con1 0x80060200 audio front end audio analog gain control register afe_aag_con 0x80060204 analog circuit control register afe_aac_con 0x80060208 analog circuit control register afe_aapdn_con 0x8006020c analog circuit control register afe_aac_new 0x80060210 analog circuit control register afe_aac_con1 0x83010300 bbrx adc analog circuit control register bbrx_ac_con 0x83010310 wbrx adc analog circuit control register wbrx_ac_con 0x83010400 bbtx dac analog circuit control register 0 bbtx_ac_con0 0x83010404 bbtx dac analog circuit control register 1 bbtx_ac_con1 0x83010408 bbtx dac analog circuit control register 2 bbtx_ac_con2 0x8301040c bbtx dac analog circuit control register 3 bbtx_ac_con3 0x83010410 bbtx dac analog circuit control register 4 bbtx_ac_con4 0x83010500 afc dac analog circuit control register afc_ac_con 0x83010600 apc dac analog circuit control register apc_ac_con 0x83010700 aux adc analog circuit control register aux_ac_con 0x83010900 txvga dac analog circuit control register txvga_ac_con 0x83010a00 vbias dac analog circuit control register vbias_ac_con table 20 analog control registers 6.1.2.1 bbrx mcu apb bus registers for bbrx adc are listed as followings. 0x83010300 bbrx adc analog-circuit control register bbrx_ac_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dith_tune dithe n qsel isel rsv gain calbias type rw r/w r/w r/w r/w r/w r/w reset 00 0 00 00 0 00 00000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1442 of 1535 set this register for analog circuit configuration controls. calbias the register field is for control of biasing current in bbrx mixed-signal module. it is coded in 2?s complement. that is, its maximum is 15 and minimum is ?16. biasing current in bbrx mixed- signal module has impact on the performance of a/d conversion. the larger the value of the register field, the larger the biasing current in bbrx mixed-signal module, and the larger the snr. gain the register bit is for configuration of gain control of analog inputs in gsm rx mixed-signal module. 00 input range is 0.8x avdd for analog inputs in gsm rx mixed-signal module. 01 input range is 0.4x avdd for analog inputs in gsm rx mixed-signal module. 10 input range is 0.57x avdd for analog inputs in gsm rx mixed-signal module. 11 input range is 0.33x avdd for analog inputs in gsm rx mixed-signal module. isel loopback configuration selection for i-channel in bbrx mixed-signal module 00 normal mode 01 loopback tx analog i 10 loopback tx analog q 11 select the grounded input qsel loopback configuration selection for q-channel in bbrx mixed-signal module 00 normal mode 01 loopback tx analog q 10 loopback tx analog i 11 select the grounded input dithdis dither feature disable control register, which can effectively reduce the thd ( total harmonic distortion) of the bbrx adc. 0 turn on the dither (default value) 1 disable the dither dith_tune dither voltage selection. 00 dither voltage=1/15*avdd 01 dither voltage=1/30*avdd 10 dither voltage=2/15*avdd 11 dither voltage=1/10*avdd 6.1.2.2 bbtx mcu apb bus registers for bbtx dac are listed as followings. 0x83010400 bbtx dac analog-circuit c ontrol register 0 bbtx_ac_con0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name calr cdon e start calr c gain calrcsel trimi trimq type r r/w r/w r/w r/w r/w reset 0 0 000 000 0000 0000 set this register for analog circuit configuration controls. the procedure to perform calibration processing for smoothing filter in bbtx mixed-signal module is as follows: 1. write 1 to the register bit startcalrc. start calibration process. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1443 of 1535 2. read the register bit calrcdone. if read as 1, then calibration process finished. otherwise repeat the step. 3. write 0 to the register bit startcalrc. stop calibration process. 4. the result of calibration process can be read from the register field calrcout of the register bbtx_ac_con1. software can set the value to the register field calrcsel for 3-db cutoff frequency selection of smoothing filter in dac of bbtx. remember to set the register field calrccont of the register bbtx_ac_con1 to 0xb before the calibration process. it only needs to be set once. trimq the register field is used to control gain trimming of q-channel dac in bbtx mixed-signal module. it is coded in 2?s complement, that is, with maximum 7 and minimum ?8. trimi the register field is used to control gain trimming of i-channel dac in bbtx mixed-signal module. it is coded in 2?s complement, that is, with maximum 7 and minimum ?8. calrcsel the register field is for selection of cutoff frequency of smoothing filter in bbtx mixed-signal module. it is coded in 2?s complement. that is, its maximum is 3 and minimum is ?4. gain the register field is used to control gain of dac in bbtx mixed-signal module. it has impact on both of i- and q-channel dac in bbtx mixed-signal module. it is coded in 2?s complement, that is, with maximum 3 and minimum ?4. startcalrc whenever 1 is writing to the bit, calibration process for smoothing filter in bbtx mixed-signal module will be triggered. once the calibration process is completed, the register bit carldone will be read as 1. calrcdone the register bit indicates if calibration process for smoothing filter in bbtx mixed-signal module has finished. when calibration processing finishes, the register bit will be 1. when the register bit startcalrc is set to 0, the register bit becomes 0 again. 0x8301 0404 bbtx dac analog-circuit control register 1 bbtx_ac_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name calrcout float calrccnt calbias cmv type r r/w r/w r./w r/w reset - 0 00000 0000 000 set this register for analog circuit configuration controls. cmv the register field is used to control common voltage in bbtx mixed-signal module. it is coded in 2?s complement, that is, with maximum 3 and minimum ?4. calbias it can control bias current from 0.5x to 2x bias current is default value* (4+cali[2:0])/4 or 4/(4+cali[2:0]) depending on cali[3]=0 or1 calrccnt parameter for calibration process of smoothing filter in bbtx mixed-signal module. default value is ?22?. note that it is not coded in 2?s complement. therefore the range of its value is from 0 to 31. remember to set it to 0x16 before bbtx calibration process if clock sent to bbtx is 26mhz. otherwise, set to 0xb if clock is 13mhz. it only needs to be set once. in MT6516, only 26mhz clock is available float the register field is used to have the outputs of dac in bbtx mixed-signal module float or not. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1444 of 1535 calrcout after calibration processing for smoothing filter in bbtx mixed-signal module, a set of 3-bit value is obtained. it is coded in 2?s complement. 0x83010408 bbtx dac analog-circuit c ontrol register 2 bbtx_ac_con2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bypass dccoarseq dccoarsei dac_ptr dwae n calr caut o calr cope n type r/w r/w r/w r/w r/w r/w r/w reset 00 00 00 0000 0 0 0 set this register for analog circuit configuration controls. calrcopen the register field is used to control normal mode( close loop) or debug mode (open loop) for bbtx comparator in mixed signal 0 normal mode (close loop) 1 debug mode (open loop) calrcauto the register field is used to control the result of calibration process of smoothing filter can automatically load to control the smoothing filter or not. 0 not auto load, need manual load (default) 1 auto load dwaen the register field is used to turn on the dwa scheme of the bbtx dac, 0 dwa scheme off (default) 1 dwa scheme on dacptr the register field is used to configured the staring pointer of 1 hot pulling of dini//q[15:0] signal to bbtx dac, range from 0~15. there are two different configurations. for dwaen = 0, pointer always starts from the configuration value (e.g. if dacptr = 4?b1, 1 hot will start pulling from dini/q[1]). however, for dwaen=1, the initial starting pointer will follow the configuration, while the pointer will move to most significant 1 hot pointer + 1 from the last dini/q[15:0] input. defulat value is 0h. dccoarsei the register field is used to control the central nominal value of bbtx dac for i channel offset 00 central nominal @ +0lsb 01 central nominal @ +30lsb 11 central nominal @ - 30lsb 10 reserved dccoarseq the register field is used to control the central nominal value of bbtx dac for q channel offset 00 central nominal @ +0lsb 01 central nominal @ +30lsb 11 central nominal @ - 30lsb 10 reserved bypass the register field is used to control the switch of bypass filter 1/2. 00 default 01 dac output to pad free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1445 of 1535 11 not be used 10 filter 1 output to pad 0x8301040c bbtx dac analog-circuit control register 3 bbtx_ac_con3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mode sel en_2g wb_gain wb_cmv wb_trimi wb_trimq type r/w r/w r/w r/w r/w r/w reset 0 0 000 000 0000 0000 set this register for analog circuit configuration controls for wcdma (since MT6516 does not support wcdma mode, wb_gain, wb_cmv, wb_trimi,wb_triq, wb_dccoarsei, and wb_dccoarseq may be omitted.): wb_trimq the register field is used to control gain trimming of q-channel dac in bbtx mixed-signal module in wcdma mode. it is coded in 2?s complement, that is, with maximum 7 and minimum ?8. for the analog circuit of bbtx, wb_trimq is the valid configuration in wcdma mode, while trimq is the valid configuration in gsm/gprs mode, respectively. wb_trimi the register field is used to control gain trimming of i-channel dac in bbtx mixed-signal module in wcdma mode. it is coded in 2?s complement, that is, with maximum 7 and minimum ?8. for the analog circuit of bbtx, wb_trimi is the valid configuration in wcdma mode, while trimi is the valid configuration in gsm/gprs mode, respectively. wb_gain the register field is used to control gain of dac in bbtx mixed-signal module in wcdma mode. it has impact on both of i- and q-channel dac in bbtx mixed-signal module. it is coded in 2?s complement, that is, with maximum 3 and minimum ?4. for the analog circuit of bbtx, wb_gain is the valid configuration in wcdma mode, while gain is the valid configuration in gsm/gprs mode, respectively. wb_cmv the register field is used to control common voltage in bbtx mixed-signal module in wcdma mode. it is coded in 2?s complement, that is, with maximum 3 and minimum ?4. for the analog circuit of bbtx, wb_cmv is the valid configuration in wcdma mode, while cmv is the valid configuration in gsm/gprs mode, respectively. en_2g software-controlled 2g mode enable. note that this register field is only valid when modesel=1. when modesel=1, 0 bbtx is in wcdma mode. (default) 1 bbtx is in gsm/gprs mode. when modesel=0, 0 bbtx mode (gsm/gprs or wcdma) is under hardware control. 1 bbtx mode (gsm/gprs or wcdma) is under hardware control. modesel the register field is used to select whether the bbtx analog circuit is 0 bbtx mode (gsm/gprs or wcdma) is under hardware control. 1 bbtx mode (gsm/gprs or wcdma) is controlled by the register field, en_2g. 0x83010410 bbtx dac analog-circuit c ontrol register 4 bbtx_ac_con4 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1446 of 1535 name wb_dccoar seq wb_dccoar sei type r/w r/w reset 00 00 wb_dccoarsei the register field is used to control the central nominal value of bbtx dac for i channel offset in wcdma mode. for the analog circuit of bbtx, wb_dccoarsei is the valid configuration in wcdma mode, while dccoarsei is the valid configuration in gsm/gprs mode, respectively. 00 central nominal @ +0 lsb 01 central nominal @ +30 lsb 11 central nominal @ - 30 lsb 10 reserved wb_dccoarseq the register field is used to control the central nominal value of bbtx dac for q channel offset in wcdma mode. for the analog circuit of bbtx, wb_dccoarseq is the valid configuration in wcdma mode, while dccoarseq is the valid configuration in gsm/gprs mode, respectively. 00 central nominal @ +0 lsb 01 central nominal @ +30 lsb 11 central nominal @ - 30 lsb 10 reserved 6.1.2.3 afc dac mcu apb bus registers for afc dac are listed as follows. 0x83010500 afc dac analog-circuit control register afc_ac_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gains el tgsel 11bs cali type r/w r/w r/w r/w reset 0 0 0 0 set this register for analog circuit configuration controls. please refer to analog functional specification for more details. gainsel gain selection of output swing 0 3/4*vdd 1 full vdd cali biasing current control. 0 00100 ? 2 1 00011 ? 7/4 2 00010 ? 6/4 3 00001 ? 5/4 4 00000 ? 1 5 10001 ? 4/5 6 10010 ? 4/6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1447 of 1535 7 10011 ? 4/7 8 10100 ? 4/8 11bs test purpose. degrade the resolution of afc from 13 bits to 11 bits. 0 13 bits. 1 11 bits tgsel the register field is used to select whether the afc dac analog circuit is 0 sample the 13-bit code at rising edge. 1 sample the 13-bit code at falling edge. 6.1.2.4 apc dac mcu apb bus registers for apc dac are listed as followings. 0x83010600 apc dac analog-circuit control register apc_ac_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name dacbuf_cali dacbuf_trim tgsel byp cali type r/w r/w r/w r/w r/w reset 0000 1000 0 0 0000 set this register for analog circuit configuration controls. please refer to analog functional specification for more details. dacbuf_trim trimming bits for dac supply buffer, including afc dac, apc dac, txvga dac, and vbias dac. dacbuf_cali dac supply buffer calibration bits, including afc dac, apc dac, txvga dac, and vbias dac. byp bypass output buffer 0 test dac + output buffer. 1 bypass output buffer. cali biasing current control 0 0100 ? 2 1 0011 ? 7/4 2 0010 ? 6/4 3 0001 ? 5/4 4 0000 ? 1 5 1001 ? 4/5 6 1010 ? 4/6 7 1011 ? 4/7 8 1100 ? 4/8 tgsel the register field is used to select whether the apc dac analog circuit is free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1448 of 1535 0 sample the 10-bit code at rising edge. 1 sample the 10-bit code at falling edge. 6.1.2.5 auxiliary adc mcu apb bus registers for aux adc are listed as followings. 0x83010700 auxiliary adc analog-circuit control register aux_ac_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name enb cali type r/w r/w reset 0 0 set this register for analog circuit configuration controls. please refer to analog functional specification for more details. cali biasing current control 0 0100 ? 2 1 0011 ? 7/4 2 0010 ? 6/4 3 0001 ? 5/4 4 0000 ? 1 5 1001 ? 4/5 6 1010 ? 4/6 7 1011 ? 4/7 8 1100 ? 4/8 enb offset cancellation disable control. 0 comparator offset cancellation function enable. 1 comparator offset cancellation function disable. 6.1.2.6 voice front-end mcu apb bus registers for speech are listed as followings. 0x83010100 afe voice analog gain control register afe_vag_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vupg vdpg0 vzer o_dtc _cmp_ pwd vzer o_dtc _en vzero_dtc_ cali type r/w r/w r/w r/w r/w reset 00000 0000 0 0 00 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1449 of 1535 set this register for analog pga gains. vupg is set for microphone input volume control. and vdpg0 and vdpg1 are set for two output volume controls vupg voice-band up-link pga gain control bits. for vcfg[3] = 1, it is only valid for input 1. note that this field only takes effect in analog test modes for testing purpose. under normal operation, voice-band up-link pga gain is controlled by audio front end. please see the section ?audio front end? for details. vcfg[2] = ?0? gain mode table vcfg[2] = ?1? fm mode table vupg [5:0] gain vupg [5:0] gain vupg [5:0] gain vupg [5:0] gain 111111 49 db 011111 17 db 111111 43 db 011111 11db 111110 48 db 011110 16 db 111110 42 db 011110 10db 111101 47 db 011101 15 db 111101 41 db 011101 9db 111100 46 db 011100 14 db 111100 40 db 011100 8db 111011 45 db 011011 13 db 111011 39 db 011011 7db 111010 44 db 011010 12db 111010 38 db 011010 6db 111001 43 db 011001 11db 111001 37 db 011001 5db 111000 42 db 011000 10db 111000 36 db 011000 4db 110111 41 db 010111 9db 110111 35 db 010111 3db 110110 40 db 010110 8db 110110 34 db 010110 2db 110101 39 db 010101 7db 110101 33 db 010101 1db 110100 38 db 010100 6db 110100 32 db 010100 0db 110011 37 db 010011 5db 110011 31 db 010011 -1db 110010 36 db 010010 4db 110010 30 db 010010 -2db 110001 35 db 010001 3db 110001 29 db 010001 -3db 110000 34 db 010000 2db 110000 28 db 010000 -4db 101111 33 db 001111 1db 101111 27 db 001111 -5db 101110 32 db 001110 0db 101110 26db 001110 -6db 101101 31 db 001101 -1db 101101 25 db 001101 -7db 101100 30 db 001100 -2db 101100 24 db 001100 -8db 101011 29 db 001011 -3db 101011 23 db 001011 -9db 101010 28 db 001010 -4db 101010 22 db 001010 -10db 101001 27 db 001001 -5db 101001 21 db 001001 -11db 101000 26db 001000 -6db 101000 20 db 001000 -12db 100111 25 db 000111 -7db 100111 19 db 000111 -13db 100110 24 db 000110 -8db 100110 18 db 000110 -14db 100101 23 db 000101 -9db 100101 17 db 000101 -15db 100100 22 db 000100 -10db 100100 16 db 000100 -16db 100011 21 db 000011 -11db 100011 15 db 000011 -17db 100010 20 db 000010 -12db 100010 14 db 000010 -18db 100001 19 db 000001 -13db 100001 13 db 000001 -19db free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1450 of 1535 100000 18 db 000000 -14db 100000 12db 000000 -20db for vcfg[3] = 1, it is only valid for input 1. vdpg0 voice-band down-link pga0 gain control bits vdpg0 [3:0] gain 1111 8db 1110 6db 1101 4db 1100 2db 1011 0db 1010 -2db 1001 -4db 1000 -6db 0111 -8db 0110 -10db 0101 -12db 0100 -14db 0011 -16db 0010 -18db 0001 -20db 0000 -22db vzero_dtc_cali zero-detect comparator hysteresis adjust 0 13mv 1 26mv 2 40mv 3 56mv vzero_dtc_en voice buffer zero-detection enable. 0 disable 1 enable vzero_dtc_cmp_pwd reserved. 0x83010104 afe voice analog-circuit control register 0 afe_vac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vdc_c oupl e vmic_ shor t vmic_vref vcfg vtx_t estm ode vdse nd0 vcali type r/w r/w r/w r/w r/w r/w r/w reset 0 0 00 00000 0 00 00000 set this register for analog circuit configuration controls. vtx_testmode config pad_vin1_p/ pad_vin1_n. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1451 of 1535 0 pad_vin1_p/pad_vin1_n are used for inputs from microphone. 1 pad_vin1_p/pad_vin1_n are configured to be vbitx pga?s differential outputs for testing. vdc_couple selectively choose dc couple microphone sense. (this cannot work in MT6516.) 0 disable dc couple sense of microphone 1 enable dc couple sense of microphone vmic_short selectively short au_micbiasp / au_micbiasn. 0 float mic_biasn and short it to mic_biasp when handsfree mode mic is plugged in 1 short mic_biasn to ground when handsfree mode mic is plugged in. in this mode, differential mic has current leakage and cause power loss. vmic_vref tuning micbiasp dc voltage. 00 1.9v 01 2.0v 10 2.1v 11 2.2v vcfg[4] microphone biasing control 0 differential biasing 1 single-ended biasing vcfg[3] gain mode control. this control register is only valid to input 1. others can be amplification mode only. 0 amplification 1 bypass vbitx pga to test adc only vcfg[2] coupling control 0 ac 1 dc vcfg[1:0] input select control 00 input 0 01 input 1 10 fm 11 reserved vdsend0 reserved vcali biasing current control, in 2?s complement format 0x83010108 afe voice analog-circuit control register 1 afe_vac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vupo p_en vbias_en voc_e n vadci nmod e vcmb uf_en vcm_ rlad der_e n viboo t vfloa t vrsd on vgbo ot vadc_ dvref _cal vadc_ denb vbuf_bias type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 set this register for analog circuit configuration controls. there are several loop back modes and test modes implemented for test purposes. suggested value is 0280h. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1452 of 1535 vupop_en de-pop noise enable 0 disable 1 enable vbias_en voice downlink path bias enable 0 disable. 1 enable. voc_en voice downlink buffer over current protection 0 disable 1 enable vcm_rladder_en vcm resistor ladder enable. 0 disable 1 enable vcmbuf_en reference buffer enable. 0 disable 1 enable viboot reserved vfloat voice-band output driver float 0 normal operating mode 1 float mode vrsdon voice-band redundant signed digit function on 0 1-bit 2-level mode 1 2-bit 3-level mode vadc_dvref_cal adc dither reference voltage calibration 0 3/15 vdd reference is fed to dither path 1 2/15 vdd reference is fed to dither path vadc_denb adc dither enable 0 adc dither enable 1 adc dither disable vadcinmode voice-band adc output mode. 0 normal operating mode 1 the adc input from the dac output vbuf_bias voice downlink buffer output stage bias current adjust 0 3/3 x 1 4/3 x 2 1/3 x 3 2/3 x 0x8301010c afe voice analog power down control register afe_vapdn_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1453 of 1535 name vpd_d ct_en vpdv cm_e n vpdn_ bias vpdn_ lna vpdn_ adc v pdn _ out0 type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 set this register to power up analog blocks. 0: power down, 1: power up. vpdvcm_en rreserved vpd_dct_en dac dct circuit power on. 0 off 1 on vpdn_bias mic-bias block power on. 0 off 1 on vpdn_lna low noise amplifier block 0 off 1 on vpdn_adc adc block 0 off 1 on vpdn_out0 dac buffer. 0 off 1 on 0x83010110 afe voice analog-circuit control register 2 afe_vac_con 2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vloo pbac k vrxcali vclk2 x_inv _en vclk_ inv_e n vclk_sel_en vbias_dct_en type r/w r/w r/w r/w r/w r/w reset 0 00000 0 0 0000 0000 set this register for analog circuit configuration controls. vloopback voice tx and rx loop back mode. 0 disable loop back mode. 1 enable loop back mode. vbias_dct_en bias current tunning register for dct. 0~15 corresponds to 8/8,7/8,6/8,5/8,4/8,3/8,2/8,1/8,16/8,15/8,14/8,13/8,12/8,11/8,10/8,9/8 vclk_sel_en non-overlap clock timing tunning register [3:2] clock delay fine tune [1:0] non-overlapping clock fine tune1 vclk_inv_en dac 6.5mhz clock phase inversion 0 not inverted. 1 inverted. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1454 of 1535 vclk2x_inv_en dac 13mhz clock phase inversion. (only 3 lsb-bit are used) 0 not inverted. 1 inverted. vrxcali vbirx dac bias current control. 0 4/4 x iu 1 3/4 x iu 2 2/4 x iu 3 1/4 x iu 4 8/4 x iu 5 7/4 x iu 6 6/4 x iu 7 5/4 x iu 6.1.2.7 audio front-end mcu apb bus registers for audio are listed as followings. 0x80060200 afe audio analog gain control register afe_aag_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apgr apgl type r/w r/w reset 0000 0000 set this register for analog pga gains. apgr audio pga r-channel gain control apgl audio pga l-channel gain control apgr [3:0] / apgl [3:0] gain 1111 23db 1110 20db 1101 17db 1100 14db 1011 13db 1010 8db 1001 5db 1000 2db 0111 -1db 0110 -4db 0101 -7db 0100 -10db 0011 -13db 0010 -16db 0001 -19db free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1455 of 1535 0000 -22db 0x80060204 afe audio analog-circuit control register afe_aac_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apro_sc adepop abufselr abufsell acali type r/w r/w r/w r/w r/w reset 0 0 000 000 00000 set this register for analog circuit configuration controls. apro_sc short circuit protection. 0 disable 1 enable adepop de-pop noise. 0 disable 1 enable abufselr audio buffer r-channel input selection 001 audio dac r-channel output 010 voice dac output 100 external fm r/l-channel radio output, stereo to mono 101 external fm r-channel radio output others reserved. abufsell audio buffer l-channel input selection 001 audio dac l-channel output 010 voice dac output 100 external fm r/l-channel radio output, stereo to mono 101 external fm l-channel radio output others reserved. acali audio bias current control, in 2?s complement format. (only 3 lsb-bit are used) 0 4/4 x iu 1 3/4 x iu 2 2/4 x iu 3 1/4 x iu 4 8/4 x iu 5 7/4 x iu 6 6/4 x iu 7 5/4 x iu 0x80060208 afe audio analog power down control register afe_aapdn_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name apdv cm_e n apdn_ bias apdn_ dacr apdn_ dacl apdn_ outr apdn _outl type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 set this register to power up analog blocks. 0: power down, 1: power up. suggested value is 00ffh. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1456 of 1535 apdnvcm_en power on vcm circuit (reserved) 0 off 1 on apdn_bias power on bias circuit 0 off 1 on apdn_dacr power on r-channel dac dct circuit 0 off 1 on apdn_dacl power on l-channel dac dct circuit 0 off 1 on apdn_outr power on r-channel out buffer block 0 off 1 on apdn_outl power on l-channel out buffer block 0 off 1 on 0x8006020c enhanced audio analog front end control & parameters afe_aac_new bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf_bias mux avcm gen_e n vcm_ mode type r/w r/w r/w r/w reset 0 00 0 0 MT6516 ehnahced audio dac application circuitry selection and control parameters. buf_bias select audio buffer output stage quasi bias current. 00 1x 01 1.5x 10 0.5x 11 0.75x mux mux audio dac output to dm r/l pins. (configure fminr/fminl i/o) 00 fm input 01 fm input 10 left channel dac differential output 11 right channel dac differential output avcmgen_en power down buffer vcm generation circuit (active low) 0 off 1 on vcm_mode change output buffer common mode generation circuitry. 0 new vcm circuitry 1 old vcm circuitry free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1457 of 1535 0x80060210 afe audio analog-circuit control register 1 afe_aac_con1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name aclk2 x_inv _en aclk_ inv_e n aclk_sel_en abias_dct_en type r/w r/w r/w r/w reset 0 0 0000 0000 set this register for analog circuit configuration controls. abias_dac_en bias current tunning register for dct. 0~15 corresponds to 8/8,7/8,6/8,5/8,4/8,3/8,2/8,1/8,16/8,15/8,14/8,13/8,12/8,11/8,10/8,9/8 aclk_sel_en non-overlap clock timing tunning register [3:2] clock delay fine tune. [1:0] non-overlapping clock fine tune. aclk_inv_en dac 6.5mhz clock phase inversion 0 not inverted. 1 inverted. aclk2x_inv_en dac 13mhz clock phase inversion. 0 not inverted. 1 inverted. 6.1.2.8 register setting path 0x8301000c switch the register configuring path cci_wr_path bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ad_in f_pat h pll_w r_pat h mode m_wr _path vbi_w r_pat h abi_w r_pat h type r/w r/w r/w r/w r/w reset 0 0 0 0 0 wr_path 0 switch the register setting to mcu side 1 switch the register setting to manually control by trace32 through jtag the bit is to facilitate acd members for verifying purpose; the hardware supports write path switching, without being disturbed by existing mcu load. however, when with manually control, all register addresses are offset by 0x1000. for example, mcu configures afe_aac_new through the address 0x8301020c, while the manually control path take effect when configuring 0x8301120c. notice that before finishing manual control, the register must be reset to be 0. the modem part includes bbrx, bbtx, apc, afc, wbrx, txvga, vbias and auxadc. ad_inf_path the register bit decides the input/output path of the mixed-mode module. for abi and vbi, it can be configured to feed the pattern from afe or from chip i/o (shared with a_func_mode). for bbtx, txvga, vbias, apc, and afc, the input selection interface is divided at either mix_dig or chip i/o (also shared with a_func_mode). as for the bbrx and wbrx, the output pattern can be bypass to chipio with this register bit being true. the bit is for convenient debug-use in normal mode, such that the data pattern can be observed or be feed-in by external device, while control register free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1458 of 1535 setting still comes from the chip internally(by use of jtag). it should be notice that this special debug mode should be accompanied by proper setting of gpio, which decides the pad oe when in normal function. 0 data pattern comes from chip internally, and the output data cannot be bypassed to chip i/o 1 analog debug mode in normal function 6.1.2.9 reserved some registers are reserved for further extensions. 0x83010900h reserved 1 analog circuit control register 0 res1_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010904h reserved 1 analog circuit control register 1 res1_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010a00h reserved 2 analog circuit control register 0 res2_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010a04h reserved 2 analog circuit control register 1 res2_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010b00h reserved 3 analog circuit control register 0 res3_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1459 of 1535 0x83010b04h reserved 3 analog circuit control register 1 res3_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010c00h reserved 4 analog circuit control register 0 res4_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010c04h reserved 4 analog circuit control register 1 res4_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010d00h reserved 5 analog circuit control register 0 res5_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010d04h reserved 5 analog circuit control register 1 res5_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010e00h reserved 6 analog circuit control register 0 res6_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1460 of 1535 0x83010e04h reserved 6 analog circuit control register 1 res6_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010f00h reserved 7 analog circuit control register 0 res7_ac_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x83010f04h reserved 7 analog circuit control register 1 res7_ac_con 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.1.3 programming guide 6.1.3.1 bbrx register setup the register used to control analog base-band receiver is bbrx_ac_con. 6.1.3.1.1 programmable biasing current to maximize the yield in modern digital process, the receiver features providing 5-bit 32-level programmable current to bias internal analog blocks. the 5-bits registers calbias [4:0] is coded with 2?s complement format. 6.1.3.1.2 offset / gain calibration the base-band downlink receiver (rx), together with the base-band uplink transmitter (tx) introduced in the next section, provides necessary analog hardware for dsp algorithm to correct the mismatch and offset error. the connection for measurement of both rx/tx mismatch and gain error is shown in figure 150 , and the corresponding calibration procedure is described below. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1461 of 1535 figure 150 base-band a/d and d/a offset and gain calibration 6.1.3.1.3 downlink rx offset error calibration the rx offset measurement is achieved by selecting grounded input to a/d converter (set isel [1:0] =?11? and qsel [1:0] =?11? to select channel 3 of the analog input multiplexer, as shown in figure . the output of the adc is sent to dsp for further offset cancellation. the offset cancellation accuracy depends on the number of samples being converted. that is, more accurate measurement can be obtained by collecting more samples followed by averaging algorithm. figure 5 downlink adc offset error measurement 6.1.3.1.4 downlink rx and uplink tx gain error calibration to measure the gain mismatch error, both i/q uplink txs should be programmed to produce full-scale pure sinusoidal waves output. such signals are then fed to downlink rx for a/d conversion, in the following two steps. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1462 of 1535 a. the uplink (both in gsm and wcdma mode) i-channel output are connected to the downlink i-channel input, and the uplink q-channel output are connected to the downlink q-channel input. this can be achieved by setting isel [1:0] =?01? and qsel [1:0] =?01? (shown in figure 151 (a)).. b. the uplink (both in gsm and wcdma mode) i-channel output are then connected to the downlink q- channel input, and the uplink q-channel output are connected to the downlink i-channel input. this can be achieved by setting isel [1:0] =?10? and qsel [1:0] =?10? (shown in figure 151 (b)). figure 151 downlink rx and up-link tx gain mismatch measurement (a) i/q tx connect to i/q rx (b) i/q tx connect to q/i rx once above successive procedures are completed, rx/tx gain mismatch could be easily obtained because the amplitude mismatch on rx digitized result in step a and b is the sum and difference of rx and tx gain mismatch, respectively. the gain error of the downlink rx can be corrected in the dsp section and the uplink tx gain error can be corrected by the gain trimming facility that tx block provide. 6.1.3.1.5 uplink tx offset error calibration once the offset of the downlink rx is known and corrected, the offset of the uplink tx alone could be easily estimated. the offset error of tx should be corrected in the digital domain by means of the programmable feature of the digital gmsk modulator. finally, it is important that above three calibration procedures should be exercised in order, that is, correct the rx offset first, then rx/tx gain mismatch, and finally tx offset. this is owing to that analog gain calibration in tx will affect its offset, while the digital offset correction has no effect on gain. 6.1.3.2 bbtx register setup the register used to control analog base-band transmitter is bbtx_ac_con0~4. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1463 of 1535 6.1.3.2.1 output gain control the output swing of the uplink transmitter is controlled by register gain [2:0] ( or wb_gain[2:0] ) coded in 2?s complement with about 2db step. when trimi [3:0] (wb_trimi[3:0]) / trimq [3:0] (wb_trimq[3:0]) = 4?b0000 the swing is listed in table 141, defined to be the difference between positive and negative output signal. gain [2:0] / wb_gain[2:0] output swing for avdd=2.8 (v) +3 (011) avdd*0.526 (+3.36 db) 1.46 +2 (010) avdd*0.462 (+2.24 db) 1.29 +1 (001) avdd*0.406 (+1.12 db) 1.14 +0 (000) avdd*0.357 (+0.00 db) 1 -1 (111) avdd*0.314 (-1.12 db) 0.88 -2 (110) avdd*0.278 (-2.24 db) 0.78 -3 (101) avdd*0.243 (-3.36 db) 0.68 -4 (100) avdd*0.214 (-4.48 db) 0.6 table 141 output swing control table 6.1.3.2.2 output gain trimming i/q channels can also be trimmed in gsm/gprs or wcdma mode separately to compensate gain mismatch in the base-band transmitter or the whole transmission path including rf module. the gain trimming is adjusted in 16 steps spread from ?0.96db to +0.84db ( table 142), compared to the full-scale range set by gain [2:0]=3?b000. trimi [3:0] / trimq [3:0] wb_trimi[3:0]/wb_trimq[3:0] gain step (db) +7 (0111) 0.84 +6 (0110) 0.72 +5 (0101) 0.60 +4 (0100) 0.48 +3 (0011) 0.36 +2 (0010) 0.24 +1 (0001) 0.12 +0 (0000) 0.00 -1 (1111) -0.12 -2 (1110) -0.24 -3 (1101) -0.36 -4 (1100) -0.48 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1464 of 1535 -5 (1011) -0.60 -6 (1010) -0.72 -7 (1001) -0.84 -8 (1000) -0.96 table 142 gain trimming control table 6.1.3.2.3 output common-mode voltage the output common-mode voltage is controlled by cmv [2:0] (wb_cmv[2:0]) with about 0.08*avdd step, as listed in the following table. cmv [2:0] / wb_cmv[2:0] common-mode voltage +3 (011) avdd*0.70 +2 (010) avdd*0.62 +1 (001) avdd*0.54 +0 (000) avdd*0.50 -1 (111) avdd*0.46 -2 (110) avdd*0.42 -3 (101) avdd*0.38 -4 (100) avdd*0.30 table 143 output common-mode voltage control table 6.1.3.2.4 programmable biasing current the transmitter features providing 4-bit 9-level programmable current to bias internal analog blocks. it can control bias current from 0.5x to 2x. 6.1.3.2.5 smoothing filter characteristic the 3 rd ?order butterworth smoothing filter is used to suppress the image at dac output: it provides more than 60db attenuation at the 4.33mhz sampling frequency. to tackle with the digital process component variation, programmable cutoff frequency control bits calrcsel [2:0] are included. user can directly change the filter cut-off frequency by different calrcsel value (coded with 2?s complement format and with a default value 0). in addition, an internal calibration process is provided, by setting start calrc to high and calrccnt to an appropriate value (default is 11). after the calibration process, the filter cut-off frequency is calibrated to 350khz +/- 50 khz and a new calrcout value is stored in the register. during the calibration process, the output of the cell is high-impedance. after this calibration, cut-off frequency of the filter in wcdma mode is also set to its applicable value. 6.1.3.3 afc-dac register setup the register used to control the apc dac is afc_ac_con, which providing 9 different programmable current to bias internal analog blocks. note that the 5-bits registers cali [4:0] is not coded with 2?s complement format. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1465 of 1535 there is another 1-bit register tgsel to control the sampling phase, either rising edge or falling edge, for dac code. 6.1.3.4 apc-dac register setup the register used to control the apc dac is afc_ac_con, which providing 9 different programmable current to bias internal analog blocks. note that the 5-bits registers cali [4:0] is not coded with 2?s complement format. there is another 1-bit register tgsel to control the sampling phase, either rising edge or falling edge, for dac code. 6.1.3.5 auxiliary a/d conversion register setup the register used to control the aux-adc is aux_ac_con. for this register, which providing 9 different programmable current to bias internal analog blocks.. 6.1.3.6 voice-band blocks register setup the registers used to control amb are afe_vag_con, afe_vac_con0, afe_vac_con1, and afe_vapdn_con. for these registers, please refer to chapter ?analog front end & analog blocks? 6.1.3.6.1 reference circuit the voice-band blocks include internal bias circuits, a differential bandgap voltage reference circuit and a differential microphone bias circuit. internal bias current could be calibrated by varying vcali[4:0] (coded with 2?s complement format). for proper operation, there should be an external 1uf capacitor connected between differential output pins au_vcm_po and au_vcm_no. the following table illustrates typical 0dbm0 voltage when uplink/downlink programmable gains are unity. for other gain setting, 0dbm0 reference level should be scaled accordingly. symbol parameter min typical max unit v 0dbm0 , up 0dbm0 voltage for uplink path, applied differentially between positive and negative microphone input pins 0.2v v-rms v 0dbm0,dn 0dbm0 voltage for downlink path, appeared differentially between positive and negative power amplifier output pins 0.6v v-rms table 144 0dbm0 reference level for unity uplink/downlink gain the microphone bias circuit generates a single-ended output voltage on au_micbias_p for external electret type microphone. typical output voltage is 1.9 v. the max current supplied by microphone bias circuit is 2ma. 6.1.3.6.2 uplink path uplink path of voice-band blocks includes an uplink programmable gain amplifier and a sigma-delta modulator. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1466 of 1535 6.1.3.6.3 uplink programmable gain amplifier input to the pga is a multiplexer controlled by vcfg [3:0], as described in the following table. in normal operation, both input ac and dc coupling are feasible for attenuation the input signal (gain <= 0db). however, only ac coupling is suggested if amplification of input signal is desired (gain>=0db). control signal function descriptions vcfg [0] input selector 0: input 0 (from au_vin0_p / au_vin0_n) is selected 1: input 1 (from au_vin1_p / au_vin1_n) is selected vcfg [1] input selector 1: input fm (from au_fminl / au_fminr) is selected vcfg [2] coupling mode 0: ac coupling 1: dc coupling vcfg [3] gain mode 0: amplification mode (gain range -20~43 db) 1: bypass mode table 145 uplink pga input configuration setting the pga itself provides programmable gain (through vupg [5:0]) with step of 1db, as listed in the following table. vupg [5:0] gain vupg [5:0] gain 111111 43 db 011111 11db 111110 42 db 011110 10db 111101 41 db 011101 9db 111100 40 db 011100 8db 111011 39 db 011011 7db 111010 38 db 011010 6db 111001 37 db 011001 5db 111000 36 db 011000 4db 110111 35 db 010111 3db 110110 34 db 010110 2db 110101 33 db 010101 1db 110100 32 db 010100 0db 110011 31 db 010011 -1db 110010 30 db 010010 -2db 110001 29 db 010001 -3db 110000 28 db 010000 -4db 101111 27 db 001111 -5db 101110 26 db 001110 -6db 101101 25 db 001101 -7db 101100 24 db 001100 -8db free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1467 of 1535 101011 23 db 001011 -9db 101010 22 db 001010 -10db 101001 21 db 001001 -11db 101000 20db 001000 -12db 100111 19 db 000111 -13db 100110 18 db 000110 -14db 100101 17 db 000101 -15db 100100 16 db 000100 -16db 100011 15 db 000011 -17db 100010 14 db 000010 -18db 100001 13 db 000001 -19db 100000 12db 000000 -20 db table 146 uplink pga gain setting when inputs apply at microphone (vupg [5:0]) the following table illustrates typically the 0dbm0 voltage applied at the microphone inputs, differentially, for several gain settings. vcfg [3] =?0? vcfg [3] =?1? (only valid for input 1) vupg [5:0] 0dbm0 (v-rms) vupg [5:0] 0dbm0 (v-rms) 111100 2mv xxxxxx 0.2v 101000 20mv 100000 50mv 010100 0.2v table 147 0dbm0 voltage at microphone input pins 6.1.3.6.4 sigma-delta modulator analog-to-digital conversion in uplink path is made with a second-order sigma-delta modulator (sdm) whose sampling rate is 4096khz. output signals are coded in either one-bit or rsd format, optionally controlled by vrsdon register. for test purpose, one can set vadcinmode to hi to form a look-back path from downlink dac output to sdm input. the default value of vadcinmode is zero. 6.1.3.6.5 downlink path downlink path of voice-band blocks includes a digital to analog converter (dac) and two programmable output power amplifiers. 6.1.3.6.6 digital to analog converter the dac converts input bit-stream to analog signal by sampling rate of 4096khz. . besides, it performs a 2 nd - order 40khz butterworth filtering. the dac receives input signals from MT6516 dsp by set vdacinmode = 0. it can also take inputs from sdm output by setting vdacinmode = 1. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1468 of 1535 6.1.3.6.7 downlink programmable power amplifier voice-band analog blocks include two identical output power amplifiers with programmable gain. amplifier 0 and amplifier 1 can be configured to either differential or single-ended mode by adjusting vdsend [0] and vdsend [1], respectively. in single-ended mode, when vdsend[0] =1, output signal is present at au_vout0_p pin respect to ground. same as vdsend[1] for au_vout1_p pin. for the amplifier itself, programmable gain setting is described in the following table. vdpg0 [3:0] / vdpg1 [3:0] gain 1111 8db 1110 6db 1101 4db 1100 2db 1011 0db 1010 -2db 1001 -4db 1000 -6db 0111 -8db 0110 -10db 0101 -12db 0100 -14db 0011 -16db 0010 -18db 0001 -20db 0000 -22db table 148 downlink power amplifier gain setting control signal vfloat, when set to ?hi?, is used to make output nodes totally floating in power down mode. if vfloat is set to ?low? in power down mode, there will be a resistor of 50k ohm (typical) between au_vout0_p and au_vout0_n, as well as between au_vout0_p and au_vout0_n. the amplifiers deliver signal power to drive external earphone. the minimum resistive load is 28 ohm and the upper limit of the output current is 50ma. on the basis that 3.14dbm0 digital input signal into downlink path produces dac output differential voltage of 0.87v-rms (typical), the following table illustrates the power amplifier output signal level (in v-rms) and signal power for an external 32 ohm resistive load. vdpg output signal level (v-rms) output signal power (mw / dbm) 0010 0.11 0.37/-4.3 0110 0.27 2.28/3.6 1010 0.69 14.8/11.7 1110 1.74 94.6/19.8 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1469 of 1535 table 149 output signal level/power for 3.14dbm0 input. external resistive load = 32 ohm the following table illustrates the output signal level and power for different resistive load when vdpg =1110. rload output signal level (v-rms) output signal power (mw / dbm) 30 1.74 101/20 100 1.74 30.3/14.8 600 1.74 5/7 table 150 output signal level/power for 3.14dbm0 input, vdpg =1110 6.1.3.6.8 power down control each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table. control signal descriptions vpdn_bias power down reference circuits (active low) vpdn_lna power down uplink pga (active low) vpdn_adc power down uplink sdm (active low) vpdn_dac power down dac (active low) vpdn_out0 power down downlink power amp 0 (active low) vpdn_out1 power down downlink power amp 1 (active low) table 151 voice-band blocks power down control 6.1.3.7 audio-band blocks register setup the registers used to control audio blocks are afe_aag_con, afe_aac_con, afe_aac_con, afe_aac_new_con, afe_aac_con1 and afe_aapdn_con. 6.1.3.7.1 output gain control audio blocks include stereo audio dacs and programmable output power amplifiers. the dacs convert input bit-stream to analog signal by sampling rate of 6500khz by sample-rate converter. the two identical output power amplifiers with programmable gain are designed to driving external ac-coupled single-end speaker. the minimum resistor load is 16 ohm. the programmable gain setting, controlled by apgr[] and apgl[], is the same as that of the voice-band amplifiers. unlike voice signals, 0dbfs defines the full-scale audio signals amplitude. the following table illustrates the power amplifier output signal level (in v-rms) and signal power for an external 16 ohm resistive load. apgr[]/ apgl[] output signal level (v-rms) output signal power (mw / dbm) 0010 0.055 0.19/-7.2 0110 0.135 1.14/0.6 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1470 of 1535 1010 0.345 7.44/8.7 1110 0.87 47.3/16.7 table 152 output signal level/power for 0dbfs input. external resistive load = 16 ohm 6.1.3.7.2 mute function and power down control by setting amuter (amutel) to high, right (left) channel output will be muted. each block inside audio mixed-signal blocks features dedicated power-down control, as illustrated in the following table. control signal descriptions apdn_bias power down audio bias circuits (active low) apdn_dacl power down l-channel dac (active low) apdn_dacr power down r-channel dac (active low) apdn_outl power down l-channel audio amplifier (active low) apdn_outr power down r-channel audio amplifier (active low) avcmgen_en power down buffer vcm generation circuit (active low) table 153 audio-band blocks power down control 6.1.3.8 multiplexers for audio and voice amplifiers the audio/voice amplifiers feature accepting signals from various signal sources including au_fminr/au_fminl pins, that aimed to receive stereo am/fm signal from external radio chip: 1) voice-band amplifier accepts signals from voice dac output only. 2) audio left/right channel amplifiers receive signals from either voice dac, audio dac, or am/fm radio input pins (controlled by registers abufsell[] and abufselr[] ), too. left and right channel amplifiers will produce identical output waveforms when receiving mono signals from voice dac. 6.1.3.9 preferred microphone and earphone connections in this section, preferred microphone and earphone connections are discussed. differential connection of microphone is shown below. this is the application circuits compatible with previous products c1 and rin form an ac coupling and high-pass network. c1*rin should be chosen such that the in- band signal will not be attenuated too much. for differential minimum resistance of 13k ohm, minimum value of c1 is 170nf for less than 1db attenuation at 300hz. r2 is determined by microphone sensitivity. c2 and r2 form another low-pass filter to filtering noise coming from microphone bias pins. pole frequency less than 50hz is recommended. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1471 of 1535 figure 6 differential microphone connection another suggested connection method of microphone is shown below. r1 is chosen based on microphone sensitivity requirement. c1 and rin form an ac coupling and high-pass network. r2 needs proper adjustment to obtain the best noise performance on the voice uplink input terminals. figure 7 suggested microphone connection for earphone, both connections can be used. the application circuit shown in figure 7 is highly recommended to achieve the better performance . 6.1.3.10 clock squarer register setup the register used to control clock squarer is clk_con. for this register, please refer to chapter ?clocks? . the register used to control the clksq are clksq_div2_pwd and clksq_div2_sel, in which clksq_div2_sel is a 1bit register that is used to provide correct input frequency for pll under different clksq input frequency. and clksq_div2_pwd is also 1bit register to control divider by 2 circuit in clksq to turn on or not . please refer to the register table for detail free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1472 of 1535 6.1.3.11 phase-locked loop register setup for registers control the pll, please refer to chapter ?clocks? and ?software power down control? 6.1.3.11.1 frequency setup camera pll is the only one pll that is frequency adjustable. the register used to control the cpll output frequency is cpll_fbdiv, which providing 6-bit to control pll feedback divider. please refer to the register table for detail 6.1.3.11.2 programmable biasing current the plls feature providing 5-bit 32-level programmable current to bias internal analog blocks. the 5-bits registers cali [4:0] is coded with 2?s complement format. 6.1.3.12 32-khz crystal oscillator register setup for registers that control the oscillator, please refer to chapter ?real time clock? and ?software power down control?. xosccali[4:0] is the calibration control registers of the bias current, and is coded with 2?s complement format. cl is the parallel combination of c1 and c2 in the block diagram. 6.2 clocks there are two major time bases in the MT6516. for the faster one is the 13 mhz clock originating from an off- chip temperature-compensated voltage controlled oscillator (tcvcxo) that can be either 13mhz or 26mhz. this signal is the input from the sysclk pad then is converted to the square-wave signal. the other time base is the 32768 hz clock generated by an on-chip oscillator connected to an external crystal. figure 152 shows the clock sources as well as their utilizations inside the chip. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1473 of 1535 figure 152 clock distributions inside the MT6516 6.2.1 32.768 khz time base the 32768 hz clock is always running. it?s mainly used as the time base of the real time clock (rtc) module, which maintains time and date with counters. therefore, both the 32768hz oscillator and the rtc module is powered by separate voltage supplies that shall not be powered down when the other supplies do. in low power mode, the 13 mhz time base is turned off, so the 32768 hz clock shall be employed to update the critical tdma timer and watchdog timer. this time base is also used to clocks the keypad scanner logic. 6.2.2 13 mhz time base one 1/2-dividers for pll existing to allow using 26 or 13 mhz tcvcxo. one phase-locked loops (mpll) to generate 104mhz and 416mhz, for two clocks, dsp_clock and mcu_clock, respectively. these two primary clocks then feed to dsp clock domain and mcu clock domain, respectively. another phase-locked loop (upll) is to generate 48mhz for the two clocks, usb_clock and irda_clock, respectively. the pll require no off-chip components for operations and can be turn off in order to save power. after power-on, the plls are off by default and the source clock signal is selected through multiplexers. the free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1474 of 1535 software shall take cares of the pll lock time while changing the clock selections. the pll and usages are listed below. upll supplies two clock source usb system clock, usb_clock . the 48mhz is sent to usb module for its operation. irda system clock, irda_clock . the 48mhz is sent to irda module for its operation. mpll supplies two clock source dsp system clock, dsp_clock . the outputted 182mhz clock is connected to dsp dcm (dynamic clock manager) for dynamically adjusting clock rate by digital clock divider. mcu system clock, mcu_clock , which paces the operations of the mcu cores, mcu memory system, and mcu peripherals as well. the outputted 416mhz clock is connected to arm dcm and ahb dcm for dynamically adjusting clock rate by digital clock divider. the usage of dcm is described in mcuclk_con registers of config. cpll supplies one clock source camera clock, cam_clock . the outputted 104~208mhz clock is connected to a digital clock divider to get 13~208mhz clock for camera system. tpll supplies one clock source tv system clock, tv_clock . the outputted 27mhz clock is connected to tv-out dac. cevapll supplies one clock source ceva dsp system clock, ceva dsp_clock . the outputted 104mhz~416mhz clock is connected to ceva dsp domain. mcpll supplies one clock source memory card system clock, mc clock . the outputted 91mhz clock is connected to memory card control unit. note that pll need some time to become stable after being powered up. the software shall take cares of the pll lock time before switching them to the proper frequency. usually, a software loop longer than the pll lock time is employed to deal with the problem. for power management, the mcu software program may stop mcu clock by setting the sleep control register. any interrupt requests to mcu can pause the sleep mode, and thus mcu return to the running mode. ahb also can be stop by setting the sleep control register. however the behavior of ahb in sleep mode is a little different from that of mcu. after entering sleep mode, it can be temporarily waken up by any ?hreq? (bus request), and then goes back to sleep automatically after all ?hreqs? de-assert. any transactions can take place as usual in sleep mode, and it can save power while there is no transaction on it. however the penalty is losing a little system efficiency for switching on and off bus clock, but the impact is small. 6.2.3 dynamic clock switch of mcu clock dynamic clock manager is implemented to allow mcu and dsp switching clock dynamically without any jitter, and enabling signal drift, and system can operate stably during any clock rate switch. before switching to pll clocks, th e clock from pll div2 will feed th rough dynamic clock manager (dcm) directly. that means if pll div2 is enabled, the internal clock rate is the half of sysclk. contrarily, the internal clock rate is identical to sysclk. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1475 of 1535 however, the settings of some hardware modules are required to be changed before or after clock rate change. software has the responsibility to change them at proper timing. the following table is list of hardware modules needed to be changed their setting during clock rate change. module name programming sequence nand 1. low clock speed -> high clock speed changing wait state before clock change. new wait state will not take effect until current emi access is complete. software should insert a period of time before switching clock. 2. high clock speed -> low clock speed changing wait state after clock change. lcd change wait state while lcd in idle state. table 154 programming sequence during clock switch 6.2.4 standard pll power-on sequence *pdn_con = 0x1e // power-on mpll(dpll), upll *cevapll2 = 0x1f // power-on cevapll *clk_con = 0x83 // switch to 13mhz for pll input frequency // after power-on pll..... *upll = 0x0080; // reset upll *mpll = 0x0080; // reset mpll *cevapll = 0x0800; // reset cevapll *upll = 0x0000; // release upll reset *mpll = 0x0000; // release mpll reset *cevapll = 0x0000; // release cevapll reset for (i=0;i<200;i++); *clk_con = 0x00f3; // select pll outputs 6.2.5 register definitions table2 list clock and pll control registers and their address mapping to the mcu address space. the clock and pll control register addresses starts from the base address 0x80060000. register address register function acronym 0x80060010 power-down control register pdn_con 0x80060014 clock control register clk_con 0x80060018 reserved. - 0x8006001c reserved. - 0x80060020 mcu (dsp) pll control register mpll 0x80060024 mcu (dsp) pll control register 2 mpll2 0x80060028 reserved. - 0x8006002c reserved. - 0x80060030 usb pll control register upll 0x80060034 usb pll control register 2 upll2 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1476 of 1535 0x80060038 camera pll control register cpll 0x8006003c camera pll control register 2 cpll2 0x80060040 tv pll control register tpll 0x80060044 tv pll control register 2 tpll2 0x80060048 camera pll control register 3 cpll3 0x8006004c pll reserved control register 0 pll_res_con0 0x80060050 pll bias control register pll_bias 0x80060054 reserved. - 0x80060058 memory card pll control register mcpll 0x8006005c memory card pll control register 2 mcpll2 0x80060060 ceva pll control register cevapll 0x80060064 ceva pll control register 2 cevapll2 0x80060070 pll idn control register pll_idn 0x8006007c xosc32 analog circuit control register xosc32_ac_con table 155 clock/pll control registers 0x80060010 power-down control pdn_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name upll_ pwdb dpll_ pwdb mpll_ pwdb clks q_pw db clks q_div 2_pw d type r/w r/w r/w r/w r/w reset 0 0 0 1 0 clksq_div2_pwd control clksq divide-by-2 power-down (active-high) 0 power-on 1 power-down clksq_pwdb control clksq power-down. (active-low) (default on) 0 power-down 1 power-on mpll_pwdb control mcu pll power-down for mcu clock (active-low) 0 power-down 1 power-on dpll_pwdb control dsp pll power-down for dsp clock (active-low) 0 power-down 1 power-on upll_pwdb control usb pll power-down for usb clock and mpll clock source. (active-low) 0 power-down free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1477 of 1535 1 power-on 0x80060014 clock control register clk_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name clks q_byp srcc lk uplls el dplls el mpllsel clks q_pld clks q_div 2_mcu clks q_div 2_dsp type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 00 0 0 0 clksq_div2_dsp control the clock divider for dsp clock domain 0 divider bypassed 1 divider not bypassed clksq_div2_mcu control the x2 clock divider for mcu clock domain 0 divider bypassed 1 divider not bypassed clksq_pld pull down control (for debug only) 0 disable 1 enables mpllsel select mcu clock source. using this mux to gate out unstable clock output from pll after system boot up 00 pll bypassed, using clk from clksq, default value after chip power up. 01 pll bypassed, using clk from sysclk 10 using pll clock for mcu 11 reserved dpllsel select dsp clock source. using this mux to gate out unstable clock output from pll after system boot up 0 pll bypassed, using clk from clksq 1 using pll clock for dsp upllsel select usb clock source. using this mux to gate out unstable clock output from pll after system boot up 0 pll bypassed, using clk from clksq 1 using pll clock for usb srcclk off-chip temperature-compensated voltage controlled oscillator (tcvcxo) frequency identifier. 0 13mhz 1 26mhz clksq_byp clksq bypass test mode (for debug only) 0 disable 1 enables 0x80060020h mcu (dsp) pll control register mpll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpll_ vcoc alok mpll_cp_p mpll_ rst mpll_cm type r r/w r/w r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1478 of 1535 reset - 000 0 0000 mpll_vcocalok mpll vcoband calibration ok 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective when mpll_vcocal_en (in register mpll2) is high. mpll_cp_p mpll bandwidth control (for debug only) mpll_rst reset control of mpll 0 normal operation 1 reset the pll mpll_cm mpll capacitor multiplier ratio (for debug only) 0x80060024h mcu (dsp pll) control register 2 mpll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpll_tmonclksel mpll_ relat chen mpll_vcovt sel mpll_vcoca lselb mpll_vcoca lsela mpll_ vcoc al_en mpll_vcoband type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 mpll_tmonclksel mpll testmode clock selection (for debug only) mpll_relatchen mpll feedback divider relatch function enable (for debug only) mpll_vcovtsel mpll vcocal slicer voltage selection (for debug only) mpll_vcocalselb mpll vcocal period b selection (for debug only) mpll_vcocalsela mpll vcocal period a selection (for debug only) mpll_vcocal_en mpll vcocal function enable. 0 disable. 1 enable. (default). mpll_vcoband mpll vco band selection (for debug only) 0x80060028h mcu (dsp pll) control register 3 mpll3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mpll_fbdiv type r/w reset 011110 mpll_fbdiv mpll feedback divider ratio control in analog part. divider ratio= mpll_fbdiv[5:0] + 2. analog frequency = 13mhz * (mpll_fbdiv+2). *** mpll_fbdiv_should range from 6?d26 to 6?d34 (364mhz ~ 468mhz) 0x80060030h usb pll control register upll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name upll_ vcoc alok upll_cp_p upll_ rst upll_cm type r r/w r/w r/w reset - 000 0 0000 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1479 of 1535 upll_vcocalok upll vcoband calibration ok 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective when upll_vcocal_en (in register upll2) is high. upll_cp_p upll bandwidth control (for debug only) upll_rst reset control of upll 0 normal operation 1 reset the pll upll_cm upll capacitor multiplier ratio 0x80060034h usb pll control register 2 upll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name upll_tmonclksel upll_ relat chen upll_vcovt sel upll_vcoca lselb upll_vcoca lsela upll_ vcoc al_en upll_vcoband type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 upll_tmonclksel upll testmode clock selection (for debug only) upll_relatchen upll feedback divider relatch function enable (for debug only) upll_vcovtsel upll vcocal slicer voltage selection (for debug only) upll_vcocalselb upll vcocal period b selection (for debug only) upll_vcocalsela upll vcocal period a selection (for debug only) upll_vcocal_en upll vcocal function enable (for debug only) 0 disable. 1 enable. (default). upll_vcoband upll vco band selection (for debug only) 0x80060038h camera pll control register cpll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cpll_ vcoc alok cpll_cp_p cpll_ rst cpll_fbdiv cpll_cm type r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset - 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 cpll is a pll dedicated for output clock feeding to backend module. the pll clock range from 13mhz to 208mhz with step of 3.25mhz. in view of analog block, it only provides clocks from 104mhz to 208mhz, controlled by cpll_fbdiv. as for the lower frequency range (13mhz ~ 104mhz), it is derived with aid of digital divider, controlled by cpll_digdiv (please see register ?cpll3? for details). for example, to derive 104mhz, software can make decision that analog block directly give 104mhz, or generate 208mhz then digitally divided by 2 cpll_vcocalok cpll vcoband calibration ok 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective when cpll_vcocal_en (in register cpll2) is high. cpll_cp_p cpll bandwidth control (for debug only) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1480 of 1535 cpll_rst reset control of cpll 0 normal operation 1 reset the pll cpll_fbdiv cpll feedback divider ratio control in analog part. divider ratio= cpll_fbdiv[5:0] + 2. analog frequency = 3.25mhz x (cpll_fbdiv+2). cpll_fbdiv_should range from 30 to 62. cpll_cm cpll capacitor multiplier ratio (for debug only) 0x8006003ch camera pll control register 2 cpll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cpll_tmonclksel cpll_ relat chen cpll_vcovt sel cpll_vcoca lselb cpll_vcoca lsela cpll_ vcoc al_en cpll_vcoband cpll_ pwdb type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 cpll_tmonclksel cpll testmode clock selection (for debug only) cpll_relatchen cpll feedback divider relatch function enable (for debug only) cpll_vcovtsel cpll vcocal slicer voltage selection (for debug only) cpll_vcocalselb cpll vcocal period b selection (for debug only) cpll_vcocalsela cpll vcocal period a selection (for debug only) cpll_vcocal_en cpll vcocal function enable (for debug only) 0 disable. 1 enable. (default). cpll_vcoband cpll vco band selection (for debug only) cpll_pwdb control cpll power-down (active-low) 0 power-down 1 power-on 0x80060048h camera pll control register 3 cpll3 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cpll_digdiv type r/w r/w r/w r/w reset 0 0 0 0 cpll_digdiv camera pll divider in digital part. it should range within {0, 1, 3, 7, 15}. 0000 output camera pll?s output directly, i.e. divided by 1. 0001 divided by 2. 0011 divided by 4. 0111 divided by 8. 1111 divided by 16. 0x80060040h tv pll control register tpll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tpll_ vcoc alok tpll_cp_p tpll_ rst tpll_cm type r r/w r/w r/w r/w r/w r/w r/w r/w reset - 0 0 0 0 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1481 of 1535 tpll_vcocalok tpll vcoband calibration ok 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective when tpll_vcocal_en (in register tpll2) is high. tpll_cp_p tpll bandwidth control (for debug only) tpll_rst reset control of tpll 0 normal operation 1 reset the pll tpll_cm tpll capacitor multiplier ratio (for debug only) 0x80060044h tv pll control register 2 tpll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tpll_tmonclksel tpll_ relat chen tpll_vcovt sel tpll_vcoca lselb tpll_vcoca lsela tpll_ vcoc al_en tpll_vcoband tpll_ pwdb type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 tpll_tmonclksel tpll testmode clock selection (for debug only) tpll_relatchen tpll feedback divider relatch function enable (for debug only) tpll_vcovtsel tpll vcocal slicer voltage selection (for debug only) tpll_vcocalselb tpll vcocal period b selection (for debug only) tpll_vcocalsela tpll vcocal period a selection (for debug only) tpll_vcocal_en tpll vcocal function enable (for debug only) 0 disable. 1 enable. (default). tpll_vcoband tpll vco band selection (for debug only) tpll_pwdb control tpll power-down (active-low) 0 power-down 1 power-on 0x80060058h memory card pll control register mcpll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mcpl l_vco calo k mcpll_cp_p mcpl l_rst mcpll_cm type r r/w r/w r/w r/w r/w r/w r/w r/w reset - 0 0 0 0 0 0 0 0 mcpll is a pll dedicated for output clock feeding to the memory card module. in view of analog block, it only provides 91mhz clock. mcpll_vcocalok mcpll vcoband calibration ok 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective whenm cpll_vcocal_en (in register mcpll2) is high. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1482 of 1535 mcpll_cp_p mcpll bandwidth control (for debug only) mcpll_rst reset control of mcpll 0 normal operation 1 reset the pll mcpll_cm mcpll capacitor multiplier ratio (for debug only) 0x8006005ch memory card pll control register 2 mcpll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name mcpll_tmonclksel mcpl l_rel atch en mcpll_vcov tsel mcpll_vcoc alselb mcpll_vcoc alsela mcpl l_vco cal_e n mcpll_vcoband mcpl l_pw db type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 mcpll_tmonclksel mcpll testmode clock selection (for debug only) mcpll_vcovtsel mcpll vcocal slicer voltage selection (for debug only) mcpll_vcocalselb mcpll vcocal period b selection (for debug only) mcpll_vcocalsela mcpll vcocal period a selection (for debug only) mcpll_vcocal_en mcpll vcocal function enable (for debug only) 0 disable. 1 enable. (default). mcpll_vcoband mcpll vco band selection (for debug only) mcpll_pwdb control mcpll power-down (active-low) 0 power-down 1 power-on 0x80060060h cevapll control register cevapll bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cevap ll_vc ocal ok cevapll_cp_p ceva pll_r st ceva pll_d igdiv cevapll_fbdiv cevapll_cm type r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 cevapll is a pll dedicated for output clock feeding to the ceva dsp. the pll clock range from 104mhz to 416mhz with step of 13mhz. in view of analog block, it only provides clocks from 208mhz to 416mhz, controlled by cevapll_divctrl. as for the lower frequency range (104mhz ~ 208mhz), it is derived with aid of digital divider, controlled by cevapll_digdiv. for example, to derive 104mhz, software can make decision that analog block gives 208mhz, then digitally divided by 2; or analog block directly give 104mhz clock. cevapll_vcocalok cevapll vcoband calibration ok . 0 pll auto calibration has not done. 1 pll auto calibration is ok. note that this bit is only effective whenm cpll_vcocal_en (in register cevapll2) is high. cevapll_cp_p cevapll bandwidth control (for debug only) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1483 of 1535 cevapll_digdiv ceva pll divider in digital part . 0 output camera pll?s output directly, i.e. divided by 1 1 divided by 2. cevapll_fbdiv cevapll feedback divider ratio control in analog part. divider ratio= mpll_fbdiv[5:0] + 2. analog frequency = 13mhz x (cevapll_fbdiv+2). cevapll_fbdiv_should range from 14 to 30 cevapll_rst reset control of cevapll 0 normal operation 1 reset the pll cevapll_cm cevapll capacitor multiplier ratio (for debug only) 0x80060064h cevapll control register 2 cevapll2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cevapll_tmonclksel ceva pll_r elatc hen cevapll_vc ovtsel cevapll_vc ocalselb cevapll_vc ocalsela ceva pll_v coca l_en cevapll_vcoband ceva pll_p wdb type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 cevapll_tmonclksel cevapll testmode clock selection (for debug only) cevapll_vcovtsel cevapll vcocal slicer voltage selection (for debug only) cevapll_vcocalselb cevapll vcocal period b selection (for debug only) cevapll_vcocalsela cevapll vcocal period a selection (for debug only) cevapll_vcocal_en cevapll vcocal function enable (for debug only) 0 disable. 1 enable. (default). cevapll_vcoband cevapll vco band selection (for debug only) cevapll_pwdb control cevapll power-down (active-low) 0 power-down 1 power-on 0x80060050h pll bias control pll_bias bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_pll_vldo_cali rg_cali_bias clks q_div 2_sel rg_pll_testmode type r/w r/w r/e r/w reset 0000 0000 1 0000 rg_pll_vldo_cali pll ldo calibration. (for debug only) rg_pllbias_cai pll ldo bias calibration. (for debug only) clksq_div2_sel indicator of pll input frequency from clksq. 0 send clksq divided by 1 clock to pll input 1 send clksq divided by 2 clock to pll input rg_pll_testmdoe pll testmode (for debug only) free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1484 of 1535 0x8006004c pll reserved control register 0 pll_res_con 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rg_pll_resb rg_pll_resa type r/w r/w reset 0000 0000 rg_pll_resa[0] mipi macro reference clock source disable. 0 send the 26mhz clock to mipi macro as its reference clock. 1 disable the 26mhz clock to mipi macro. rg_pll_resa[3:1] reserved a-set. (for debug only) rg_pll_resb reserved b-set (for debug only) 0x80060070h idn control idn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name upll_ idn dpll_ idn mpll_ idn clks q_idn type r/w r/w r/w r/w reset 0 0 0 0 the register is for debug usage. in normal function, it can power-on clksq or corresponding pll without regards to srclkena (ie. sleep-mode indication) but still need to set pdn_con at first. in acd test mode, it can power-on corresponding pll directly (clksq excluded), but still need to set pdn_con at first. 0x8006007ch xosc32 analog circuit control xosc32_con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwdb cali type r/w r/w reset 0 00101 the register is for debug usage. only when MT6516 is in stamp mode, these register fields will take effect. pwdb power down xosc32 circuit (active-low). it is only valid when MT6516 is in stamp mode. when MT6516 is in normal mode, xosc32 is always on. 0 power down. 1 power on. cali[4:0] gm value of xosc32 circuit. it is only valid when MT6516 is in stamp mode. when MT6516 is in normal mode, xosc32?s gm value is tied to ?00101?. 6.3 pulse-width modulation outputs 6.3.1 general description six generic pulse-width modulators are implemented to generate pulse sequences with programmable frequency and duration for lcd backlight, charging or other purpose. before enabling pwm, the pulse sequences must be prepared either in the memory or registers. then pwm, as shown in fig. 36, will read the pulse sequences to generate random waveform to meet all kinds of applications. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1485 of 1535 pwm data 32-bit fig. 36 the generation procedure of pwm. there are two basic operational modes about pwm, which is set by pwm_mode. in periodical mode, all pulse sequence with be repeatedly generated by the number of wave_num[15:0]. if wave_num is 0 which means infinite, the waveform generation could be stopped by pwm_en. as for the pulse sequence data source in the periodical mode, if the data are less than or equal to 64 bits, they can be directly set in send_data0[31:0] and send_data1[31:0] and srcsel=0 to reduce memory bandwidth. stop_bitpos[5:0] is used to indicate the stop bit position in the total 64-bits data. for example, if stop_bitpos is 0, only send_data0[0] will be generated, and so on until send_data1[31]. if srcsel=1 which means memory mode, the pulse sequence data are put in memory with address set by buf0_base_addr and the length is buf0_size. stop_bitpos[4:0] is to indicate the stop bit position in the last 32-bits data. the format of pulse sequences that stored in periodical mode is as shown in fig. 37. send data0 64-bit or 32-bit memory send data1 fig. 37 the pulse sequence in periodical mode. on the other hand, the pulse sequence is stored in dual memory buffers in random mode. the format of pulse sequences that stored in the memory is as shown in fig. 38. valid bit is used to indicate data are ready in the respective memory buffer. the pwm generation will clear this bit after all data in that buffer are fetched. the memory buffers are set by address buf0_base_addr and buf0_size for memory buffer0 and buf1_base_addr and buf1_size for memory buffer1. the program should prepare the pulse sequence and set the valid to 1 in time before all data in the other memory buffer are fetched or the hw will issue underflow interrupt to inform pulse generation will be stopped because of no valid data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1486 of 1535 32-bit memory 0 32-bit memory 1 valid 0 valid 1 fig. 38 the pulse sequence in random mode pwm always reference bus block clock (52mhz) as base, and clkdiv[2:0] and clksel can decide the sample rate of each pwm. when system is in the sleep mode, block clock will be disabled and only old_pwm_mode with clksel=1 (32 khz) is supported. only pwm1, pwm2 and pwm3 support old_pwm_mode. for each sample output, the duration is decided by hduration[15:0] when output is high and lduration[15:0] when output is low. if the pulse sequence is repeated which is specified by wave_num[15:0], a special output could be set by guard_value and guard_duration[15:0] between these pulse sequence. the pwm output will be the value specified by idle_value when pwm is not enabled or the pulse sequence is finished. 0 1 send_data0 n send_data1 n guard_duration guard_value hduration lduration 1 0 1 0 1 send_data0 n send_data1 n 1 0 1 idle_value fig. 39 the pulse sequence output pattern in order to provide precise timing relation between different pwm outputs, we provide pwm_seq_mode. in this mode, the starting position of waveform outputs of pwm3, pwm4, pwm5 and pwm6 will follow the previous one by the delay values pwm4_dealy_duration[15:0], pwm5_dealy_duration[15:0] and pwm6_dealy_duration[15:0]. also the clock scale of each delay can be specified by pwm4_delay_clksel, pwm5_delay_clksel and pwm6_delay_clksel. pwm4 pwm3 pwm4_delay_duration pwm5 pwm5_delay_duration pwm6 pwm6_delay_duration fig. 40 the sequential output mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1487 of 1535 also pwm1, pwm2 and pwm3 support original pwm output mode. the output waveform is specified by data_width[12:0] and thresh[12:0]. the output waveform is shown in fig. 41. guard_period guard_value data_width pwm_thresh data_width pwm_thresh fig. 41 the old pwm mode for hardware and system consideration, clksrc might be slightly different in different situations. the following table is to summary all possible situations. ? pwm_old_mode ? pwm_clksel ? clksrc ? 0 ? block clock ? ? 1 ? 1 ? 32 khz ? 0 ? block clock ? ? 0 ? 1 ? block clock / 1625 ? 6.3.2 register table register address register function acronym pwm + 0000h pwm enable register pwm_enable pwm + 0004h pwm4 delay duration register pwm4_delay pwm + 0008h pwm5 delay duration register pwm5_delay pwm + 000ch pwm6 delay duration register pwm6_delay pwm + 0010h pwm1 control register pwm1_con pwm + 0014h pwm1 high duration register pwm1_hduration pwm + 0018h pwm1 low duration register pwm1_lduration pwm + 001ch pwm1 guard duration register pwm1_gduration pwm + 0020h pwm1 buffer0 base address register pwm1_buf0_base_addr pwm + 0024h pwm1 buffer0 size register pwm1_buf0_size pwm + 0028h pwm1 buffer1 base address register pwm1_buf1_base_addr pwm + 002ch pwm1 buffer1 size register pwm1_buf1_size pwm + 0030h pwm1 send data0 register pwm1_send_data0 pwm + 0034h pwm1 send data1 register pwm1_send_data1 pwm + 0038h pwm1 wave number register pwm1_wave_num free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1488 of 1535 pwm + 003ch pwm1 data width pwm1_data_width pwm + 0040h pwm1 threshold register pwm1_thresh pwm + 0044h pwm1 send waveform number register pwm1_send_wavenum pwm + 0048h pwm1 valid register pwm1_valid pwm + 0050h pwm2 control register pwm2_con pwm + 0054h pwm2 high duration register pwm2_hduration pwm + 0058h pwm2 low duration register pwm2_lduration pwm + 005ch pwm2 guard duration register pwm2_gduration pwm + 0060h pwm2 buffer0 base address register pwm2_buf0_base_addr pwm + 0064h pwm2 buffer0 size register pwm2_buf0_size pwm + 0068h pwm2 buffer1 base address register pwm2_buf1_base_addr pwm + 006ch pwm2 buffer1 size register pwm2_buf1_size pwm + 0070h pwm2 send data0 register pwm2_send_data0 pwm + 0074h pwm2 send data1 register pwm2_send_data1 pwm + 0078h pwm2 wave number register pwm2_wave_num pwm + 007ch pwm2 data width pwm2_data_width pwm + 0080h pwm2 threshold register pwm2_thresh pwm + 0084h pwm2 send waveform number register pwm2_send_wavenum pwm + 0088h pwm2 valid register pwm2_valid pwm + 0090h pwm3 control register pwm3_con pwm + 0094h pwm3 high duration register pwm3_hduration pwm + 0098h pwm3 low duration register pwm3_lduration pwm + 009ch pwm3 guard duration register pwm3_gduration pwm + 00a0h pwm3 buffer0 base address register pwm3_buf0_base_addr pwm + 00a4h pwm3 buffer0 size register pwm3_buf0_size pwm + 00a8h pwm3 buffer1 base address register pwm3_buf1_base_addr pwm + 00ach pwm3 buffer1 size register pwm3_buf1_size pwm + 00b0h pwm3 send data0 register pwm3_send_data0 pwm + 00b4h pwm3 send data1 register pwm3_send_data1 pwm + 00b8h pwm3 wave number register pwm3_wave_num pwm + 00bch pwm3 data width pwm3_data_width pwm + 00c0h pwm3 threshold register pwm3_thresh pwm + 00c4h pwm3 send waveform number register pwm3_send_wavenum pwm + 00c8h pwm3 valid register pwm3_valid pwm + 00d0h pwm4 control register pwm4_con pwm + 00d4h pwm4 high duration register pwm4_hduration free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1489 of 1535 pwm + 00d8h pwm4 low duration register pwm4_lduration pwm + 00dch pwm4 guard duration register pwm4_gduration pwm + 00e0h pwm4 buffer0 base address register pwm4_buf0_base_addr pwm + 00e4h pwm4 buffer0 size register pwm4_buf0_size pwm + 00e8h pwm4 buffer1 base address register pwm4_buf1_base_addr pwm + 00ech pwm4 buffer1 size register pwm4_buf1_size pwm + 00f0h pwm4 send data0 register pwm4_send_data0 pwm + 00f4h pwm4 send data1 register pwm4_send_data1 pwm + 00f8h pwm4 wave number register pwm4_wave_num pwm + 00fch pwm4 send waveform number register pwm4_send_wavenum pwm + 0100h pwm4 valid register pwm4_valid pwm + 0110h pwm5 control register pwm5_con pwm + 0114h pwm5 high duration register pwm5_hduration pwm + 0118h pwm5 low duration register pwm5_lduration pwm + 011ch pwm5 guard duration register pwm5_gduration pwm + 0120h pwm5 buffer0 base address register pwm5_buf0_base_addr pwm + 0124h pwm5 buffer0 size register pwm5_buf0_size pwm + 0128h pwm5 buffer1 base address register pwm5_buf1_base_addr pwm + 012ch pwm5 buffer1 size register pwm5_buf1_size pwm + 0130h pwm5 send data0 register pwm5_send_data0 pwm + 0134h pwm5 send data1 register pwm5_send_data1 pwm + 0138h pwm5 wave number register pwm5_wave_num pwm + 013ch pwm5 send waveform number register pwm5_send_wavenum pwm + 0140h pwm5 valid register pwm5_valid pwm + 0150h pwm6 control register pwm6_con pwm + 0154h pwm6 high duration register pwm6_hduration pwm + 0158h pwm6 low duration register pwm6_lduration pwm + 015ch pwm6 guard duration register pwm6_gduration pwm + 0160h pwm6 buffer0 base address register pwm6_buf0_base_addr pwm + 0164h pwm6 buffer0 size register pwm6_buf0_size pwm + 0168h pwm6 buffer1 base address register pwm6_buf1_base_addr pwm + 016ch pwm6 buffer1 size register pwm6_buf1_size pwm + 0170h pwm6 send data0 register pwm6_send_data0 pwm + 0174h pwm6 send data1 register pwm6_send_data1 pwm + 0178h pwm6 wave number register pwm6_wave_num pwm + 017ch pwm6 send waveform number register pwm6_send_wavenum pwm + 0180h pwm6 valid register pwm6_valid free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1490 of 1535 pwm + 0190h pwm interrupt enable register pwm_int_enable pwm + 0194h pwm interrupt status register pwm_int_status pwm + 0198h pwm interrupt acknowledge register pwm_int_ack pwm + 01a0h pwm0 control register pwm0_con pwm + 01a4h pwm0 high duration register pwm0_hduration pwm + 01a8h pwm0 low duration register pwm0_lduration pwm + 01ach pwm0 guard duration register pwm0_gduration pwm + 01b0h pwm0 buffer0 base address register pwm0_buf0_base_addr pwm + 01b4h pwm0 buffer0 size register pwm0_buf0_size pwm + 01b8h pwm0 buffer1 base address register pwm0_buf1_base_addr pwm + 01bch pwm0 buffer1 size register pwm0_buf1_size pwm + 01c0h pwm0 send data0 register pwm0_send_data0 pwm + 01c4h pwm0 send data1 register pwm0_send_data1 pwm + 01c8h pwm0 wave number register pwm0_wave_num pwm + 01cch pwm0 data width pwm0_data_width pwm + 01d0h pwm0 threshold register pwm0_thresh pwm + 01d4h pwm0 send waveform number register pwm0_send_wavenum pwm + 01d8h pwm0 valid register pwm0_valid table 156 pwm registers 6.3.3 register definitions pwm+0000h pwm enable register pwm_enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm_ test_ sel pwm_ seq_ mode pwm6 _en pwm5 _en pwm4 _en pwm3 _en pwm2 _en pwm1 _en pwm0 _en type rw r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 pwm0_en set to 1 to enable pwm0 pwm1_en set to 1 to enable pwm1 pwm2_en set to 1 to enable pwm2 pwm3_en set to 1 to enable pwm3 pwm4_en set to 1 to enable pwm4 pwm5_en set to 1 to enable pwm5 pwm6_en set to 1 to enable pwm6 note : when turning off pwm unit (pwm_en = 1 0), pwm needs some clock periods (32khz or 52mhz clock ) to shut down. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1491 of 1535 pwm_seq_mode set to 1 to enable pwm3, pwm4, pwm5 and pwm6 sequential delay mode. in this mode, pwm3 starts first and then after pwm4_delay_time, pwm4 will start. after pwm4 starts, pwm5 will start after pwm5_delay_time and so on for pwm6. note: the output of pwm_seq_mode is started after pwm3 is enabled. and pwm_seq_mode should be set before pwm4, pwm5 and pwm6 are enabled or at the same time. also this mode doesn?t work when pwm3 is set at old_pwm_mode and clksel=1. pwm_test_sel set to 1 to enable the switch of the pwm output signal between pwm unit1, pwm unit2 and pwm unit5, pwm unit6. the default (0) behavior is to select the output of pwm unit5 and pwm unit6. if set to 1, the output of pwm unit1 will be selected instead of pwm unit5, and the output of pwm unit2 will be selected instead of pwm unit6. pwm+0004h pwm4 delay duration register pwm4_delay bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dela y_cl ksel type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm4_delay_duration[15:0] type r/w reset 0 pwm4_delay_duration the time difference between pwm3 and pwm4. delay_clksel the clock unit of pwm4_delay_duration. 0 clk=clksrc 1 clk=clksrc/1625 pwm+0008h pwm5 delay duration register pwm5_delay bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dela y_cl ksel type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm5_delay_duration[15:0] type r/w reset 0 pwm5_delay_duration the time difference between pwm4 and pwm5. delay_clksel the clock unit of pwm5_delay_duration. 0 clk=clksrc 1 clk=clksrc/1625 pwm+000ch pwm6 delay duration register pwm6_delay bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name dela y_cl ksel free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1492 of 1535 type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm6_delay_duration[15:0] type r/w reset 0 pwm6_delay_duration the time difference between pwm5 and pwm6. delay_clksel the clock unit of pwm6_delay_duration. 0 clk=clksrc 1 clk=clksrc/1625 pwm+0010h pwm1 control register pwm1_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm1 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm1 data source 0 fifo mode 1 memory mode mode select random generator mode 0 periodical pwm mode. 1 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm1 output value when idle state. guard_value pwm1 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. old_pwm_mode use old pwm mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1493 of 1535 0 new pwm mode 1 old pwm mode note: using old pwm mode also means periodical mode. so srcsel and mode is ignored in this situation. only old pwm mode with 32 khz clock source could work in the system sleep-mode. pwm+0014h pwm1 high duration register pwm1_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm1 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+0018h pwm1 low duration register pwm1_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm1 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+001ch pwm1 guard duration register pwm1_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1494 of 1535 pwm+0020h pwm1 buffer0 base address register pwm1_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm1?s waveform data. pwm+0024h pwm1 buffer0 size register pwm1_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm1 should generate. if it equals to n, need to program n-1 in this register. note: the size is in unit of 32-bit data. pwm+0028h pwm1 buffer1 base address register pwm1_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm1?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+002ch pwm1 buffer1 size register pwm1_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1495 of 1535 type r/w reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm1 should generate. if it equals to n, need to program n-1 in this register. pwm+0030h pwm1 send data0 register pwm1_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm1 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0034h pwm1 send data1 register pwm1_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm1 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0038h pwm1 wave number register pwm1_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm1 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1496 of 1535 pwm+003ch pwm1 data width register pwm1_data_ width bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data_width[12:0] type r/w reset 0 data_width the pwm1 pulse data width in the old pwm mode. pwm+0040h pwm1 thresh register pwm1_thres h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thresh[12:0] type r/w reset 0 thresh the pwm1 pulse data high/low switching threshold in the old pwm mode. pwm+0044h pwm1 send wave number register pwm1_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm1 has already generated from the specified data source in the periodical mode. pwm+0048h pwm1 valid register pwm1_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1497 of 1535 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. pwm+0050h pwm2 control register pwm2_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm2 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm2 data source 0 fifo mode 1 memory mode mode select random generator mode 0 periodical pwm mode. 1 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm2 output value when idle state. guard_value pwm2 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. old_pwm_mode use old pwm mode 0 new pwm mode 1 old pwm mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1498 of 1535 note: using old pwm mode also means periodical mode. so srcsel and mode is ignored in this situation. only old pwm mode with 32 khz clock source could work in the system sleep-mode. pwm+0054h pwm2 high duration register pwm2_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm2 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+0058h pwm2 low duration register pwm2_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm2 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+005ch pwm2 guard duration register pwm2_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1499 of 1535 pwm+0060h pwm2 buffer0 base address register pwm2_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm2?s waveform data. pwm+0064h pwm2 buffer0 size register pwm2_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm2 should generate. if it equals to n, need to program n-1 in this register. pwm+0068h pwm2 buffer1 base address register pwm2_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm2?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+006ch pwm2 buffer1 size register pwm2_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1500 of 1535 reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm2 should generate. if it equals to n, need to program n-1 in this register. pwm+0070h pwm2 send data0 register pwm2_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm2 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0074h pwm2 send data1 register pwm2_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm2 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0078h pwm2 wave number register pwm2_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm2 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1501 of 1535 pwm+007ch pwm2 data width register pwm2_data_ width bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data_width[12:0] type r/w reset 0 data_width the pwm2 pulse data width in the old pwm mode. pwm+0080h pwm2 thresh register pwm2_thres h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thresh[12:0] type r/w reset 0 thresh the pwm2 pulse data high/low switching threshold in the old pwm mode. pwm+0084h pwm2 send wave number register pwm2_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm2 has already generated from the specified data source in the periodical mode. pwm+0088h pwm2 valid register pwm2_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1502 of 1535 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. pwm+0090h pwm3 control register pwm3_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm3 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm3 data source 0 fifo mode 1 memory mode mode select random generator mode 0 periodical pwm mode. 1 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm3 output value when idle state. guard_value pwm3 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. old_pwm_mode use old pwm mode 0 new pwm mode 1 old pwm mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1503 of 1535 note: using old pwm mode also means periodical mode. so srcsel and mode is ignored in this situation. only old pwm mode with 32 khz clock source could work in the system sleep-mode. pwm+0094h pwm3 high duration register pwm3_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm3 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+0098h pwm3 low duration register pwm3_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm3 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+009ch pwm3 guard duration register pwm3_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1504 of 1535 pwm+00a0h pwm3 buffer0 base address register pwm3_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm3?s waveform data. pwm+00a4h pwm3 buffer0 size register pwm3_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm3 should generate. if it equals to n, need to program n-1 in this register. pwm+00a8h pwm3 buffer1 base address register pwm3_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm3?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+00ach pwm3 buffer1 size register pwm3_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1505 of 1535 reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm3 should generate. if it equals to n, need to program n-1 in this register. pwm+00b0h pwm3 send data0 register pwm3_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm3 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+00b4h pwm3 send data1 register pwm3_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm3 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+00b8h pwm3 wave number register pwm3_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm3 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1506 of 1535 pwm+00bch pwm3 data width register pwm3_data_ width bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data_width[12:0] type r/w reset 0 data_width the pwm3 pulse data width in the old pwm mode. pwm+00c0h pwm3 thresh register pwm3_thres h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thresh[12:0] type r/w reset 0 thresh the pwm3 pulse data high/low switching threshold in the old pwm mode. pwm+00c4h pwm3 send wave number register pwm3_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm3 has already generated from the specified data source in the periodical mode. pwm+00c8h pwm3 valid register pwm3_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1507 of 1535 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. pwm+00d0h pwm4 control register pwm4_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm4 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm4 data source 0 fifo mode 1 memory mode mode select random generator mode 0 periodical pwm mode. 1 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm4 output value when idle state. guard_value pwm4 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. pwm+00d4h pwm4 high duration register pwm4_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1508 of 1535 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm4 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+00d8h pwm4 low duration register pwm4_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm4 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+00dch pwm4 guard duration register pwm4_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. pwm+00e0h pwm4 buffer0 base address register pwm4_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1509 of 1535 reset 0 buf0_bs_addr the base address of memory buffer0 for pwm4?s waveform data. pwm+00e4h pwm4 buffer0 size register pwm4_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm4 should generate. if it equals to n, need to program n-1 in this register. pwm+00e8h pwm4 buffer1 base address register pwm4_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm4?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+00ech pwm4 buff er1 size register pwm4_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm4 should generate. if it equals to n, need to program n-1 in this register. pwm+00f0h pwm4 send data0 register pwm4_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1510 of 1535 reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm4 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+00f4h pwm4 send data1 register pwm4_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm4 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+00f8h pwm4 wave number register pwm4_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm4 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. pwm+00fch pwm4 send wave number register pwm4_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1511 of 1535 send_wavenum the number by which pwm4 has already generated from the specified data source in the periodical mode. pwm+0100h pwm4 valid register pwm4_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. pwm+0110h pwm5 control register pwm5_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm5 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm5 data source 0 fifo mode 2 memory mode free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1512 of 1535 mode select random generator mode 2 periodical pwm mode. 3 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm5 output value when idle state. guard_value pwm5 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. pwm+0114h pwm5 high duration register pwm5_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm5 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+0118h pwm5 low duration register pwm5_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm5 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+011ch pwm5 guard duration register pwm5_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1513 of 1535 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. pwm+0120h pwm5 buffer0 base address register pwm5_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm5?s waveform data. pwm+0124h pwm5 buffer0 size register pwm5_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm5 should generate. if it equals to n, need to program n-1 in this register. pwm+0128h pwm5 buffer1 base address register pwm5_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm5?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+012ch pwm5 buffer1 size register pwm5_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1514 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm5 should generate. if it equals to n, need to program n-1 in this register. pwm+0130h pwm5 send data0 register pwm5_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm5 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0134h pwm5 send data1 register pwm5_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm5 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0138h pwm5 wave number register pwm5_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm5 will generate from the pulse data repeatedly. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1515 of 1535 note: if wave_num=0, the waveform generation will not stop until it is disabled. pwm+013ch pwm5 send wave number register pwm5_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm5 has already generated from the specified data source in the periodical mode. pwm+0140h pwm5 valid register pwm5_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. pwm+0150h pwm6 control register pwm6_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm6 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1516 of 1535 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm1 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm6 data source 0 fifo mode 3 memory mode mode select random generator mode 4 periodical pwm mode. 5 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm6 output value when idle state. guard_value pwm6 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. pwm+0154h pwm6 high duration register pwm6_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 hduration pwm6 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+0158h pwm6 low duration register pwm6_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm6 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1517 of 1535 note: the duration of pwm must not be 0. pwm+015ch pwm6 guard duration register pwm6_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. pwm+0160h pwm6 buffer0 base address register pwm6_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm6?s waveform data. pwm+0164h pwm6 buffer0 size register pwm6_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm6 should generate. if it equals to n, need to program n-1 in this register. pwm+0168h pwm6 buffer1 base address register pwm6_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1518 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm6?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+016ch pwm6 buffer1 size register pwm6_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm6 should generate. if it equals to n, need to program n-1 in this register. pwm+0170h pwm6 send data0 register pwm6_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm6 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+0174h pwm6 send data1 register pwm6_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm6 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1519 of 1535 pwm+0178h pwm6 wave number register pwm6_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm6 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. pwm+017ch pwm6 send wave number register pwm6_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm6 has already generated from the specified data source in the periodical mode. pwm+0180h pwm6 valid register pwm6_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1520 of 1535 pwm+0190h pwm interrupt enable register pwm_int_ena ble bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm6 _int_ unde rflo w_en pwm6 _int_f inish_ en pwm5 _int_ unde rflo w_en pwm5 _int_f inish_ en pwm4 _int_ unde rflo w_en pwm4 _int_f inish_ en pwm3 _int_ unde rflo w_en pwm3 _int_f inish_ en pwm2 _int_ unde rflo w_en pwm2 _int_f inish_ en pwm1 _int_ unde rflo w_en pwm1 _int_f inish_ en pwm0 _int_ unde rflo w_en pwm0 _int_f inish_ en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pwm0_int_finish_en set to 1 to enable pwm0 finish interrupt pwm0_int_underflow_en set to 1 to enable pwm0 underflow interrupt pwm1_int_finish_en set to 1 to enable pwm1 finish interrupt pwm1_int_underflow_en set to 1 to enable pwm1 underflow interrupt pwm2_int_finish_en set to 1 to enable pwm2 finish interrupt pwm2_int_underflow_en set to 1 to enable pwm2 underflow interrupt pwm3_int_finish_en set to 1 to enable pwm3 finish interrupt pwm3_int_underflow_en set to 1 to enable pwm3 underflow interrupt pwm4_int_finish_en set to 1 to enable pwm4 finish interrupt pwm4_int_underflow_en set to 1 to enable pwm4 underflow interrupt pwm5_int_finish_en set to 1 to enable pwm5 finish interrupt pwm5_int_underflow_en set to 1 to enable pwm5 underflow interrupt pwm6_int_finish_en set to 1 to enable pwm6 finish interrupt pwm6_int_underflow_en set to 1 to enable pwm6 underflow interrupt note: interrupt can not be supported when 32khz clock. (old_mode = 1, clksel = 1) pwm+0194h pwm interrupt status register pwm_int_sta tus bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm6 _int_ unde rflo w_st pwm6 _int_f inish_ st pwm5 _int_ unde rflo w_st pwm5 _int_f inish_ st pwm4 _int_ unde rflo w_st pwm4 _int_f inish_ st pwm3 _int_ unde rflo w_st pwm3 _int_f inish_ st pwm2 _int_ unde rflo w_st pwm2 _int_f inish_ st pwm1 _int_ unde rflo w_st pwm1 _int_f inish_ st pwm0 _int_ unde rflo w_st pwm0 _int_f inish_ st type r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pwm0_int_finish_st pwm0 finish status pwm0_int_underflow_st pwm0 underflow status pwm1_int_finish_st pwm1 finish status free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1521 of 1535 pwm1_int_underflow_st pwm1 underflow status pwm2_int_finish_st pwm2 finish status pwm2_int_underflow_st pwm2 underflow status pwm3_int_finish_st pwm3 finish status pwm3_int_underflow_st pwm3 underflow status pwm4_int_finish_st pwm4 finish status pwm4_int_underflow_st pwm4 underflow status pwm5_int_finish_st pwm5 finish status pwm5_int_underflow_st pwm5 underflow status pwm6_int_finish_st pwm6 finish status pwm6_int_underflow_st pwm6 underflow status note: the interrupt status will be auto-cleared if interrupt enable or pwm enable is cleared. pwm+0198h pwm interrupt acknowledge register pwm_int_ack bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pwm6 _int_ unde rflo w_ac k pwm6 _int_f inish_ ack pwm5 _int_ unde rflo w_ac k pwm5 _int_f inish_ ack pwm4 _int_ unde rflo w_ac k pwm4 _int_f inish_ ack pwm3 _int_ unde rflo w_ac k pwm3 _int_f inish_ ack pwm2 _int_ unde rflo w_ac k pwm2 _int_f inish_ ack pwm1 _int_ unde rflo w_ac k pwm1 _int_f inish_ ack pwm0 _int_ unde rflo w_ac k pwm0 _int_f inish_ ack type w w w w w w w w w w w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pwm0_int_finish_ack set to 1 to clear pwm0 finish interrupt pwm0_int_underflow_ack set to 1 to clear pwm0 underflow interrupt pwm1_int_finish_ack set to 1 to clear pwm1 finish interrupt pwm1_int_underflow_ack set to 1 to clear pwm1 underflow interrupt pwm2_int_finish_ack set to 1 to clear pwm2 finish interrupt pwm2_int_underflow_ack set to 1 to clear pwm2 underflow interrupt pwm3_int_finish_ack set to 1 to clear pwm3 finish interrupt pwm3_int_underflow_ack set to 1 to clear pwm3 underflow interrupt pwm4_int_finish_ack set to 1 to clear pwm4 finish interrupt pwm4_int_underflow_ack set to 1 to clear pwm4 underflow interrupt pwm5_int_finish_ack set to 1 to clear pwm5 finish interrupt pwm5_int_underflow_ack set to 1 to clear pwm5 underflow interrupt pwm6_int_finish_ack set to 1 to clear pwm6 finish interrupt pwm6_int_underflow_ack set to 1 to clear pwm6 underflow interrupt pwm+01a0h pwm0 control register pwm0_con bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1522 of 1535 reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name old_p wm_m ode stop_bitpos[5:0] guar d_val ue idle_ value mode srcs el clkse l clkdiv [2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 3fh 0 0 0 0 0 0 clkdiv select pwm0 clock scale. 000 clk hz 001 clk/2 hz 010 clk/4 hz 011 clk/8 hz 100 clk/16 hz 101 clk/32 hz 110 clk/64 hz 111 clk/128 hz clksel select pwm0 clock 0 clk=clksrc 1 clk=clksrc/1625 srcsel select pwm0 data source 0 fifo mode 2 memory mode mode select random generator mode 2 periodical pwm mode. 3 random pwm mode note: when using random generator mode, the data source comes from dual buffers in memory. idle_value pwm0 output value when idle state. guard_value pwm0 output value when guard time. stop_bitpos the stop bit position for source data in periodical mode. in fifo mode, it?s used to indicate the stop bit position in total 64 bits. in memory mode, it?s for the stop bit position in the last 32 bits. old_pwm_mode use old pwm mode 2 new pwm mode 3 old pwm mode note: using old pwm mode also means periodical mode. so srcsel and mode is ignored in this situation. only old pwm mode with 32 khz clock source could work in the system sleep-mode. pwm+01a4h pwm0 high duration register pwm0_hdura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name hduration[15:0] type r/w reset 1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1523 of 1535 hduration pwm0 pulse duration based on the current clock when pwm output is high. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+01a8h pwm0 low duration register pwm0_ldura tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name lduration[15:0] type r/w reset 1 lduration pwm0 pulse duration based on the current clock when pwm output is low. if duration =n, need to program n-1 in this register. note: the duration of pwm must not be 0. pwm+01ach pwm0 guard duration register pwm0_gdrua tion bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guard_duration[15:0] type r/w reset 0 guard_duration it?s the guarding interval between individual waveforms and the output is decided by guard_value. also if it equals to n, it needs to program n-1 in this register. note: if this duration is 0, it means no guarding interval. pwm+01b0h pwm0 buffer0 base address register pwm0_buf0_bas e_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf0_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_bs_addr[15:0] type r/w reset 0 buf0_bs_addr the base address of memory buffer0 for pwm0?s waveform data. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1524 of 1535 pwm+01b4h pwm0 buffer0 size register pwm0_buf0_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf0_size[15:0] type r/w reset 0 buf0_size the length of the waveform data in memory buffer0 that pwm0 should generate. if it equals to n, need to program n-1 in this register. note: the size is in unit of 32-bit data. pwm+01b8h pwm0 buffer1 base address register pwm0_buf1_ _base_ addr bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name buf1_bs_addr[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_bs_addr[15:0] type r/w reset 0 buf1_bs_addr the base address of memory buffer1 for pwm0?s waveform data. note: the memory buffer1 is useless in periodical mode. pwm+01bch pwm0 buffer1 size register pwm0_buf1_s ize bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_size[15:0] type r/w reset 0 buf1_size the length of the waveform data in memory buffer1 that pwm0 should generate. if it equals to n, need to program n-1 in this register. pwm+01c0h pwm0 send data0 register pwm0_send_dat a0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data0 [31:16] type r/w reset 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1525 of 1535 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data0[15:0] type r/w reset 0 send_data0 pwm0 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+01c4h pwm0 send data1 register pwm0_send_dat a1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name send_data1[31:16] type r/w reset 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_data1[15:0] type r/w reset 0 send_data1 pwm0 local buffer0 of pulse sequence data to be generated. note: this value should be written only in periodically fifo mode. in other mode, this buffer is for internal memory access. pwm+01c8h pwm0 wave number register pwm0_wave_ num bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wave_num[15:0] type r/w reset 0 wave_num the number by which pwm0 will generate from the pulse data repeatedly. note: if wave_num=0, the waveform generation will not stop until it is disabled. pwm+01cch pwm0 data width register pwm0_data_ width bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name data_width[12:0] type r/w reset 0 data_width the pwm0 pulse data width in the old pwm mode. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1526 of 1535 pwm+01d0h pwm0 thresh register pwm0_thres h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name thresh[12:0] type r/w reset 0 thresh the pwm0 pulse data high/low switching threshold in the old pwm mode. pwm+01d4h pwm0 send wave number register pwm0_send_ wavenum bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name send_wavenum[15:0] type ro reset 0 send_wavenum the number by which pwm0 has already generated from the specified data source in the periodical mode. pwm+01d8h pwm0 valid register pwm0_valid bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name type reset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name buf1_ valid _wen buf1_ valid buf0_ valid _wen buf0_ valid type w r/w w r/w reset 0 0 0 0 buf0_valid the valid status is used to indicate pulse data in memory buffer0 is ready. buf0_valid_wen this bit must be set to modify buf0_valid. buf1_valid the valid status is used to indicate pulse data in memory buffer1 is ready. buf1_valid_wen this bit must be set to modify buf1_valid. note: the program should set these bits after data are prepared in memory. the hw will clear these bits after it has used all data in the specified memory. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1527 of 1535 6.4 real time clock 6.4.1 general description the real time clock (rtc) module provides time and data information. the clock is based on a 32.768khz oscillator with an independent power supply. when the mobile handset is powered off, a dedicated regulator supplies the rtc block. if the main battery is not present, a backup supply such as a small mercury cell battery or a large capacitor is used. in addition to providing timing data, an alarm interrupt is generated and can be used to power up the baseband core via the bbwakeup pin. regulator interrupts corresponding to seconds, minutes, hours and days can be generated whenever the time counter value reaches a maximum value (e.g., 59 for seconds and minutes, 23 for hours, etc.). the year span is supported up to 2127. the maximum day-of-month values, which depend on the leap year condition, are stored in the rtc block. 6.4.2 register definitions register address register name synonym rtc+0000h baseband power up rtc_bbpu rtc+0004h rtc irq status rtc_irq_sta rtc+0008h rtc irq enable rtc_irq_en rtc+000ch counter increment irq enable rtc_cii_en rtc+0010h rtc alarm mask rtc_al_mask rtc+0014h rtc seconds time counter register rtc_tc_sec rtc+0018h rtc minutes time counter register rtc_tc_min rtc+001ch rtc hours time counter register rtc_tc_hou rtc+0020h rtc day-of-month time counter register rtc_tc_dom rtc+0024h rtc day-of-week time counter register rtc_tc_dow rtc+0028h rtc month time counter register rtc_tc_mth rtc+002ch rtc year time counter register rtc_tc_yea rtc+0030h rtc second alarm setting register rtc_al_sec rtc+0034h rtc minute alarm setting register rtc_al_min rtc+0038h rtc hour alarm setting register rtc_al_hou rtc+003ch rtc day-of-month alarm setting register rtc_al_dom rtc+0040h rtc day-of-week alarm setting register rtc_al_dow rtc+0044h rtc month alarm setting register rtc_al_mth rtc+0048h rtc year alarm setting register rtc_al_yea rtc+004ch xosc bias current control register rtc_xosccali rtc+0050h rtc_powerkey1 register rtc_powerkey1 rtc+0054h rtc_powerkey2 register rtc_powerkey2 rtc+0058h pdn1 rtc_pdn1 rtc+005ch pdn2 rtc_pdn2 rtc+0064h spare register for specific purpose rtc_spar1 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1528 of 1535 rtc+0068h lock / unlock scheme to prevent rtc miswriting rtc_prot rtc+006ch one-time calibration offset rtc_diff rtc+0074h enable the transfers from core to rtc in the queue rtc_wrtgr table 157 rtc register map rtc+0000h baseband power up rtc_bbpu bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name key_bbpu dbing cbus y relo ad clrp ky auto bbpu write_e n pwre n type wo ro ro wo wo r/w r/w r/w r/w key_bbpu a bus write is acceptable only when key_bbpu=0x43. dbing this bit indicates rtc is still de-bouncing. cbusy the read/write channels between rtc / core is busy. this bit indicates high after software program sequence to anyone of rtc data registers and enable the transfer by rtc_wrtgr=1. by the way, it is high after the reset from low to high because rtc reload process. notice: the cbusy is always high in lock mode (powerkeys not match), please refer to the timeout period in rtc sop documents. reload reload the values from rtc domain to core domain. generally speaking, rtc will reload synchronize the data from rtc to core when reset from 0 to 1. this bit can be treated as debug bit. clrpky clear powerkey1 and powerkey2 at the same time. in some cases, software may clear powerkey1 & powerkey2. the bbwakeup depends on the matching specific patterns of powerkey1 and powerkey2. if any one of powerkey1 or powerkey2 or bbpu is cleared, bbwakeup goes low immediately. software can?t program the other control bits without power. by program rtc_bbpu with clrpky=1 and bbpu=0 condition, rtc can clear powerkey1, powerkey2 and bbpu at the same moment. auto controls if bbwakeup is automatically in the low state when sysrst# transitions from high to low . 0 bbwakeup is not automatically in the low state when sysrst# transitions from high to low. 1 bbwakeup is automatically in the low state when sysrst# transitions from high to low. bbpu controls the power of pmic. if powerkey1=a357h and powerkey2=67d2h, pmic takes on the value programmed by software; otherwise pmic is low. 0 power down 1 power on write_en when write_en is write 0 by the mcu, the rtc programing interface is disabled immediately (mcu can't program rtc). after the debounce counter is time-out, the interface enabled again (mcu can program rtc). the debounce counter time-out period is decided by rtc_pdn1. note that the write_en value read out is meaningless. the hardware only care about the "write-0 action" to write_en control bit. when write_en==0, avoid to "read out rtc_bbpu, and/or something and write back", like this -> *rtc_bbpu=*rtc_bbpu|rtc_bbpu_key|0x1. this would disable rtc write interface for a while and hard to debug. pwren 0 rtc alarm has no action on power switch. 1 when an rtc alarm occurs, bbpu is set to 1 and the system powers on by rtc alarm wakeup. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1529 of 1535 rtc+0004h rtc irq status rtc_irq_sta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tcsta alst a type r/c r/c alsta this register indicates the irq status and whether or not the alarm condition has been met. 0 no irq occurred; the alarm condition has not been met. 1 irq occurred; the alarm condition has been met. tcsta this register indicates the irq status and whether or not the tick condition has been met. 0 no irq occurred; the tick condition has not been met. 1 irq occurred; the tick condition has been met. rtc+0008h rtc irq enable rtc_irq_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name onesho t tc_en al_en type r/w r/w r/w the function is only active when rtc_powerkey1 & rtc_powerkey2 match the correct values. oneshot controls automatic reset of al_en and tc_en. al_en this register enables the control bit for irq generation if the alarm condition has been met. 0 disable irq generations. 1 enable the alarm time match interrupt. clear the interrupt when oneshot is high upon generation of the corresponding irq. tc_en this register enables the control bit for irq generation if the tick condition has been met. 0 disable irq generations. 1 enable the tick time match interrupt. clear the interrupt when oneshot is high upon generation of the corresponding irq. rtc+000ch counter incremen t irq enable rtc_cii_en bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name 1/8sec cii 1/4sec cii 1/2sec cii yeacii mthci i dowc ii domci i houci i mincii secci i type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this register activates or de-activates the irq generation when the tc counter reaches its maximum value. seccii set this bit to 1 to activate the irq at each second update. mincii set the bit to 1 to activate the irq at each minute update. houcii set the bit to 1 to activate the irq at each hour update. domcii set the bit to 1 to activate the irq at each day-of-month update. dowcii set the bit to 1 to activate the irq at each day-of-week update. mthcii set the bit to 1 to activate the irq at each month update. yeacii set the bit to 1 to activate the irq at each year update. 1/2seccii set the bit to 1 to activate the irq at each one-half of a second update. 1/4seccii set the bit to 1 to activate the irq at each one-fourth of a second update. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1530 of 1535 1/8seccii set the bit to 1 to activate the irq at each one-eighth of a second update. rtc+0010h rtc alarm mask rtc_al_mask bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name yea_m sk mth_m sk dow_m sk dom_m sk hou_m sk min_ms k sec_m sk type r/w r/w r/w r/w r/w r/w r/w the alarm condition for alarm irq generation depends on whether or not the corresponding bit in this register is masked. warning: if you set all bits 1 in rtc_al_mask (i.e. rtc_al_mask=0x7f) and pwren=1 in rtc_bbpu, it means alarm comes every second, not disabled. sec_msk 0 condition (rtc_tc_sec = rtc_al_sec) is checked to generate the alarm signal. 1 condition (rtc_tc_sec = rtc_al_sec) is masked, i.e. the value of rtc_tc_sec does not affect the alarm irq generation. min_msk 0 condition (rtc_tc_min = rtc_al_min) is checked to generate the alarm signal. 1 condition (rtc_tc_min = rtc_al_min) is masked, i.e. the value of rtc_tc_min does not affect the alarm irq generation. hou_msk 0 condition (rtc_tc_hou = rtc_al_hou) is checked to generate the alarm signal. 1 condition (rtc_tc_hou = rtc_al_hou) is masked, i.e. the value of rtc_tc_hou does not affect the alarm irq generation. dom_msk 0 condition (rtc_tc_dom = rtc_al_dom) is checked to generate the alarm signal. 1 condition (rtc_tc_dom = rtc_al_dom) is masked, i.e. the value of rtc_tc_dom does not affect the alarm irq generation. dow_msk 0 condition (rtc_tc_dow = rtc_al_dow) is checked to generate the alarm signal. 1 condition (rtc_tc_dow = rtc_al_dow) is masked, i.e. the value of rtc_tc_dow does not affect the alarm irq generation. mth_msk 0 condition (rtc_tc_mth = rtc_al_mth) is checked to generate the alarm signal. 1 condition (rtc_tc_mth = rtc_al_mth) is masked, i.e. the value of rtc_tc_mth does not affect the alarm irq generation. yea_msk 0 condition (rtc_tc_yea = rtc_al_yea) is checked to generate the alarm signal. 1 condition (rtc_tc_yea = rtc_al_yea) is masked, i.e. the value of rtc_tc_yea does not affect the alarm irq generation. rtc+0014h rtc seconds time c ounter register rtc_tc_sec bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_second type r/w free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1531 of 1535 tc_second the second initial value for the time counter. the range of its value is: 0-59. rtc+0018h rtc minutes time counter register rtc_tc_min bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_minute type r/w tc_minute the minute initial value for the time counter. the range of its value is: 0-59. rtc+001ch rtc hours time c ounter register rtc_tc_hou bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_hour type r/w tc_hour the hour initial value for the time counter. the range of its value is: 0-23. rtc+0020h rtc day-of-month time counter register rtc_tc_dom bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_dom type r/w tc_dom the day-of-month initial value for the time counter. the day-of-month maximum value depends on the leap year condition, i.e. 2 lsb of year time counter are zeros. rtc+0024h rtc day-of-week time counter register rtc_tc_dow bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_dow type r/w tc_dow the day-of-week initial value for the time counter. the range of its value is: 1-7. rtc+0028h rtc month time counter register rtc_tc_mth bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name tc_month type r/w tc_month the month initial value for the time counter. the range of its value is: 1-12. rtc+002ch rtc year time c ounter register rtc_tc_yea bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_second type r/w tc_year the year initial value for the time counter. the range of its value is: 0-127. (2000-2127) rtc+0030h rtc second alarm setting register rtc_al_sec bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_second type r/w al_second the second value of the alarm counter setting. the range of its value is: 0-59. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1532 of 1535 rtc+0034h rtc minute alarm setting register rtc_al_min bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_minute type r/w al_minute the minute value of the alarm counter setting. the range of its value is: 0-59. rtc+0038h rtc hour alarm setting register rtc_al_hou bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_hour type r/w al_hour the hour value of the alarm counter setting. the range of its value is: 0-23. rtc+003ch rtc day-of-month alarm setting register rtc_al_dom bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_dom type r/w al_dom the day-of-month value of the alarm counter setting. the day-of-month maximum value depends on the leap year condition, i.e. 2 lsb of year time counter are zeros. rtc+0040h rtc day-of-week alarm setting register rtc_al_dow bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_dow type r/w al_dow the day-of-week value of the alarm counter setting. the range of its value is: 1-7. rtc+0044h rtc month alarm setting register rtc_al_mth bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_month type r/w al_month the month value of the alarm counter setting. the range of its value is: 1-12. rtc+0048h rtc year alarm setting register rtc_al_yea bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name al_year type r/w al_year the year value of the alarm counter setting. the range of its value is: 0-127. (2000-2127) rtc+004ch xosc bias current control register rtc_xosccal i bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name xosccali type wo the function is only active when rtc_powerkey1 & rtc_powerkey2 match the correct values. free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1533 of 1535 xosccali this register controls the xosc32 bias current. rtc+0050h rtc_powerkey1 register rtc_powerk ey1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_powerkey1 type r/w rtc+0054h rtc_powerkey2 register rtc_powerk ey2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_powerkey2 type r/w these register sets are used to determine if the real time clock has been programmed by software; i.e. the time value in real time clock is correct. when the real time clock is first powered on, the register contents are all undefined, therefore the time values shown are incorrect. software needs to know if the real time clock has been programmed. hence, these two registers are defined to solve this power-on issue. after software programs the correct value, these two register sets do not need to be updated. in addition to programming the correct time value, when the contents of these register sets are wrong, the interrupt is not generated. therefore, the real time clock does not generate the interrupts before the software programs the registers; unwanted interrupt due to wrong time value do not occur. the correct values of these two register sets are: rtc_powerkey1 a357h rtc_powerkey2 67d2h rtc+0058h pdn1 rtc_pdn1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_pdn1[7:0] type r/w rtc_pdn1[3:1] is for reset de-bounce mechanism. when rtc_powerkey1 & rtc_powerkey2 do not match the correct values, rtc_pdn1[3:1] is set to 3(011 in binary). 0 2ms 1 8ms 2 32ms 3 128ms 4 256ms 5 512ms 6 1024ms 7 2048ms rtc_pdn1[7:4] & rtc_pdn1[0] is the spare register for software to keep power on and power off state information. rtc+005ch pdn2 rtc_pdn2 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1534 of 1535 name rtc_pdn2[7:0] type r/w rtc_pdn2 the spare register for software to keep power on and power off state information. rtc+0064h spare register for specific purpose rtc_spar1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_spar1 type r/w rtc_spar 1 these registers are reserved for specific purpose. rtc+0068h lock / unlock scheme to prevent rtc miswriting rtc_prot bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_prot type r/w rtc_prot the rtc write interface is protected by rtc_prot. whether the rtc writing interface is enabled or not is decided by rtc_prot contents. when rtc_powerkey1 & rtc_powerkey2 are not equal to the correct values, the rtc writing interface is always enabled. but when they match, users have to perform unlock flow to enable the writing interface. unlock flow: step1: *rtc_prot=0x9136; // compare 15 bits: bit 15~1 step2: *rtc_wrtrg=1; step3: while(*rtc_bbpu & 0x40) {}; // timeout period: 120usec lock flow: step1: *rtc_prot=0x0; step2: *rtc_wrtrg=1; step3: while(*rtc_bbpu & 0x40) {}; // timeout period: 120usec once the normal rtc content writing is complete, it is suggested to perform lock flow to turn off the interface to avoid accident writing. rtc+006ch one-time calibration offset rtc_diff bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name rtc_diff type r/w the function is only active when rtc_powerkey1 & rtc_powerkey2 match the correct values. rtc_diff these registers are used to adjust the internal counter of rtc. it effects once and returns to zero in done. in some cases, you observe the rtc is faster or slower than the standard. to change rtc_tc_sec is coarse and may cause alarm problem. rtc_diff provides a finer time unit. an internal 15-bit counter accumulates in each 32768-hz clock. entering a non-zero value into the rtc_diff causes the internal rtc counter increases or decreases rtc_diff when rtc_diff changes to zero again. rtc_diff represents as 2?s completement form. for example, if you fill in 0xfff into rtc_diff, the internal counter decreases 1 when rtc_diff returns to zero. in other words, you can only use rtc_diff continuously if rtc_diff is equal to free datasheet http://www.datasheet-pdf.com/
MT6516 data sheet confidential a mediatek confidential ? 2009 mediatek inc. page 1535 of 1535 zero now. note: rtc_diff ranges from 0x800 (-2048) to 0x7fd (2045). 0x7ff & 0x7fe are forbid to use. rtc+0074h enable the transfers from core to rtc in the queue rtc_wrtgr bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name wrtg r type wo wrtgr this register enables the transfers from core to rtc. after you modify all the rtc registers you?d like to change, you must write rtc_wrtgr to 1 to trigger the transfer. the prior writing operations are queued at core power domain. the pending data will not be transferred to rtc domain until wrtgr=1. after wrtgr=1, the pending data is transferred to rtc domain sequentially in order of register address, from low to high. for example: rtc_bbpu -> rtc_irq_en -> rtc_cii_en -> rtc_al_mask -> rtc_tc_sec -> etc. the cbusy in rtc_bbpu is equal to 1 in writing process. you can observe cbusy to determine when the transmission completes. free datasheet http://www.datasheet-pdf.com/

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